Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	346	1			T9	1		T14	3		T15	2
auto[ReadAddrCrossIntoMailbox]	244	1			T9	1		T14	2		T15	4
auto[ReadAddrCrossOutOfMailbox]	243	1			T14	4		T15	2		T16	1
auto[ReadAddrCrossAllMailbox]	181	1			T16	2		T17	1		T28	2
auto[ReadAddrOutsideMailbox]	2979	1			T9	13		T14	24		T15	20

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1954

1

T9

8

T14

23

T15

8

auto[1]

2039

1

T9

7

T14

10

T15

20

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	700	1			T9	2		T14	5		T15	8
read_ops[0x0b]	650	1			T9	3		T14	4		T15	1
read_ops[0x3b]	695	1			T9	3		T14	8		T15	4
read_ops[0x6b]	653	1			T14	7		T15	6		T16	1
read_ops[0xbb]	654	1			T9	1		T14	3		T15	8
read_ops[0xeb]	641	1			T9	6		T14	6		T15	1

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	32	1			T51	1		T178	1		T177	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	45	1			T15	1		T16	1		T28	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	24	1			T15	1		T170	1		T22	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	18	1			T15	1		T180	1		T201	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	10	1			T178	1		T92	1		T224	2
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	26	1			T18	1		T219	1		T38	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	12	1			T38	1		T230	1		T201	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T180	1		T91	1		T208	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	261	1			T14	1		T15	1		T46	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	256	1			T9	2		T14	4		T15	4
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	23	1			T18	1		T177	1		T38	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	23	1			T178	1		T177	1		T38	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	16	1			T16	1		T177	1		T22	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	13	1			T14	1		T28	1		T51	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	23	1			T22	1		T38	2		T91	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	17	1			T214	1		T219	1		T38	3
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	14	1			T205	2		T92	1		T203	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	13	1			T180	1		T38	2		T199	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	254	1			T9	1		T14	2		T15	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	254	1			T9	2		T14	1		T17	5
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	24	1			T14	2		T47	1		T18	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	21	1			T47	1		T180	1		T22	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	16	1			T200	1		T227	1		T143	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	22	1			T28	1		T178	1		T38	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	18	1			T14	2		T15	1		T16	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	30	1			T28	2		T18	1		T180	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	13	1			T16	1		T18	1		T177	2
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	9	1			T18	1		T178	1		T219	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	264	1			T9	2		T14	4		T17	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	278	1			T9	1		T15	3		T16	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	30	1			T18	2		T177	2		T205	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	26	1			T15	1		T18	1		T51	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	19	1			T28	1		T38	1		T203	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	21	1			T14	1		T28	1		T18	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	16	1			T17	1		T208	1		T238	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	18	1			T14	1		T18	2		T51	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T177	1		T214	1		T205	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	18	1			T28	1		T200	1		T221	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	227	1			T14	4		T15	1		T16	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	263	1			T14	1		T15	4		T17	4
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	34	1			T14	1		T18	1		T180	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	37	1			T180	1		T90	2		T177	2
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	22	1			T170	1		T22	1		T197	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	29	1			T15	1		T177	2		T214	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	17	1			T90	1		T177	1		T221	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	23	1			T15	1		T28	2		T179	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T28	1		T179	1		T38	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T16	1		T17	1		T18	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	242	1			T9	1		T14	2		T15	2
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	218	1			T15	4		T17	8		T28	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	27	1			T9	1		T47	1		T179	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	24	1			T47	1		T18	1		T177	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	20	1			T9	1		T15	1		T179	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	24	1			T18	1		T178	1		T170	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	23	1			T14	1		T28	1		T18	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	22	1			T18	2		T178	1		T200	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T205	1		T226	1		T197	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	23	1			T51	1		T180	1		T178	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	226	1			T9	2		T14	4		T17	4
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	236	1			T9	2		T14	1		T17	2