Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg
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Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 18 0 18 100.00
Crosses 128 0 128 100.00


Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_data 8 0 8 100.00 100 1 1 0
cp_mask 8 0 8 100.00 100 1 1 0
cp_payload_swap_en 2 0 2 100.00 100 1 1 2


Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 128 0 128 100.00 100 1 1 0


Summary for Variable cp_data

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 0 8 100.00


User Defined Bins for cp_data

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0] 3155 1 T14 114 T15 20 T49 8
values[1] 3309 1 T15 20 T93 10 T17 46
values[2] 3795 1 T3 4 T8 22 T12 2
values[3] 3414 1 T14 35 T15 40 T17 47
values[4] 3007 1 T4 14 T14 20 T16 24
values[5] 2905 1 T14 29 T17 21 T28 20
values[6] 4360 1 T9 102 T14 156 T15 20
values[7] 3849 1 T9 59 T14 35 T15 20



Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 0 8 100.00


User Defined Bins for cp_mask

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0] 3090 1 T14 20 T15 20 T46 2
values[1] 2889 1 T17 23 T28 40 T180 23
values[2] 3321 1 T4 14 T9 20 T15 20
values[3] 3673 1 T14 64 T15 20 T49 8
values[4] 3468 1 T3 4 T8 22 T14 173
values[5] 3513 1 T14 35 T15 40 T16 43
values[6] 4504 1 T9 141 T12 2 T14 194
values[7] 3336 1 T15 20 T17 26 T18 116



Summary for Variable cp_payload_swap_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_payload_swap_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 27132 1 T3 4 T4 14 T8 10
auto[1] 662 1 T8 12 T9 1 T14 7



Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 128 0 128 100.00


Automatically Generated Cross Bins for cr_all

Bins
cp_payload_swap_encp_datacp_maskCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] values[0] values[0] 419 1 T177 28 T170 51 T219 20
auto[0] values[0] values[1] 451 1 T180 23 T177 20 T31 93
auto[0] values[0] values[2] 418 1 T205 20 T31 20 T256 14
auto[0] values[0] values[3] 550 1 T15 18 T49 8 T47 4
auto[0] values[0] values[4] 361 1 T14 74 T212 18 T270 18
auto[0] values[0] values[5] 240 1 T48 6 T170 21 T219 20
auto[0] values[0] values[6] 254 1 T14 38 T266 2 T170 24
auto[0] values[0] values[7] 383 1 T18 75 T178 20 T91 20
auto[0] values[1] values[0] 325 1 T15 19 T17 20 T28 17
auto[0] values[1] values[1] 146 1 T38 20 T217 12 T271 4
auto[0] values[1] values[2] 509 1 T93 10 T118 4 T177 97
auto[0] values[1] values[3] 552 1 T51 18 T92 17 T272 10
auto[0] values[1] values[4] 454 1 T18 19 T220 22 T138 166
auto[0] values[1] values[5] 408 1 T18 87 T51 20 T178 19
auto[0] values[1] values[6] 394 1 T22 65 T197 61 T230 20
auto[0] values[1] values[7] 448 1 T17 23 T18 35 T273 2
auto[0] values[2] values[0] 494 1 T17 43 T179 19 T225 2
auto[0] values[2] values[1] 360 1 T28 18 T178 19 T230 20
auto[0] values[2] values[2] 502 1 T28 40 T177 20 T31 20
auto[0] values[2] values[3] 359 1 T94 16 T214 18 T219 20
auto[0] values[2] values[4] 579 1 T3 4 T8 10 T14 96
auto[0] values[2] values[5] 400 1 T16 42 T28 18 T180 23
auto[0] values[2] values[6] 836 1 T12 2 T170 22 T22 20
auto[0] values[2] values[7] 173 1 T15 20 T38 27 T197 20
auto[0] values[3] values[0] 363 1 T17 20 T213 10 T214 20
auto[0] values[3] values[1] 396 1 T177 96 T209 2 T214 20
auto[0] values[3] values[2] 389 1 T18 47 T180 24 T214 19
auto[0] values[3] values[3] 376 1 T18 20 T179 21 T178 19
auto[0] values[3] values[4] 375 1 T170 19 T214 20 T92 20
auto[0] values[3] values[5] 535 1 T14 35 T15 20 T28 20
auto[0] values[3] values[6] 616 1 T15 19 T17 24 T201 23
auto[0] values[3] values[7] 275 1 T36 22 T177 67 T38 21
auto[0] values[4] values[0] 340 1 T14 20 T219 36 T38 20
auto[0] values[4] values[1] 250 1 T17 23 T178 20 T219 20
auto[0] values[4] values[2] 372 1 T4 14 T16 24 T253 61
auto[0] values[4] values[3] 303 1 T236 22 T274 8 T275 4
auto[0] values[4] values[4] 341 1 T28 20 T179 20 T276 14
auto[0] values[4] values[5] 473 1 T17 23 T51 20 T179 18
auto[0] values[4] values[6] 332 1 T17 20 T18 80 T178 20
auto[0] values[4] values[7] 535 1 T38 26 T198 20 T277 10
auto[0] values[5] values[0] 233 1 T178 18 T38 20 T197 20
auto[0] values[5] values[1] 673 1 T28 20 T177 112 T91 20
auto[0] values[5] values[2] 280 1 T91 19 T251 4 T203 21
auto[0] values[5] values[3] 406 1 T14 26 T18 20 T179 20
auto[0] values[5] values[4] 144 1 T18 29 T258 8 T278 4
auto[0] values[5] values[5] 227 1 T244 20 T279 16 T198 28
auto[0] values[5] values[6] 518 1 T17 20 T18 22 T177 51
auto[0] values[5] values[7] 354 1 T171 16 T205 20 T91 38
auto[0] values[6] values[0] 302 1 T174 2 T233 16 T280 2
auto[0] values[6] values[1] 283 1 T177 28 T205 20 T201 17
auto[0] values[6] values[2] 413 1 T15 19 T178 19 T170 22
auto[0] values[6] values[3] 634 1 T17 20 T18 128 T179 20
auto[0] values[6] values[4] 702 1 T170 19 T211 12 T205 22
auto[0] values[6] values[5] 474 1 T178 20 T38 20 T198 20
auto[0] values[6] values[6] 928 1 T9 101 T14 155 T17 29
auto[0] values[6] values[7] 519 1 T281 6 T221 20 T203 20
auto[0] values[7] values[0] 525 1 T46 2 T28 20 T18 23
auto[0] values[7] values[1] 245 1 T178 19 T230 59 T282 4
auto[0] values[7] values[2] 366 1 T9 20 T18 39 T22 18
auto[0] values[7] values[3] 382 1 T14 35 T18 20 T197 20
auto[0] values[7] values[4] 433 1 T50 14 T178 20 T205 18
auto[0] values[7] values[5] 684 1 T15 20 T177 33 T170 21
auto[0] values[7] values[6] 550 1 T9 39 T51 20 T222 8
auto[0] values[7] values[7] 571 1 T214 20 T22 42 T38 40
auto[1] values[0] values[0] 9 1 T177 1 T283 3 T284 1
auto[1] values[0] values[1] 11 1 T31 5 T208 1 T285 2
auto[1] values[0] values[2] 18 1 T92 3 T230 1 T286 2
auto[1] values[0] values[3] 13 1 T15 2 T74 2 T200 2
auto[1] values[0] values[4] 7 1 T14 2 T283 1 T287 1
auto[1] values[0] values[5] 6 1 T205 4 T283 1 T288 1
auto[1] values[0] values[6] 11 1 T170 3 T214 6 T219 1
auto[1] values[0] values[7] 4 1 T18 4 - - - -
auto[1] values[1] values[0] 17 1 T15 1 T28 3 T38 1
auto[1] values[1] values[1] 7 1 T38 2 T289 1 T290 2
auto[1] values[1] values[2] 6 1 T177 2 T91 1 T268 2
auto[1] values[1] values[3] 19 1 T51 2 T92 3 T238 2
auto[1] values[1] values[4] 6 1 T18 1 T138 1 T291 1
auto[1] values[1] values[5] 2 1 T178 1 T203 1 - -
auto[1] values[1] values[6] 5 1 T22 1 T265 1 T292 3
auto[1] values[1] values[7] 11 1 T17 3 T18 2 T199 1
auto[1] values[2] values[0] 10 1 T17 1 T179 2 T200 1
auto[1] values[2] values[1] 14 1 T28 2 T178 1 T230 2
auto[1] values[2] values[2] 8 1 T202 3 T268 2 T293 3
auto[1] values[2] values[3] 16 1 T214 2 T138 1 T294 5
auto[1] values[2] values[4] 22 1 T8 12 T14 1 T235 1
auto[1] values[2] values[5] 13 1 T16 1 T28 2 T295 3
auto[1] values[2] values[6] 8 1 T201 3 T218 1 T289 3
auto[1] values[2] values[7] 1 1 T38 1 - - - -
auto[1] values[3] values[0] 16 1 T213 6 T198 1 T264 2
auto[1] values[3] values[1] 14 1 T177 2 T209 4 T219 1
auto[1] values[3] values[2] 10 1 T18 3 T180 1 T214 1
auto[1] values[3] values[3] 12 1 T178 1 T267 2 T216 3
auto[1] values[3] values[4] 1 1 T170 1 - - - -
auto[1] values[3] values[5] 14 1 T18 3 T178 2 T170 2
auto[1] values[3] values[6] 14 1 T15 1 T17 3 T296 2
auto[1] values[3] values[7] 8 1 T177 1 T38 1 T91 1
auto[1] values[4] values[0] 8 1 T219 4 T297 2 T298 2
auto[1] values[4] values[1] 6 1 T38 2 T138 3 T228 1
auto[1] values[4] values[2] 3 1 T299 1 T292 2 - -
auto[1] values[4] values[3] 5 1 T203 1 T53 2 T300 1
auto[1] values[4] values[4] 12 1 T301 2 T53 1 T302 2
auto[1] values[4] values[5] 11 1 T17 3 T179 2 T303 2
auto[1] values[4] values[6] 6 1 T18 3 T285 1 T265 1
auto[1] values[4] values[7] 10 1 T92 4 T201 3 T234 2
auto[1] values[5] values[0] 14 1 T178 2 T38 1 T199 2
auto[1] values[5] values[1] 12 1 T177 1 T285 2 T304 1
auto[1] values[5] values[2] 7 1 T91 1 T203 1 T138 1
auto[1] values[5] values[3] 12 1 T14 3 T230 1 T304 2
auto[1] values[5] values[4] 2 1 T92 1 T305 1 - -
auto[1] values[5] values[5] 6 1 T198 1 T202 1 T306 2
auto[1] values[5] values[6] 10 1 T17 1 T31 2 T238 1
auto[1] values[5] values[7] 7 1 T91 2 T199 1 T307 2
auto[1] values[6] values[0] 6 1 T244 1 T304 2 T294 1
auto[1] values[6] values[1] 10 1 T177 2 T201 3 T53 2
auto[1] values[6] values[2] 10 1 T15 1 T178 1 T170 4
auto[1] values[6] values[3] 29 1 T18 3 T179 2 T91 3
auto[1] values[6] values[4] 19 1 T170 3 T205 1 T208 2
auto[1] values[6] values[5] 6 1 T306 1 T305 1 T308 4
auto[1] values[6] values[6] 13 1 T9 1 T14 1 T18 2
auto[1] values[6] values[7] 12 1 T136 2 T145 2 T309 3
auto[1] values[7] values[0] 9 1 T214 1 T229 2 T310 2
auto[1] values[7] values[1] 11 1 T178 1 T230 2 T307 3
auto[1] values[7] values[2] 10 1 T22 2 T311 2 T312 1
auto[1] values[7] values[3] 5 1 T138 1 T145 2 T283 2
auto[1] values[7] values[4] 10 1 T50 2 T205 2 T216 1
auto[1] values[7] values[5] 14 1 T177 1 T219 2 T312 1
auto[1] values[7] values[6] 9 1 T221 3 T145 1 T307 1
auto[1] values[7] values[7] 25 1 T22 3 T38 3 T199 6

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