Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	858	1			T19	17		T20	31		T21	8
all_values[1]	858	1			T19	17		T20	31		T21	8
all_values[2]	858	1			T19	17		T20	31		T21	8
all_values[3]	858	1			T19	17		T20	31		T21	8
all_values[4]	858	1			T19	17		T20	31		T21	8
all_values[5]	858	1			T19	17		T20	31		T21	8
all_values[6]	858	1			T19	17		T20	31		T21	8
all_values[7]	858	1			T19	17		T20	31		T21	8

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3622

1

T19

53

T20

125

T21

40

auto[1]

3242

1

T19

83

T20

123

T21

24

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2755

1

T19

57

T20

100

T21

31

auto[1]

4109

1

T19

79

T20

148

T21

33

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3943

1

T19

84

T20

139

T21

40

auto[1]

2921

1

T19

52

T20

109

T21

24

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	158	1			T19	4		T20	7		T21	1
all_values[0]	auto[0]	auto[0]	auto[1]	83	1			T19	1		T20	1		T21	3
all_values[0]	auto[0]	auto[1]	auto[0]	128	1			T19	2		T20	1		T22	1
all_values[0]	auto[0]	auto[1]	auto[1]	101	1			T19	2		T20	4		T22	3
all_values[0]	auto[1]	auto[0]	auto[1]	235	1			T19	5		T20	13		T21	4
all_values[0]	auto[1]	auto[1]	auto[1]	153	1			T19	3		T20	5		T31	2
all_values[1]	auto[0]	auto[0]	auto[0]	171	1			T19	2		T20	5		T21	3
all_values[1]	auto[0]	auto[0]	auto[1]	91	1			T19	4		T20	2		T22	1
all_values[1]	auto[0]	auto[1]	auto[0]	168	1			T19	2		T20	9		T21	4
all_values[1]	auto[0]	auto[1]	auto[1]	81	1			T19	1		T20	1		T22	4
all_values[1]	auto[1]	auto[0]	auto[1]	173	1			T19	5		T20	3		T21	1
all_values[1]	auto[1]	auto[1]	auto[1]	174	1			T19	3		T20	11		T22	2
all_values[2]	auto[0]	auto[0]	auto[0]	183	1			T19	1		T20	3		T21	1
all_values[2]	auto[0]	auto[0]	auto[1]	76	1			T20	3		T21	1		T22	1
all_values[2]	auto[0]	auto[1]	auto[0]	142	1			T19	8		T20	8		T31	2
all_values[2]	auto[0]	auto[1]	auto[1]	86	1			T19	3		T20	4		T21	2
all_values[2]	auto[1]	auto[0]	auto[1]	210	1			T19	2		T20	8		T21	2
all_values[2]	auto[1]	auto[1]	auto[1]	161	1			T19	3		T20	5		T21	2
all_values[3]	auto[0]	auto[0]	auto[0]	186	1			T19	5		T20	6		T21	3
all_values[3]	auto[0]	auto[0]	auto[1]	85	1			T19	2		T20	5		T22	2
all_values[3]	auto[0]	auto[1]	auto[0]	155	1			T19	1		T20	7		T21	3
all_values[3]	auto[0]	auto[1]	auto[1]	85	1			T19	2		T20	1		T23	1
all_values[3]	auto[1]	auto[0]	auto[1]	189	1			T19	5		T20	7		T21	2
all_values[3]	auto[1]	auto[1]	auto[1]	158	1			T19	2		T20	5		T22	3
all_values[4]	auto[0]	auto[0]	auto[0]	168	1			T19	4		T20	8		T21	3
all_values[4]	auto[0]	auto[0]	auto[1]	74	1			T20	2		T22	1		T23	1
all_values[4]	auto[0]	auto[1]	auto[0]	165	1			T19	7		T20	5		T21	1
all_values[4]	auto[0]	auto[1]	auto[1]	85	1			T19	1		T20	1		T22	1
all_values[4]	auto[1]	auto[0]	auto[1]	187	1			T19	1		T20	10		T21	4
all_values[4]	auto[1]	auto[1]	auto[1]	179	1			T19	4		T20	5		T31	2
all_values[5]	auto[0]	auto[0]	auto[0]	279	1			T19	3		T20	11		T21	2
all_values[5]	auto[0]	auto[1]	auto[0]	222	1			T19	8		T20	6		T21	3
all_values[5]	auto[1]	auto[0]	auto[1]	181	1			T19	4		T20	7		T21	3
all_values[5]	auto[1]	auto[1]	auto[1]	176	1			T19	2		T20	7		T22	2
all_values[6]	auto[0]	auto[0]	auto[0]	158	1			T19	1		T20	3		T21	3
all_values[6]	auto[0]	auto[0]	auto[1]	65	1			T19	1		T20	1		T21	1
all_values[6]	auto[0]	auto[1]	auto[0]	169	1			T19	5		T20	6		T21	1
all_values[6]	auto[0]	auto[1]	auto[1]	97	1			T19	3		T20	7		T21	1
all_values[6]	auto[1]	auto[0]	auto[1]	188	1			T19	1		T20	6		T21	1
all_values[6]	auto[1]	auto[1]	auto[1]	181	1			T19	6		T20	8		T21	1
all_values[7]	auto[0]	auto[0]	auto[0]	182	1			T20	5		T22	3		T23	4
all_values[7]	auto[0]	auto[0]	auto[1]	96	1			T19	1		T20	6		T22	2
all_values[7]	auto[0]	auto[1]	auto[0]	121	1			T19	4		T20	10		T21	3
all_values[7]	auto[0]	auto[1]	auto[1]	83	1			T19	6		T20	1		T21	1
all_values[7]	auto[1]	auto[0]	auto[1]	204	1			T19	1		T20	3		T21	2
all_values[7]	auto[1]	auto[1]	auto[1]	172	1			T19	5		T20	6		T21	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal