Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1740

1

T1

2

T6

6

T11

9

auto[1]

1752

1

T1

1

T6

4

T11

5

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1806

1

T1

1

T11

13

T13

22

auto[1]

1686

1

T1

2

T6

10

T11

1

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2737

1

T1

2

T6

10

T11

5

auto[1]

755

1

T1

1

T11

9

T13

5

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	645	1			T1	1		T6	2		T11	3
valid[1]	694	1			T1	1		T6	1		T11	5
valid[2]	729	1			T1	1		T6	2		T11	4
valid[3]	734	1			T6	1		T11	2		T13	4
valid[4]	690	1			T6	4		T13	6		T16	2

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	93	1			T13	2		T17	1		T179	4
auto[0]	auto[0]	valid[0]	auto[1]	130	1			T1	1		T6	2		T17	1
auto[0]	auto[0]	valid[1]	auto[0]	121	1			T11	1		T13	1		T17	2
auto[0]	auto[0]	valid[1]	auto[1]	156	1			T11	1		T17	1		T88	3
auto[0]	auto[0]	valid[2]	auto[0]	104	1			T11	1		T13	2		T29	2
auto[0]	auto[0]	valid[2]	auto[1]	176	1			T1	1		T6	2		T37	5
auto[0]	auto[0]	valid[3]	auto[0]	110	1			T11	1		T13	2		T29	2
auto[0]	auto[0]	valid[3]	auto[1]	168	1			T6	1		T17	2		T37	2
auto[0]	auto[0]	valid[4]	auto[0]	102	1			T13	1		T16	1		T29	1
auto[0]	auto[0]	valid[4]	auto[1]	182	1			T6	1		T17	3		T37	1
auto[0]	auto[1]	valid[0]	auto[0]	92	1			T11	1		T16	1		T17	2
auto[0]	auto[1]	valid[0]	auto[1]	172	1			T18	2		T37	1		T88	1
auto[0]	auto[1]	valid[1]	auto[0]	99	1			T13	2		T16	1		T17	1
auto[0]	auto[1]	valid[1]	auto[1]	178	1			T6	1		T17	2		T37	4
auto[0]	auto[1]	valid[2]	auto[0]	99	1			T13	2		T180	1		T170	1
auto[0]	auto[1]	valid[2]	auto[1]	196	1			T17	5		T37	6		T89	2
auto[0]	auto[1]	valid[3]	auto[0]	122	1			T13	2		T16	1		T17	1
auto[0]	auto[1]	valid[3]	auto[1]	180	1			T37	6		T89	1		T170	1
auto[0]	auto[1]	valid[4]	auto[0]	109	1			T13	3		T17	3		T179	2
auto[0]	auto[1]	valid[4]	auto[1]	148	1			T6	3		T17	2		T37	3
auto[1]	auto[0]	valid[0]	auto[0]	83	1			T11	1		T16	1		T324	1
auto[1]	auto[0]	valid[1]	auto[0]	72	1			T11	2		T13	1		T17	3
auto[1]	auto[0]	valid[2]	auto[0]	84	1			T11	1		T16	1		T29	1
auto[1]	auto[0]	valid[3]	auto[0]	85	1			T11	1		T17	3		T52	1
auto[1]	auto[0]	valid[4]	auto[0]	74	1			T13	2		T16	1		T17	2
auto[1]	auto[1]	valid[0]	auto[0]	75	1			T11	1		T13	1		T17	3
auto[1]	auto[1]	valid[1]	auto[0]	68	1			T1	1		T11	1		T13	1
auto[1]	auto[1]	valid[2]	auto[0]	70	1			T11	2		T16	1		T52	1
auto[1]	auto[1]	valid[3]	auto[0]	69	1			T16	1		T17	1		T52	2
auto[1]	auto[1]	valid[4]	auto[0]	75	1			T52	1		T168	1		T170	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal