Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

46213

1

T1

80

T10

7

T11

241

auto[1]

18431

1

T1

14

T6

144

T11

27

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

47507

1

T1

63

T6

144

T10

3

auto[1]

17137

1

T1

31

T10

4

T11

90

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	33456	1			T1	47		T6	68		T10	2
others[1]	5383	1			T1	8		T6	11		T10	4
others[2]	5460	1			T1	7		T6	11		T10	1
others[3]	6217	1			T1	15		T6	13		T11	30
interest[1]	3633	1			T1	1		T6	14		T11	13
interest[4]	21810	1			T1	28		T6	49		T10	2
interest[64]	10495	1			T1	16		T6	27		T11	39

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	14953	1			T1	22		T10	2		T11	74
auto[0]	auto[0]	others[1]	2423	1			T1	5		T11	16		T13	22
auto[0]	auto[0]	others[2]	2423	1			T1	5		T10	1		T11	13
auto[0]	auto[0]	others[3]	2838	1			T1	8		T11	16		T13	29
auto[0]	auto[0]	interest[1]	1668	1			T1	1		T11	8		T13	8
auto[0]	auto[0]	interest[4]	9674	1			T1	12		T10	2		T11	42
auto[0]	auto[0]	interest[64]	4771	1			T1	8		T11	24		T13	27
auto[0]	auto[1]	others[0]	9699	1			T1	6		T6	68		T11	13
auto[0]	auto[1]	others[1]	1531	1			T1	1		T6	11		T11	3
auto[0]	auto[1]	others[2]	1521	1			T6	11		T11	2		T14	1
auto[0]	auto[1]	others[3]	1696	1			T1	5		T6	13		T11	4
auto[0]	auto[1]	interest[1]	1044	1			T6	14		T14	2		T17	13
auto[0]	auto[1]	interest[4]	6416	1			T1	4		T6	49		T11	10
auto[0]	auto[1]	interest[64]	2940	1			T1	2		T6	27		T11	5
auto[1]	auto[0]	others[0]	8804	1			T1	19		T11	53		T13	65
auto[1]	auto[0]	others[1]	1429	1			T1	2		T10	4		T11	6
auto[1]	auto[0]	others[2]	1516	1			T1	2		T11	6		T13	13
auto[1]	auto[0]	others[3]	1683	1			T1	2		T11	10		T13	16
auto[1]	auto[0]	interest[1]	921	1			T11	5		T13	9		T16	4
auto[1]	auto[0]	interest[4]	5720	1			T1	12		T11	34		T13	45
auto[1]	auto[0]	interest[64]	2784	1			T1	6		T11	10		T13	24

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal