Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.07 98.45 94.10 98.62 89.36 97.29 95.43 99.26


Total test records in report: 1151
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html
T1033 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2479082661 Aug 05 04:29:20 PM PDT 24 Aug 05 04:29:21 PM PDT 24 22532493 ps
T1034 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.3632948984 Aug 05 04:29:18 PM PDT 24 Aug 05 04:29:19 PM PDT 24 50416338 ps
T112 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3284210236 Aug 05 04:29:06 PM PDT 24 Aug 05 04:29:09 PM PDT 24 661538711 ps
T117 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.2137941580 Aug 05 04:29:23 PM PDT 24 Aug 05 04:29:37 PM PDT 24 1083677266 ps
T1035 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.3122605633 Aug 05 04:29:08 PM PDT 24 Aug 05 04:29:09 PM PDT 24 37888005 ps
T1036 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.2467876382 Aug 05 04:29:00 PM PDT 24 Aug 05 04:29:01 PM PDT 24 11582160 ps
T123 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1727836432 Aug 05 04:28:56 PM PDT 24 Aug 05 04:29:31 PM PDT 24 2177430008 ps
T161 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.746171217 Aug 05 04:28:59 PM PDT 24 Aug 05 04:29:04 PM PDT 24 432523253 ps
T188 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.2889773761 Aug 05 04:29:01 PM PDT 24 Aug 05 04:29:14 PM PDT 24 798076336 ps
T176 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.3098677767 Aug 05 04:29:21 PM PDT 24 Aug 05 04:29:34 PM PDT 24 205735351 ps
T1037 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3743941600 Aug 05 04:29:15 PM PDT 24 Aug 05 04:29:18 PM PDT 24 58957546 ps
T124 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.1110359773 Aug 05 04:28:52 PM PDT 24 Aug 05 04:28:54 PM PDT 24 75143223 ps
T1038 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.1548065630 Aug 05 04:28:49 PM PDT 24 Aug 05 04:28:50 PM PDT 24 12366610 ps
T1039 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1346351504 Aug 05 04:29:18 PM PDT 24 Aug 05 04:29:20 PM PDT 24 163162151 ps
T110 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2081782003 Aug 05 04:28:49 PM PDT 24 Aug 05 04:28:52 PM PDT 24 255433572 ps
T1040 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.1314798242 Aug 05 04:29:07 PM PDT 24 Aug 05 04:29:09 PM PDT 24 141578811 ps
T1041 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.4161509249 Aug 05 04:28:48 PM PDT 24 Aug 05 04:28:50 PM PDT 24 73904042 ps
T125 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.2832432838 Aug 05 04:28:52 PM PDT 24 Aug 05 04:29:07 PM PDT 24 530151191 ps
T84 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2020885959 Aug 05 04:28:58 PM PDT 24 Aug 05 04:28:59 PM PDT 24 201129573 ps
T103 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.3064644556 Aug 05 04:29:16 PM PDT 24 Aug 05 04:29:19 PM PDT 24 155144269 ps
T1042 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.4222828896 Aug 05 04:29:39 PM PDT 24 Aug 05 04:29:40 PM PDT 24 34937802 ps
T104 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.2507822454 Aug 05 04:29:04 PM PDT 24 Aug 05 04:29:09 PM PDT 24 152070034 ps
T1043 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.422443841 Aug 05 04:29:06 PM PDT 24 Aug 05 04:29:07 PM PDT 24 44043244 ps
T85 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.4230035125 Aug 05 04:29:09 PM PDT 24 Aug 05 04:29:10 PM PDT 24 22856993 ps
T126 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.611712526 Aug 05 04:29:00 PM PDT 24 Aug 05 04:29:02 PM PDT 24 178513650 ps
T114 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.3877725421 Aug 05 04:29:23 PM PDT 24 Aug 05 04:29:27 PM PDT 24 135273609 ps
T105 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.3561681573 Aug 05 04:29:03 PM PDT 24 Aug 05 04:29:08 PM PDT 24 282597318 ps
T1044 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3744280101 Aug 05 04:29:05 PM PDT 24 Aug 05 04:29:05 PM PDT 24 11942486 ps
T1045 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.1560238772 Aug 05 04:29:03 PM PDT 24 Aug 05 04:29:04 PM PDT 24 107023675 ps
T1046 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.4140962125 Aug 05 04:29:13 PM PDT 24 Aug 05 04:29:15 PM PDT 24 119221122 ps
T1047 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.4274994656 Aug 05 04:28:55 PM PDT 24 Aug 05 04:28:59 PM PDT 24 47891853 ps
T1048 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.241452331 Aug 05 04:28:51 PM PDT 24 Aug 05 04:28:53 PM PDT 24 141661680 ps
T106 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.4181563075 Aug 05 04:29:03 PM PDT 24 Aug 05 04:29:08 PM PDT 24 455135642 ps
T127 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.3705453129 Aug 05 04:28:43 PM PDT 24 Aug 05 04:28:57 PM PDT 24 608680448 ps
T1049 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.1924391995 Aug 05 04:29:05 PM PDT 24 Aug 05 04:29:08 PM PDT 24 461765362 ps
T1050 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.712075499 Aug 05 04:28:47 PM PDT 24 Aug 05 04:28:48 PM PDT 24 14009735 ps
T1051 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.2282588573 Aug 05 04:28:44 PM PDT 24 Aug 05 04:28:45 PM PDT 24 10189587 ps
T1052 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.2980341243 Aug 05 04:28:52 PM PDT 24 Aug 05 04:28:55 PM PDT 24 232630493 ps
T108 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.4090462327 Aug 05 04:29:01 PM PDT 24 Aug 05 04:29:06 PM PDT 24 201593511 ps
T1053 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.2446577638 Aug 05 04:29:01 PM PDT 24 Aug 05 04:29:04 PM PDT 24 164940165 ps
T189 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1882337353 Aug 05 04:29:02 PM PDT 24 Aug 05 04:29:16 PM PDT 24 2260466827 ps
T1054 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.2615096781 Aug 05 04:28:41 PM PDT 24 Aug 05 04:28:42 PM PDT 24 40161702 ps
T1055 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2423122310 Aug 05 04:29:13 PM PDT 24 Aug 05 04:29:17 PM PDT 24 60907418 ps
T128 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1761649304 Aug 05 04:29:03 PM PDT 24 Aug 05 04:29:05 PM PDT 24 368559655 ps
T1056 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.3442575569 Aug 05 04:29:14 PM PDT 24 Aug 05 04:29:32 PM PDT 24 298336846 ps
T1057 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2909554924 Aug 05 04:29:02 PM PDT 24 Aug 05 04:29:15 PM PDT 24 821293386 ps
T1058 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.4290099653 Aug 05 04:29:17 PM PDT 24 Aug 05 04:29:17 PM PDT 24 13923391 ps
T1059 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3695909744 Aug 05 04:28:56 PM PDT 24 Aug 05 04:28:59 PM PDT 24 99926425 ps
T1060 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.2328403744 Aug 05 04:29:05 PM PDT 24 Aug 05 04:29:06 PM PDT 24 15644943 ps
T1061 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.4223787303 Aug 05 04:28:45 PM PDT 24 Aug 05 04:28:54 PM PDT 24 722763730 ps
T1062 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.98889148 Aug 05 04:29:02 PM PDT 24 Aug 05 04:29:06 PM PDT 24 607633827 ps
T190 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2834475730 Aug 05 04:28:59 PM PDT 24 Aug 05 04:29:07 PM PDT 24 704445680 ps
T1063 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.3164368771 Aug 05 04:28:47 PM PDT 24 Aug 05 04:28:48 PM PDT 24 15919315 ps
T129 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3496987612 Aug 05 04:28:53 PM PDT 24 Aug 05 04:29:27 PM PDT 24 2090769119 ps
T1064 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.611339602 Aug 05 04:29:18 PM PDT 24 Aug 05 04:29:19 PM PDT 24 31984105 ps
T107 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1132827834 Aug 05 04:29:03 PM PDT 24 Aug 05 04:29:08 PM PDT 24 184376312 ps
T1065 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.903316133 Aug 05 04:29:34 PM PDT 24 Aug 05 04:29:35 PM PDT 24 31330771 ps
T1066 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.1297487364 Aug 05 04:29:05 PM PDT 24 Aug 05 04:29:05 PM PDT 24 15488308 ps
T1067 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3019598700 Aug 05 04:29:00 PM PDT 24 Aug 05 04:29:01 PM PDT 24 28110133 ps
T1068 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.2314518284 Aug 05 04:28:53 PM PDT 24 Aug 05 04:28:54 PM PDT 24 37204499 ps
T1069 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1807991630 Aug 05 04:29:02 PM PDT 24 Aug 05 04:29:05 PM PDT 24 139791739 ps
T111 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.2792954842 Aug 05 04:29:08 PM PDT 24 Aug 05 04:29:13 PM PDT 24 170321911 ps
T130 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.3111584606 Aug 05 04:29:07 PM PDT 24 Aug 05 04:29:09 PM PDT 24 106436552 ps
T1070 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3585281666 Aug 05 04:29:01 PM PDT 24 Aug 05 04:29:27 PM PDT 24 4470674269 ps
T1071 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.1257426595 Aug 05 04:29:18 PM PDT 24 Aug 05 04:29:21 PM PDT 24 664193886 ps
T1072 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.1119962679 Aug 05 04:29:14 PM PDT 24 Aug 05 04:29:17 PM PDT 24 175136507 ps
T115 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2031627492 Aug 05 04:29:00 PM PDT 24 Aug 05 04:29:05 PM PDT 24 162874081 ps
T1073 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.2195431197 Aug 05 04:29:45 PM PDT 24 Aug 05 04:30:19 PM PDT 24 949207498 ps
T1074 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.890906422 Aug 05 04:29:04 PM PDT 24 Aug 05 04:29:05 PM PDT 24 16279977 ps
T1075 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1020649696 Aug 05 04:29:05 PM PDT 24 Aug 05 04:29:07 PM PDT 24 40933037 ps
T1076 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.3585926238 Aug 05 04:29:05 PM PDT 24 Aug 05 04:29:06 PM PDT 24 11699904 ps
T131 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.3011983095 Aug 05 04:29:10 PM PDT 24 Aug 05 04:29:12 PM PDT 24 118432782 ps
T1077 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.36930241 Aug 05 04:29:14 PM PDT 24 Aug 05 04:29:18 PM PDT 24 262352852 ps
T1078 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3429648085 Aug 05 04:29:16 PM PDT 24 Aug 05 04:29:17 PM PDT 24 12632950 ps
T1079 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.111710867 Aug 05 04:29:19 PM PDT 24 Aug 05 04:29:25 PM PDT 24 12140704 ps
T1080 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3100232309 Aug 05 04:29:03 PM PDT 24 Aug 05 04:29:07 PM PDT 24 248172893 ps
T1081 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.1218344184 Aug 05 04:29:11 PM PDT 24 Aug 05 04:29:12 PM PDT 24 15106256 ps
T1082 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.1566457545 Aug 05 04:29:00 PM PDT 24 Aug 05 04:29:01 PM PDT 24 46903203 ps
T1083 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.2101265075 Aug 05 04:28:57 PM PDT 24 Aug 05 04:28:59 PM PDT 24 197298079 ps
T1084 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.3753597998 Aug 05 04:29:12 PM PDT 24 Aug 05 04:29:26 PM PDT 24 1837678250 ps
T1085 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.311183739 Aug 05 04:29:04 PM PDT 24 Aug 05 04:29:07 PM PDT 24 107954937 ps
T187 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.2258202423 Aug 05 04:29:17 PM PDT 24 Aug 05 04:29:20 PM PDT 24 51400853 ps
T1086 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.1097853066 Aug 05 04:28:59 PM PDT 24 Aug 05 04:29:07 PM PDT 24 111753961 ps
T1087 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.2089023638 Aug 05 04:29:28 PM PDT 24 Aug 05 04:29:30 PM PDT 24 26430974 ps
T1088 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2920796063 Aug 05 04:29:04 PM PDT 24 Aug 05 04:29:07 PM PDT 24 200676640 ps
T1089 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.426760596 Aug 05 04:29:03 PM PDT 24 Aug 05 04:29:07 PM PDT 24 2608131397 ps
T1090 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.2552583686 Aug 05 04:28:53 PM PDT 24 Aug 05 04:28:57 PM PDT 24 290087411 ps
T1091 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3139162685 Aug 05 04:29:03 PM PDT 24 Aug 05 04:29:06 PM PDT 24 184769759 ps
T1092 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.4276312438 Aug 05 04:29:06 PM PDT 24 Aug 05 04:29:07 PM PDT 24 93783499 ps
T1093 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.3729415123 Aug 05 04:28:57 PM PDT 24 Aug 05 04:28:57 PM PDT 24 11414426 ps
T1094 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2216580256 Aug 05 04:29:07 PM PDT 24 Aug 05 04:29:10 PM PDT 24 539397520 ps
T1095 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.1848879423 Aug 05 04:29:12 PM PDT 24 Aug 05 04:29:13 PM PDT 24 46780416 ps
T1096 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2237114232 Aug 05 04:29:01 PM PDT 24 Aug 05 04:29:03 PM PDT 24 73790370 ps
T1097 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.2648971519 Aug 05 04:29:13 PM PDT 24 Aug 05 04:29:14 PM PDT 24 78397313 ps
T1098 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3701245423 Aug 05 04:29:04 PM PDT 24 Aug 05 04:29:32 PM PDT 24 1120215624 ps
T1099 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.2173812229 Aug 05 04:28:59 PM PDT 24 Aug 05 04:29:00 PM PDT 24 29974642 ps
T1100 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.4216186216 Aug 05 04:29:10 PM PDT 24 Aug 05 04:29:12 PM PDT 24 1349421370 ps
T1101 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.1950314920 Aug 05 04:28:53 PM PDT 24 Aug 05 04:28:56 PM PDT 24 96103959 ps
T1102 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.486544370 Aug 05 04:29:02 PM PDT 24 Aug 05 04:29:05 PM PDT 24 176819685 ps
T1103 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.4168773035 Aug 05 04:29:04 PM PDT 24 Aug 05 04:29:19 PM PDT 24 3271193096 ps
T1104 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.1035207024 Aug 05 04:29:07 PM PDT 24 Aug 05 04:29:09 PM PDT 24 293859205 ps
T1105 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.2884743074 Aug 05 04:29:18 PM PDT 24 Aug 05 04:29:19 PM PDT 24 43075365 ps
T1106 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.4159926121 Aug 05 04:29:12 PM PDT 24 Aug 05 04:29:12 PM PDT 24 36745093 ps
T1107 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.1928197771 Aug 05 04:28:48 PM PDT 24 Aug 05 04:28:49 PM PDT 24 29852783 ps
T1108 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.2929243735 Aug 05 04:29:04 PM PDT 24 Aug 05 04:29:04 PM PDT 24 15035036 ps
T1109 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.3788136358 Aug 05 04:28:51 PM PDT 24 Aug 05 04:28:52 PM PDT 24 22678499 ps
T1110 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1237038905 Aug 05 04:29:06 PM PDT 24 Aug 05 04:29:07 PM PDT 24 29518575 ps
T1111 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2142845390 Aug 05 04:28:53 PM PDT 24 Aug 05 04:28:55 PM PDT 24 65571530 ps
T1112 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.987994197 Aug 05 04:29:20 PM PDT 24 Aug 05 04:29:21 PM PDT 24 36893704 ps
T1113 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.4235026520 Aug 05 04:29:29 PM PDT 24 Aug 05 04:29:31 PM PDT 24 105873059 ps
T1114 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3642372863 Aug 05 04:28:48 PM PDT 24 Aug 05 04:28:52 PM PDT 24 354023956 ps
T1115 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.3124396659 Aug 05 04:29:03 PM PDT 24 Aug 05 04:29:04 PM PDT 24 13640805 ps
T86 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3564812324 Aug 05 04:28:50 PM PDT 24 Aug 05 04:28:51 PM PDT 24 15569484 ps
T1116 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.3124518958 Aug 05 04:29:12 PM PDT 24 Aug 05 04:29:12 PM PDT 24 44075050 ps
T1117 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.2462940464 Aug 05 04:28:43 PM PDT 24 Aug 05 04:28:58 PM PDT 24 557462324 ps
T1118 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.1581649018 Aug 05 04:28:48 PM PDT 24 Aug 05 04:28:50 PM PDT 24 117410635 ps
T1119 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.2814830868 Aug 05 04:29:03 PM PDT 24 Aug 05 04:29:10 PM PDT 24 602193828 ps
T1120 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.1771118870 Aug 05 04:29:07 PM PDT 24 Aug 05 04:29:10 PM PDT 24 42661626 ps
T1121 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.2760697242 Aug 05 04:28:52 PM PDT 24 Aug 05 04:28:56 PM PDT 24 54254286 ps
T1122 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.994351065 Aug 05 04:28:57 PM PDT 24 Aug 05 04:29:02 PM PDT 24 598133570 ps
T1123 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.141644129 Aug 05 04:29:03 PM PDT 24 Aug 05 04:29:05 PM PDT 24 47720953 ps
T1124 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.383805876 Aug 05 04:29:02 PM PDT 24 Aug 05 04:29:05 PM PDT 24 106639333 ps
T1125 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.2497044626 Aug 05 04:29:40 PM PDT 24 Aug 05 04:29:41 PM PDT 24 61448600 ps
T1126 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.3306268864 Aug 05 04:28:52 PM PDT 24 Aug 05 04:28:53 PM PDT 24 26687575 ps
T1127 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.3110246044 Aug 05 04:29:18 PM PDT 24 Aug 05 04:29:19 PM PDT 24 50937599 ps
T1128 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.129401787 Aug 05 04:29:03 PM PDT 24 Aug 05 04:29:06 PM PDT 24 87673365 ps
T1129 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.4184969333 Aug 05 04:29:07 PM PDT 24 Aug 05 04:29:08 PM PDT 24 19181126 ps
T1130 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3873318080 Aug 05 04:28:46 PM PDT 24 Aug 05 04:28:48 PM PDT 24 26571190 ps
T1131 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.3686009479 Aug 05 04:28:57 PM PDT 24 Aug 05 04:28:59 PM PDT 24 91887740 ps
T1132 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.4281578325 Aug 05 04:29:12 PM PDT 24 Aug 05 04:29:13 PM PDT 24 69482012 ps
T191 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.1484720621 Aug 05 04:29:08 PM PDT 24 Aug 05 04:29:15 PM PDT 24 456458917 ps
T1133 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3694695944 Aug 05 04:28:49 PM PDT 24 Aug 05 04:28:52 PM PDT 24 137882210 ps
T1134 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.2965689886 Aug 05 04:29:12 PM PDT 24 Aug 05 04:29:15 PM PDT 24 417120113 ps
T1135 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.1576559613 Aug 05 04:29:03 PM PDT 24 Aug 05 04:29:05 PM PDT 24 527794686 ps
T1136 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.232867058 Aug 05 04:28:57 PM PDT 24 Aug 05 04:29:10 PM PDT 24 199575856 ps
T1137 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.573378613 Aug 05 04:28:52 PM PDT 24 Aug 05 04:28:54 PM PDT 24 252858286 ps
T1138 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.3582150932 Aug 05 04:29:03 PM PDT 24 Aug 05 04:29:04 PM PDT 24 44104970 ps
T1139 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3590567746 Aug 05 04:28:47 PM PDT 24 Aug 05 04:28:49 PM PDT 24 28596773 ps
T1140 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.4029491082 Aug 05 04:29:03 PM PDT 24 Aug 05 04:29:06 PM PDT 24 374453467 ps
T1141 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.3454610458 Aug 05 04:29:02 PM PDT 24 Aug 05 04:29:03 PM PDT 24 17778733 ps
T1142 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2174085918 Aug 05 04:28:39 PM PDT 24 Aug 05 04:28:40 PM PDT 24 32867004 ps
T1143 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.491682258 Aug 05 04:29:18 PM PDT 24 Aug 05 04:29:24 PM PDT 24 25043240 ps
T109 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.771483233 Aug 05 04:29:04 PM PDT 24 Aug 05 04:29:12 PM PDT 24 367969767 ps
T1144 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.112813726 Aug 05 04:29:12 PM PDT 24 Aug 05 04:29:13 PM PDT 24 15813140 ps
T1145 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.1024378440 Aug 05 04:29:15 PM PDT 24 Aug 05 04:29:15 PM PDT 24 56825313 ps
T1146 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1920094592 Aug 05 04:29:03 PM PDT 24 Aug 05 04:29:17 PM PDT 24 551179549 ps
T1147 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.4197254134 Aug 05 04:29:22 PM PDT 24 Aug 05 04:29:23 PM PDT 24 82243294 ps
T1148 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.3502370472 Aug 05 04:29:10 PM PDT 24 Aug 05 04:29:12 PM PDT 24 374859840 ps
T1149 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.2698909991 Aug 05 04:29:03 PM PDT 24 Aug 05 04:29:08 PM PDT 24 805877219 ps
T1150 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2791571682 Aug 05 04:28:57 PM PDT 24 Aug 05 04:28:57 PM PDT 24 74251102 ps
T1151 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.1290592097 Aug 05 04:28:58 PM PDT 24 Aug 05 04:29:00 PM PDT 24 261400901 ps

Test location /workspace/coverage/default/20.spi_device_flash_all.1571832929
Short name T9
Test name
Test status
Simulation time 1528080805 ps
CPU time 19.53 seconds
Started Aug 05 04:50:37 PM PDT 24
Finished Aug 05 04:50:57 PM PDT 24
Peak memory 241636 kb
Host smart-be1a9237-f808-41e1-847e-daa524fe5fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571832929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.1571832929
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.3786131964
Short name T17
Test name
Test status
Simulation time 287807348925 ps
CPU time 710.82 seconds
Started Aug 05 04:50:08 PM PDT 24
Finished Aug 05 05:01:59 PM PDT 24
Peak memory 273092 kb
Host smart-89ec688f-ed69-4ad4-aaf4-c9384ed3ecb0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786131964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.3786131964
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.3257033631
Short name T21
Test name
Test status
Simulation time 54001437471 ps
CPU time 514.65 seconds
Started Aug 05 04:50:02 PM PDT 24
Finished Aug 05 04:58:37 PM PDT 24
Peak memory 266228 kb
Host smart-36637b15-68ed-449e-9eac-2f82216c675d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257033631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.3257033631
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3382596628
Short name T99
Test name
Test status
Simulation time 675801305 ps
CPU time 14.14 seconds
Started Aug 05 04:29:01 PM PDT 24
Finished Aug 05 04:29:16 PM PDT 24
Peak memory 215468 kb
Host smart-b2325fbf-8830-4684-a506-0d0da9958044
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382596628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.3382596628
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.1016522596
Short name T13
Test name
Test status
Simulation time 35525241661 ps
CPU time 334.98 seconds
Started Aug 05 04:51:01 PM PDT 24
Finished Aug 05 04:56:37 PM PDT 24
Peak memory 255692 kb
Host smart-b7fe5757-3b9d-44f3-9730-ba96096ed0ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016522596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.1016522596
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.2144060478
Short name T18
Test name
Test status
Simulation time 11421834806 ps
CPU time 212.31 seconds
Started Aug 05 04:49:45 PM PDT 24
Finished Aug 05 04:53:18 PM PDT 24
Peak memory 282620 kb
Host smart-a2843ed1-da99-46dc-a60a-acf995d05fcf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144060478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.2144060478
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.1857053600
Short name T68
Test name
Test status
Simulation time 17055329 ps
CPU time 0.76 seconds
Started Aug 05 04:49:37 PM PDT 24
Finished Aug 05 04:49:38 PM PDT 24
Peak memory 216552 kb
Host smart-9d2f9a1f-fcbd-4007-a176-f836e704907b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857053600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.1857053600
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.930365787
Short name T285
Test name
Test status
Simulation time 348497727974 ps
CPU time 618.09 seconds
Started Aug 05 04:49:57 PM PDT 24
Finished Aug 05 05:00:15 PM PDT 24
Peak memory 260224 kb
Host smart-1774abb7-8b99-49db-b23d-07d543b60f65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930365787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stress
_all.930365787
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.2223457070
Short name T201
Test name
Test status
Simulation time 64485498397 ps
CPU time 683.31 seconds
Started Aug 05 04:50:55 PM PDT 24
Finished Aug 05 05:02:18 PM PDT 24
Peak memory 282644 kb
Host smart-635587ca-7340-4535-bcab-2d17306058a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223457070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.2223457070
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.3784233083
Short name T170
Test name
Test status
Simulation time 197497334591 ps
CPU time 473.17 seconds
Started Aug 05 04:50:00 PM PDT 24
Finished Aug 05 04:57:54 PM PDT 24
Peak memory 271000 kb
Host smart-f660835c-aea3-4492-874d-654620ef3d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784233083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.3784233083
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.766882180
Short name T45
Test name
Test status
Simulation time 1843195175 ps
CPU time 22.74 seconds
Started Aug 05 04:49:51 PM PDT 24
Finished Aug 05 04:50:14 PM PDT 24
Peak memory 250864 kb
Host smart-edd64c43-2e0d-4f6e-87fd-a86909f00f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766882180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.766882180
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.4090096166
Short name T178
Test name
Test status
Simulation time 30262642848 ps
CPU time 263.07 seconds
Started Aug 05 04:49:48 PM PDT 24
Finished Aug 05 04:54:11 PM PDT 24
Peak memory 270196 kb
Host smart-1f292b52-c0b5-453b-a03b-c7e81af28ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090096166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds
.4090096166
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.2574368635
Short name T386
Test name
Test status
Simulation time 16441134 ps
CPU time 0.72 seconds
Started Aug 05 04:49:59 PM PDT 24
Finished Aug 05 04:49:59 PM PDT 24
Peak memory 205896 kb
Host smart-2a648d2d-cabd-4a4b-99fd-f9d5d167136a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574368635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
2574368635
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.2507822454
Short name T104
Test name
Test status
Simulation time 152070034 ps
CPU time 5.02 seconds
Started Aug 05 04:29:04 PM PDT 24
Finished Aug 05 04:29:09 PM PDT 24
Peak memory 215804 kb
Host smart-d3b7d5f0-b6b4-4db3-8880-d197eb375bd5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507822454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
2507822454
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.1996886248
Short name T138
Test name
Test status
Simulation time 5582534671 ps
CPU time 135.61 seconds
Started Aug 05 04:50:23 PM PDT 24
Finished Aug 05 04:52:38 PM PDT 24
Peak memory 269232 kb
Host smart-9478a3fc-3e2a-4ab9-bb33-e598f372ba8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996886248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.1996886248
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.2832432838
Short name T125
Test name
Test status
Simulation time 530151191 ps
CPU time 14.44 seconds
Started Aug 05 04:28:52 PM PDT 24
Finished Aug 05 04:29:07 PM PDT 24
Peak memory 215364 kb
Host smart-38882b93-b727-4329-9e76-708a51b5176e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832432838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.2832432838
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.3162862600
Short name T307
Test name
Test status
Simulation time 330469498934 ps
CPU time 477.11 seconds
Started Aug 05 04:51:30 PM PDT 24
Finished Aug 05 04:59:27 PM PDT 24
Peak memory 273764 kb
Host smart-62e3c468-3bd0-4218-8e70-0686e743d40d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162862600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.3162862600
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.1276686359
Short name T31
Test name
Test status
Simulation time 60092870215 ps
CPU time 239.93 seconds
Started Aug 05 04:51:17 PM PDT 24
Finished Aug 05 04:55:17 PM PDT 24
Peak memory 266144 kb
Host smart-24faf7c3-0b66-4cb4-9c3b-5c1efdd2167d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276686359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.1276686359
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.329483483
Short name T145
Test name
Test status
Simulation time 5326581392 ps
CPU time 107.25 seconds
Started Aug 05 04:51:27 PM PDT 24
Finished Aug 05 04:53:15 PM PDT 24
Peak memory 253032 kb
Host smart-a15f161a-93fd-475b-9da0-7f1f878d5d2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329483483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idle
.329483483
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.264768276
Short name T41
Test name
Test status
Simulation time 35298935 ps
CPU time 1.08 seconds
Started Aug 05 04:49:48 PM PDT 24
Finished Aug 05 04:49:49 PM PDT 24
Peak memory 217132 kb
Host smart-3d5ec908-6e35-40f9-89e7-ec3c278e06c0
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264768276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.spi_device_mem_parity.264768276
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.2274162631
Short name T38
Test name
Test status
Simulation time 80595927251 ps
CPU time 794.67 seconds
Started Aug 05 04:49:58 PM PDT 24
Finished Aug 05 05:03:13 PM PDT 24
Peak memory 266296 kb
Host smart-88be3dc3-5ead-471a-826d-87f5bc095897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274162631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.2274162631
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.175379882
Short name T91
Test name
Test status
Simulation time 33367024957 ps
CPU time 244.61 seconds
Started Aug 05 04:51:36 PM PDT 24
Finished Aug 05 04:55:41 PM PDT 24
Peak memory 255184 kb
Host smart-4ccb4f8a-97ef-4ba1-aa6e-fc60fb54ac43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175379882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmds
.175379882
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.3892462564
Short name T71
Test name
Test status
Simulation time 170147907 ps
CPU time 1.29 seconds
Started Aug 05 04:49:27 PM PDT 24
Finished Aug 05 04:49:28 PM PDT 24
Peak memory 237536 kb
Host smart-4cd69a6b-65ab-43c7-8c26-43008f9d5149
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892462564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.3892462564
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.2556466566
Short name T101
Test name
Test status
Simulation time 820576240 ps
CPU time 19.56 seconds
Started Aug 05 04:29:15 PM PDT 24
Finished Aug 05 04:29:35 PM PDT 24
Peak memory 215380 kb
Host smart-1f72e50f-953e-46d9-acfa-4bfe75ed1178
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556466566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.2556466566
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.4155377245
Short name T306
Test name
Test status
Simulation time 570145345578 ps
CPU time 928.14 seconds
Started Aug 05 04:50:30 PM PDT 24
Finished Aug 05 05:05:59 PM PDT 24
Peak memory 278480 kb
Host smart-0907b36b-4981-4810-81b4-2226d189ef61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155377245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.4155377245
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.693397561
Short name T970
Test name
Test status
Simulation time 207006193033 ps
CPU time 517.19 seconds
Started Aug 05 04:49:36 PM PDT 24
Finished Aug 05 04:58:14 PM PDT 24
Peak memory 289916 kb
Host smart-d402dbd3-5615-45e3-a029-0d7344f16954
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693397561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stress
_all.693397561
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.2369850077
Short name T242
Test name
Test status
Simulation time 98522309492 ps
CPU time 243.71 seconds
Started Aug 05 04:50:23 PM PDT 24
Finished Aug 05 04:54:32 PM PDT 24
Peak memory 267928 kb
Host smart-45eec835-5889-4946-9ef8-ca87f3c2bad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369850077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.2369850077
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.3714743175
Short name T53
Test name
Test status
Simulation time 297602065597 ps
CPU time 757.15 seconds
Started Aug 05 04:49:53 PM PDT 24
Finished Aug 05 05:02:30 PM PDT 24
Peak memory 287292 kb
Host smart-5f98677f-cefa-484d-9011-c423da15874f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714743175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.3714743175
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.1428522268
Short name T221
Test name
Test status
Simulation time 2757087208 ps
CPU time 69.4 seconds
Started Aug 05 04:49:23 PM PDT 24
Finished Aug 05 04:50:32 PM PDT 24
Peak memory 252088 kb
Host smart-2c7cc550-1a8f-435d-80cd-3a43849548ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428522268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.1428522268
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.3985194571
Short name T179
Test name
Test status
Simulation time 75816961871 ps
CPU time 190.37 seconds
Started Aug 05 04:49:42 PM PDT 24
Finished Aug 05 04:52:53 PM PDT 24
Peak memory 252456 kb
Host smart-2959647b-63a3-4694-a6e0-b8f6fdc83088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985194571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.3985194571
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.4043862848
Short name T283
Test name
Test status
Simulation time 105986733925 ps
CPU time 365.65 seconds
Started Aug 05 04:50:59 PM PDT 24
Finished Aug 05 04:57:05 PM PDT 24
Peak memory 266444 kb
Host smart-a3992912-1bb7-4d63-8990-4ec564a1cd2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043862848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.4043862848
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.4109989917
Short name T92
Test name
Test status
Simulation time 225149702220 ps
CPU time 375.66 seconds
Started Aug 05 04:51:19 PM PDT 24
Finished Aug 05 04:57:35 PM PDT 24
Peak memory 261296 kb
Host smart-11a7bc26-e710-4c20-9616-59df8d17c2c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109989917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmd
s.4109989917
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1132827834
Short name T107
Test name
Test status
Simulation time 184376312 ps
CPU time 4.8 seconds
Started Aug 05 04:29:03 PM PDT 24
Finished Aug 05 04:29:08 PM PDT 24
Peak memory 215816 kb
Host smart-1474f80e-a90b-4de3-b708-e67817df2d02
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132827834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
1132827834
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.2956044962
Short name T32
Test name
Test status
Simulation time 37882655568 ps
CPU time 150.68 seconds
Started Aug 05 04:50:22 PM PDT 24
Finished Aug 05 04:52:53 PM PDT 24
Peak memory 264460 kb
Host smart-12dd3d68-379f-46ff-a12c-08478122934c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956044962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.2956044962
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.217864291
Short name T315
Test name
Test status
Simulation time 574549988 ps
CPU time 8.96 seconds
Started Aug 05 04:50:55 PM PDT 24
Finished Aug 05 04:51:04 PM PDT 24
Peak memory 241328 kb
Host smart-9be31a39-d80e-4b10-8e86-aefb4e79363c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217864291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.217864291
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.4011652290
Short name T214
Test name
Test status
Simulation time 2442851348 ps
CPU time 58.24 seconds
Started Aug 05 04:50:38 PM PDT 24
Finished Aug 05 04:51:41 PM PDT 24
Peak memory 253132 kb
Host smart-8abbb98b-16fe-4a17-a763-865edd0df18a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011652290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmd
s.4011652290
Directory /workspace/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.4188946135
Short name T292
Test name
Test status
Simulation time 40877382167 ps
CPU time 264 seconds
Started Aug 05 04:51:13 PM PDT 24
Finished Aug 05 04:55:37 PM PDT 24
Peak memory 268608 kb
Host smart-4592003e-97df-4c3d-8e41-f196cbc1688a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188946135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.4188946135
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.4223787303
Short name T1061
Test name
Test status
Simulation time 722763730 ps
CPU time 8.45 seconds
Started Aug 05 04:28:45 PM PDT 24
Finished Aug 05 04:28:54 PM PDT 24
Peak memory 215436 kb
Host smart-38974ce8-8b7f-4620-bce1-f355786fed72
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223787303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.4223787303
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.4165773122
Short name T98
Test name
Test status
Simulation time 204238689 ps
CPU time 11.83 seconds
Started Aug 05 04:28:51 PM PDT 24
Finished Aug 05 04:29:03 PM PDT 24
Peak memory 215368 kb
Host smart-e9fdfa9b-3827-482c-81df-fb2d89d35eac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165773122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.4165773122
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.1363804986
Short name T951
Test name
Test status
Simulation time 186517378748 ps
CPU time 319.24 seconds
Started Aug 05 04:49:37 PM PDT 24
Finished Aug 05 04:55:01 PM PDT 24
Peak memory 254836 kb
Host smart-9b06904d-b586-4e48-acbb-d77e57a86ba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363804986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds
.1363804986
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.895790450
Short name T29
Test name
Test status
Simulation time 4415597724 ps
CPU time 15.04 seconds
Started Aug 05 04:50:01 PM PDT 24
Finished Aug 05 04:50:17 PM PDT 24
Peak memory 217368 kb
Host smart-35c9cd77-b412-4568-8392-a16a213f41c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895790450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.895790450
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.323958849
Short name T298
Test name
Test status
Simulation time 24827888655 ps
CPU time 46.15 seconds
Started Aug 05 04:50:06 PM PDT 24
Finished Aug 05 04:50:52 PM PDT 24
Peak memory 241652 kb
Host smart-f48c48d6-86e9-4833-a5df-8488fec2f60c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323958849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.323958849
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.703736548
Short name T37
Test name
Test status
Simulation time 797903098 ps
CPU time 6.12 seconds
Started Aug 05 04:50:02 PM PDT 24
Finished Aug 05 04:50:08 PM PDT 24
Peak memory 216804 kb
Host smart-91ff64fc-8910-42a8-bf37-bdee80e12dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703736548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.703736548
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.2500347704
Short name T268
Test name
Test status
Simulation time 41749540609 ps
CPU time 383.32 seconds
Started Aug 05 04:50:34 PM PDT 24
Finished Aug 05 04:56:57 PM PDT 24
Peak memory 282688 kb
Host smart-fa2d177d-42b7-43a4-a9d4-4823a66f6609
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500347704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.2500347704
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.4230280421
Short name T840
Test name
Test status
Simulation time 21040064436 ps
CPU time 182.65 seconds
Started Aug 05 04:49:44 PM PDT 24
Finished Aug 05 04:52:47 PM PDT 24
Peak memory 249828 kb
Host smart-3f532683-9f96-44e9-b622-90dca0ef6cfc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230280421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.4230280421
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.383137612
Short name T317
Test name
Test status
Simulation time 858205518 ps
CPU time 22.21 seconds
Started Aug 05 04:50:37 PM PDT 24
Finished Aug 05 04:50:59 PM PDT 24
Peak memory 233388 kb
Host smart-f5ad2dad-32b1-4f55-b5a8-43e4e5a75df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383137612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.383137612
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.2193987710
Short name T764
Test name
Test status
Simulation time 2802421900 ps
CPU time 13.69 seconds
Started Aug 05 04:50:35 PM PDT 24
Finished Aug 05 04:50:52 PM PDT 24
Peak memory 249788 kb
Host smart-62cf28df-0a59-4e56-b04d-0208d4c8de8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193987710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.2193987710
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.3408209641
Short name T36
Test name
Test status
Simulation time 3003583611 ps
CPU time 11.94 seconds
Started Aug 05 04:49:42 PM PDT 24
Finished Aug 05 04:49:54 PM PDT 24
Peak memory 233412 kb
Host smart-3dda31ce-a0c7-4637-be41-b329b0c84dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408209641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.3408209641
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_upload.2588641281
Short name T87
Test name
Test status
Simulation time 2843108243 ps
CPU time 5.66 seconds
Started Aug 05 04:50:26 PM PDT 24
Finished Aug 05 04:50:32 PM PDT 24
Peak memory 218764 kb
Host smart-62258a21-a139-4d3d-a0da-148f636ba006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588641281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.2588641281
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.3561681573
Short name T105
Test name
Test status
Simulation time 282597318 ps
CPU time 4.42 seconds
Started Aug 05 04:29:03 PM PDT 24
Finished Aug 05 04:29:08 PM PDT 24
Peak memory 215612 kb
Host smart-11748be7-b77c-453c-8a1e-a86d50aaf437
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561681573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
3561681573
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.4230035125
Short name T85
Test name
Test status
Simulation time 22856993 ps
CPU time 0.95 seconds
Started Aug 05 04:29:09 PM PDT 24
Finished Aug 05 04:29:10 PM PDT 24
Peak memory 206976 kb
Host smart-8187ca56-b5bc-460d-bece-891cb27ba8ed
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230035125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.4230035125
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.771483233
Short name T109
Test name
Test status
Simulation time 367969767 ps
CPU time 7.88 seconds
Started Aug 05 04:29:04 PM PDT 24
Finished Aug 05 04:29:12 PM PDT 24
Peak memory 216008 kb
Host smart-d3e35002-3a51-413a-a85d-29bb56989af5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771483233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_
tl_intg_err.771483233
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.2195431197
Short name T1073
Test name
Test status
Simulation time 949207498 ps
CPU time 32.96 seconds
Started Aug 05 04:29:45 PM PDT 24
Finished Aug 05 04:30:19 PM PDT 24
Peak memory 215312 kb
Host smart-760a8cdb-1931-4650-a61c-86c83b127ab5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195431197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.2195431197
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2142845390
Short name T1111
Test name
Test status
Simulation time 65571530 ps
CPU time 0.99 seconds
Started Aug 05 04:28:53 PM PDT 24
Finished Aug 05 04:28:55 PM PDT 24
Peak memory 206964 kb
Host smart-99da3702-a47b-4441-b88f-6a5640b95693
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142845390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.2142845390
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2081782003
Short name T110
Test name
Test status
Simulation time 255433572 ps
CPU time 2.76 seconds
Started Aug 05 04:28:49 PM PDT 24
Finished Aug 05 04:28:52 PM PDT 24
Peak memory 217264 kb
Host smart-3cb3eb06-0daf-45fe-91ae-740185638e42
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081782003 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.2081782003
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.573378613
Short name T1137
Test name
Test status
Simulation time 252858286 ps
CPU time 2 seconds
Started Aug 05 04:28:52 PM PDT 24
Finished Aug 05 04:28:54 PM PDT 24
Peak memory 215444 kb
Host smart-4b90b1ac-2835-4e8b-bbe0-440d8db93120
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573378613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.573378613
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.3164368771
Short name T1063
Test name
Test status
Simulation time 15919315 ps
CPU time 0.83 seconds
Started Aug 05 04:28:47 PM PDT 24
Finished Aug 05 04:28:48 PM PDT 24
Peak memory 203852 kb
Host smart-1df44e44-4797-4f5f-9bbc-b10335bc40c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164368771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.3
164368771
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.1928197771
Short name T1107
Test name
Test status
Simulation time 29852783 ps
CPU time 1.12 seconds
Started Aug 05 04:28:48 PM PDT 24
Finished Aug 05 04:28:49 PM PDT 24
Peak memory 215360 kb
Host smart-8c9a69eb-183a-4bd4-b73a-1cc5cc6ca71f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928197771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.1928197771
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.3788136358
Short name T1109
Test name
Test status
Simulation time 22678499 ps
CPU time 0.67 seconds
Started Aug 05 04:28:51 PM PDT 24
Finished Aug 05 04:28:52 PM PDT 24
Peak memory 203788 kb
Host smart-1874b488-1ba6-4ca2-bfd8-0fe5da82c9f3
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788136358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.3788136358
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3694695944
Short name T1133
Test name
Test status
Simulation time 137882210 ps
CPU time 2.5 seconds
Started Aug 05 04:28:49 PM PDT 24
Finished Aug 05 04:28:52 PM PDT 24
Peak memory 215444 kb
Host smart-95ce0e0c-6f81-4a17-80a9-a2e1332b6936
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694695944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.3694695944
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.2698909991
Short name T1149
Test name
Test status
Simulation time 805877219 ps
CPU time 4.63 seconds
Started Aug 05 04:29:03 PM PDT 24
Finished Aug 05 04:29:08 PM PDT 24
Peak memory 215604 kb
Host smart-7ff1dd34-0111-4dae-a5ab-b38f6af1a1f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698909991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.2
698909991
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.3705453129
Short name T127
Test name
Test status
Simulation time 608680448 ps
CPU time 14.36 seconds
Started Aug 05 04:28:43 PM PDT 24
Finished Aug 05 04:28:57 PM PDT 24
Peak memory 215348 kb
Host smart-7996f66b-6922-4b93-b6f6-361cd878a89d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705453129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.3705453129
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3496987612
Short name T129
Test name
Test status
Simulation time 2090769119 ps
CPU time 33.34 seconds
Started Aug 05 04:28:53 PM PDT 24
Finished Aug 05 04:29:27 PM PDT 24
Peak memory 207180 kb
Host smart-0bb8411d-8350-4313-923d-4e75828af9c3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496987612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.3496987612
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.196755348
Short name T83
Test name
Test status
Simulation time 56004690 ps
CPU time 1.13 seconds
Started Aug 05 04:29:02 PM PDT 24
Finished Aug 05 04:29:04 PM PDT 24
Peak memory 216416 kb
Host smart-f596a585-0258-4128-8f56-393ab33f01ee
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196755348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_hw_reset.196755348
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.1950314920
Short name T1101
Test name
Test status
Simulation time 96103959 ps
CPU time 2.77 seconds
Started Aug 05 04:28:53 PM PDT 24
Finished Aug 05 04:28:56 PM PDT 24
Peak memory 216772 kb
Host smart-15404b65-64f5-4d7b-9593-036b601252e6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950314920 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.1950314920
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3873318080
Short name T1130
Test name
Test status
Simulation time 26571190 ps
CPU time 1.66 seconds
Started Aug 05 04:28:46 PM PDT 24
Finished Aug 05 04:28:48 PM PDT 24
Peak memory 207064 kb
Host smart-8deff672-af3b-4880-ac1b-2036463db07f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873318080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.3
873318080
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.1548065630
Short name T1038
Test name
Test status
Simulation time 12366610 ps
CPU time 0.8 seconds
Started Aug 05 04:28:49 PM PDT 24
Finished Aug 05 04:28:50 PM PDT 24
Peak memory 204232 kb
Host smart-38a3c73d-c3f3-4d41-ab1d-ad91c9c729ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548065630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.1
548065630
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2174085918
Short name T1142
Test name
Test status
Simulation time 32867004 ps
CPU time 1.44 seconds
Started Aug 05 04:28:39 PM PDT 24
Finished Aug 05 04:28:40 PM PDT 24
Peak memory 215420 kb
Host smart-e7c75c65-775d-4ed1-b968-b092739280fd
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174085918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.2174085918
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.2282588573
Short name T1051
Test name
Test status
Simulation time 10189587 ps
CPU time 0.69 seconds
Started Aug 05 04:28:44 PM PDT 24
Finished Aug 05 04:28:45 PM PDT 24
Peak memory 204112 kb
Host smart-b9e294fa-dbcb-4d40-8c54-7d346ca501bd
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282588573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.2282588573
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3590567746
Short name T1139
Test name
Test status
Simulation time 28596773 ps
CPU time 1.91 seconds
Started Aug 05 04:28:47 PM PDT 24
Finished Aug 05 04:28:49 PM PDT 24
Peak memory 207208 kb
Host smart-227f297b-1934-4bea-9ceb-6789bc06867d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590567746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.3590567746
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.2552583686
Short name T1090
Test name
Test status
Simulation time 290087411 ps
CPU time 4.02 seconds
Started Aug 05 04:28:53 PM PDT 24
Finished Aug 05 04:28:57 PM PDT 24
Peak memory 215820 kb
Host smart-a5d8364a-f3aa-46df-a8ac-bf5896930e43
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552583686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.2
552583686
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.2462940464
Short name T1117
Test name
Test status
Simulation time 557462324 ps
CPU time 14.44 seconds
Started Aug 05 04:28:43 PM PDT 24
Finished Aug 05 04:28:58 PM PDT 24
Peak memory 215836 kb
Host smart-9f5cc07c-5b9d-4c54-95e5-7ae044d7b830
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462940464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.2462940464
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.486544370
Short name T1102
Test name
Test status
Simulation time 176819685 ps
CPU time 2.92 seconds
Started Aug 05 04:29:02 PM PDT 24
Finished Aug 05 04:29:05 PM PDT 24
Peak memory 216904 kb
Host smart-0af8d595-3ffc-4d50-85ea-6344059f0b2e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486544370 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.486544370
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.611712526
Short name T126
Test name
Test status
Simulation time 178513650 ps
CPU time 2.67 seconds
Started Aug 05 04:29:00 PM PDT 24
Finished Aug 05 04:29:02 PM PDT 24
Peak memory 215456 kb
Host smart-588ed53f-1538-4aa9-a3fb-2f7841e3a797
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611712526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.611712526
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.3110246044
Short name T1127
Test name
Test status
Simulation time 50937599 ps
CPU time 0.76 seconds
Started Aug 05 04:29:18 PM PDT 24
Finished Aug 05 04:29:19 PM PDT 24
Peak memory 204204 kb
Host smart-b45ac8f3-173e-46b4-82c0-538ba1c13d50
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110246044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
3110246044
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1020649696
Short name T1075
Test name
Test status
Simulation time 40933037 ps
CPU time 2.5 seconds
Started Aug 05 04:29:05 PM PDT 24
Finished Aug 05 04:29:07 PM PDT 24
Peak memory 215416 kb
Host smart-5b115893-47f3-4178-b877-a8869910ea49
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020649696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.1020649696
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.4048631701
Short name T95
Test name
Test status
Simulation time 65442372 ps
CPU time 1.79 seconds
Started Aug 05 04:29:06 PM PDT 24
Finished Aug 05 04:29:08 PM PDT 24
Peak memory 215620 kb
Host smart-691f5e4e-0961-4262-b2f1-bd75480905bd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048631701 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.4048631701
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.365508946
Short name T121
Test name
Test status
Simulation time 112281510 ps
CPU time 1.82 seconds
Started Aug 05 04:29:22 PM PDT 24
Finished Aug 05 04:29:24 PM PDT 24
Peak memory 207484 kb
Host smart-7defc09f-0b4b-47f9-8f26-ea069527db25
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365508946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.365508946
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.1053231609
Short name T1031
Test name
Test status
Simulation time 18144578 ps
CPU time 0.74 seconds
Started Aug 05 04:29:07 PM PDT 24
Finished Aug 05 04:29:07 PM PDT 24
Peak memory 203924 kb
Host smart-b7527e4a-915d-4087-9671-2eed24a32a94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053231609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
1053231609
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3139162685
Short name T1091
Test name
Test status
Simulation time 184769759 ps
CPU time 2.8 seconds
Started Aug 05 04:29:03 PM PDT 24
Finished Aug 05 04:29:06 PM PDT 24
Peak memory 215416 kb
Host smart-99fc047a-7bb2-4a14-bae7-7561abe28f3c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139162685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.3139162685
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.4181563075
Short name T106
Test name
Test status
Simulation time 455135642 ps
CPU time 5.26 seconds
Started Aug 05 04:29:03 PM PDT 24
Finished Aug 05 04:29:08 PM PDT 24
Peak memory 215892 kb
Host smart-a82a1725-0239-4ca7-8d46-48c2e225955c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181563075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
4181563075
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.4168773035
Short name T1103
Test name
Test status
Simulation time 3271193096 ps
CPU time 14.32 seconds
Started Aug 05 04:29:04 PM PDT 24
Finished Aug 05 04:29:19 PM PDT 24
Peak memory 215804 kb
Host smart-1927ae69-0cd4-499c-b2c0-5e737f07dc8d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168773035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.4168773035
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3100232309
Short name T1080
Test name
Test status
Simulation time 248172893 ps
CPU time 3.86 seconds
Started Aug 05 04:29:03 PM PDT 24
Finished Aug 05 04:29:07 PM PDT 24
Peak memory 217008 kb
Host smart-a3ec009a-0521-4b00-80aa-2422ad4cb4db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100232309 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.3100232309
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.1771118870
Short name T1120
Test name
Test status
Simulation time 42661626 ps
CPU time 2.56 seconds
Started Aug 05 04:29:07 PM PDT 24
Finished Aug 05 04:29:10 PM PDT 24
Peak memory 207260 kb
Host smart-13af2f2d-f1ba-4b1a-ad73-8b2ca9d28997
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771118870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
1771118870
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.4184969333
Short name T1129
Test name
Test status
Simulation time 19181126 ps
CPU time 0.75 seconds
Started Aug 05 04:29:07 PM PDT 24
Finished Aug 05 04:29:08 PM PDT 24
Peak memory 203836 kb
Host smart-efc73fed-3b8f-407a-b847-6e6aee059557
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184969333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
4184969333
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3743941600
Short name T1037
Test name
Test status
Simulation time 58957546 ps
CPU time 3.33 seconds
Started Aug 05 04:29:15 PM PDT 24
Finished Aug 05 04:29:18 PM PDT 24
Peak memory 215384 kb
Host smart-9b2c2bc8-9da5-4175-818e-f7bf1abd6e14
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743941600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.3743941600
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.4029491082
Short name T1140
Test name
Test status
Simulation time 374453467 ps
CPU time 2.68 seconds
Started Aug 05 04:29:03 PM PDT 24
Finished Aug 05 04:29:06 PM PDT 24
Peak memory 215660 kb
Host smart-e5ef2076-5a25-4704-be09-3414f5306fc1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029491082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
4029491082
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.3753597998
Short name T1084
Test name
Test status
Simulation time 1837678250 ps
CPU time 14.61 seconds
Started Aug 05 04:29:12 PM PDT 24
Finished Aug 05 04:29:26 PM PDT 24
Peak memory 217900 kb
Host smart-e536218c-5d64-41a9-9fe6-07f7ab1d17ad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753597998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.3753597998
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2237114232
Short name T1096
Test name
Test status
Simulation time 73790370 ps
CPU time 2.54 seconds
Started Aug 05 04:29:01 PM PDT 24
Finished Aug 05 04:29:03 PM PDT 24
Peak memory 218308 kb
Host smart-d5b039b1-6715-45dc-9008-eb1b9d55a270
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237114232 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.2237114232
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.141644129
Short name T1123
Test name
Test status
Simulation time 47720953 ps
CPU time 1.75 seconds
Started Aug 05 04:29:03 PM PDT 24
Finished Aug 05 04:29:05 PM PDT 24
Peak memory 215428 kb
Host smart-9a0b6a23-6297-43bc-8425-9574671e5f05
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141644129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.141644129
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3744280101
Short name T1044
Test name
Test status
Simulation time 11942486 ps
CPU time 0.75 seconds
Started Aug 05 04:29:05 PM PDT 24
Finished Aug 05 04:29:05 PM PDT 24
Peak memory 203908 kb
Host smart-97a09d18-6f83-4ff8-a979-11ad83befdff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744280101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
3744280101
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.2446577638
Short name T1053
Test name
Test status
Simulation time 164940165 ps
CPU time 2.61 seconds
Started Aug 05 04:29:01 PM PDT 24
Finished Aug 05 04:29:04 PM PDT 24
Peak memory 215348 kb
Host smart-828336b9-839d-49ce-ae10-0705555281e8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446577638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.2446577638
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.2258202423
Short name T187
Test name
Test status
Simulation time 51400853 ps
CPU time 2.98 seconds
Started Aug 05 04:29:17 PM PDT 24
Finished Aug 05 04:29:20 PM PDT 24
Peak memory 215616 kb
Host smart-53c79743-d83b-4e39-8e6c-56d0c55e5c6f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258202423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
2258202423
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2978323190
Short name T113
Test name
Test status
Simulation time 430510289 ps
CPU time 2.88 seconds
Started Aug 05 04:29:01 PM PDT 24
Finished Aug 05 04:29:04 PM PDT 24
Peak memory 216480 kb
Host smart-aadf5f10-3503-4abd-bbca-a2f0e7c9ed2c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978323190 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.2978323190
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.3111584606
Short name T130
Test name
Test status
Simulation time 106436552 ps
CPU time 1.9 seconds
Started Aug 05 04:29:07 PM PDT 24
Finished Aug 05 04:29:09 PM PDT 24
Peak memory 215420 kb
Host smart-d8f22ee3-ebf2-4cc8-85a7-7038f35434e0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111584606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
3111584606
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.903316133
Short name T1065
Test name
Test status
Simulation time 31330771 ps
CPU time 0.76 seconds
Started Aug 05 04:29:34 PM PDT 24
Finished Aug 05 04:29:35 PM PDT 24
Peak memory 203876 kb
Host smart-556786d5-cc97-4990-9a0d-a6ff79221d53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903316133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.903316133
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.429560598
Short name T149
Test name
Test status
Simulation time 393925538 ps
CPU time 2.68 seconds
Started Aug 05 04:28:54 PM PDT 24
Finished Aug 05 04:28:57 PM PDT 24
Peak memory 215468 kb
Host smart-6e8c8707-36e9-450e-8b13-81d3a1f43a4f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429560598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.s
pi_device_same_csr_outstanding.429560598
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.3502370472
Short name T1148
Test name
Test status
Simulation time 374859840 ps
CPU time 1.76 seconds
Started Aug 05 04:29:10 PM PDT 24
Finished Aug 05 04:29:12 PM PDT 24
Peak memory 215688 kb
Host smart-fb1d387f-21f9-40ae-bf47-64ec995621c5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502370472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
3502370472
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.2889773761
Short name T188
Test name
Test status
Simulation time 798076336 ps
CPU time 12.81 seconds
Started Aug 05 04:29:01 PM PDT 24
Finished Aug 05 04:29:14 PM PDT 24
Peak memory 215460 kb
Host smart-b015adee-9b42-4fa2-be73-e9a117baafc9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889773761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.2889773761
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.36930241
Short name T1077
Test name
Test status
Simulation time 262352852 ps
CPU time 3.24 seconds
Started Aug 05 04:29:14 PM PDT 24
Finished Aug 05 04:29:18 PM PDT 24
Peak memory 217100 kb
Host smart-3f56b462-25f3-4098-a0fe-e3ad0a7064b0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36930241 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.36930241
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.1924391995
Short name T1049
Test name
Test status
Simulation time 461765362 ps
CPU time 2.75 seconds
Started Aug 05 04:29:05 PM PDT 24
Finished Aug 05 04:29:08 PM PDT 24
Peak memory 215444 kb
Host smart-21a6f458-2837-47c6-915f-8c9f21481b2d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924391995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
1924391995
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.2815437037
Short name T1030
Test name
Test status
Simulation time 19355659 ps
CPU time 0.71 seconds
Started Aug 05 04:29:15 PM PDT 24
Finished Aug 05 04:29:16 PM PDT 24
Peak memory 203860 kb
Host smart-f96d44d7-4e2c-4bbf-99b8-054eec708454
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815437037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
2815437037
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.3686009479
Short name T1131
Test name
Test status
Simulation time 91887740 ps
CPU time 1.65 seconds
Started Aug 05 04:28:57 PM PDT 24
Finished Aug 05 04:28:59 PM PDT 24
Peak memory 215420 kb
Host smart-da737341-9c3c-46e7-a028-17311d1b3f09
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686009479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.3686009479
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.3442575569
Short name T1056
Test name
Test status
Simulation time 298336846 ps
CPU time 17.3 seconds
Started Aug 05 04:29:14 PM PDT 24
Finished Aug 05 04:29:32 PM PDT 24
Peak memory 215440 kb
Host smart-f5084e0c-5cc2-4baa-8331-4d1806a3e648
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442575569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.3442575569
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3284210236
Short name T112
Test name
Test status
Simulation time 661538711 ps
CPU time 2.71 seconds
Started Aug 05 04:29:06 PM PDT 24
Finished Aug 05 04:29:09 PM PDT 24
Peak memory 217292 kb
Host smart-2e3e856a-8816-45d7-a7c2-f1cabfb54028
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284210236 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.3284210236
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.2965689886
Short name T1134
Test name
Test status
Simulation time 417120113 ps
CPU time 2.55 seconds
Started Aug 05 04:29:12 PM PDT 24
Finished Aug 05 04:29:15 PM PDT 24
Peak memory 215444 kb
Host smart-532a0165-a0c5-49a4-8069-6d54abf1e106
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965689886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
2965689886
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3019598700
Short name T1067
Test name
Test status
Simulation time 28110133 ps
CPU time 0.74 seconds
Started Aug 05 04:29:00 PM PDT 24
Finished Aug 05 04:29:01 PM PDT 24
Peak memory 203860 kb
Host smart-7822a265-33fa-4ee7-959a-0cc2e620d707
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019598700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
3019598700
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.4140962125
Short name T1046
Test name
Test status
Simulation time 119221122 ps
CPU time 1.92 seconds
Started Aug 05 04:29:13 PM PDT 24
Finished Aug 05 04:29:15 PM PDT 24
Peak memory 215364 kb
Host smart-686298c6-d295-4d48-88f6-9db036f7473c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140962125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.4140962125
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.426760596
Short name T1089
Test name
Test status
Simulation time 2608131397 ps
CPU time 3.72 seconds
Started Aug 05 04:29:03 PM PDT 24
Finished Aug 05 04:29:07 PM PDT 24
Peak memory 215820 kb
Host smart-d804799e-e59c-424b-b233-5a987b3dc470
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426760596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.426760596
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1920094592
Short name T1146
Test name
Test status
Simulation time 551179549 ps
CPU time 13.63 seconds
Started Aug 05 04:29:03 PM PDT 24
Finished Aug 05 04:29:17 PM PDT 24
Peak memory 223508 kb
Host smart-55ac0b5c-d9d8-4aed-9eb8-d8beaf12638c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920094592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.1920094592
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1807991630
Short name T1069
Test name
Test status
Simulation time 139791739 ps
CPU time 2.46 seconds
Started Aug 05 04:29:02 PM PDT 24
Finished Aug 05 04:29:05 PM PDT 24
Peak memory 216656 kb
Host smart-a3bdaa23-cf96-4dbd-a265-4e4ea090d81e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807991630 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.1807991630
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.4235026520
Short name T1113
Test name
Test status
Simulation time 105873059 ps
CPU time 1.78 seconds
Started Aug 05 04:29:29 PM PDT 24
Finished Aug 05 04:29:31 PM PDT 24
Peak memory 215400 kb
Host smart-04594f42-9121-44b6-b40d-2eafddf3574c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235026520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
4235026520
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.2497044626
Short name T1125
Test name
Test status
Simulation time 61448600 ps
CPU time 0.78 seconds
Started Aug 05 04:29:40 PM PDT 24
Finished Aug 05 04:29:41 PM PDT 24
Peak memory 203860 kb
Host smart-56de5800-24e0-447e-9fb1-abc099639fb4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497044626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
2497044626
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.311183739
Short name T1085
Test name
Test status
Simulation time 107954937 ps
CPU time 3.05 seconds
Started Aug 05 04:29:04 PM PDT 24
Finished Aug 05 04:29:07 PM PDT 24
Peak memory 215396 kb
Host smart-eff3f51c-23b8-4a1e-af47-6d8a6bcae9da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311183739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.s
pi_device_same_csr_outstanding.311183739
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.3064644556
Short name T103
Test name
Test status
Simulation time 155144269 ps
CPU time 3.38 seconds
Started Aug 05 04:29:16 PM PDT 24
Finished Aug 05 04:29:19 PM PDT 24
Peak memory 216660 kb
Host smart-e67dd827-a08a-49fb-a6a5-d0953cdc4dd8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064644556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
3064644556
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.2137941580
Short name T117
Test name
Test status
Simulation time 1083677266 ps
CPU time 14.37 seconds
Started Aug 05 04:29:23 PM PDT 24
Finished Aug 05 04:29:37 PM PDT 24
Peak memory 215424 kb
Host smart-7718e994-f222-45bc-841f-cff6f15df8c3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137941580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.2137941580
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.3877725421
Short name T114
Test name
Test status
Simulation time 135273609 ps
CPU time 3.62 seconds
Started Aug 05 04:29:23 PM PDT 24
Finished Aug 05 04:29:27 PM PDT 24
Peak memory 217608 kb
Host smart-367aa8d5-a7c3-4623-a90d-fdffaf55f4a1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877725421 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.3877725421
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.4281578325
Short name T1132
Test name
Test status
Simulation time 69482012 ps
CPU time 1.19 seconds
Started Aug 05 04:29:12 PM PDT 24
Finished Aug 05 04:29:13 PM PDT 24
Peak memory 207148 kb
Host smart-cfdcd0be-340d-47a3-a6b6-a50c1857ed73
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281578325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
4281578325
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.987994197
Short name T1112
Test name
Test status
Simulation time 36893704 ps
CPU time 0.74 seconds
Started Aug 05 04:29:20 PM PDT 24
Finished Aug 05 04:29:21 PM PDT 24
Peak memory 204180 kb
Host smart-7308c128-3243-44b0-97c5-170b052fbe62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987994197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.987994197
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2423122310
Short name T1055
Test name
Test status
Simulation time 60907418 ps
CPU time 3.73 seconds
Started Aug 05 04:29:13 PM PDT 24
Finished Aug 05 04:29:17 PM PDT 24
Peak memory 215384 kb
Host smart-6dc10a8e-ab9b-4bf4-a256-407da1ef1f8f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423122310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.2423122310
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.3604519151
Short name T100
Test name
Test status
Simulation time 3763250814 ps
CPU time 7.42 seconds
Started Aug 05 04:29:05 PM PDT 24
Finished Aug 05 04:29:12 PM PDT 24
Peak memory 215556 kb
Host smart-fc26dc15-cdcb-492c-8cdd-7b2145d61218
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604519151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.3604519151
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2216580256
Short name T1094
Test name
Test status
Simulation time 539397520 ps
CPU time 3.51 seconds
Started Aug 05 04:29:07 PM PDT 24
Finished Aug 05 04:29:10 PM PDT 24
Peak memory 218120 kb
Host smart-2c5fd880-f97b-425e-a1ae-ce95bbf008ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216580256 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.2216580256
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1346351504
Short name T1039
Test name
Test status
Simulation time 163162151 ps
CPU time 1.25 seconds
Started Aug 05 04:29:18 PM PDT 24
Finished Aug 05 04:29:20 PM PDT 24
Peak memory 215420 kb
Host smart-76b7ab7d-8ee4-4e71-b89e-bba24db69475
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346351504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
1346351504
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.1404541731
Short name T1027
Test name
Test status
Simulation time 35546871 ps
CPU time 0.71 seconds
Started Aug 05 04:29:06 PM PDT 24
Finished Aug 05 04:29:06 PM PDT 24
Peak memory 204192 kb
Host smart-1335ae15-ab87-42bf-b715-d8e6aa2f6e46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404541731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
1404541731
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1164201361
Short name T150
Test name
Test status
Simulation time 369771585 ps
CPU time 3.81 seconds
Started Aug 05 04:29:04 PM PDT 24
Finished Aug 05 04:29:07 PM PDT 24
Peak memory 215384 kb
Host smart-c3e20843-d1f2-469e-9551-948e99c9940d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164201361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.1164201361
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2031627492
Short name T115
Test name
Test status
Simulation time 162874081 ps
CPU time 4.22 seconds
Started Aug 05 04:29:00 PM PDT 24
Finished Aug 05 04:29:05 PM PDT 24
Peak memory 215656 kb
Host smart-8e664178-c014-4e98-b1e0-0f4282b3c677
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031627492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
2031627492
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.3098677767
Short name T176
Test name
Test status
Simulation time 205735351 ps
CPU time 12.46 seconds
Started Aug 05 04:29:21 PM PDT 24
Finished Aug 05 04:29:34 PM PDT 24
Peak memory 215532 kb
Host smart-732e6358-8a79-439a-96e0-6fe2af56c82f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098677767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.3098677767
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.3816590561
Short name T122
Test name
Test status
Simulation time 1911336173 ps
CPU time 19.89 seconds
Started Aug 05 04:29:03 PM PDT 24
Finished Aug 05 04:29:23 PM PDT 24
Peak memory 215352 kb
Host smart-503e79a3-724e-4b2f-b895-94a007ccbda6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816590561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.3816590561
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1727836432
Short name T123
Test name
Test status
Simulation time 2177430008 ps
CPU time 34.44 seconds
Started Aug 05 04:28:56 PM PDT 24
Finished Aug 05 04:29:31 PM PDT 24
Peak memory 207328 kb
Host smart-e3faecfe-ab57-4e55-b540-7fc35c4d5c45
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727836432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.1727836432
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2020885959
Short name T84
Test name
Test status
Simulation time 201129573 ps
CPU time 1.21 seconds
Started Aug 05 04:28:58 PM PDT 24
Finished Aug 05 04:28:59 PM PDT 24
Peak memory 207220 kb
Host smart-7cb708ac-e37c-4546-ab89-2cbc86d8693b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020885959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.2020885959
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.129401787
Short name T1128
Test name
Test status
Simulation time 87673365 ps
CPU time 2.53 seconds
Started Aug 05 04:29:03 PM PDT 24
Finished Aug 05 04:29:06 PM PDT 24
Peak memory 217800 kb
Host smart-9a590281-be6b-44fe-8ba2-59c52dd372f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129401787 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.129401787
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.4161509249
Short name T1041
Test name
Test status
Simulation time 73904042 ps
CPU time 1.23 seconds
Started Aug 05 04:28:48 PM PDT 24
Finished Aug 05 04:28:50 PM PDT 24
Peak memory 207140 kb
Host smart-a684083b-7f6e-46dd-b650-62b707b4f719
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161509249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.4
161509249
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.712075499
Short name T1050
Test name
Test status
Simulation time 14009735 ps
CPU time 0.78 seconds
Started Aug 05 04:28:47 PM PDT 24
Finished Aug 05 04:28:48 PM PDT 24
Peak memory 204184 kb
Host smart-4f54260b-5f30-40e6-b6cd-80c17fc1fcd4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712075499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.712075499
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.1581649018
Short name T1118
Test name
Test status
Simulation time 117410635 ps
CPU time 1.38 seconds
Started Aug 05 04:28:48 PM PDT 24
Finished Aug 05 04:28:50 PM PDT 24
Peak memory 215400 kb
Host smart-2c298e95-fb5f-4f47-91ca-0626fa75e120
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581649018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.1581649018
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.2615096781
Short name T1054
Test name
Test status
Simulation time 40161702 ps
CPU time 0.68 seconds
Started Aug 05 04:28:41 PM PDT 24
Finished Aug 05 04:28:42 PM PDT 24
Peak memory 203800 kb
Host smart-63af0dcd-dcd7-4a5c-bf1c-e4a6ec8c2afb
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615096781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.2615096781
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3695909744
Short name T1059
Test name
Test status
Simulation time 99926425 ps
CPU time 2.94 seconds
Started Aug 05 04:28:56 PM PDT 24
Finished Aug 05 04:28:59 PM PDT 24
Peak memory 215464 kb
Host smart-c9d02cae-f083-4cb5-a8b0-f92bc0a25df4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695909744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.3695909744
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3642372863
Short name T1114
Test name
Test status
Simulation time 354023956 ps
CPU time 3.78 seconds
Started Aug 05 04:28:48 PM PDT 24
Finished Aug 05 04:28:52 PM PDT 24
Peak memory 215632 kb
Host smart-7be8c4ca-9119-43eb-9082-27dbf86a8525
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642372863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.3
642372863
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.611339602
Short name T1064
Test name
Test status
Simulation time 31984105 ps
CPU time 0.72 seconds
Started Aug 05 04:29:18 PM PDT 24
Finished Aug 05 04:29:19 PM PDT 24
Peak memory 203868 kb
Host smart-2680b4ec-7283-47ec-8342-d75111dd8d06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611339602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.611339602
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.1297487364
Short name T1066
Test name
Test status
Simulation time 15488308 ps
CPU time 0.7 seconds
Started Aug 05 04:29:05 PM PDT 24
Finished Aug 05 04:29:05 PM PDT 24
Peak memory 204212 kb
Host smart-5240212e-5330-4eb0-9f1c-91df71b4b0b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297487364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
1297487364
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3429648085
Short name T1078
Test name
Test status
Simulation time 12632950 ps
CPU time 0.71 seconds
Started Aug 05 04:29:16 PM PDT 24
Finished Aug 05 04:29:17 PM PDT 24
Peak memory 203872 kb
Host smart-02a81e3b-8580-4619-8fe4-b97824154948
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429648085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
3429648085
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2818399279
Short name T1028
Test name
Test status
Simulation time 13227201 ps
CPU time 0.77 seconds
Started Aug 05 04:29:06 PM PDT 24
Finished Aug 05 04:29:07 PM PDT 24
Peak memory 204228 kb
Host smart-6252c70d-55fc-4421-bc3c-93da38a2188c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818399279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
2818399279
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1237038905
Short name T1110
Test name
Test status
Simulation time 29518575 ps
CPU time 0.74 seconds
Started Aug 05 04:29:06 PM PDT 24
Finished Aug 05 04:29:07 PM PDT 24
Peak memory 203860 kb
Host smart-7d448a5a-297d-41f2-9cea-8a4c5a927ec9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237038905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
1237038905
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.1024378440
Short name T1145
Test name
Test status
Simulation time 56825313 ps
CPU time 0.73 seconds
Started Aug 05 04:29:15 PM PDT 24
Finished Aug 05 04:29:15 PM PDT 24
Peak memory 204224 kb
Host smart-dd1e46b1-796b-480d-9c47-432f6631cbe4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024378440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
1024378440
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.4197254134
Short name T1147
Test name
Test status
Simulation time 82243294 ps
CPU time 0.7 seconds
Started Aug 05 04:29:22 PM PDT 24
Finished Aug 05 04:29:23 PM PDT 24
Peak memory 203852 kb
Host smart-57d1785d-4aee-4af4-b284-6cd2edacfa67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197254134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
4197254134
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.4222828896
Short name T1042
Test name
Test status
Simulation time 34937802 ps
CPU time 0.71 seconds
Started Aug 05 04:29:39 PM PDT 24
Finished Aug 05 04:29:40 PM PDT 24
Peak memory 203900 kb
Host smart-5d811df7-79b6-4d28-8c5a-7a09099fea9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222828896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
4222828896
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.4290099653
Short name T1058
Test name
Test status
Simulation time 13923391 ps
CPU time 0.72 seconds
Started Aug 05 04:29:17 PM PDT 24
Finished Aug 05 04:29:17 PM PDT 24
Peak memory 203900 kb
Host smart-de081a9e-d272-4e3f-ab74-6b1b7a49f046
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290099653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
4290099653
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2479082661
Short name T1033
Test name
Test status
Simulation time 22532493 ps
CPU time 0.7 seconds
Started Aug 05 04:29:20 PM PDT 24
Finished Aug 05 04:29:21 PM PDT 24
Peak memory 203876 kb
Host smart-67a96bf3-2546-4218-8b9d-6370179013e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479082661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
2479082661
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.1097853066
Short name T1086
Test name
Test status
Simulation time 111753961 ps
CPU time 8.01 seconds
Started Aug 05 04:28:59 PM PDT 24
Finished Aug 05 04:29:07 PM PDT 24
Peak memory 215424 kb
Host smart-c43d1338-b8e3-4f10-a4dc-f0c1ec0524b8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097853066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.1097853066
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3585281666
Short name T1070
Test name
Test status
Simulation time 4470674269 ps
CPU time 25.93 seconds
Started Aug 05 04:29:01 PM PDT 24
Finished Aug 05 04:29:27 PM PDT 24
Peak memory 215416 kb
Host smart-7aedb491-58d2-40e3-89a5-fe26573092a6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585281666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.3585281666
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.4216186216
Short name T1100
Test name
Test status
Simulation time 1349421370 ps
CPU time 2.6 seconds
Started Aug 05 04:29:10 PM PDT 24
Finished Aug 05 04:29:12 PM PDT 24
Peak memory 217616 kb
Host smart-580ea5e0-a8b3-4948-bba4-caf51fe3c562
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216186216 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.4216186216
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.3011983095
Short name T131
Test name
Test status
Simulation time 118432782 ps
CPU time 2.02 seconds
Started Aug 05 04:29:10 PM PDT 24
Finished Aug 05 04:29:12 PM PDT 24
Peak memory 207236 kb
Host smart-c1995d27-c4bf-42f7-a8d8-cd5d77b8c871
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011983095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.3
011983095
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.4159926121
Short name T1106
Test name
Test status
Simulation time 36745093 ps
CPU time 0.71 seconds
Started Aug 05 04:29:12 PM PDT 24
Finished Aug 05 04:29:12 PM PDT 24
Peak memory 204220 kb
Host smart-44547223-662e-4e3b-86b3-871308707be0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159926121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.4
159926121
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.180630180
Short name T120
Test name
Test status
Simulation time 137471400 ps
CPU time 1.31 seconds
Started Aug 05 04:28:56 PM PDT 24
Finished Aug 05 04:28:57 PM PDT 24
Peak memory 215416 kb
Host smart-556ce189-4cb7-463a-80c1-f044d512be57
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180630180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_
device_mem_partial_access.180630180
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.2173812229
Short name T1099
Test name
Test status
Simulation time 29974642 ps
CPU time 0.68 seconds
Started Aug 05 04:28:59 PM PDT 24
Finished Aug 05 04:29:00 PM PDT 24
Peak memory 203840 kb
Host smart-58276e80-b67c-4ace-8926-0ebe847c92ba
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173812229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.2173812229
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.4274994656
Short name T1047
Test name
Test status
Simulation time 47891853 ps
CPU time 2.99 seconds
Started Aug 05 04:28:55 PM PDT 24
Finished Aug 05 04:28:59 PM PDT 24
Peak memory 215404 kb
Host smart-6e5e6833-1ed0-4c52-8fee-7c7ec55fcfc8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274994656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.4274994656
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.1576559613
Short name T1135
Test name
Test status
Simulation time 527794686 ps
CPU time 1.75 seconds
Started Aug 05 04:29:03 PM PDT 24
Finished Aug 05 04:29:05 PM PDT 24
Peak memory 215752 kb
Host smart-bd6c4b1d-17b3-454f-b4fd-7c963bc41c40
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576559613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.1
576559613
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2834475730
Short name T190
Test name
Test status
Simulation time 704445680 ps
CPU time 7.55 seconds
Started Aug 05 04:28:59 PM PDT 24
Finished Aug 05 04:29:07 PM PDT 24
Peak memory 223532 kb
Host smart-38811d42-ffe8-4569-93c3-7b733bb59aa4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834475730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.2834475730
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.2648971519
Short name T1097
Test name
Test status
Simulation time 78397313 ps
CPU time 0.79 seconds
Started Aug 05 04:29:13 PM PDT 24
Finished Aug 05 04:29:14 PM PDT 24
Peak memory 204256 kb
Host smart-c81f60c9-8429-43f3-a0c9-739cd31c2981
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648971519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
2648971519
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.3124518958
Short name T1116
Test name
Test status
Simulation time 44075050 ps
CPU time 0.73 seconds
Started Aug 05 04:29:12 PM PDT 24
Finished Aug 05 04:29:12 PM PDT 24
Peak memory 203924 kb
Host smart-02a785dc-3703-486a-8e41-9295660d0307
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124518958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
3124518958
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.3632948984
Short name T1034
Test name
Test status
Simulation time 50416338 ps
CPU time 0.73 seconds
Started Aug 05 04:29:18 PM PDT 24
Finished Aug 05 04:29:19 PM PDT 24
Peak memory 203900 kb
Host smart-90e315e6-8e63-45bf-a747-2d2a6e29baf0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632948984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
3632948984
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.3122605633
Short name T1035
Test name
Test status
Simulation time 37888005 ps
CPU time 0.68 seconds
Started Aug 05 04:29:08 PM PDT 24
Finished Aug 05 04:29:09 PM PDT 24
Peak memory 203904 kb
Host smart-417bca15-643e-43bc-a55b-b09ae326c596
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122605633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
3122605633
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.2884743074
Short name T1105
Test name
Test status
Simulation time 43075365 ps
CPU time 0.72 seconds
Started Aug 05 04:29:18 PM PDT 24
Finished Aug 05 04:29:19 PM PDT 24
Peak memory 203928 kb
Host smart-c1e45268-0415-4ef5-9a64-7e60490f33a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884743074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
2884743074
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.1218344184
Short name T1081
Test name
Test status
Simulation time 15106256 ps
CPU time 0.74 seconds
Started Aug 05 04:29:11 PM PDT 24
Finished Aug 05 04:29:12 PM PDT 24
Peak memory 204216 kb
Host smart-50bf066a-9504-46ba-a9dc-8b07c612e2d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218344184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
1218344184
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.1566457545
Short name T1082
Test name
Test status
Simulation time 46903203 ps
CPU time 0.74 seconds
Started Aug 05 04:29:00 PM PDT 24
Finished Aug 05 04:29:01 PM PDT 24
Peak memory 203892 kb
Host smart-720122b1-1e16-4474-ae34-daf76ec61136
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566457545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
1566457545
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.2328403744
Short name T1060
Test name
Test status
Simulation time 15644943 ps
CPU time 0.74 seconds
Started Aug 05 04:29:05 PM PDT 24
Finished Aug 05 04:29:06 PM PDT 24
Peak memory 204180 kb
Host smart-bd12a0e8-dae1-483d-a00f-3ec81ad725fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328403744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
2328403744
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.890906422
Short name T1074
Test name
Test status
Simulation time 16279977 ps
CPU time 0.74 seconds
Started Aug 05 04:29:04 PM PDT 24
Finished Aug 05 04:29:05 PM PDT 24
Peak memory 203860 kb
Host smart-3d9cba51-541b-4750-b73a-54a00edefc83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890906422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.890906422
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.112813726
Short name T1144
Test name
Test status
Simulation time 15813140 ps
CPU time 0.71 seconds
Started Aug 05 04:29:12 PM PDT 24
Finished Aug 05 04:29:13 PM PDT 24
Peak memory 204200 kb
Host smart-1f7ffe4e-f4c1-45c7-b158-10e166674083
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112813726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.112813726
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3701245423
Short name T1098
Test name
Test status
Simulation time 1120215624 ps
CPU time 22.78 seconds
Started Aug 05 04:29:04 PM PDT 24
Finished Aug 05 04:29:32 PM PDT 24
Peak memory 215344 kb
Host smart-84ec18f2-cdb1-415d-aa54-019e0112ceb1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701245423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.3701245423
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.1279777713
Short name T159
Test name
Test status
Simulation time 9362225506 ps
CPU time 34.72 seconds
Started Aug 05 04:29:01 PM PDT 24
Finished Aug 05 04:29:35 PM PDT 24
Peak memory 207288 kb
Host smart-6fefe9c9-890e-401b-8c29-b2429fcc5a4f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279777713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.1279777713
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3564812324
Short name T86
Test name
Test status
Simulation time 15569484 ps
CPU time 0.97 seconds
Started Aug 05 04:28:50 PM PDT 24
Finished Aug 05 04:28:51 PM PDT 24
Peak memory 206968 kb
Host smart-693ac74b-aa87-4753-86dd-a73b3907129a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564812324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.3564812324
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3458699139
Short name T96
Test name
Test status
Simulation time 637718079 ps
CPU time 2.64 seconds
Started Aug 05 04:28:59 PM PDT 24
Finished Aug 05 04:29:02 PM PDT 24
Peak memory 216660 kb
Host smart-b21b8d89-e333-44ad-8865-2e7bd0d48cca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458699139 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.3458699139
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.1110359773
Short name T124
Test name
Test status
Simulation time 75143223 ps
CPU time 1.84 seconds
Started Aug 05 04:28:52 PM PDT 24
Finished Aug 05 04:28:54 PM PDT 24
Peak memory 215372 kb
Host smart-61ba79da-f0db-442f-89ee-047d8f3f531d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110359773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.1
110359773
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.2314518284
Short name T1068
Test name
Test status
Simulation time 37204499 ps
CPU time 0.7 seconds
Started Aug 05 04:28:53 PM PDT 24
Finished Aug 05 04:28:54 PM PDT 24
Peak memory 204224 kb
Host smart-64db05c3-cb53-4422-9e24-c92cbd648cce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314518284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.2
314518284
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1761649304
Short name T128
Test name
Test status
Simulation time 368559655 ps
CPU time 2.17 seconds
Started Aug 05 04:29:03 PM PDT 24
Finished Aug 05 04:29:05 PM PDT 24
Peak memory 215384 kb
Host smart-10ce7a4d-5ffa-4b19-b635-79b46ca4cd91
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761649304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.1761649304
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.3729415123
Short name T1093
Test name
Test status
Simulation time 11414426 ps
CPU time 0.67 seconds
Started Aug 05 04:28:57 PM PDT 24
Finished Aug 05 04:28:57 PM PDT 24
Peak memory 203784 kb
Host smart-9d2557b1-1d76-4f9a-863f-de5fa74af579
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729415123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.3729415123
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.98889148
Short name T1062
Test name
Test status
Simulation time 607633827 ps
CPU time 4.08 seconds
Started Aug 05 04:29:02 PM PDT 24
Finished Aug 05 04:29:06 PM PDT 24
Peak memory 215396 kb
Host smart-ef804103-4796-43a6-be02-1cd050d42259
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98889148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_same_csr_outstanding.98889148
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.4001213918
Short name T102
Test name
Test status
Simulation time 31569096 ps
CPU time 1.96 seconds
Started Aug 05 04:29:03 PM PDT 24
Finished Aug 05 04:29:05 PM PDT 24
Peak memory 215688 kb
Host smart-86a08ef7-de75-41cb-9775-fee93cc7fd30
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001213918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.4
001213918
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2909554924
Short name T1057
Test name
Test status
Simulation time 821293386 ps
CPU time 13.17 seconds
Started Aug 05 04:29:02 PM PDT 24
Finished Aug 05 04:29:15 PM PDT 24
Peak memory 215408 kb
Host smart-ba3405d1-4e5b-42ab-815a-988ed3ef24fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909554924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.2909554924
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.3582150932
Short name T1138
Test name
Test status
Simulation time 44104970 ps
CPU time 0.7 seconds
Started Aug 05 04:29:03 PM PDT 24
Finished Aug 05 04:29:04 PM PDT 24
Peak memory 203896 kb
Host smart-47981720-185c-485b-9524-79cc19f9e894
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582150932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
3582150932
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.3124396659
Short name T1115
Test name
Test status
Simulation time 13640805 ps
CPU time 0.8 seconds
Started Aug 05 04:29:03 PM PDT 24
Finished Aug 05 04:29:04 PM PDT 24
Peak memory 204192 kb
Host smart-f97c5c39-49fc-4c1b-83ba-2dca34be57d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124396659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
3124396659
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.2929243735
Short name T1108
Test name
Test status
Simulation time 15035036 ps
CPU time 0.74 seconds
Started Aug 05 04:29:04 PM PDT 24
Finished Aug 05 04:29:04 PM PDT 24
Peak memory 203864 kb
Host smart-8c23e0a4-439f-4485-82de-31d2f390677c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929243735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
2929243735
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.3585926238
Short name T1076
Test name
Test status
Simulation time 11699904 ps
CPU time 0.72 seconds
Started Aug 05 04:29:05 PM PDT 24
Finished Aug 05 04:29:06 PM PDT 24
Peak memory 204200 kb
Host smart-8c78686a-eb43-4d83-ac86-cd04a2922174
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585926238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
3585926238
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.534044220
Short name T1032
Test name
Test status
Simulation time 29706045 ps
CPU time 0.77 seconds
Started Aug 05 04:29:16 PM PDT 24
Finished Aug 05 04:29:17 PM PDT 24
Peak memory 203880 kb
Host smart-7308520f-8af8-4aaa-b354-fcd9b373c747
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534044220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.534044220
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.4276312438
Short name T1092
Test name
Test status
Simulation time 93783499 ps
CPU time 0.72 seconds
Started Aug 05 04:29:06 PM PDT 24
Finished Aug 05 04:29:07 PM PDT 24
Peak memory 204212 kb
Host smart-8290291d-9668-4abb-b810-8211820068b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276312438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
4276312438
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.111710867
Short name T1079
Test name
Test status
Simulation time 12140704 ps
CPU time 0.7 seconds
Started Aug 05 04:29:19 PM PDT 24
Finished Aug 05 04:29:25 PM PDT 24
Peak memory 203876 kb
Host smart-d0122842-57cb-44b1-89e7-8b0ec933bd77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111710867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.111710867
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.1848879423
Short name T1095
Test name
Test status
Simulation time 46780416 ps
CPU time 0.71 seconds
Started Aug 05 04:29:12 PM PDT 24
Finished Aug 05 04:29:13 PM PDT 24
Peak memory 203884 kb
Host smart-116d3053-623e-448e-b09c-1700a70bd818
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848879423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
1848879423
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2791571682
Short name T1150
Test name
Test status
Simulation time 74251102 ps
CPU time 0.79 seconds
Started Aug 05 04:28:57 PM PDT 24
Finished Aug 05 04:28:57 PM PDT 24
Peak memory 203876 kb
Host smart-fbed62c3-4050-46f0-8054-f54546ce928b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791571682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
2791571682
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.422443841
Short name T1043
Test name
Test status
Simulation time 44043244 ps
CPU time 0.71 seconds
Started Aug 05 04:29:06 PM PDT 24
Finished Aug 05 04:29:07 PM PDT 24
Peak memory 204196 kb
Host smart-01777c31-3117-45c4-b0bf-56c76513d61b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422443841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.422443841
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.2980341243
Short name T1052
Test name
Test status
Simulation time 232630493 ps
CPU time 3.16 seconds
Started Aug 05 04:28:52 PM PDT 24
Finished Aug 05 04:28:55 PM PDT 24
Peak memory 217000 kb
Host smart-f1a31bf1-e19f-4b5c-adaf-86331427dcc9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980341243 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.2980341243
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.2101265075
Short name T1083
Test name
Test status
Simulation time 197298079 ps
CPU time 2.13 seconds
Started Aug 05 04:28:57 PM PDT 24
Finished Aug 05 04:28:59 PM PDT 24
Peak memory 207244 kb
Host smart-9b25c7c2-dd57-4d38-b45a-ce427a51324c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101265075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.2
101265075
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.1560238772
Short name T1045
Test name
Test status
Simulation time 107023675 ps
CPU time 0.66 seconds
Started Aug 05 04:29:03 PM PDT 24
Finished Aug 05 04:29:04 PM PDT 24
Peak memory 203852 kb
Host smart-d604bffc-24f6-449b-b619-9474d756a7dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560238772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.1
560238772
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.1119962679
Short name T1072
Test name
Test status
Simulation time 175136507 ps
CPU time 2.62 seconds
Started Aug 05 04:29:14 PM PDT 24
Finished Aug 05 04:29:17 PM PDT 24
Peak memory 215348 kb
Host smart-ecf20b49-73c1-4cd8-8afe-e7c701d74487
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119962679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.1119962679
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.994351065
Short name T1122
Test name
Test status
Simulation time 598133570 ps
CPU time 4.34 seconds
Started Aug 05 04:28:57 PM PDT 24
Finished Aug 05 04:29:02 PM PDT 24
Peak memory 215636 kb
Host smart-18fb7831-170b-4631-a129-bf00082fbf87
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994351065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.994351065
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.232867058
Short name T1136
Test name
Test status
Simulation time 199575856 ps
CPU time 12.11 seconds
Started Aug 05 04:28:57 PM PDT 24
Finished Aug 05 04:29:10 PM PDT 24
Peak memory 215364 kb
Host smart-20557374-3f4f-4840-917b-aec08955df13
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232867058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_
tl_intg_err.232867058
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.2760697242
Short name T1121
Test name
Test status
Simulation time 54254286 ps
CPU time 3.69 seconds
Started Aug 05 04:28:52 PM PDT 24
Finished Aug 05 04:28:56 PM PDT 24
Peak memory 217732 kb
Host smart-78443c94-4001-461b-900c-98cd3c177a82
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760697242 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.2760697242
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.1290592097
Short name T1151
Test name
Test status
Simulation time 261400901 ps
CPU time 2.03 seconds
Started Aug 05 04:28:58 PM PDT 24
Finished Aug 05 04:29:00 PM PDT 24
Peak memory 215308 kb
Host smart-1cfcc5d8-f005-49cc-9b26-e8732477a785
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290592097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.1
290592097
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.3306268864
Short name T1126
Test name
Test status
Simulation time 26687575 ps
CPU time 0.74 seconds
Started Aug 05 04:28:52 PM PDT 24
Finished Aug 05 04:28:53 PM PDT 24
Peak memory 203860 kb
Host smart-bd13dfac-305f-4256-8f54-ae320bbc709c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306268864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.3
306268864
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.1035207024
Short name T1104
Test name
Test status
Simulation time 293859205 ps
CPU time 1.62 seconds
Started Aug 05 04:29:07 PM PDT 24
Finished Aug 05 04:29:09 PM PDT 24
Peak memory 215448 kb
Host smart-c1ae429b-2c35-41b4-87ad-8bcf27999772
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035207024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.1035207024
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2920796063
Short name T1088
Test name
Test status
Simulation time 200676640 ps
CPU time 3.02 seconds
Started Aug 05 04:29:04 PM PDT 24
Finished Aug 05 04:29:07 PM PDT 24
Peak memory 215548 kb
Host smart-e136efd6-8d75-4486-ac51-f3d264a94e23
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920796063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.2
920796063
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1882337353
Short name T189
Test name
Test status
Simulation time 2260466827 ps
CPU time 13.96 seconds
Started Aug 05 04:29:02 PM PDT 24
Finished Aug 05 04:29:16 PM PDT 24
Peak memory 215588 kb
Host smart-8458a206-150f-4605-adf4-6a57f1a30d0d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882337353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.1882337353
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.241452331
Short name T1048
Test name
Test status
Simulation time 141661680 ps
CPU time 1.8 seconds
Started Aug 05 04:28:51 PM PDT 24
Finished Aug 05 04:28:53 PM PDT 24
Peak memory 216420 kb
Host smart-6d25d6d2-e4c1-4236-b5ef-d59871a4a8ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241452331 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.241452331
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.2089023638
Short name T1087
Test name
Test status
Simulation time 26430974 ps
CPU time 1.57 seconds
Started Aug 05 04:29:28 PM PDT 24
Finished Aug 05 04:29:30 PM PDT 24
Peak memory 207220 kb
Host smart-5c433baa-e41b-4c4a-a18d-264746637b78
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089023638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.2
089023638
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.3454610458
Short name T1141
Test name
Test status
Simulation time 17778733 ps
CPU time 0.71 seconds
Started Aug 05 04:29:02 PM PDT 24
Finished Aug 05 04:29:03 PM PDT 24
Peak memory 204424 kb
Host smart-29f9d929-52c2-44b3-ac80-ebdd9691d820
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454610458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.3
454610458
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.825083010
Short name T160
Test name
Test status
Simulation time 405439991 ps
CPU time 4.23 seconds
Started Aug 05 04:29:01 PM PDT 24
Finished Aug 05 04:29:05 PM PDT 24
Peak memory 215416 kb
Host smart-38a1d89e-1da5-4e09-863a-b6cc59559947
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825083010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sp
i_device_same_csr_outstanding.825083010
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.491682258
Short name T1143
Test name
Test status
Simulation time 25043240 ps
CPU time 1.56 seconds
Started Aug 05 04:29:18 PM PDT 24
Finished Aug 05 04:29:24 PM PDT 24
Peak memory 215564 kb
Host smart-e0166d9c-65e0-4f4f-a436-f7e84ecbfdec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491682258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.491682258
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.4154915953
Short name T97
Test name
Test status
Simulation time 926732776 ps
CPU time 1.8 seconds
Started Aug 05 04:29:01 PM PDT 24
Finished Aug 05 04:29:03 PM PDT 24
Peak memory 216556 kb
Host smart-d3ac4152-87b0-43d5-80e7-cd278d7376eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154915953 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.4154915953
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.1314798242
Short name T1040
Test name
Test status
Simulation time 141578811 ps
CPU time 1.43 seconds
Started Aug 05 04:29:07 PM PDT 24
Finished Aug 05 04:29:09 PM PDT 24
Peak memory 215460 kb
Host smart-2ec93b68-8473-4a73-93be-6b55e0ef6dd4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314798242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.1
314798242
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.2467876382
Short name T1036
Test name
Test status
Simulation time 11582160 ps
CPU time 0.73 seconds
Started Aug 05 04:29:00 PM PDT 24
Finished Aug 05 04:29:01 PM PDT 24
Peak memory 203884 kb
Host smart-f22c5333-6243-4d14-a7c5-386c3ec28c50
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467876382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.2
467876382
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.746171217
Short name T161
Test name
Test status
Simulation time 432523253 ps
CPU time 4.47 seconds
Started Aug 05 04:28:59 PM PDT 24
Finished Aug 05 04:29:04 PM PDT 24
Peak memory 215448 kb
Host smart-8692e34c-5ef1-48fd-913d-a68b24cc71ac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746171217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sp
i_device_same_csr_outstanding.746171217
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.2792954842
Short name T111
Test name
Test status
Simulation time 170321911 ps
CPU time 4.94 seconds
Started Aug 05 04:29:08 PM PDT 24
Finished Aug 05 04:29:13 PM PDT 24
Peak memory 215652 kb
Host smart-f2bce266-0ca2-4b9f-841e-918031199a21
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792954842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.2
792954842
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.2814830868
Short name T1119
Test name
Test status
Simulation time 602193828 ps
CPU time 7.28 seconds
Started Aug 05 04:29:03 PM PDT 24
Finished Aug 05 04:29:10 PM PDT 24
Peak memory 215984 kb
Host smart-93a661cd-78b6-4ce3-a368-7422156b6b41
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814830868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.2814830868
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.948806912
Short name T116
Test name
Test status
Simulation time 1025706058 ps
CPU time 1.88 seconds
Started Aug 05 04:28:57 PM PDT 24
Finished Aug 05 04:28:59 PM PDT 24
Peak memory 215516 kb
Host smart-232205ca-0f9c-45a4-832d-02423d17c8fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948806912 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.948806912
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.1257426595
Short name T1071
Test name
Test status
Simulation time 664193886 ps
CPU time 2.7 seconds
Started Aug 05 04:29:18 PM PDT 24
Finished Aug 05 04:29:21 PM PDT 24
Peak memory 215460 kb
Host smart-2aa8d036-c539-47c3-884e-b67a2b1c6d3c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257426595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.1
257426595
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.553320639
Short name T1029
Test name
Test status
Simulation time 35576406 ps
CPU time 0.72 seconds
Started Aug 05 04:29:08 PM PDT 24
Finished Aug 05 04:29:09 PM PDT 24
Peak memory 203916 kb
Host smart-80b1f969-f96c-4222-a5c3-a3bcba9fff69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553320639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.553320639
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.383805876
Short name T1124
Test name
Test status
Simulation time 106639333 ps
CPU time 2.88 seconds
Started Aug 05 04:29:02 PM PDT 24
Finished Aug 05 04:29:05 PM PDT 24
Peak memory 215320 kb
Host smart-8ea628b7-8287-43db-8a45-2fd640d2bdaf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383805876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sp
i_device_same_csr_outstanding.383805876
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.4090462327
Short name T108
Test name
Test status
Simulation time 201593511 ps
CPU time 4.91 seconds
Started Aug 05 04:29:01 PM PDT 24
Finished Aug 05 04:29:06 PM PDT 24
Peak memory 215664 kb
Host smart-63f1636d-0564-4963-a553-db5308f77c70
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090462327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.4
090462327
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.1484720621
Short name T191
Test name
Test status
Simulation time 456458917 ps
CPU time 7.18 seconds
Started Aug 05 04:29:08 PM PDT 24
Finished Aug 05 04:29:15 PM PDT 24
Peak memory 215680 kb
Host smart-6258e0df-c022-4ab5-aa8e-da9d0da30c1b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484720621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.1484720621
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.2489751364
Short name T437
Test name
Test status
Simulation time 80433856 ps
CPU time 0.74 seconds
Started Aug 05 04:49:31 PM PDT 24
Finished Aug 05 04:49:32 PM PDT 24
Peak memory 205204 kb
Host smart-b5f30a69-4207-4b7a-ae64-c6c392eb724e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489751364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.2
489751364
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.4224407196
Short name T480
Test name
Test status
Simulation time 62696195 ps
CPU time 2.42 seconds
Started Aug 05 04:49:45 PM PDT 24
Finished Aug 05 04:49:47 PM PDT 24
Peak memory 233344 kb
Host smart-5b79b081-c156-45c5-ac00-beef35f9d06c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224407196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.4224407196
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.2940568529
Short name T998
Test name
Test status
Simulation time 65213457 ps
CPU time 0.81 seconds
Started Aug 05 04:49:27 PM PDT 24
Finished Aug 05 04:49:28 PM PDT 24
Peak memory 207244 kb
Host smart-e6cf54ee-c3ae-4a9e-8785-840ada65deb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940568529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.2940568529
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.381259212
Short name T508
Test name
Test status
Simulation time 13337265425 ps
CPU time 126.19 seconds
Started Aug 05 04:49:33 PM PDT 24
Finished Aug 05 04:51:39 PM PDT 24
Peak memory 250088 kb
Host smart-6320e608-086f-4720-aac2-d0b7f577fa8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381259212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.381259212
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.1290658084
Short name T185
Test name
Test status
Simulation time 2260121138 ps
CPU time 23.22 seconds
Started Aug 05 04:49:32 PM PDT 24
Finished Aug 05 04:49:55 PM PDT 24
Peak memory 231468 kb
Host smart-c0816abb-76d6-464b-8972-ebff57f77267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290658084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.1290658084
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.4037595453
Short name T404
Test name
Test status
Simulation time 1741315715 ps
CPU time 26.99 seconds
Started Aug 05 04:49:30 PM PDT 24
Finished Aug 05 04:49:57 PM PDT 24
Peak memory 241480 kb
Host smart-ce7ccac4-1602-4246-a99f-31e8e49221ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037595453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.4037595453
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_intercept.605906401
Short name T496
Test name
Test status
Simulation time 109265493 ps
CPU time 2.5 seconds
Started Aug 05 04:49:39 PM PDT 24
Finished Aug 05 04:49:41 PM PDT 24
Peak memory 233000 kb
Host smart-4eaf0718-5940-44f8-bee1-aa8d38fd080f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605906401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.605906401
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.2533068017
Short name T806
Test name
Test status
Simulation time 115312395 ps
CPU time 2.25 seconds
Started Aug 05 04:49:32 PM PDT 24
Finished Aug 05 04:49:35 PM PDT 24
Peak memory 225136 kb
Host smart-cafe8de6-3367-4210-be45-d5261e91e0dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533068017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.2533068017
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.205001084
Short name T737
Test name
Test status
Simulation time 236947336 ps
CPU time 1.16 seconds
Started Aug 05 04:49:33 PM PDT 24
Finished Aug 05 04:49:34 PM PDT 24
Peak memory 217084 kb
Host smart-2965fdd1-03e1-4285-869c-5d8efe448a0b
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205001084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.spi_device_mem_parity.205001084
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.604560003
Short name T636
Test name
Test status
Simulation time 1552492664 ps
CPU time 6.5 seconds
Started Aug 05 04:49:36 PM PDT 24
Finished Aug 05 04:49:43 PM PDT 24
Peak memory 233488 kb
Host smart-1aac7b90-b09e-4b0e-8570-4a576a544b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604560003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap.
604560003
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.4140478652
Short name T952
Test name
Test status
Simulation time 10396968085 ps
CPU time 12.93 seconds
Started Aug 05 04:49:45 PM PDT 24
Finished Aug 05 04:49:58 PM PDT 24
Peak memory 233436 kb
Host smart-c06f7d66-81fa-403a-a941-26788450264e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140478652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.4140478652
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.3169232897
Short name T418
Test name
Test status
Simulation time 4933915094 ps
CPU time 11.91 seconds
Started Aug 05 04:49:31 PM PDT 24
Finished Aug 05 04:49:43 PM PDT 24
Peak memory 219492 kb
Host smart-bc20b2c3-b32e-4860-a1be-222d8dffe8d8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3169232897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.3169232897
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.4265629317
Short name T325
Test name
Test status
Simulation time 6325196059 ps
CPU time 31.91 seconds
Started Aug 05 04:49:36 PM PDT 24
Finished Aug 05 04:50:08 PM PDT 24
Peak memory 217060 kb
Host smart-7ab01f3a-4256-4da9-b692-ddbef1b6b958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265629317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.4265629317
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.2389091715
Short name T753
Test name
Test status
Simulation time 1879848335 ps
CPU time 6.11 seconds
Started Aug 05 04:49:16 PM PDT 24
Finished Aug 05 04:49:22 PM PDT 24
Peak memory 216900 kb
Host smart-fda232c7-024b-437f-be22-e81f086a8860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389091715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.2389091715
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.2392140260
Short name T406
Test name
Test status
Simulation time 701031344 ps
CPU time 2.25 seconds
Started Aug 05 04:49:56 PM PDT 24
Finished Aug 05 04:49:58 PM PDT 24
Peak memory 208692 kb
Host smart-97302b55-e9f9-402c-a634-9ae0429dbca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392140260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.2392140260
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.877049358
Short name T470
Test name
Test status
Simulation time 19432340 ps
CPU time 0.77 seconds
Started Aug 05 04:49:27 PM PDT 24
Finished Aug 05 04:49:28 PM PDT 24
Peak memory 206436 kb
Host smart-94183bcb-73e8-4fbe-8bc1-a993bdf98751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877049358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.877049358
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.3130829399
Short name T4
Test name
Test status
Simulation time 342173665 ps
CPU time 2.52 seconds
Started Aug 05 04:49:40 PM PDT 24
Finished Aug 05 04:49:43 PM PDT 24
Peak memory 225148 kb
Host smart-cb7d75a9-1877-41bc-9196-290e446c524c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130829399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.3130829399
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.1890594025
Short name T912
Test name
Test status
Simulation time 23458508 ps
CPU time 0.76 seconds
Started Aug 05 04:49:40 PM PDT 24
Finished Aug 05 04:49:42 PM PDT 24
Peak memory 204268 kb
Host smart-0dedf00e-87cc-4e9e-b955-769349a3989d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890594025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.1
890594025
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.3923892755
Short name T276
Test name
Test status
Simulation time 888384079 ps
CPU time 5.84 seconds
Started Aug 05 04:49:51 PM PDT 24
Finished Aug 05 04:49:57 PM PDT 24
Peak memory 233384 kb
Host smart-a1a925a8-0f42-4707-9859-ede3bad34647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923892755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.3923892755
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.1829241115
Short name T801
Test name
Test status
Simulation time 19990529 ps
CPU time 0.78 seconds
Started Aug 05 04:49:36 PM PDT 24
Finished Aug 05 04:49:37 PM PDT 24
Peak memory 206952 kb
Host smart-03992b52-118a-4f49-a26b-4d57008e4a2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829241115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.1829241115
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.2507851438
Short name T690
Test name
Test status
Simulation time 66686773407 ps
CPU time 51.24 seconds
Started Aug 05 04:49:34 PM PDT 24
Finished Aug 05 04:50:26 PM PDT 24
Peak memory 236376 kb
Host smart-09eeec50-4b60-405b-b1ad-3c255f2f0d49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507851438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.2507851438
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.2514904271
Short name T602
Test name
Test status
Simulation time 34850521489 ps
CPU time 308.66 seconds
Started Aug 05 04:49:40 PM PDT 24
Finished Aug 05 04:54:49 PM PDT 24
Peak memory 252192 kb
Host smart-2d227fa5-f196-43b6-86fe-95874eca5061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514904271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.2514904271
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.365659858
Short name T193
Test name
Test status
Simulation time 14397110372 ps
CPU time 130.64 seconds
Started Aug 05 04:49:36 PM PDT 24
Finished Aug 05 04:51:47 PM PDT 24
Peak memory 250880 kb
Host smart-69a0ec93-cfa1-4721-9c38-06dd36423ea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365659858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle.
365659858
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.3632503480
Short name T570
Test name
Test status
Simulation time 6463847846 ps
CPU time 30.15 seconds
Started Aug 05 04:49:37 PM PDT 24
Finished Aug 05 04:50:07 PM PDT 24
Peak memory 225232 kb
Host smart-dfcc05f9-8c94-40bb-a92b-0d8040670c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632503480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.3632503480
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.896291948
Short name T454
Test name
Test status
Simulation time 410994849835 ps
CPU time 223.81 seconds
Started Aug 05 04:49:52 PM PDT 24
Finished Aug 05 04:53:35 PM PDT 24
Peak memory 252880 kb
Host smart-4ba1391e-1063-46b3-acf7-596cf1f6ff64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896291948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds.
896291948
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/1.spi_device_intercept.3424820056
Short name T922
Test name
Test status
Simulation time 552097795 ps
CPU time 5.16 seconds
Started Aug 05 04:49:47 PM PDT 24
Finished Aug 05 04:49:52 PM PDT 24
Peak memory 233380 kb
Host smart-a4caeca1-e075-47fa-a6e0-4062b489438e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424820056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.3424820056
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.3692114019
Short name T1017
Test name
Test status
Simulation time 177137047 ps
CPU time 2.57 seconds
Started Aug 05 04:49:45 PM PDT 24
Finished Aug 05 04:49:47 PM PDT 24
Peak memory 225144 kb
Host smart-e963995e-e5a1-4c9a-970e-758d2d0b039d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692114019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.3692114019
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.3196921933
Short name T443
Test name
Test status
Simulation time 272850628 ps
CPU time 3.49 seconds
Started Aug 05 04:49:37 PM PDT 24
Finished Aug 05 04:49:41 PM PDT 24
Peak memory 225192 kb
Host smart-f9764009-984a-4525-acb2-1f0350e4bfaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196921933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.3196921933
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.3836819159
Short name T156
Test name
Test status
Simulation time 1444172585 ps
CPU time 3.71 seconds
Started Aug 05 04:49:57 PM PDT 24
Finished Aug 05 04:50:01 PM PDT 24
Peak memory 219328 kb
Host smart-dd10e673-6343-438f-8df2-3b8a125c015b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3836819159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.3836819159
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.2885314174
Short name T73
Test name
Test status
Simulation time 87176871 ps
CPU time 1.16 seconds
Started Aug 05 04:49:54 PM PDT 24
Finished Aug 05 04:49:55 PM PDT 24
Peak memory 235516 kb
Host smart-75f00054-ff86-4b86-ae63-41befc32bfa7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885314174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.2885314174
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.1690209690
Short name T691
Test name
Test status
Simulation time 6915796680 ps
CPU time 35.64 seconds
Started Aug 05 04:49:53 PM PDT 24
Finished Aug 05 04:50:28 PM PDT 24
Peak memory 216996 kb
Host smart-3dec1ea8-4f8b-47ca-9413-3341702da894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690209690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.1690209690
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.1068848961
Short name T504
Test name
Test status
Simulation time 1726684787 ps
CPU time 6.17 seconds
Started Aug 05 04:49:31 PM PDT 24
Finished Aug 05 04:49:38 PM PDT 24
Peak memory 216868 kb
Host smart-74f0662d-ad11-4453-8209-457d9ff98830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068848961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.1068848961
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.1937986900
Short name T624
Test name
Test status
Simulation time 20625792 ps
CPU time 0.87 seconds
Started Aug 05 04:49:36 PM PDT 24
Finished Aug 05 04:49:37 PM PDT 24
Peak memory 208436 kb
Host smart-886c4658-02ec-4936-82ee-5ef1b35284bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937986900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.1937986900
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.2077431762
Short name T632
Test name
Test status
Simulation time 167124863 ps
CPU time 0.84 seconds
Started Aug 05 04:49:27 PM PDT 24
Finished Aug 05 04:49:28 PM PDT 24
Peak memory 206520 kb
Host smart-818865f7-3a48-494c-82ee-efe928f026df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077431762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.2077431762
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.2764663551
Short name T588
Test name
Test status
Simulation time 6940982922 ps
CPU time 18.96 seconds
Started Aug 05 04:49:43 PM PDT 24
Finished Aug 05 04:50:02 PM PDT 24
Peak memory 235312 kb
Host smart-243ff784-a55c-4790-b74a-7e4db7ccd488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764663551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.2764663551
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.2182399116
Short name T553
Test name
Test status
Simulation time 11649743 ps
CPU time 0.7 seconds
Started Aug 05 04:50:06 PM PDT 24
Finished Aug 05 04:50:07 PM PDT 24
Peak memory 205168 kb
Host smart-312498a2-4a6c-4a92-ad1f-63bdadfc7f88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182399116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
2182399116
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.3640045237
Short name T248
Test name
Test status
Simulation time 215833939 ps
CPU time 4.66 seconds
Started Aug 05 04:50:17 PM PDT 24
Finished Aug 05 04:50:22 PM PDT 24
Peak memory 233344 kb
Host smart-492dbc3c-c8d4-473a-932d-635d78b9686d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640045237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.3640045237
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.48712051
Short name T382
Test name
Test status
Simulation time 64030853 ps
CPU time 0.84 seconds
Started Aug 05 04:49:58 PM PDT 24
Finished Aug 05 04:49:59 PM PDT 24
Peak memory 206932 kb
Host smart-c569fd55-75a0-4a2e-a5fe-d30f284bd28f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48712051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.48712051
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.2765509337
Short name T246
Test name
Test status
Simulation time 1041027607 ps
CPU time 5.27 seconds
Started Aug 05 04:50:13 PM PDT 24
Finished Aug 05 04:50:18 PM PDT 24
Peak memory 225120 kb
Host smart-d0e00851-b87d-4bc7-8492-c299ccacefa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765509337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.2765509337
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.3594146291
Short name T831
Test name
Test status
Simulation time 54245356697 ps
CPU time 102.88 seconds
Started Aug 05 04:50:28 PM PDT 24
Finished Aug 05 04:52:11 PM PDT 24
Peak memory 252876 kb
Host smart-49349be2-5017-45bb-ada4-efda5269fab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594146291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.3594146291
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.460466617
Short name T34
Test name
Test status
Simulation time 111527707 ps
CPU time 3.38 seconds
Started Aug 05 04:50:16 PM PDT 24
Finished Aug 05 04:50:20 PM PDT 24
Peak memory 233384 kb
Host smart-7710c633-1a50-421c-9cbd-b691a9197eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460466617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.460466617
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.1390563402
Short name T447
Test name
Test status
Simulation time 21505283381 ps
CPU time 45.14 seconds
Started Aug 05 04:49:59 PM PDT 24
Finished Aug 05 04:50:44 PM PDT 24
Peak memory 240696 kb
Host smart-546f24e8-217d-420c-ba57-a68932645d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390563402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmd
s.1390563402
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/10.spi_device_intercept.3061578811
Short name T47
Test name
Test status
Simulation time 24726753828 ps
CPU time 15.56 seconds
Started Aug 05 04:50:13 PM PDT 24
Finished Aug 05 04:50:28 PM PDT 24
Peak memory 225176 kb
Host smart-ec578390-3c95-4c6b-b5b3-3bc04dfd65c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061578811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.3061578811
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.3381093222
Short name T486
Test name
Test status
Simulation time 58368387 ps
CPU time 2.98 seconds
Started Aug 05 04:49:57 PM PDT 24
Finished Aug 05 04:50:01 PM PDT 24
Peak memory 233336 kb
Host smart-0e7f659f-2787-42fc-8dec-da5a9e34c9b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381093222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.3381093222
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.3122656078
Short name T2
Test name
Test status
Simulation time 46388053 ps
CPU time 1.14 seconds
Started Aug 05 04:50:00 PM PDT 24
Finished Aug 05 04:50:01 PM PDT 24
Peak memory 217124 kb
Host smart-0fea6c5e-87ff-4768-8400-1f2026d38a93
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122656078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.spi_device_mem_parity.3122656078
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.3287012383
Short name T882
Test name
Test status
Simulation time 90860774 ps
CPU time 2.67 seconds
Started Aug 05 04:50:03 PM PDT 24
Finished Aug 05 04:50:11 PM PDT 24
Peak memory 232944 kb
Host smart-e82c5035-96a0-4454-8d30-366b24134e14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287012383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.3287012383
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.687940654
Short name T472
Test name
Test status
Simulation time 6700296876 ps
CPU time 13.71 seconds
Started Aug 05 04:50:07 PM PDT 24
Finished Aug 05 04:50:21 PM PDT 24
Peak memory 233372 kb
Host smart-8b6d9798-4d1e-474e-8bbd-156b49c9136d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687940654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.687940654
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.4043488791
Short name T525
Test name
Test status
Simulation time 739318888 ps
CPU time 7.4 seconds
Started Aug 05 04:49:57 PM PDT 24
Finished Aug 05 04:50:04 PM PDT 24
Peak memory 218988 kb
Host smart-df3c3d2d-8242-4a8a-a83e-63a95e8486f5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4043488791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.4043488791
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.2171847224
Short name T899
Test name
Test status
Simulation time 6121486841 ps
CPU time 23.34 seconds
Started Aug 05 04:49:58 PM PDT 24
Finished Aug 05 04:50:21 PM PDT 24
Peak memory 217040 kb
Host smart-c445fd37-7acb-4ef3-a143-008c8154b8b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171847224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.2171847224
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.4250432156
Short name T947
Test name
Test status
Simulation time 2692134249 ps
CPU time 10.54 seconds
Started Aug 05 04:49:54 PM PDT 24
Finished Aug 05 04:50:05 PM PDT 24
Peak memory 217020 kb
Host smart-4a829a38-5e9b-482c-aa50-0adbd9a2899b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250432156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.4250432156
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.1494578958
Short name T380
Test name
Test status
Simulation time 161586698 ps
CPU time 1.84 seconds
Started Aug 05 04:49:52 PM PDT 24
Finished Aug 05 04:49:54 PM PDT 24
Peak memory 216924 kb
Host smart-4f330c96-0fd3-4dff-be02-86c1288a09b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494578958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.1494578958
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.2637256053
Short name T988
Test name
Test status
Simulation time 79402453 ps
CPU time 0.82 seconds
Started Aug 05 04:50:13 PM PDT 24
Finished Aug 05 04:50:14 PM PDT 24
Peak memory 206476 kb
Host smart-a63f5f37-de89-4bbe-8cbe-a365f84b2ecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637256053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.2637256053
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.3686808368
Short name T847
Test name
Test status
Simulation time 19136453300 ps
CPU time 17.28 seconds
Started Aug 05 04:50:03 PM PDT 24
Finished Aug 05 04:50:20 PM PDT 24
Peak memory 233372 kb
Host smart-fc483ed9-26af-4928-b4bc-d9b28a595483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686808368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.3686808368
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.675713328
Short name T729
Test name
Test status
Simulation time 13898644 ps
CPU time 0.74 seconds
Started Aug 05 04:49:56 PM PDT 24
Finished Aug 05 04:50:02 PM PDT 24
Peak memory 206100 kb
Host smart-7e9d8a51-ae18-453f-b987-c66d4c99990d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675713328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.675713328
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.1192611942
Short name T194
Test name
Test status
Simulation time 230023819 ps
CPU time 3.55 seconds
Started Aug 05 04:50:28 PM PDT 24
Finished Aug 05 04:50:31 PM PDT 24
Peak memory 225172 kb
Host smart-85d29cad-3b02-48c6-bbfa-7768fd05a51f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192611942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.1192611942
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.2746310363
Short name T850
Test name
Test status
Simulation time 123456174 ps
CPU time 0.86 seconds
Started Aug 05 04:50:00 PM PDT 24
Finished Aug 05 04:50:01 PM PDT 24
Peak memory 207316 kb
Host smart-3a731da5-7970-48e9-b5dc-a029e1b5d32c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746310363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.2746310363
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.2928187004
Short name T466
Test name
Test status
Simulation time 2928732098 ps
CPU time 38.68 seconds
Started Aug 05 04:50:04 PM PDT 24
Finished Aug 05 04:50:43 PM PDT 24
Peak memory 249764 kb
Host smart-462e159d-09b5-4855-aa96-a567d0400ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928187004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.2928187004
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.4017133113
Short name T965
Test name
Test status
Simulation time 9848687210 ps
CPU time 82.99 seconds
Started Aug 05 04:50:08 PM PDT 24
Finished Aug 05 04:51:31 PM PDT 24
Peak memory 225268 kb
Host smart-91aab630-edce-48ac-baf5-d59aadac2042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017133113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.4017133113
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.4198186987
Short name T510
Test name
Test status
Simulation time 6389402214 ps
CPU time 63.33 seconds
Started Aug 05 04:50:23 PM PDT 24
Finished Aug 05 04:51:27 PM PDT 24
Peak memory 251924 kb
Host smart-e89c51ed-c12d-44c6-8d41-457e83a08824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198186987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.4198186987
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.4111308826
Short name T314
Test name
Test status
Simulation time 560921515 ps
CPU time 10.24 seconds
Started Aug 05 04:50:26 PM PDT 24
Finished Aug 05 04:50:37 PM PDT 24
Peak memory 241500 kb
Host smart-0097a6d7-f7c7-442d-bfe6-9f55ae6d6e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111308826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.4111308826
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.326806360
Short name T547
Test name
Test status
Simulation time 50657554598 ps
CPU time 89.42 seconds
Started Aug 05 04:50:07 PM PDT 24
Finished Aug 05 04:51:36 PM PDT 24
Peak memory 249832 kb
Host smart-3b6fcaf5-0cd7-412b-93de-1563576cebdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326806360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmds
.326806360
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_intercept.1626630975
Short name T813
Test name
Test status
Simulation time 289322200 ps
CPU time 5.55 seconds
Started Aug 05 04:50:14 PM PDT 24
Finished Aug 05 04:50:19 PM PDT 24
Peak memory 233324 kb
Host smart-9a4bcd89-fb96-4f6b-bd17-3f697530defb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626630975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.1626630975
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.1804653217
Short name T274
Test name
Test status
Simulation time 14993793796 ps
CPU time 32.58 seconds
Started Aug 05 04:50:05 PM PDT 24
Finished Aug 05 04:50:38 PM PDT 24
Peak memory 225176 kb
Host smart-ecc889c2-2114-46d5-8137-a2f3e1673d20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804653217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.1804653217
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.3295983167
Short name T446
Test name
Test status
Simulation time 27551119 ps
CPU time 1.07 seconds
Started Aug 05 04:49:58 PM PDT 24
Finished Aug 05 04:49:59 PM PDT 24
Peak memory 217084 kb
Host smart-25535875-91b9-44fb-93a5-36db02492540
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295983167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.spi_device_mem_parity.3295983167
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.3451505557
Short name T209
Test name
Test status
Simulation time 371475286 ps
CPU time 3.37 seconds
Started Aug 05 04:49:58 PM PDT 24
Finished Aug 05 04:50:02 PM PDT 24
Peak memory 233332 kb
Host smart-cea565fa-8a4f-4e6d-a8a5-81864d058097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451505557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.3451505557
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.1663635823
Short name T742
Test name
Test status
Simulation time 811183236 ps
CPU time 5.35 seconds
Started Aug 05 04:49:58 PM PDT 24
Finished Aug 05 04:50:03 PM PDT 24
Peak memory 233312 kb
Host smart-70bbccfe-b562-426e-a99a-02ea9e4d4292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663635823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.1663635823
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.1431376708
Short name T420
Test name
Test status
Simulation time 791294868 ps
CPU time 3.78 seconds
Started Aug 05 04:49:58 PM PDT 24
Finished Aug 05 04:50:02 PM PDT 24
Peak memory 220700 kb
Host smart-9fae26f2-9636-409d-b899-31442ab8bbb9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1431376708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.1431376708
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.2097801955
Short name T779
Test name
Test status
Simulation time 6652932778 ps
CPU time 54.89 seconds
Started Aug 05 04:50:21 PM PDT 24
Finished Aug 05 04:51:16 PM PDT 24
Peak memory 237980 kb
Host smart-34076245-dfdd-4b6f-9f6c-fc93dca969f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097801955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.2097801955
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.2071784626
Short name T430
Test name
Test status
Simulation time 3821035432 ps
CPU time 4.11 seconds
Started Aug 05 04:49:58 PM PDT 24
Finished Aug 05 04:50:02 PM PDT 24
Peak memory 216920 kb
Host smart-ceac594f-8780-4e4d-abce-3e517e2c1af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071784626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.2071784626
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.1758087217
Short name T688
Test name
Test status
Simulation time 136851223 ps
CPU time 1.96 seconds
Started Aug 05 04:49:57 PM PDT 24
Finished Aug 05 04:49:59 PM PDT 24
Peak memory 216588 kb
Host smart-69cfe9a7-f55c-4dd5-8090-db0b5144c333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758087217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.1758087217
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.4247003352
Short name T833
Test name
Test status
Simulation time 87013591 ps
CPU time 0.73 seconds
Started Aug 05 04:50:00 PM PDT 24
Finished Aug 05 04:50:01 PM PDT 24
Peak memory 206504 kb
Host smart-1cbe4430-5996-4228-a9fd-6a2e951724f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247003352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.4247003352
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.3484180595
Short name T195
Test name
Test status
Simulation time 1410003704 ps
CPU time 4.96 seconds
Started Aug 05 04:50:00 PM PDT 24
Finished Aug 05 04:50:05 PM PDT 24
Peak memory 225132 kb
Host smart-c36cf961-3d8f-4a7a-bad8-eb0b00291b96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484180595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.3484180595
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.1529300600
Short name T761
Test name
Test status
Simulation time 81982466 ps
CPU time 2.92 seconds
Started Aug 05 04:49:59 PM PDT 24
Finished Aug 05 04:50:02 PM PDT 24
Peak memory 233320 kb
Host smart-6cdbaa88-c33f-4071-9ae0-f7b76f2296eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529300600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.1529300600
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.2901150581
Short name T342
Test name
Test status
Simulation time 16534961 ps
CPU time 0.72 seconds
Started Aug 05 04:50:16 PM PDT 24
Finished Aug 05 04:50:17 PM PDT 24
Peak memory 205932 kb
Host smart-9c72b2eb-9514-43bd-8aea-ea3bf95e2a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901150581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.2901150581
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.1600030152
Short name T181
Test name
Test status
Simulation time 49112696373 ps
CPU time 90.62 seconds
Started Aug 05 04:50:09 PM PDT 24
Finished Aug 05 04:51:39 PM PDT 24
Peak memory 240892 kb
Host smart-1289fed1-560f-4820-b09d-620d4a436f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600030152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.1600030152
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.761243149
Short name T668
Test name
Test status
Simulation time 596001300630 ps
CPU time 306.22 seconds
Started Aug 05 04:50:31 PM PDT 24
Finished Aug 05 04:55:37 PM PDT 24
Peak memory 268864 kb
Host smart-c90f9a57-cf4d-4fe2-99ef-d967cb1aa60c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761243149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idle
.761243149
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.1958986404
Short name T313
Test name
Test status
Simulation time 15308011032 ps
CPU time 43.99 seconds
Started Aug 05 04:50:10 PM PDT 24
Finished Aug 05 04:50:54 PM PDT 24
Peak memory 233432 kb
Host smart-13dcbed7-6640-4f3a-80d2-6947e7f3548f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958986404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.1958986404
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.95959953
Short name T58
Test name
Test status
Simulation time 69089363669 ps
CPU time 222.55 seconds
Started Aug 05 04:50:24 PM PDT 24
Finished Aug 05 04:54:06 PM PDT 24
Peak memory 250124 kb
Host smart-dc6778e6-cc4e-4d0a-8be2-3088ce98c956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95959953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmds.95959953
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_intercept.2884241970
Short name T810
Test name
Test status
Simulation time 263056716 ps
CPU time 4.46 seconds
Started Aug 05 04:50:16 PM PDT 24
Finished Aug 05 04:50:21 PM PDT 24
Peak memory 233668 kb
Host smart-cb3f3758-ad3b-42e2-a6e0-43254a85d722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884241970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.2884241970
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.1078771098
Short name T250
Test name
Test status
Simulation time 2291517117 ps
CPU time 28.95 seconds
Started Aug 05 04:50:04 PM PDT 24
Finished Aug 05 04:50:33 PM PDT 24
Peak memory 233424 kb
Host smart-cfb26220-0c98-459e-8889-de789ef423d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078771098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.1078771098
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.3100184967
Short name T694
Test name
Test status
Simulation time 89470876 ps
CPU time 1.11 seconds
Started Aug 05 04:50:22 PM PDT 24
Finished Aug 05 04:50:24 PM PDT 24
Peak memory 217084 kb
Host smart-43d5e836-3052-4f57-86aa-96fb43cf156f
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100184967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.spi_device_mem_parity.3100184967
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.1394724733
Short name T301
Test name
Test status
Simulation time 12130410583 ps
CPU time 34.76 seconds
Started Aug 05 04:50:21 PM PDT 24
Finished Aug 05 04:50:56 PM PDT 24
Peak memory 240780 kb
Host smart-da0cfcb4-7aef-40b1-9515-b84d2157289f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394724733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.1394724733
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.1608950443
Short name T1021
Test name
Test status
Simulation time 33805986 ps
CPU time 1.99 seconds
Started Aug 05 04:50:08 PM PDT 24
Finished Aug 05 04:50:10 PM PDT 24
Peak memory 225092 kb
Host smart-d60d4c91-f7db-4ae1-841d-9b7eeecf6574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608950443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.1608950443
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.78014297
Short name T152
Test name
Test status
Simulation time 1502179848 ps
CPU time 8.87 seconds
Started Aug 05 04:50:20 PM PDT 24
Finished Aug 05 04:50:29 PM PDT 24
Peak memory 222900 kb
Host smart-ca207c46-2847-4c06-a05c-3d68d3cec382
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=78014297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_direc
t.78014297
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.4037508920
Short name T863
Test name
Test status
Simulation time 1742339230 ps
CPU time 13.83 seconds
Started Aug 05 04:50:03 PM PDT 24
Finished Aug 05 04:50:17 PM PDT 24
Peak memory 216996 kb
Host smart-8b2fc8e2-078d-4a25-9d2b-a085e36a5b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037508920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.4037508920
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.1611369813
Short name T719
Test name
Test status
Simulation time 4839143841 ps
CPU time 7.63 seconds
Started Aug 05 04:50:17 PM PDT 24
Finished Aug 05 04:50:25 PM PDT 24
Peak memory 216976 kb
Host smart-a4e7c344-2f75-4b30-97d9-eaaeb5d490f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611369813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.1611369813
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.215310002
Short name T358
Test name
Test status
Simulation time 90968570 ps
CPU time 1.84 seconds
Started Aug 05 04:50:01 PM PDT 24
Finished Aug 05 04:50:03 PM PDT 24
Peak memory 216924 kb
Host smart-e34e362b-6fce-438b-8ecb-6af5e1ae163e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215310002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.215310002
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.2014495093
Short name T836
Test name
Test status
Simulation time 30026629 ps
CPU time 0.76 seconds
Started Aug 05 04:50:24 PM PDT 24
Finished Aug 05 04:50:25 PM PDT 24
Peak memory 206476 kb
Host smart-9b3d998e-5f1e-4448-bd3d-445e40650ba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014495093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.2014495093
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.970181713
Short name T715
Test name
Test status
Simulation time 35026924 ps
CPU time 2.18 seconds
Started Aug 05 04:50:02 PM PDT 24
Finished Aug 05 04:50:04 PM PDT 24
Peak memory 224736 kb
Host smart-949d4f0f-9bc9-44c4-b99b-f7762bf2095b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970181713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.970181713
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.3781795251
Short name T666
Test name
Test status
Simulation time 11762992 ps
CPU time 0.76 seconds
Started Aug 05 04:50:42 PM PDT 24
Finished Aug 05 04:50:43 PM PDT 24
Peak memory 206136 kb
Host smart-6abc7743-b175-47d0-b54c-c11637c4d8b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781795251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
3781795251
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.314634536
Short name T635
Test name
Test status
Simulation time 147600017 ps
CPU time 2.83 seconds
Started Aug 05 04:50:03 PM PDT 24
Finished Aug 05 04:50:06 PM PDT 24
Peak memory 233312 kb
Host smart-9a0b484e-d7d8-482a-a3fd-5751b9f78244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314634536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.314634536
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.2518617622
Short name T604
Test name
Test status
Simulation time 53496350 ps
CPU time 0.76 seconds
Started Aug 05 04:49:59 PM PDT 24
Finished Aug 05 04:50:00 PM PDT 24
Peak memory 207268 kb
Host smart-d63b854c-936a-4565-86b3-f6ffc304b99f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518617622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.2518617622
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.3577071938
Short name T550
Test name
Test status
Simulation time 54593263281 ps
CPU time 197.25 seconds
Started Aug 05 04:50:15 PM PDT 24
Finished Aug 05 04:53:32 PM PDT 24
Peak memory 249924 kb
Host smart-6aa3c62f-5769-4979-bc84-776d15066ea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577071938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.3577071938
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.835353058
Short name T593
Test name
Test status
Simulation time 19414465675 ps
CPU time 174.22 seconds
Started Aug 05 04:50:07 PM PDT 24
Finished Aug 05 04:53:01 PM PDT 24
Peak memory 251160 kb
Host smart-11f860a0-5860-4ae1-8975-792aed65c76c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835353058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.835353058
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.2048037103
Short name T137
Test name
Test status
Simulation time 12421897312 ps
CPU time 35.72 seconds
Started Aug 05 04:50:05 PM PDT 24
Finished Aug 05 04:50:41 PM PDT 24
Peak memory 242020 kb
Host smart-4440d6ac-b74a-4628-81a8-bc158d808111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048037103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.2048037103
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.3520281163
Short name T359
Test name
Test status
Simulation time 232290384 ps
CPU time 3.69 seconds
Started Aug 05 04:50:11 PM PDT 24
Finished Aug 05 04:50:15 PM PDT 24
Peak memory 230380 kb
Host smart-d487e462-0537-4d71-b9db-8072e94e0aeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520281163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.3520281163
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.756413507
Short name T880
Test name
Test status
Simulation time 89727757787 ps
CPU time 76.26 seconds
Started Aug 05 04:50:15 PM PDT 24
Finished Aug 05 04:51:31 PM PDT 24
Peak memory 250216 kb
Host smart-26445a1a-55db-4304-8582-e1cd3c62705d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756413507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmds
.756413507
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/13.spi_device_intercept.1233322829
Short name T765
Test name
Test status
Simulation time 88661313 ps
CPU time 2.62 seconds
Started Aug 05 04:50:00 PM PDT 24
Finished Aug 05 04:50:03 PM PDT 24
Peak memory 225200 kb
Host smart-8d05ad0c-b30a-4d5d-bcf4-d2c18df945a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233322829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.1233322829
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.2222178260
Short name T827
Test name
Test status
Simulation time 634697996 ps
CPU time 7.21 seconds
Started Aug 05 04:50:05 PM PDT 24
Finished Aug 05 04:50:23 PM PDT 24
Peak memory 234764 kb
Host smart-4f8c2209-4faa-47e5-a1e7-5522730e8582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222178260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.2222178260
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.2716582644
Short name T962
Test name
Test status
Simulation time 124222277 ps
CPU time 1.09 seconds
Started Aug 05 04:50:24 PM PDT 24
Finished Aug 05 04:50:25 PM PDT 24
Peak memory 217328 kb
Host smart-f3fcdcd6-2bc6-4473-b656-9b78cc92d22f
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716582644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.spi_device_mem_parity.2716582644
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.1958902137
Short name T225
Test name
Test status
Simulation time 64130686 ps
CPU time 2.02 seconds
Started Aug 05 04:50:14 PM PDT 24
Finished Aug 05 04:50:17 PM PDT 24
Peak memory 225336 kb
Host smart-85f25a1c-981d-4021-b4f4-789754747737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958902137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.1958902137
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.2561346134
Short name T236
Test name
Test status
Simulation time 11106065994 ps
CPU time 17.53 seconds
Started Aug 05 04:50:21 PM PDT 24
Finished Aug 05 04:50:39 PM PDT 24
Peak memory 225236 kb
Host smart-7a910933-15d1-4ca5-b552-79871d933f70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561346134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.2561346134
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.2237791267
Short name T695
Test name
Test status
Simulation time 1260550327 ps
CPU time 5.06 seconds
Started Aug 05 04:49:58 PM PDT 24
Finished Aug 05 04:50:03 PM PDT 24
Peak memory 219744 kb
Host smart-bab1f3da-0ff5-4637-8e39-523fd418d0e1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2237791267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.2237791267
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.1889444242
Short name T900
Test name
Test status
Simulation time 16584021172 ps
CPU time 83.46 seconds
Started Aug 05 04:50:28 PM PDT 24
Finished Aug 05 04:51:52 PM PDT 24
Peak memory 256864 kb
Host smart-2c442368-2259-472e-b1a4-1f042442ccb1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889444242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.1889444242
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.2519978045
Short name T657
Test name
Test status
Simulation time 3008707815 ps
CPU time 25.43 seconds
Started Aug 05 04:50:09 PM PDT 24
Finished Aug 05 04:50:35 PM PDT 24
Peak memory 221092 kb
Host smart-dd3bd64e-6a4c-4df8-8973-9af840d323b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519978045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.2519978045
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.131017091
Short name T452
Test name
Test status
Simulation time 43458142499 ps
CPU time 10.17 seconds
Started Aug 05 04:50:05 PM PDT 24
Finished Aug 05 04:50:16 PM PDT 24
Peak memory 216920 kb
Host smart-222056e8-db84-4d81-9dd7-fbd16a6cd922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131017091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.131017091
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.2311826500
Short name T394
Test name
Test status
Simulation time 88138729 ps
CPU time 1.14 seconds
Started Aug 05 04:50:11 PM PDT 24
Finished Aug 05 04:50:12 PM PDT 24
Peak memory 207660 kb
Host smart-a19305e8-d6be-439c-8fa3-9ddada9fd767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311826500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.2311826500
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.2218138856
Short name T1015
Test name
Test status
Simulation time 93186380 ps
CPU time 0.77 seconds
Started Aug 05 04:50:04 PM PDT 24
Finished Aug 05 04:50:05 PM PDT 24
Peak memory 206472 kb
Host smart-376e418b-5e17-4c04-bf65-a5867b67ce01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218138856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.2218138856
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.3191001025
Short name T881
Test name
Test status
Simulation time 157554563 ps
CPU time 2.7 seconds
Started Aug 05 04:50:02 PM PDT 24
Finished Aug 05 04:50:05 PM PDT 24
Peak memory 225212 kb
Host smart-62d93513-435a-48e7-b436-7531a7d8f2bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191001025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.3191001025
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.2464901930
Short name T542
Test name
Test status
Simulation time 39606179 ps
CPU time 0.69 seconds
Started Aug 05 04:50:07 PM PDT 24
Finished Aug 05 04:50:08 PM PDT 24
Peak memory 205288 kb
Host smart-065e3c53-8cf8-483b-9179-a9c439d61a16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464901930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
2464901930
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.2591095032
Short name T917
Test name
Test status
Simulation time 777271741 ps
CPU time 3.42 seconds
Started Aug 05 04:50:15 PM PDT 24
Finished Aug 05 04:50:18 PM PDT 24
Peak memory 225128 kb
Host smart-c1783944-a624-496a-a962-95ea487a4206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591095032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.2591095032
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.1014923340
Short name T646
Test name
Test status
Simulation time 36811555 ps
CPU time 0.73 seconds
Started Aug 05 04:50:08 PM PDT 24
Finished Aug 05 04:50:09 PM PDT 24
Peak memory 206980 kb
Host smart-e2a8573e-da9a-4065-a8fa-aa8eb5ad006e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014923340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.1014923340
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.4072024643
Short name T287
Test name
Test status
Simulation time 2923514519 ps
CPU time 70.04 seconds
Started Aug 05 04:50:06 PM PDT 24
Finished Aug 05 04:51:16 PM PDT 24
Peak memory 252152 kb
Host smart-81a39106-d2c0-4d45-a14a-4bed8bd33050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072024643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.4072024643
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.1347502421
Short name T750
Test name
Test status
Simulation time 15052827332 ps
CPU time 45.22 seconds
Started Aug 05 04:50:18 PM PDT 24
Finished Aug 05 04:51:03 PM PDT 24
Peak memory 240532 kb
Host smart-0ae8e69f-d581-4a9d-afeb-80c0ee345414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347502421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.1347502421
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.2346399773
Short name T54
Test name
Test status
Simulation time 37262701426 ps
CPU time 197.94 seconds
Started Aug 05 04:50:16 PM PDT 24
Finished Aug 05 04:53:34 PM PDT 24
Peak memory 252344 kb
Host smart-a22ae8a5-b732-4edc-9e16-538a2be4a956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346399773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.2346399773
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.3761494876
Short name T351
Test name
Test status
Simulation time 737305887 ps
CPU time 3.74 seconds
Started Aug 05 04:50:03 PM PDT 24
Finished Aug 05 04:50:07 PM PDT 24
Peak memory 225100 kb
Host smart-0e89d5bc-83cf-4280-afb3-087b7ce4c150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761494876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.3761494876
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.2088049303
Short name T871
Test name
Test status
Simulation time 13148078549 ps
CPU time 44.19 seconds
Started Aug 05 04:50:25 PM PDT 24
Finished Aug 05 04:51:10 PM PDT 24
Peak memory 249808 kb
Host smart-913ca227-5016-4001-aea6-561ebd124274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088049303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmd
s.2088049303
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/14.spi_device_intercept.1724532358
Short name T916
Test name
Test status
Simulation time 215739765 ps
CPU time 3.19 seconds
Started Aug 05 04:50:05 PM PDT 24
Finished Aug 05 04:50:08 PM PDT 24
Peak memory 233384 kb
Host smart-8a797301-1a94-432f-9a9d-35b99ea288c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724532358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.1724532358
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.2446544925
Short name T260
Test name
Test status
Simulation time 17720826634 ps
CPU time 128.17 seconds
Started Aug 05 04:50:18 PM PDT 24
Finished Aug 05 04:52:26 PM PDT 24
Peak memory 233468 kb
Host smart-9c428373-e0aa-471e-a02e-62d61874f228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446544925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.2446544925
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.1930189648
Short name T697
Test name
Test status
Simulation time 63701808 ps
CPU time 1.12 seconds
Started Aug 05 04:50:03 PM PDT 24
Finished Aug 05 04:50:04 PM PDT 24
Peak memory 217096 kb
Host smart-ce0193f2-a30d-446b-8921-6e0583fc12d8
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930189648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.spi_device_mem_parity.1930189648
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.3984728088
Short name T12
Test name
Test status
Simulation time 396145105 ps
CPU time 3.49 seconds
Started Aug 05 04:50:01 PM PDT 24
Finished Aug 05 04:50:04 PM PDT 24
Peak memory 225088 kb
Host smart-95350927-7d51-428a-a6ab-1539831f8d76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984728088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.3984728088
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.1874712036
Short name T562
Test name
Test status
Simulation time 371926387 ps
CPU time 3.33 seconds
Started Aug 05 04:50:20 PM PDT 24
Finished Aug 05 04:50:23 PM PDT 24
Peak memory 233356 kb
Host smart-11edb985-7e0e-4541-8014-a7d4eeee6867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874712036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.1874712036
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.1310053782
Short name T79
Test name
Test status
Simulation time 1114085743 ps
CPU time 5.72 seconds
Started Aug 05 04:50:50 PM PDT 24
Finished Aug 05 04:50:55 PM PDT 24
Peak memory 223580 kb
Host smart-4113053f-91d2-472f-af7f-c23b014487f5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1310053782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.1310053782
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.2787297740
Short name T162
Test name
Test status
Simulation time 40201346 ps
CPU time 0.89 seconds
Started Aug 05 04:50:00 PM PDT 24
Finished Aug 05 04:50:01 PM PDT 24
Peak memory 205980 kb
Host smart-1e2f494e-4d5f-4dfd-adc3-ef84c692b87b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787297740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.2787297740
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.4155960756
Short name T556
Test name
Test status
Simulation time 9322331157 ps
CPU time 26.5 seconds
Started Aug 05 04:50:02 PM PDT 24
Finished Aug 05 04:50:29 PM PDT 24
Peak memory 216976 kb
Host smart-28c9a54a-b448-43ad-9c9e-3c2865b84377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155960756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.4155960756
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.452215434
Short name T797
Test name
Test status
Simulation time 350038755 ps
CPU time 2.03 seconds
Started Aug 05 04:50:00 PM PDT 24
Finished Aug 05 04:50:02 PM PDT 24
Peak memory 216864 kb
Host smart-83f8e666-845f-49d6-9ba1-06fddd0e6734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452215434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.452215434
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.2788265590
Short name T464
Test name
Test status
Simulation time 27596437 ps
CPU time 0.8 seconds
Started Aug 05 04:50:35 PM PDT 24
Finished Aug 05 04:50:36 PM PDT 24
Peak memory 206392 kb
Host smart-f6588fe6-d840-4b1a-916b-868f6e44a155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788265590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.2788265590
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.1834485842
Short name T75
Test name
Test status
Simulation time 6728514574 ps
CPU time 10.29 seconds
Started Aug 05 04:50:20 PM PDT 24
Finished Aug 05 04:50:30 PM PDT 24
Peak memory 233376 kb
Host smart-3598205f-66b6-42e9-906e-d3d43e22bf02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834485842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.1834485842
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.3349268957
Short name T356
Test name
Test status
Simulation time 14863336 ps
CPU time 0.7 seconds
Started Aug 05 04:50:24 PM PDT 24
Finished Aug 05 04:50:25 PM PDT 24
Peak memory 205768 kb
Host smart-559d7dbc-fa1a-4ffd-8c9c-ab1767a5257e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349268957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
3349268957
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.1204267609
Short name T914
Test name
Test status
Simulation time 555944596 ps
CPU time 4.29 seconds
Started Aug 05 04:50:00 PM PDT 24
Finished Aug 05 04:50:04 PM PDT 24
Peak memory 233304 kb
Host smart-13454fd0-c28b-4285-8c3b-02df9fbbe675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204267609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.1204267609
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.1173819064
Short name T381
Test name
Test status
Simulation time 34818802 ps
CPU time 0.78 seconds
Started Aug 05 04:50:19 PM PDT 24
Finished Aug 05 04:50:20 PM PDT 24
Peak memory 206960 kb
Host smart-caa03841-e03a-4032-bc1a-1bd7df5bb130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173819064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.1173819064
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.2725810291
Short name T485
Test name
Test status
Simulation time 130217165686 ps
CPU time 221.76 seconds
Started Aug 05 04:50:16 PM PDT 24
Finished Aug 05 04:53:58 PM PDT 24
Peak memory 266220 kb
Host smart-2243f889-18c3-4042-a0c9-b22641e88c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725810291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.2725810291
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.692676365
Short name T216
Test name
Test status
Simulation time 3775627045 ps
CPU time 76.15 seconds
Started Aug 05 04:50:13 PM PDT 24
Finished Aug 05 04:51:29 PM PDT 24
Peak memory 256168 kb
Host smart-6ecd9578-7df1-493a-b6c0-d771c677eaf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692676365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.692676365
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.1717307388
Short name T640
Test name
Test status
Simulation time 77148652775 ps
CPU time 182.16 seconds
Started Aug 05 04:50:18 PM PDT 24
Finished Aug 05 04:53:20 PM PDT 24
Peak memory 249896 kb
Host smart-d84a76f7-41fb-457d-8366-d157e2cd86d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717307388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.1717307388
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.3985504754
Short name T1022
Test name
Test status
Simulation time 8815299235 ps
CPU time 27.33 seconds
Started Aug 05 04:50:08 PM PDT 24
Finished Aug 05 04:50:36 PM PDT 24
Peak memory 241612 kb
Host smart-b1d2c9b8-952a-4f30-bff6-c41fd78331f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985504754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.3985504754
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.690428002
Short name T908
Test name
Test status
Simulation time 17051085 ps
CPU time 0.78 seconds
Started Aug 05 04:50:12 PM PDT 24
Finished Aug 05 04:50:13 PM PDT 24
Peak memory 216348 kb
Host smart-2e839df6-8fb2-4ea4-9d1c-8e5beacdb8f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690428002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmds
.690428002
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/15.spi_device_intercept.2567031976
Short name T515
Test name
Test status
Simulation time 120596510 ps
CPU time 2.42 seconds
Started Aug 05 04:50:08 PM PDT 24
Finished Aug 05 04:50:11 PM PDT 24
Peak memory 232980 kb
Host smart-bd557472-ac99-4981-82cd-3d6e942dee0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567031976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.2567031976
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.3943106825
Short name T507
Test name
Test status
Simulation time 348760052 ps
CPU time 7.65 seconds
Started Aug 05 04:50:09 PM PDT 24
Finished Aug 05 04:50:17 PM PDT 24
Peak memory 225120 kb
Host smart-74ebf827-19ad-4bf4-a2ec-d5aa0319746c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943106825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.3943106825
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.1263035484
Short name T671
Test name
Test status
Simulation time 28231410 ps
CPU time 1.02 seconds
Started Aug 05 04:50:24 PM PDT 24
Finished Aug 05 04:50:25 PM PDT 24
Peak memory 218404 kb
Host smart-cf159121-3573-4940-a5f6-d46a1c2d6da3
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263035484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.spi_device_mem_parity.1263035484
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.2283627885
Short name T717
Test name
Test status
Simulation time 12781385435 ps
CPU time 16.27 seconds
Started Aug 05 04:50:41 PM PDT 24
Finished Aug 05 04:50:57 PM PDT 24
Peak memory 225144 kb
Host smart-0812b646-a083-45fb-a968-16915c30db95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283627885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.2283627885
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.2127062711
Short name T584
Test name
Test status
Simulation time 1110302600 ps
CPU time 5.57 seconds
Started Aug 05 04:50:21 PM PDT 24
Finished Aug 05 04:50:27 PM PDT 24
Peak memory 225148 kb
Host smart-b7202d53-f2de-4acb-8f8a-f3a319ce69d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127062711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.2127062711
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.1079646174
Short name T692
Test name
Test status
Simulation time 9501980714 ps
CPU time 13.99 seconds
Started Aug 05 04:50:25 PM PDT 24
Finished Aug 05 04:50:39 PM PDT 24
Peak memory 222136 kb
Host smart-ed48ec22-14ba-4bdc-9a23-2fccd5ef8264
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1079646174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.1079646174
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.354834405
Short name T166
Test name
Test status
Simulation time 130374037 ps
CPU time 0.9 seconds
Started Aug 05 04:50:06 PM PDT 24
Finished Aug 05 04:50:07 PM PDT 24
Peak memory 207756 kb
Host smart-471eebf0-ef71-44a4-bc0d-b514c917e971
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354834405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stres
s_all.354834405
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.3145069486
Short name T681
Test name
Test status
Simulation time 124641220 ps
CPU time 0.71 seconds
Started Aug 05 04:50:24 PM PDT 24
Finished Aug 05 04:50:25 PM PDT 24
Peak memory 206108 kb
Host smart-edb3e1be-23a1-452d-b8ad-bb307cd73bc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145069486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.3145069486
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.1063254800
Short name T778
Test name
Test status
Simulation time 2154317771 ps
CPU time 5.44 seconds
Started Aug 05 04:50:14 PM PDT 24
Finished Aug 05 04:50:19 PM PDT 24
Peak memory 216956 kb
Host smart-5f1b65ab-2de4-4a9f-8533-bd702334cdbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063254800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.1063254800
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.3159787150
Short name T582
Test name
Test status
Simulation time 60972546 ps
CPU time 0.84 seconds
Started Aug 05 04:49:53 PM PDT 24
Finished Aug 05 04:49:54 PM PDT 24
Peak memory 206612 kb
Host smart-a343bc96-b778-4140-8392-c78e88a1c3a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159787150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.3159787150
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.501573623
Short name T139
Test name
Test status
Simulation time 228381063 ps
CPU time 0.98 seconds
Started Aug 05 04:50:06 PM PDT 24
Finished Aug 05 04:50:12 PM PDT 24
Peak memory 207588 kb
Host smart-b95109cc-ff0e-4f6d-8f90-2682512825f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501573623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.501573623
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.375743073
Short name T494
Test name
Test status
Simulation time 21111916880 ps
CPU time 19.49 seconds
Started Aug 05 04:50:44 PM PDT 24
Finished Aug 05 04:51:04 PM PDT 24
Peak memory 249568 kb
Host smart-a6c0d31d-0e98-4c1d-8858-7f9b09c0be2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375743073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.375743073
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.1467339661
Short name T751
Test name
Test status
Simulation time 37948313 ps
CPU time 0.74 seconds
Started Aug 05 04:50:27 PM PDT 24
Finished Aug 05 04:50:28 PM PDT 24
Peak memory 205196 kb
Host smart-4f4913ac-2849-4d8b-86ea-44f3a68175d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467339661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
1467339661
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.1797938070
Short name T617
Test name
Test status
Simulation time 552146247 ps
CPU time 6.92 seconds
Started Aug 05 04:50:25 PM PDT 24
Finished Aug 05 04:50:32 PM PDT 24
Peak memory 233208 kb
Host smart-eeba0ffd-3a9e-46e8-a15b-ed55edbfee0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797938070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.1797938070
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.3807677597
Short name T413
Test name
Test status
Simulation time 19559157 ps
CPU time 0.75 seconds
Started Aug 05 04:50:12 PM PDT 24
Finished Aug 05 04:50:13 PM PDT 24
Peak memory 207280 kb
Host smart-7954ead5-1049-41de-a170-959941cbb398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807677597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.3807677597
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.2171544356
Short name T208
Test name
Test status
Simulation time 1149924256 ps
CPU time 24.3 seconds
Started Aug 05 04:50:03 PM PDT 24
Finished Aug 05 04:50:27 PM PDT 24
Peak memory 241556 kb
Host smart-46398a49-f960-46bb-811f-d41873e49550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171544356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.2171544356
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.1865589310
Short name T308
Test name
Test status
Simulation time 4074004613 ps
CPU time 111.32 seconds
Started Aug 05 04:50:11 PM PDT 24
Finished Aug 05 04:52:02 PM PDT 24
Peak memory 254868 kb
Host smart-f46c51ea-b403-4ed1-8ff3-7d3f9ec9ea33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865589310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.1865589310
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.981571272
Short name T230
Test name
Test status
Simulation time 6724718822 ps
CPU time 138.59 seconds
Started Aug 05 04:50:24 PM PDT 24
Finished Aug 05 04:52:43 PM PDT 24
Peak memory 252784 kb
Host smart-f21c2716-8d71-49c3-a55b-dec6f3d8a872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981571272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idle
.981571272
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.1208135573
Short name T362
Test name
Test status
Simulation time 4426179935 ps
CPU time 12.15 seconds
Started Aug 05 04:50:11 PM PDT 24
Finished Aug 05 04:50:23 PM PDT 24
Peak memory 233428 kb
Host smart-00087737-fd3d-4912-8bbd-89aa5111d8c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208135573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.1208135573
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.3857685044
Short name T726
Test name
Test status
Simulation time 4812591306 ps
CPU time 20.55 seconds
Started Aug 05 04:50:12 PM PDT 24
Finished Aug 05 04:50:32 PM PDT 24
Peak memory 235968 kb
Host smart-4ad25cbe-7b46-45ac-bfc3-4ff29cbba953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857685044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmd
s.3857685044
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/16.spi_device_intercept.654446496
Short name T748
Test name
Test status
Simulation time 1146158325 ps
CPU time 12.07 seconds
Started Aug 05 04:50:19 PM PDT 24
Finished Aug 05 04:50:31 PM PDT 24
Peak memory 225184 kb
Host smart-2b62724a-9707-42bb-9131-80db09a0c148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654446496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.654446496
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.2060256274
Short name T55
Test name
Test status
Simulation time 15230023977 ps
CPU time 59.69 seconds
Started Aug 05 04:50:07 PM PDT 24
Finished Aug 05 04:51:06 PM PDT 24
Peak memory 249932 kb
Host smart-08f00ba6-f163-469e-8f05-c2a1d5309ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060256274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.2060256274
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.3884117347
Short name T835
Test name
Test status
Simulation time 60927981 ps
CPU time 1.01 seconds
Started Aug 05 04:50:11 PM PDT 24
Finished Aug 05 04:50:12 PM PDT 24
Peak memory 217116 kb
Host smart-2c2aae6e-fcca-4974-923d-1656798f5e12
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884117347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.spi_device_mem_parity.3884117347
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.861508894
Short name T985
Test name
Test status
Simulation time 60891883 ps
CPU time 2.44 seconds
Started Aug 05 04:50:01 PM PDT 24
Finished Aug 05 04:50:04 PM PDT 24
Peak memory 232956 kb
Host smart-fb13751a-e0ab-460a-b7e6-a70fc0bb1ac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861508894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swap
.861508894
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.3080824092
Short name T93
Test name
Test status
Simulation time 1430923965 ps
CPU time 10.94 seconds
Started Aug 05 04:50:32 PM PDT 24
Finished Aug 05 04:50:43 PM PDT 24
Peak memory 234536 kb
Host smart-dc0bd9c2-86d9-4e2f-96d3-7d59459d888c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080824092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.3080824092
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.1143286223
Short name T374
Test name
Test status
Simulation time 4185955470 ps
CPU time 8.05 seconds
Started Aug 05 04:50:07 PM PDT 24
Finished Aug 05 04:50:15 PM PDT 24
Peak memory 222716 kb
Host smart-739e21e2-5ac8-4e1f-9c61-f1225f30cc77
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1143286223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.1143286223
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.491491188
Short name T23
Test name
Test status
Simulation time 2353892443 ps
CPU time 50.83 seconds
Started Aug 05 04:50:05 PM PDT 24
Finished Aug 05 04:50:56 PM PDT 24
Peak memory 249964 kb
Host smart-ca203920-4f82-49cc-8f07-2159a9f4e01c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491491188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stres
s_all.491491188
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.2931981853
Short name T841
Test name
Test status
Simulation time 1387118675 ps
CPU time 3.72 seconds
Started Aug 05 04:50:12 PM PDT 24
Finished Aug 05 04:50:16 PM PDT 24
Peak memory 219604 kb
Host smart-f3763840-d6c3-4379-9b1c-83ecf0d6ef2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931981853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.2931981853
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.829134393
Short name T953
Test name
Test status
Simulation time 1026584396 ps
CPU time 7.3 seconds
Started Aug 05 04:50:10 PM PDT 24
Finished Aug 05 04:50:18 PM PDT 24
Peak memory 216872 kb
Host smart-4e8e2b9b-43c1-4ef3-bce4-70c3c2757a03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829134393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.829134393
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.4088595203
Short name T360
Test name
Test status
Simulation time 56328058 ps
CPU time 0.9 seconds
Started Aug 05 04:50:00 PM PDT 24
Finished Aug 05 04:50:01 PM PDT 24
Peak memory 206504 kb
Host smart-8964f9c2-3d5d-4fd6-90d6-65e31fd5033a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088595203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.4088595203
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.1037425519
Short name T451
Test name
Test status
Simulation time 89884691 ps
CPU time 0.75 seconds
Started Aug 05 04:50:33 PM PDT 24
Finished Aug 05 04:50:34 PM PDT 24
Peak memory 206512 kb
Host smart-c76f5a07-30ad-4eca-9c2f-c30616a3bce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037425519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.1037425519
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.1058534445
Short name T257
Test name
Test status
Simulation time 1266233441 ps
CPU time 5.43 seconds
Started Aug 05 04:50:11 PM PDT 24
Finished Aug 05 04:50:17 PM PDT 24
Peak memory 225252 kb
Host smart-93686a1e-ce49-45ef-877a-968261b280cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058534445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.1058534445
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.2968178224
Short name T419
Test name
Test status
Simulation time 14306434 ps
CPU time 0.77 seconds
Started Aug 05 04:50:20 PM PDT 24
Finished Aug 05 04:50:21 PM PDT 24
Peak memory 206072 kb
Host smart-444bc286-35fe-466e-a0fe-5d5b6a617600
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968178224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
2968178224
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.3232293866
Short name T780
Test name
Test status
Simulation time 214779152 ps
CPU time 3.85 seconds
Started Aug 05 04:50:25 PM PDT 24
Finished Aug 05 04:50:29 PM PDT 24
Peak memory 225100 kb
Host smart-1290a170-2f98-43b7-8025-5cc55282f491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232293866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.3232293866
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.3743997504
Short name T469
Test name
Test status
Simulation time 197325608 ps
CPU time 0.73 seconds
Started Aug 05 04:50:11 PM PDT 24
Finished Aug 05 04:50:12 PM PDT 24
Peak memory 205932 kb
Host smart-9abbcdd3-5a38-45e2-968c-bede12849978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743997504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.3743997504
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.3373239537
Short name T1008
Test name
Test status
Simulation time 38345115748 ps
CPU time 106.27 seconds
Started Aug 05 04:50:10 PM PDT 24
Finished Aug 05 04:51:57 PM PDT 24
Peak memory 253528 kb
Host smart-a8279e41-02a4-49f1-9c5a-d9bb012a5340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373239537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.3373239537
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.2107195925
Short name T289
Test name
Test status
Simulation time 42982388797 ps
CPU time 148.72 seconds
Started Aug 05 04:50:23 PM PDT 24
Finished Aug 05 04:52:52 PM PDT 24
Peak memory 265012 kb
Host smart-e1881824-f2d5-46c7-96e9-52e21e2b3b66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107195925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.2107195925
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.109514357
Short name T752
Test name
Test status
Simulation time 230200711 ps
CPU time 4.04 seconds
Started Aug 05 04:50:39 PM PDT 24
Finished Aug 05 04:50:43 PM PDT 24
Peak memory 233280 kb
Host smart-27eb0c73-8d45-402d-b84a-b8c05206c06d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109514357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.109514357
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.1651154876
Short name T676
Test name
Test status
Simulation time 1020695241 ps
CPU time 15.86 seconds
Started Aug 05 04:50:10 PM PDT 24
Finished Aug 05 04:50:26 PM PDT 24
Peak memory 239500 kb
Host smart-053ac0ed-e338-4a7b-b0fa-8dd5efbead64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651154876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmd
s.1651154876
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/17.spi_device_intercept.1061673443
Short name T340
Test name
Test status
Simulation time 60043794 ps
CPU time 2.41 seconds
Started Aug 05 04:50:12 PM PDT 24
Finished Aug 05 04:50:15 PM PDT 24
Peak memory 233008 kb
Host smart-588a8fa1-94cd-4346-9120-0e9a6a3b8f2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061673443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.1061673443
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.3391703543
Short name T217
Test name
Test status
Simulation time 1657705499 ps
CPU time 24.95 seconds
Started Aug 05 04:50:23 PM PDT 24
Finished Aug 05 04:50:48 PM PDT 24
Peak memory 249760 kb
Host smart-a0b56090-fd51-435c-b815-0b982e86067b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391703543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.3391703543
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.630938680
Short name T465
Test name
Test status
Simulation time 33519635 ps
CPU time 1.13 seconds
Started Aug 05 04:50:01 PM PDT 24
Finished Aug 05 04:50:02 PM PDT 24
Peak memory 217108 kb
Host smart-c3683de9-4fcb-4bad-95f2-a4754b3320d4
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630938680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.spi_device_mem_parity.630938680
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.67353658
Short name T213
Test name
Test status
Simulation time 480456497 ps
CPU time 7.69 seconds
Started Aug 05 04:50:07 PM PDT 24
Finished Aug 05 04:50:15 PM PDT 24
Peak memory 239692 kb
Host smart-e4c57fdd-0973-40c4-8161-51df96f4f411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67353658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swap.67353658
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.3071185534
Short name T261
Test name
Test status
Simulation time 14919626591 ps
CPU time 11.45 seconds
Started Aug 05 04:50:11 PM PDT 24
Finished Aug 05 04:50:22 PM PDT 24
Peak memory 241536 kb
Host smart-9fb3bffc-51b4-4a37-a6b5-596d640cd368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071185534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.3071185534
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.1072060983
Short name T536
Test name
Test status
Simulation time 799846502 ps
CPU time 4.47 seconds
Started Aug 05 04:50:29 PM PDT 24
Finished Aug 05 04:50:33 PM PDT 24
Peak memory 223760 kb
Host smart-9e538ef9-b1c4-40c5-95f3-914f01bb8b33
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1072060983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.1072060983
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.3149919029
Short name T475
Test name
Test status
Simulation time 17565020428 ps
CPU time 18.71 seconds
Started Aug 05 04:50:27 PM PDT 24
Finished Aug 05 04:50:45 PM PDT 24
Peak memory 217080 kb
Host smart-7d09ddc8-478d-4e70-86db-c89403feb8b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149919029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.3149919029
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.2434979416
Short name T578
Test name
Test status
Simulation time 732263454 ps
CPU time 3.75 seconds
Started Aug 05 04:50:30 PM PDT 24
Finished Aug 05 04:50:34 PM PDT 24
Peak memory 216976 kb
Host smart-487a0f60-d47c-4876-9967-dac55955dfae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434979416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.2434979416
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.1981940816
Short name T763
Test name
Test status
Simulation time 18612437 ps
CPU time 0.81 seconds
Started Aug 05 04:50:14 PM PDT 24
Finished Aug 05 04:50:15 PM PDT 24
Peak memory 206484 kb
Host smart-b144b36f-70e8-4645-a9f8-eca907526d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981940816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.1981940816
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.1331279620
Short name T497
Test name
Test status
Simulation time 188132664 ps
CPU time 0.79 seconds
Started Aug 05 04:50:24 PM PDT 24
Finished Aug 05 04:50:25 PM PDT 24
Peak memory 206520 kb
Host smart-af37546c-638f-46c5-b498-4df1bac2888e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331279620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.1331279620
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.2784124788
Short name T277
Test name
Test status
Simulation time 5692813714 ps
CPU time 21.99 seconds
Started Aug 05 04:50:14 PM PDT 24
Finished Aug 05 04:50:36 PM PDT 24
Peak memory 241640 kb
Host smart-3ef9c026-793d-4f6b-b295-1398fc64359c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784124788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.2784124788
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.3239715855
Short name T370
Test name
Test status
Simulation time 26903708 ps
CPU time 0.77 seconds
Started Aug 05 04:50:26 PM PDT 24
Finished Aug 05 04:50:27 PM PDT 24
Peak memory 205736 kb
Host smart-39260ffe-51c7-4d9c-9c8c-909ac126ce22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239715855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
3239715855
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.1933980031
Short name T993
Test name
Test status
Simulation time 750441840 ps
CPU time 3.86 seconds
Started Aug 05 04:50:14 PM PDT 24
Finished Aug 05 04:50:18 PM PDT 24
Peak memory 225444 kb
Host smart-875d37c5-66a6-4434-ad5e-499f77b70cdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933980031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.1933980031
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.3722913052
Short name T670
Test name
Test status
Simulation time 21927981 ps
CPU time 0.79 seconds
Started Aug 05 04:50:17 PM PDT 24
Finished Aug 05 04:50:18 PM PDT 24
Peak memory 206284 kb
Host smart-5075f5d8-507b-4924-b61e-3e99cbb91038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722913052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.3722913052
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.2568596737
Short name T5
Test name
Test status
Simulation time 24409754417 ps
CPU time 87.01 seconds
Started Aug 05 04:50:08 PM PDT 24
Finished Aug 05 04:51:40 PM PDT 24
Peak memory 238996 kb
Host smart-8aad1595-8c59-4e31-b99d-7b122c98309e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568596737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.2568596737
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.1348083680
Short name T228
Test name
Test status
Simulation time 19350050389 ps
CPU time 127.31 seconds
Started Aug 05 04:50:32 PM PDT 24
Finished Aug 05 04:52:40 PM PDT 24
Peak memory 265328 kb
Host smart-f14d6d87-c650-48d7-96b5-5d86e2aac050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348083680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.1348083680
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.260810201
Short name T933
Test name
Test status
Simulation time 1998183587 ps
CPU time 27.87 seconds
Started Aug 05 04:50:31 PM PDT 24
Finished Aug 05 04:50:59 PM PDT 24
Peak memory 237656 kb
Host smart-d7c0bb3e-54f1-4946-bccb-905aeb73b865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260810201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idle
.260810201
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.319239344
Short name T463
Test name
Test status
Simulation time 814622016 ps
CPU time 3.57 seconds
Started Aug 05 04:50:20 PM PDT 24
Finished Aug 05 04:50:24 PM PDT 24
Peak memory 225184 kb
Host smart-01ab3994-2b61-495f-b98c-f299217d2730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319239344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.319239344
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.3347484584
Short name T140
Test name
Test status
Simulation time 17716428297 ps
CPU time 140.09 seconds
Started Aug 05 04:50:23 PM PDT 24
Finished Aug 05 04:52:44 PM PDT 24
Peak memory 249800 kb
Host smart-44d805e1-4fcc-4e15-9bbe-3a47312a0ec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347484584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmd
s.3347484584
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/18.spi_device_intercept.3195998913
Short name T660
Test name
Test status
Simulation time 9355434494 ps
CPU time 27.06 seconds
Started Aug 05 04:50:37 PM PDT 24
Finished Aug 05 04:51:04 PM PDT 24
Peak memory 225344 kb
Host smart-6d05d9da-2fad-46ac-ad1e-f4df9ff735f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195998913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.3195998913
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.452524842
Short name T254
Test name
Test status
Simulation time 2366882244 ps
CPU time 22.83 seconds
Started Aug 05 04:50:02 PM PDT 24
Finished Aug 05 04:50:25 PM PDT 24
Peak memory 233368 kb
Host smart-829a0ed1-b329-46e8-a36c-fa253d4c75cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452524842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.452524842
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.3988220621
Short name T592
Test name
Test status
Simulation time 212307442 ps
CPU time 1.08 seconds
Started Aug 05 04:50:24 PM PDT 24
Finished Aug 05 04:50:26 PM PDT 24
Peak memory 217208 kb
Host smart-92e1ff9c-6186-430a-b120-c717a80bcdf8
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988220621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.spi_device_mem_parity.3988220621
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.2228599752
Short name T872
Test name
Test status
Simulation time 1191876189 ps
CPU time 5.08 seconds
Started Aug 05 04:50:12 PM PDT 24
Finished Aug 05 04:50:18 PM PDT 24
Peak memory 225128 kb
Host smart-22f64ae6-2781-4c3e-9384-1c318f3ec178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228599752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.2228599752
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.4124744744
Short name T712
Test name
Test status
Simulation time 30205005 ps
CPU time 2.06 seconds
Started Aug 05 04:50:14 PM PDT 24
Finished Aug 05 04:50:16 PM PDT 24
Peak memory 223548 kb
Host smart-4beec97a-fffa-4c05-a254-48b1e5ba49d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124744744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.4124744744
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.3635952571
Short name T888
Test name
Test status
Simulation time 1706211048 ps
CPU time 6.38 seconds
Started Aug 05 04:50:17 PM PDT 24
Finished Aug 05 04:50:23 PM PDT 24
Peak memory 223048 kb
Host smart-4f93149a-228d-4d70-87d9-f8bccb261a54
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3635952571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.3635952571
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.2895028208
Short name T384
Test name
Test status
Simulation time 1116628114 ps
CPU time 18.93 seconds
Started Aug 05 04:50:24 PM PDT 24
Finished Aug 05 04:50:43 PM PDT 24
Peak memory 217032 kb
Host smart-5cae1685-1882-4385-8f17-221ed61f2a0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895028208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.2895028208
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.252929603
Short name T605
Test name
Test status
Simulation time 9881313047 ps
CPU time 15.03 seconds
Started Aug 05 04:50:31 PM PDT 24
Finished Aug 05 04:50:46 PM PDT 24
Peak memory 216956 kb
Host smart-224a246d-bbe1-487d-a8a0-dc49276c1cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252929603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.252929603
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.1237827198
Short name T945
Test name
Test status
Simulation time 37837762 ps
CPU time 1.21 seconds
Started Aug 05 04:50:27 PM PDT 24
Finished Aug 05 04:50:29 PM PDT 24
Peak memory 216832 kb
Host smart-afbbd67b-36f8-4e0e-8ae6-67c81d30fa2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237827198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.1237827198
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.2040677521
Short name T354
Test name
Test status
Simulation time 32243187 ps
CPU time 0.83 seconds
Started Aug 05 04:50:16 PM PDT 24
Finished Aug 05 04:50:17 PM PDT 24
Peak memory 206472 kb
Host smart-1a9ae908-add5-4c6e-8ef5-5f71d0bd680d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040677521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.2040677521
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.477916365
Short name T239
Test name
Test status
Simulation time 5616315815 ps
CPU time 21.19 seconds
Started Aug 05 04:50:14 PM PDT 24
Finished Aug 05 04:50:36 PM PDT 24
Peak memory 237652 kb
Host smart-c16c0eaa-b228-4c0d-8943-35a7df9d57cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477916365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.477916365
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.3513554817
Short name T390
Test name
Test status
Simulation time 14880151 ps
CPU time 0.74 seconds
Started Aug 05 04:50:19 PM PDT 24
Finished Aug 05 04:50:20 PM PDT 24
Peak memory 206224 kb
Host smart-afcf80cd-2a43-4bca-aa12-afbd22763067
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513554817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
3513554817
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.2018383086
Short name T527
Test name
Test status
Simulation time 776070106 ps
CPU time 3.98 seconds
Started Aug 05 04:50:37 PM PDT 24
Finished Aug 05 04:50:41 PM PDT 24
Peak memory 225288 kb
Host smart-069ef018-f12e-4a48-a75e-a340a11f5480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018383086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.2018383086
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.2835049710
Short name T619
Test name
Test status
Simulation time 19335618 ps
CPU time 0.78 seconds
Started Aug 05 04:50:29 PM PDT 24
Finished Aug 05 04:50:30 PM PDT 24
Peak memory 207304 kb
Host smart-b1ea2fac-07d6-4a1b-a352-c5d5cd3da538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835049710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.2835049710
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.1799745694
Short name T218
Test name
Test status
Simulation time 3679820323 ps
CPU time 77.81 seconds
Started Aug 05 04:50:29 PM PDT 24
Finished Aug 05 04:51:47 PM PDT 24
Peak memory 273568 kb
Host smart-98a636ee-da9e-4b93-b7d8-4eee4a4e8069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799745694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.1799745694
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.1594768853
Short name T205
Test name
Test status
Simulation time 28554373130 ps
CPU time 114.71 seconds
Started Aug 05 04:50:28 PM PDT 24
Finished Aug 05 04:52:23 PM PDT 24
Peak memory 252148 kb
Host smart-9a9167f8-e077-473a-9834-e11a268b6531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594768853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.1594768853
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.2128076143
Short name T940
Test name
Test status
Simulation time 5143572195 ps
CPU time 54.37 seconds
Started Aug 05 04:50:22 PM PDT 24
Finished Aug 05 04:51:16 PM PDT 24
Peak memory 251048 kb
Host smart-b0b5771f-9eb1-4703-aa16-645c672b979c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128076143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.2128076143
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.2281288209
Short name T323
Test name
Test status
Simulation time 281924085 ps
CPU time 5.53 seconds
Started Aug 05 04:50:27 PM PDT 24
Finished Aug 05 04:50:33 PM PDT 24
Peak memory 233408 kb
Host smart-e717a513-88c1-4c4e-abf0-ba87e529e7ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281288209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.2281288209
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.1648180115
Short name T15
Test name
Test status
Simulation time 61221337933 ps
CPU time 228.04 seconds
Started Aug 05 04:50:32 PM PDT 24
Finished Aug 05 04:54:20 PM PDT 24
Peak memory 268924 kb
Host smart-7d70fc45-33f6-4942-946a-1057e1a74983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648180115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmd
s.1648180115
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/19.spi_device_intercept.827561187
Short name T736
Test name
Test status
Simulation time 207872597 ps
CPU time 4.75 seconds
Started Aug 05 04:50:22 PM PDT 24
Finished Aug 05 04:50:27 PM PDT 24
Peak memory 233448 kb
Host smart-24119815-f8fb-41f5-a39b-b9670a666358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827561187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.827561187
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.46731621
Short name T211
Test name
Test status
Simulation time 1266547833 ps
CPU time 13.07 seconds
Started Aug 05 04:50:22 PM PDT 24
Finished Aug 05 04:50:40 PM PDT 24
Peak memory 233328 kb
Host smart-43461fbf-35f2-4963-8b6e-6bc39db0729f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46731621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.46731621
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.3232608712
Short name T1000
Test name
Test status
Simulation time 32513696 ps
CPU time 1.05 seconds
Started Aug 05 04:50:28 PM PDT 24
Finished Aug 05 04:50:29 PM PDT 24
Peak memory 218444 kb
Host smart-bd6d51a2-5f8c-4e34-af4c-ed070f4db24c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232608712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.spi_device_mem_parity.3232608712
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.937224691
Short name T595
Test name
Test status
Simulation time 31755240907 ps
CPU time 23.65 seconds
Started Aug 05 04:50:34 PM PDT 24
Finished Aug 05 04:50:59 PM PDT 24
Peak memory 224340 kb
Host smart-641666ad-3fd6-4034-82e3-16c6177c940f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937224691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swap
.937224691
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.1149066043
Short name T607
Test name
Test status
Simulation time 26147178426 ps
CPU time 15.41 seconds
Started Aug 05 04:50:36 PM PDT 24
Finished Aug 05 04:50:52 PM PDT 24
Peak memory 225360 kb
Host smart-30ddb614-6b59-46cc-9f2b-59a776841ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149066043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.1149066043
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.1993491124
Short name T821
Test name
Test status
Simulation time 1107464577 ps
CPU time 5.3 seconds
Started Aug 05 04:50:15 PM PDT 24
Finished Aug 05 04:50:20 PM PDT 24
Peak memory 222916 kb
Host smart-45292356-3abe-4b7e-a5d4-b1c5c256bae1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1993491124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.1993491124
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.3921869252
Short name T591
Test name
Test status
Simulation time 2443666887 ps
CPU time 13.13 seconds
Started Aug 05 04:50:24 PM PDT 24
Finished Aug 05 04:50:38 PM PDT 24
Peak memory 216988 kb
Host smart-d3d497dd-1086-49a3-b6ac-46410654e72e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921869252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.3921869252
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.4029380737
Short name T800
Test name
Test status
Simulation time 5087808640 ps
CPU time 8.36 seconds
Started Aug 05 04:50:44 PM PDT 24
Finished Aug 05 04:50:52 PM PDT 24
Peak memory 216948 kb
Host smart-af915214-13de-4153-b755-99686e799f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029380737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.4029380737
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.315741831
Short name T335
Test name
Test status
Simulation time 181400745 ps
CPU time 1.33 seconds
Started Aug 05 04:50:22 PM PDT 24
Finished Aug 05 04:50:24 PM PDT 24
Peak memory 216900 kb
Host smart-b88fee23-29c2-476b-862b-242453db7cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315741831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.315741831
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.916628310
Short name T545
Test name
Test status
Simulation time 78338398 ps
CPU time 0.81 seconds
Started Aug 05 04:50:27 PM PDT 24
Finished Aug 05 04:50:28 PM PDT 24
Peak memory 206484 kb
Host smart-7568a364-42fd-4cdf-92b0-1a4fa7a99ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916628310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.916628310
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.998375127
Short name T910
Test name
Test status
Simulation time 2010257182 ps
CPU time 7.59 seconds
Started Aug 05 04:50:25 PM PDT 24
Finished Aug 05 04:50:33 PM PDT 24
Peak memory 225096 kb
Host smart-3d41ed12-1288-4176-a516-13146ef8ad9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998375127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.998375127
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.2771720686
Short name T651
Test name
Test status
Simulation time 166040092 ps
CPU time 0.72 seconds
Started Aug 05 04:49:55 PM PDT 24
Finished Aug 05 04:49:56 PM PDT 24
Peak memory 205736 kb
Host smart-580dbeaf-f2e1-4ef3-aa6a-099f80b510ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771720686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.2
771720686
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.4206627703
Short name T822
Test name
Test status
Simulation time 1345374930 ps
CPU time 4.64 seconds
Started Aug 05 04:49:43 PM PDT 24
Finished Aug 05 04:49:53 PM PDT 24
Peak memory 225164 kb
Host smart-d993b731-6475-419e-84ce-917075f1131f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206627703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.4206627703
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.1105400145
Short name T823
Test name
Test status
Simulation time 50773192 ps
CPU time 0.87 seconds
Started Aug 05 04:49:39 PM PDT 24
Finished Aug 05 04:49:40 PM PDT 24
Peak memory 206952 kb
Host smart-46e3f4a6-022a-4451-8463-7039e5c71e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105400145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.1105400145
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.2750979143
Short name T293
Test name
Test status
Simulation time 13819527144 ps
CPU time 135.43 seconds
Started Aug 05 04:49:51 PM PDT 24
Finished Aug 05 04:52:07 PM PDT 24
Peak memory 255544 kb
Host smart-ab458d49-095a-46f3-a764-d191e1b4d55f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750979143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.2750979143
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.2211645077
Short name T337
Test name
Test status
Simulation time 10425943983 ps
CPU time 127.2 seconds
Started Aug 05 04:49:43 PM PDT 24
Finished Aug 05 04:51:50 PM PDT 24
Peak memory 255492 kb
Host smart-78c90233-b833-4939-93d1-eef0404ac29f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211645077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.2211645077
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.2209602779
Short name T172
Test name
Test status
Simulation time 1454784813 ps
CPU time 8.45 seconds
Started Aug 05 04:49:40 PM PDT 24
Finished Aug 05 04:49:48 PM PDT 24
Peak memory 235812 kb
Host smart-345ba40a-428f-4725-826a-271a51aa3330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209602779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.2209602779
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.2374833511
Short name T245
Test name
Test status
Simulation time 88897921748 ps
CPU time 305.36 seconds
Started Aug 05 04:49:42 PM PDT 24
Finished Aug 05 04:54:48 PM PDT 24
Peak memory 251264 kb
Host smart-e2331166-2b15-44b3-bdd0-6af5249d7326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374833511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds
.2374833511
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_intercept.3760146795
Short name T258
Test name
Test status
Simulation time 683170683 ps
CPU time 9.65 seconds
Started Aug 05 04:49:27 PM PDT 24
Finished Aug 05 04:49:37 PM PDT 24
Peak memory 233356 kb
Host smart-e0739962-45ba-40d0-b316-e65f88aba82e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760146795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.3760146795
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.445003060
Short name T575
Test name
Test status
Simulation time 2976479457 ps
CPU time 36.89 seconds
Started Aug 05 04:49:29 PM PDT 24
Finished Aug 05 04:50:06 PM PDT 24
Peak memory 241372 kb
Host smart-d2c77435-8e26-4ae0-aa64-da230ecd188a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445003060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.445003060
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.3398642419
Short name T759
Test name
Test status
Simulation time 39199631 ps
CPU time 1.05 seconds
Started Aug 05 04:49:44 PM PDT 24
Finished Aug 05 04:49:45 PM PDT 24
Peak memory 218308 kb
Host smart-f5f60475-6a1b-47e1-8b40-d046af906ee8
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398642419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.spi_device_mem_parity.3398642419
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.1378996812
Short name T557
Test name
Test status
Simulation time 2577586445 ps
CPU time 10.5 seconds
Started Aug 05 04:49:57 PM PDT 24
Finished Aug 05 04:50:08 PM PDT 24
Peak memory 233492 kb
Host smart-5cf1ea4f-7ffd-40f6-853d-466dc0929c4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378996812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.1378996812
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.3475447325
Short name T792
Test name
Test status
Simulation time 1732271875 ps
CPU time 6.86 seconds
Started Aug 05 04:49:44 PM PDT 24
Finished Aug 05 04:49:51 PM PDT 24
Peak memory 233352 kb
Host smart-1781528e-b708-4f85-8bb5-741251ac7cc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475447325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.3475447325
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.225792075
Short name T400
Test name
Test status
Simulation time 446052030 ps
CPU time 5.17 seconds
Started Aug 05 04:49:43 PM PDT 24
Finished Aug 05 04:49:49 PM PDT 24
Peak memory 222928 kb
Host smart-674f155b-7f47-4e50-b764-5e65b39b633b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=225792075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_direc
t.225792075
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.2529752380
Short name T69
Test name
Test status
Simulation time 233952616 ps
CPU time 1.04 seconds
Started Aug 05 04:49:38 PM PDT 24
Finished Aug 05 04:49:39 PM PDT 24
Peak memory 235472 kb
Host smart-4954d04b-1230-4b45-9010-cb61826fd3bd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529752380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.2529752380
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.972757461
Short name T327
Test name
Test status
Simulation time 549682521 ps
CPU time 8.48 seconds
Started Aug 05 04:49:33 PM PDT 24
Finished Aug 05 04:49:52 PM PDT 24
Peak memory 217212 kb
Host smart-498592ff-46b8-40aa-a0dc-e6b6606bc533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972757461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.972757461
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.4127151123
Short name T887
Test name
Test status
Simulation time 6909720732 ps
CPU time 17.27 seconds
Started Aug 05 04:49:40 PM PDT 24
Finished Aug 05 04:49:57 PM PDT 24
Peak memory 216924 kb
Host smart-ece30a66-8c62-48b7-a060-a1c3760e9361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127151123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.4127151123
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.1000769662
Short name T643
Test name
Test status
Simulation time 18673213 ps
CPU time 0.78 seconds
Started Aug 05 04:49:43 PM PDT 24
Finished Aug 05 04:49:43 PM PDT 24
Peak memory 206080 kb
Host smart-46bdb2a0-d974-4d74-9019-3e4d1dadc17a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000769662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.1000769662
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.2777102875
Short name T535
Test name
Test status
Simulation time 146265711 ps
CPU time 0.89 seconds
Started Aug 05 04:49:34 PM PDT 24
Finished Aug 05 04:49:35 PM PDT 24
Peak memory 206488 kb
Host smart-4867c609-c6c5-42c1-9de1-d8c9c05da32e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777102875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.2777102875
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.3578440651
Short name T255
Test name
Test status
Simulation time 210059247 ps
CPU time 2.86 seconds
Started Aug 05 04:49:41 PM PDT 24
Finished Aug 05 04:49:44 PM PDT 24
Peak memory 225160 kb
Host smart-002932f6-78c0-41bb-9ea6-b4c8c65ab13a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578440651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.3578440651
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.2888147816
Short name T428
Test name
Test status
Simulation time 27410189 ps
CPU time 0.72 seconds
Started Aug 05 04:50:38 PM PDT 24
Finished Aug 05 04:50:38 PM PDT 24
Peak memory 205212 kb
Host smart-2b842670-387b-4195-bfc5-f7a5fa37fbd5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888147816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
2888147816
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.3963799284
Short name T982
Test name
Test status
Simulation time 2277384570 ps
CPU time 12.63 seconds
Started Aug 05 04:50:24 PM PDT 24
Finished Aug 05 04:50:37 PM PDT 24
Peak memory 233432 kb
Host smart-9d014140-b44b-4d27-9e2d-692ae278bb66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963799284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.3963799284
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.522495629
Short name T730
Test name
Test status
Simulation time 37316623 ps
CPU time 0.78 seconds
Started Aug 05 04:50:29 PM PDT 24
Finished Aug 05 04:50:30 PM PDT 24
Peak memory 206304 kb
Host smart-d9ee410e-58cc-4108-b6c9-5ddf35074f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522495629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.522495629
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.3308027747
Short name T231
Test name
Test status
Simulation time 111279832653 ps
CPU time 328.29 seconds
Started Aug 05 04:50:39 PM PDT 24
Finished Aug 05 04:56:07 PM PDT 24
Peak memory 251660 kb
Host smart-8599ad21-8840-47c9-87e9-bc1c24ba9b4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308027747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.3308027747
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.477814938
Short name T994
Test name
Test status
Simulation time 7187484444 ps
CPU time 38.09 seconds
Started Aug 05 04:50:37 PM PDT 24
Finished Aug 05 04:51:15 PM PDT 24
Peak memory 218340 kb
Host smart-05c52062-7f52-4076-a5d1-3baba8ac6786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477814938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idle
.477814938
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.419032215
Short name T686
Test name
Test status
Simulation time 8412376860 ps
CPU time 45.47 seconds
Started Aug 05 04:50:36 PM PDT 24
Finished Aug 05 04:51:21 PM PDT 24
Peak memory 250160 kb
Host smart-4d36b03c-cf6f-4716-b882-8e6b48f5eb27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419032215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmds
.419032215
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/20.spi_device_intercept.1288604581
Short name T852
Test name
Test status
Simulation time 195462819 ps
CPU time 3.24 seconds
Started Aug 05 04:50:22 PM PDT 24
Finished Aug 05 04:50:25 PM PDT 24
Peak memory 225108 kb
Host smart-22234efc-ed8a-4346-a274-d90a8d0d6faf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288604581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.1288604581
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.1924258123
Short name T903
Test name
Test status
Simulation time 29291193 ps
CPU time 2.2 seconds
Started Aug 05 04:50:22 PM PDT 24
Finished Aug 05 04:50:24 PM PDT 24
Peak memory 223680 kb
Host smart-addaef59-f0f7-474e-a92b-f0e12ae09dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924258123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.1924258123
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.1191189374
Short name T639
Test name
Test status
Simulation time 7498050880 ps
CPU time 8.94 seconds
Started Aug 05 04:50:28 PM PDT 24
Finished Aug 05 04:50:37 PM PDT 24
Peak memory 233424 kb
Host smart-427dca08-2c60-4bb6-bba6-d2d248f2afe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191189374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.1191189374
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.2301314734
Short name T270
Test name
Test status
Simulation time 4032017042 ps
CPU time 14.34 seconds
Started Aug 05 04:50:26 PM PDT 24
Finished Aug 05 04:50:41 PM PDT 24
Peak memory 233388 kb
Host smart-d4e8f1cd-2b76-407c-bb03-cbb599fc93c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301314734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.2301314734
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.1419909348
Short name T141
Test name
Test status
Simulation time 6459710234 ps
CPU time 18.62 seconds
Started Aug 05 04:50:35 PM PDT 24
Finished Aug 05 04:50:54 PM PDT 24
Peak memory 222568 kb
Host smart-28f2457a-523b-4ab5-9b05-06a498b29fcb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1419909348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.1419909348
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.2752769539
Short name T164
Test name
Test status
Simulation time 351349780 ps
CPU time 1.07 seconds
Started Aug 05 04:50:44 PM PDT 24
Finished Aug 05 04:50:45 PM PDT 24
Peak memory 207312 kb
Host smart-036bb9b3-c95e-4d08-b10e-54275a0c07ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752769539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.2752769539
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.4118000563
Short name T594
Test name
Test status
Simulation time 124495492 ps
CPU time 0.74 seconds
Started Aug 05 04:50:19 PM PDT 24
Finished Aug 05 04:50:20 PM PDT 24
Peak memory 206428 kb
Host smart-12ad8866-691d-4e9b-87f4-49dfcf616eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118000563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.4118000563
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.2244108366
Short name T891
Test name
Test status
Simulation time 370736955 ps
CPU time 2.97 seconds
Started Aug 05 04:50:16 PM PDT 24
Finished Aug 05 04:50:20 PM PDT 24
Peak memory 216900 kb
Host smart-d4d97fe9-6816-40ee-a3df-d54c56c3fe86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244108366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.2244108366
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.338323285
Short name T590
Test name
Test status
Simulation time 45430580 ps
CPU time 1.05 seconds
Started Aug 05 04:50:25 PM PDT 24
Finished Aug 05 04:50:26 PM PDT 24
Peak memory 207504 kb
Host smart-bf686ed6-d386-4a6e-93ec-cf6dc36ae655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338323285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.338323285
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.4192730394
Short name T685
Test name
Test status
Simulation time 29096181 ps
CPU time 0.8 seconds
Started Aug 05 04:50:27 PM PDT 24
Finished Aug 05 04:50:28 PM PDT 24
Peak memory 206480 kb
Host smart-923701bf-7296-4d74-87a5-fa06a8ef185b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192730394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.4192730394
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.1837670332
Short name T516
Test name
Test status
Simulation time 44901314 ps
CPU time 0.7 seconds
Started Aug 05 04:50:30 PM PDT 24
Finished Aug 05 04:50:31 PM PDT 24
Peak memory 206084 kb
Host smart-767b8f3f-f8f3-4e7e-9259-6fc9f21060eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837670332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
1837670332
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.3021715434
Short name T60
Test name
Test status
Simulation time 219202680 ps
CPU time 2.55 seconds
Started Aug 05 04:50:28 PM PDT 24
Finished Aug 05 04:50:31 PM PDT 24
Peak memory 233296 kb
Host smart-9fe6608d-f148-4435-a635-5691e7fe0d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021715434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.3021715434
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.1995958445
Short name T784
Test name
Test status
Simulation time 56208450 ps
CPU time 0.8 seconds
Started Aug 05 04:50:29 PM PDT 24
Finished Aug 05 04:50:30 PM PDT 24
Peak memory 206944 kb
Host smart-1cb3de79-df4d-4794-acdf-41872fc642f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995958445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.1995958445
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.2867068484
Short name T875
Test name
Test status
Simulation time 5517901663 ps
CPU time 50.3 seconds
Started Aug 05 04:50:18 PM PDT 24
Finished Aug 05 04:51:09 PM PDT 24
Peak memory 262704 kb
Host smart-baa7b567-9ccc-43c9-840a-9aecbdf6d092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867068484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.2867068484
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.520914663
Short name T972
Test name
Test status
Simulation time 2146032129 ps
CPU time 33.59 seconds
Started Aug 05 04:50:28 PM PDT 24
Finished Aug 05 04:51:01 PM PDT 24
Peak memory 249748 kb
Host smart-2eabebc0-151b-4615-b0a0-dd0281a0d9b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520914663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.520914663
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.2445661860
Short name T234
Test name
Test status
Simulation time 64872725899 ps
CPU time 96.76 seconds
Started Aug 05 04:50:36 PM PDT 24
Finished Aug 05 04:52:12 PM PDT 24
Peak memory 257644 kb
Host smart-e6888b9b-db0e-4d6c-a5b0-f8bb764caa57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445661860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.2445661860
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.1653399178
Short name T76
Test name
Test status
Simulation time 76000862 ps
CPU time 3.1 seconds
Started Aug 05 04:50:39 PM PDT 24
Finished Aug 05 04:50:42 PM PDT 24
Peak memory 233332 kb
Host smart-cb780baa-0424-45e0-b14e-5b1de759e87d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653399178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.1653399178
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.2894283440
Short name T243
Test name
Test status
Simulation time 7834365382 ps
CPU time 45.2 seconds
Started Aug 05 04:50:28 PM PDT 24
Finished Aug 05 04:51:13 PM PDT 24
Peak memory 250592 kb
Host smart-164179f4-2fb5-4548-95ec-6a78a1734ced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894283440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmd
s.2894283440
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_intercept.2604191270
Short name T777
Test name
Test status
Simulation time 32239957 ps
CPU time 1.92 seconds
Started Aug 05 04:50:38 PM PDT 24
Finished Aug 05 04:50:40 PM PDT 24
Peak memory 224504 kb
Host smart-e2eb2a10-333c-4dd2-a03a-e99fe838ef37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604191270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.2604191270
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.4138619565
Short name T805
Test name
Test status
Simulation time 698734615 ps
CPU time 9.77 seconds
Started Aug 05 04:50:26 PM PDT 24
Finished Aug 05 04:50:36 PM PDT 24
Peak memory 236856 kb
Host smart-c7139072-f5ec-49da-9af1-1794f935ca9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138619565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.4138619565
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.459292667
Short name T654
Test name
Test status
Simulation time 868881973 ps
CPU time 6.19 seconds
Started Aug 05 04:50:26 PM PDT 24
Finished Aug 05 04:50:33 PM PDT 24
Peak memory 233364 kb
Host smart-ac9ef086-9abc-4e4d-a1e0-381109134a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459292667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swap
.459292667
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.4054449185
Short name T427
Test name
Test status
Simulation time 473315766 ps
CPU time 4.74 seconds
Started Aug 05 04:50:12 PM PDT 24
Finished Aug 05 04:50:17 PM PDT 24
Peak memory 225168 kb
Host smart-0dac12ca-5a24-4d8c-982f-db24409a6a84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054449185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.4054449185
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.3805248517
Short name T894
Test name
Test status
Simulation time 5504790218 ps
CPU time 13.03 seconds
Started Aug 05 04:50:45 PM PDT 24
Finished Aug 05 04:50:58 PM PDT 24
Peak memory 220488 kb
Host smart-4ba12115-9d0b-4dc8-8316-2d91832379f6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3805248517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.3805248517
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.1799201311
Short name T165
Test name
Test status
Simulation time 6057768460 ps
CPU time 44.37 seconds
Started Aug 05 04:50:45 PM PDT 24
Finished Aug 05 04:51:30 PM PDT 24
Peak memory 237580 kb
Host smart-2d0a2366-054a-44ef-bf8e-9d1ceafd5643
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799201311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.1799201311
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.696971669
Short name T740
Test name
Test status
Simulation time 2163170039 ps
CPU time 14.86 seconds
Started Aug 05 04:50:25 PM PDT 24
Finished Aug 05 04:50:40 PM PDT 24
Peak memory 217012 kb
Host smart-d4161f50-526e-4db8-aabf-8406ebdd5703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696971669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.696971669
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.3085944579
Short name T387
Test name
Test status
Simulation time 7869331288 ps
CPU time 10.5 seconds
Started Aug 05 04:50:35 PM PDT 24
Finished Aug 05 04:50:46 PM PDT 24
Peak memory 216916 kb
Host smart-85403c24-9e2d-4972-b06a-237746f0d201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085944579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.3085944579
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.4141503250
Short name T558
Test name
Test status
Simulation time 43895037 ps
CPU time 1.35 seconds
Started Aug 05 04:50:35 PM PDT 24
Finished Aug 05 04:50:39 PM PDT 24
Peak memory 216832 kb
Host smart-af8c9b40-e54d-4e48-b380-44b9b0301f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141503250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.4141503250
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.2086089449
Short name T433
Test name
Test status
Simulation time 292545045 ps
CPU time 0.96 seconds
Started Aug 05 04:50:27 PM PDT 24
Finished Aug 05 04:50:29 PM PDT 24
Peak memory 206436 kb
Host smart-f55073ed-6083-43a2-837d-3af58a527568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086089449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.2086089449
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.3832035035
Short name T49
Test name
Test status
Simulation time 9200024124 ps
CPU time 16.09 seconds
Started Aug 05 04:50:27 PM PDT 24
Finished Aug 05 04:50:44 PM PDT 24
Peak memory 236076 kb
Host smart-c493a073-3b4e-4b19-9b1b-36c4dfc150cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832035035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.3832035035
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.1583871758
Short name T389
Test name
Test status
Simulation time 79912289 ps
CPU time 0.71 seconds
Started Aug 05 04:50:30 PM PDT 24
Finished Aug 05 04:50:30 PM PDT 24
Peak memory 205764 kb
Host smart-750207dc-68b4-42ac-b067-7ce41239e3fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583871758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
1583871758
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.1443295092
Short name T1010
Test name
Test status
Simulation time 2931904183 ps
CPU time 23.61 seconds
Started Aug 05 04:50:25 PM PDT 24
Finished Aug 05 04:50:49 PM PDT 24
Peak memory 225284 kb
Host smart-2c0276c0-da77-4d8c-a4ea-46f70bf90ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443295092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.1443295092
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.757393758
Short name T493
Test name
Test status
Simulation time 82031691 ps
CPU time 0.83 seconds
Started Aug 05 04:50:35 PM PDT 24
Finished Aug 05 04:50:36 PM PDT 24
Peak memory 206948 kb
Host smart-721de6c9-3cb0-458b-beaa-0c0cd86f9e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757393758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.757393758
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.4117602573
Short name T995
Test name
Test status
Simulation time 45190974721 ps
CPU time 172.35 seconds
Started Aug 05 04:50:26 PM PDT 24
Finished Aug 05 04:53:19 PM PDT 24
Peak memory 251852 kb
Host smart-d99dda6c-5f84-427e-bb1f-bc69ce04bc56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117602573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.4117602573
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.245505077
Short name T958
Test name
Test status
Simulation time 6877568603 ps
CPU time 37.81 seconds
Started Aug 05 04:50:50 PM PDT 24
Finished Aug 05 04:51:28 PM PDT 24
Peak memory 250012 kb
Host smart-da228e9f-10fe-4c5c-ac09-ec6833c14d50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245505077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.245505077
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.2477253313
Short name T148
Test name
Test status
Simulation time 2828526074 ps
CPU time 62.04 seconds
Started Aug 05 04:50:40 PM PDT 24
Finished Aug 05 04:51:43 PM PDT 24
Peak memory 251516 kb
Host smart-06b7181e-0c17-4bf9-8626-c509b0151239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477253313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.2477253313
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.2811995224
Short name T920
Test name
Test status
Simulation time 1812417856 ps
CPU time 13.65 seconds
Started Aug 05 04:50:41 PM PDT 24
Finished Aug 05 04:50:55 PM PDT 24
Peak memory 225108 kb
Host smart-e8a27dc9-cb28-4909-bd1e-abb5950381f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811995224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.2811995224
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_intercept.3198287492
Short name T598
Test name
Test status
Simulation time 11333794210 ps
CPU time 8.42 seconds
Started Aug 05 04:50:34 PM PDT 24
Finished Aug 05 04:50:43 PM PDT 24
Peak memory 225128 kb
Host smart-c1be8182-54be-4b49-9b67-1a2546ddc9b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198287492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.3198287492
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.1560011204
Short name T886
Test name
Test status
Simulation time 4360258049 ps
CPU time 49.7 seconds
Started Aug 05 04:50:37 PM PDT 24
Finished Aug 05 04:51:27 PM PDT 24
Peak memory 225240 kb
Host smart-b83def46-59a1-46f3-a4fd-89373d8ccd87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560011204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.1560011204
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.1040896620
Short name T845
Test name
Test status
Simulation time 1855709633 ps
CPU time 14.28 seconds
Started Aug 05 04:50:46 PM PDT 24
Finished Aug 05 04:51:00 PM PDT 24
Peak memory 233328 kb
Host smart-f530d321-10cd-49f0-b4f9-84470cccb33d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040896620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.1040896620
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.2242866632
Short name T249
Test name
Test status
Simulation time 2301165155 ps
CPU time 10.08 seconds
Started Aug 05 04:50:34 PM PDT 24
Finished Aug 05 04:50:45 PM PDT 24
Peak memory 233364 kb
Host smart-7894041c-f360-4990-8c76-48f6f3849709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242866632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.2242866632
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.1959943529
Short name T458
Test name
Test status
Simulation time 2443607873 ps
CPU time 4.55 seconds
Started Aug 05 04:50:42 PM PDT 24
Finished Aug 05 04:50:47 PM PDT 24
Peak memory 221072 kb
Host smart-203402a0-9fe3-4499-8c2e-a0f2b8ed1ba7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1959943529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.1959943529
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.214326547
Short name T520
Test name
Test status
Simulation time 247671288 ps
CPU time 0.85 seconds
Started Aug 05 04:50:30 PM PDT 24
Finished Aug 05 04:50:31 PM PDT 24
Peak memory 207284 kb
Host smart-554e77fa-5c73-44b5-a085-f3a49a0a66fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214326547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stres
s_all.214326547
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.2611713236
Short name T723
Test name
Test status
Simulation time 16706997105 ps
CPU time 25.25 seconds
Started Aug 05 04:50:30 PM PDT 24
Finished Aug 05 04:50:55 PM PDT 24
Peak memory 216944 kb
Host smart-148855cf-2308-4601-9dcc-4e2cd5e50f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611713236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.2611713236
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.3676914208
Short name T505
Test name
Test status
Simulation time 2374767685 ps
CPU time 8.04 seconds
Started Aug 05 04:50:26 PM PDT 24
Finished Aug 05 04:50:34 PM PDT 24
Peak memory 216920 kb
Host smart-267276bc-df96-4404-bdd5-5671960c0975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676914208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.3676914208
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.2680825584
Short name T476
Test name
Test status
Simulation time 13385130 ps
CPU time 0.74 seconds
Started Aug 05 04:50:23 PM PDT 24
Finished Aug 05 04:50:24 PM PDT 24
Peak memory 205940 kb
Host smart-711313be-b815-443c-a345-87aeffd2dd54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680825584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.2680825584
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.3723211055
Short name T615
Test name
Test status
Simulation time 68924683 ps
CPU time 0.8 seconds
Started Aug 05 04:50:38 PM PDT 24
Finished Aug 05 04:50:39 PM PDT 24
Peak memory 206476 kb
Host smart-8c7540bb-f028-4899-aa9d-7ac60a19dfd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723211055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.3723211055
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.199044987
Short name T233
Test name
Test status
Simulation time 1411794885 ps
CPU time 11.92 seconds
Started Aug 05 04:50:45 PM PDT 24
Finished Aug 05 04:50:57 PM PDT 24
Peak memory 241520 kb
Host smart-02d742cb-85e6-4bb0-8d6a-f0523cb969bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199044987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.199044987
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.1161929834
Short name T414
Test name
Test status
Simulation time 42486063 ps
CPU time 0.72 seconds
Started Aug 05 04:50:38 PM PDT 24
Finished Aug 05 04:50:39 PM PDT 24
Peak memory 205744 kb
Host smart-dd6a0d89-6984-4d3d-b018-763ed140be7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161929834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
1161929834
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.144983846
Short name T338
Test name
Test status
Simulation time 30911105 ps
CPU time 2.01 seconds
Started Aug 05 04:50:40 PM PDT 24
Finished Aug 05 04:50:42 PM PDT 24
Peak memory 224508 kb
Host smart-364f0ba2-0099-455c-9431-7917b9f8ff69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144983846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.144983846
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.353070355
Short name T484
Test name
Test status
Simulation time 29488398 ps
CPU time 0.76 seconds
Started Aug 05 04:50:40 PM PDT 24
Finished Aug 05 04:50:41 PM PDT 24
Peak memory 206964 kb
Host smart-60a6d275-11d5-4276-b7c2-38b0566f8986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353070355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.353070355
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.2424551438
Short name T586
Test name
Test status
Simulation time 50711674662 ps
CPU time 103.26 seconds
Started Aug 05 04:50:31 PM PDT 24
Finished Aug 05 04:52:14 PM PDT 24
Peak memory 257648 kb
Host smart-9c48328e-d35a-4aad-9b75-42ba1f264bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424551438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.2424551438
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.4186135114
Short name T199
Test name
Test status
Simulation time 7218086540 ps
CPU time 101.95 seconds
Started Aug 05 04:50:37 PM PDT 24
Finished Aug 05 04:52:19 PM PDT 24
Peak memory 265744 kb
Host smart-721b0d3f-8eb5-4921-ab60-73320192680e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186135114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.4186135114
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.4277674776
Short name T329
Test name
Test status
Simulation time 3064667177 ps
CPU time 42.28 seconds
Started Aug 05 04:50:41 PM PDT 24
Finished Aug 05 04:51:24 PM PDT 24
Peak memory 225268 kb
Host smart-664b091c-d3a2-4dae-83d8-c66b0de01fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277674776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.4277674776
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.3863111651
Short name T318
Test name
Test status
Simulation time 948235683 ps
CPU time 10.82 seconds
Started Aug 05 04:50:38 PM PDT 24
Finished Aug 05 04:50:49 PM PDT 24
Peak memory 225140 kb
Host smart-f10c00c3-d544-4b41-989a-4d9835e7cade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863111651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.3863111651
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.2638507054
Short name T436
Test name
Test status
Simulation time 8581165249 ps
CPU time 73.97 seconds
Started Aug 05 04:50:42 PM PDT 24
Finished Aug 05 04:51:56 PM PDT 24
Peak memory 256856 kb
Host smart-ce76dbe1-45c6-42d7-9cb4-1d7bcc7a2cba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638507054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmd
s.2638507054
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/23.spi_device_intercept.1204323465
Short name T262
Test name
Test status
Simulation time 842584714 ps
CPU time 4.08 seconds
Started Aug 05 04:50:40 PM PDT 24
Finished Aug 05 04:50:44 PM PDT 24
Peak memory 225124 kb
Host smart-dda92af5-c6af-4b94-b785-dad22fcb9560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204323465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.1204323465
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.947026529
Short name T471
Test name
Test status
Simulation time 381164597 ps
CPU time 5.06 seconds
Started Aug 05 04:50:52 PM PDT 24
Finished Aug 05 04:51:07 PM PDT 24
Peak memory 233468 kb
Host smart-1e73eee6-a086-44a8-8aa4-f068d5cb84de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947026529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.947026529
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.1690911322
Short name T577
Test name
Test status
Simulation time 10183407497 ps
CPU time 22.49 seconds
Started Aug 05 04:50:48 PM PDT 24
Finished Aug 05 04:51:10 PM PDT 24
Peak memory 249688 kb
Host smart-3de2ad40-d857-45bc-9630-b6a0dd5988cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690911322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.1690911322
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.1470639719
Short name T782
Test name
Test status
Simulation time 82946570605 ps
CPU time 26.58 seconds
Started Aug 05 04:50:37 PM PDT 24
Finished Aug 05 04:51:04 PM PDT 24
Peak memory 252028 kb
Host smart-65635e61-d0a6-48dd-88dd-95dbd4a7691f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470639719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.1470639719
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.1909576845
Short name T992
Test name
Test status
Simulation time 4518837807 ps
CPU time 27.48 seconds
Started Aug 05 04:50:43 PM PDT 24
Finished Aug 05 04:51:11 PM PDT 24
Peak memory 221244 kb
Host smart-04f3701d-7a8f-4a92-8a86-d0bba7c3c633
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1909576845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.1909576845
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.2830210695
Short name T971
Test name
Test status
Simulation time 124412099449 ps
CPU time 318.31 seconds
Started Aug 05 04:50:38 PM PDT 24
Finished Aug 05 04:55:56 PM PDT 24
Peak memory 266296 kb
Host smart-e4778c7a-9c52-4348-b785-342849ba8ad4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830210695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.2830210695
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.3480204019
Short name T721
Test name
Test status
Simulation time 1536743744 ps
CPU time 20.15 seconds
Started Aug 05 04:50:43 PM PDT 24
Finished Aug 05 04:51:04 PM PDT 24
Peak memory 216916 kb
Host smart-d4446ae1-5c80-4cf5-a0e1-1259ade4fd82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480204019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.3480204019
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.1765397828
Short name T858
Test name
Test status
Simulation time 8255098807 ps
CPU time 8.16 seconds
Started Aug 05 04:50:39 PM PDT 24
Finished Aug 05 04:50:47 PM PDT 24
Peak memory 216952 kb
Host smart-7ace4bdb-a36f-433c-8e03-b211d261909c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765397828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.1765397828
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.1584641469
Short name T477
Test name
Test status
Simulation time 59012083 ps
CPU time 1.24 seconds
Started Aug 05 04:50:36 PM PDT 24
Finished Aug 05 04:50:43 PM PDT 24
Peak memory 216888 kb
Host smart-0b92e90a-b450-4ad1-82e7-8f8481482f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584641469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.1584641469
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.4237241672
Short name T790
Test name
Test status
Simulation time 23834530 ps
CPU time 0.83 seconds
Started Aug 05 04:50:46 PM PDT 24
Finished Aug 05 04:50:46 PM PDT 24
Peak memory 206464 kb
Host smart-fac2ea93-f17e-4b35-973f-1fd9bc9968c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237241672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.4237241672
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.224968935
Short name T460
Test name
Test status
Simulation time 19648006514 ps
CPU time 46.42 seconds
Started Aug 05 04:50:36 PM PDT 24
Finished Aug 05 04:51:22 PM PDT 24
Peak memory 233420 kb
Host smart-4b39138a-f0df-402c-9eb1-e993e2ad0086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224968935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.224968935
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.3503501707
Short name T826
Test name
Test status
Simulation time 31504205 ps
CPU time 0.75 seconds
Started Aug 05 04:50:47 PM PDT 24
Finished Aug 05 04:50:48 PM PDT 24
Peak memory 205128 kb
Host smart-22f61e85-c79c-4e3d-9a73-ae30c152f41f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503501707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
3503501707
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.3099230835
Short name T252
Test name
Test status
Simulation time 85947630 ps
CPU time 2.44 seconds
Started Aug 05 04:50:54 PM PDT 24
Finished Aug 05 04:50:57 PM PDT 24
Peak memory 233640 kb
Host smart-603c06a4-847c-4f13-9936-af5e25f5271c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099230835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.3099230835
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.1679173712
Short name T445
Test name
Test status
Simulation time 37917497 ps
CPU time 0.77 seconds
Started Aug 05 04:50:37 PM PDT 24
Finished Aug 05 04:50:38 PM PDT 24
Peak memory 206968 kb
Host smart-deb8b31e-540d-4b02-b2d2-a4e20261d44f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679173712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.1679173712
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.2656131027
Short name T946
Test name
Test status
Simulation time 10386062219 ps
CPU time 89.27 seconds
Started Aug 05 04:50:37 PM PDT 24
Finished Aug 05 04:52:06 PM PDT 24
Peak memory 250120 kb
Host smart-cb013057-f8e9-4a20-bea7-7df9d58cde7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656131027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.2656131027
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.2856461917
Short name T147
Test name
Test status
Simulation time 14531416036 ps
CPU time 128.67 seconds
Started Aug 05 04:50:39 PM PDT 24
Finished Aug 05 04:52:48 PM PDT 24
Peak memory 256700 kb
Host smart-e53720e9-89f0-4853-a689-75fe8129c5d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856461917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.2856461917
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.2933159775
Short name T501
Test name
Test status
Simulation time 15113934938 ps
CPU time 63.82 seconds
Started Aug 05 04:50:47 PM PDT 24
Finished Aug 05 04:51:51 PM PDT 24
Peak memory 249872 kb
Host smart-99c675fa-2095-41f0-ba72-78fceaf8b7f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933159775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.2933159775
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.742533701
Short name T316
Test name
Test status
Simulation time 8004972061 ps
CPU time 37.57 seconds
Started Aug 05 04:50:28 PM PDT 24
Finished Aug 05 04:51:06 PM PDT 24
Peak memory 249824 kb
Host smart-cad8c853-9e7a-492a-af5a-c43331b9283c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742533701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.742533701
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.1987832754
Short name T182
Test name
Test status
Simulation time 78033572764 ps
CPU time 68.95 seconds
Started Aug 05 04:50:48 PM PDT 24
Finished Aug 05 04:51:57 PM PDT 24
Peak memory 250972 kb
Host smart-80081a62-718d-44a7-a5c2-d0ed8df3c125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987832754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmd
s.1987832754
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/24.spi_device_intercept.3192480625
Short name T551
Test name
Test status
Simulation time 519401781 ps
CPU time 3.59 seconds
Started Aug 05 04:50:42 PM PDT 24
Finished Aug 05 04:50:45 PM PDT 24
Peak memory 225140 kb
Host smart-8e5f6cee-f930-47f3-a413-9fdd7de57f1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192480625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.3192480625
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.985585544
Short name T398
Test name
Test status
Simulation time 2208190197 ps
CPU time 10.33 seconds
Started Aug 05 04:50:47 PM PDT 24
Finished Aug 05 04:50:57 PM PDT 24
Peak memory 238552 kb
Host smart-ec8826d7-5d8a-4355-8a22-747c75837793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985585544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.985585544
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.3539238291
Short name T267
Test name
Test status
Simulation time 6259216693 ps
CPU time 11.12 seconds
Started Aug 05 04:50:42 PM PDT 24
Finished Aug 05 04:50:53 PM PDT 24
Peak memory 233348 kb
Host smart-bac9d746-d8ab-40fa-a603-beb86ef84cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539238291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.3539238291
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.3433003209
Short name T204
Test name
Test status
Simulation time 11975841812 ps
CPU time 35.32 seconds
Started Aug 05 04:50:44 PM PDT 24
Finished Aug 05 04:51:19 PM PDT 24
Peak memory 252980 kb
Host smart-ba0e381a-86c9-49c9-8c20-7e8b9d64c14a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433003209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.3433003209
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.3825720617
Short name T642
Test name
Test status
Simulation time 1746701977 ps
CPU time 12.19 seconds
Started Aug 05 04:50:52 PM PDT 24
Finished Aug 05 04:51:05 PM PDT 24
Peak memory 220816 kb
Host smart-de58db5e-7aab-44e2-986c-9b9e15f124d6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3825720617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.3825720617
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.4231683609
Short name T942
Test name
Test status
Simulation time 7315023695 ps
CPU time 162.31 seconds
Started Aug 05 04:50:53 PM PDT 24
Finished Aug 05 04:53:36 PM PDT 24
Peak memory 274316 kb
Host smart-9bbab47c-0581-4f40-b0a0-f201ddfe7f0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231683609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.4231683609
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.1598313369
Short name T11
Test name
Test status
Simulation time 2595432846 ps
CPU time 13.8 seconds
Started Aug 05 04:50:41 PM PDT 24
Finished Aug 05 04:50:55 PM PDT 24
Peak memory 217008 kb
Host smart-b875d546-56a3-41b3-91bb-d6f669194164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598313369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.1598313369
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.3364702472
Short name T610
Test name
Test status
Simulation time 6708685266 ps
CPU time 18.62 seconds
Started Aug 05 04:50:37 PM PDT 24
Finished Aug 05 04:50:56 PM PDT 24
Peak memory 216908 kb
Host smart-1daae4af-a08b-4f91-b718-c06cec512d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364702472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.3364702472
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.956562919
Short name T569
Test name
Test status
Simulation time 109487962 ps
CPU time 3.15 seconds
Started Aug 05 04:50:54 PM PDT 24
Finished Aug 05 04:50:57 PM PDT 24
Peak memory 217060 kb
Host smart-d83d9c4e-add7-45db-a890-2d009dc4597a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956562919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.956562919
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.1764802541
Short name T355
Test name
Test status
Simulation time 39182836 ps
CPU time 0.76 seconds
Started Aug 05 04:50:27 PM PDT 24
Finished Aug 05 04:50:28 PM PDT 24
Peak memory 206468 kb
Host smart-575e19cb-d61f-4e48-967b-745d4b70b969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764802541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.1764802541
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.3232083882
Short name T253
Test name
Test status
Simulation time 11194678438 ps
CPU time 7.52 seconds
Started Aug 05 04:50:58 PM PDT 24
Finished Aug 05 04:51:06 PM PDT 24
Peak memory 225228 kb
Host smart-4f23e760-3a3d-4734-a413-d85a3b30072f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232083882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.3232083882
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.3773019444
Short name T366
Test name
Test status
Simulation time 11769928 ps
CPU time 0.74 seconds
Started Aug 05 04:50:50 PM PDT 24
Finished Aug 05 04:50:50 PM PDT 24
Peak memory 205164 kb
Host smart-bb93f276-ab61-4c60-a9fc-4f0867ddf9ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773019444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
3773019444
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.3616971739
Short name T756
Test name
Test status
Simulation time 86622315 ps
CPU time 2.62 seconds
Started Aug 05 04:50:46 PM PDT 24
Finished Aug 05 04:50:49 PM PDT 24
Peak memory 233288 kb
Host smart-df075b71-518c-4cfc-80f3-625a36c3fd8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616971739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.3616971739
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.4153531876
Short name T747
Test name
Test status
Simulation time 69689325 ps
CPU time 0.78 seconds
Started Aug 05 04:50:43 PM PDT 24
Finished Aug 05 04:50:44 PM PDT 24
Peak memory 206976 kb
Host smart-7f82982d-5b2b-4e12-b9c3-91968c3d70c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153531876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.4153531876
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.3225641154
Short name T448
Test name
Test status
Simulation time 31774221 ps
CPU time 0.77 seconds
Started Aug 05 04:50:46 PM PDT 24
Finished Aug 05 04:50:47 PM PDT 24
Peak memory 216368 kb
Host smart-5d7b9e54-65f2-457c-a235-1c031e7129e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225641154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.3225641154
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.3973515276
Short name T559
Test name
Test status
Simulation time 3375448859 ps
CPU time 31.58 seconds
Started Aug 05 04:50:55 PM PDT 24
Finished Aug 05 04:51:27 PM PDT 24
Peak memory 249016 kb
Host smart-b1f33a5e-caf3-40ef-b608-39a41156c85d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973515276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.3973515276
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.3795257174
Short name T934
Test name
Test status
Simulation time 24817737234 ps
CPU time 133.54 seconds
Started Aug 05 04:50:47 PM PDT 24
Finished Aug 05 04:53:01 PM PDT 24
Peak memory 266220 kb
Host smart-4fc1f5e5-c5cb-418c-bccd-f6926a4d0ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795257174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.3795257174
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.2106702447
Short name T984
Test name
Test status
Simulation time 13307594 ps
CPU time 0.76 seconds
Started Aug 05 04:50:49 PM PDT 24
Finished Aug 05 04:50:49 PM PDT 24
Peak memory 216380 kb
Host smart-b40a50df-5120-4ce4-aebe-271281f82188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106702447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmd
s.2106702447
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/25.spi_device_intercept.1877063283
Short name T943
Test name
Test status
Simulation time 7357311836 ps
CPU time 24.67 seconds
Started Aug 05 04:50:45 PM PDT 24
Finished Aug 05 04:51:10 PM PDT 24
Peak memory 225172 kb
Host smart-74a386b2-059f-4bd6-a21b-3d589cda5d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877063283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.1877063283
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.2102149150
Short name T226
Test name
Test status
Simulation time 1438706049 ps
CPU time 4.66 seconds
Started Aug 05 04:50:47 PM PDT 24
Finished Aug 05 04:50:52 PM PDT 24
Peak memory 225136 kb
Host smart-5168d053-e3a0-4cea-975c-1850043ada5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102149150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.2102149150
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.2805618994
Short name T652
Test name
Test status
Simulation time 1563833650 ps
CPU time 13.83 seconds
Started Aug 05 04:50:45 PM PDT 24
Finished Aug 05 04:50:59 PM PDT 24
Peak memory 233344 kb
Host smart-f47cbc2d-be40-4b41-a23e-1905b8c70645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805618994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.2805618994
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.2493041978
Short name T650
Test name
Test status
Simulation time 4180394202 ps
CPU time 14.93 seconds
Started Aug 05 04:50:41 PM PDT 24
Finished Aug 05 04:50:56 PM PDT 24
Peak memory 241568 kb
Host smart-db374a37-f1bc-4d1b-ac30-ae6950758d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493041978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.2493041978
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.634607142
Short name T57
Test name
Test status
Simulation time 9471722179 ps
CPU time 11.77 seconds
Started Aug 05 04:50:58 PM PDT 24
Finished Aug 05 04:51:10 PM PDT 24
Peak memory 224008 kb
Host smart-28a00e9f-c3f2-4b9c-980a-82810b492350
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=634607142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dire
ct.634607142
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.4237081284
Short name T297
Test name
Test status
Simulation time 170672632207 ps
CPU time 434.51 seconds
Started Aug 05 04:50:49 PM PDT 24
Finished Aug 05 04:58:04 PM PDT 24
Peak memory 256672 kb
Host smart-81e3ee84-d2ab-4bba-b0bc-3567216896fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237081284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.4237081284
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.3173945278
Short name T541
Test name
Test status
Simulation time 9363377484 ps
CPU time 20.23 seconds
Started Aug 05 04:50:44 PM PDT 24
Finished Aug 05 04:51:04 PM PDT 24
Peak memory 216996 kb
Host smart-6c93b280-37a1-4041-9cef-a8516ebb6afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173945278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.3173945278
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.805659858
Short name T82
Test name
Test status
Simulation time 1828878412 ps
CPU time 3.92 seconds
Started Aug 05 04:50:50 PM PDT 24
Finished Aug 05 04:50:54 PM PDT 24
Peak memory 216864 kb
Host smart-00c884ed-a370-4282-a299-9ec646688617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805659858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.805659858
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.2291882621
Short name T825
Test name
Test status
Simulation time 4387899594 ps
CPU time 9.2 seconds
Started Aug 05 04:50:38 PM PDT 24
Finished Aug 05 04:50:48 PM PDT 24
Peak memory 217292 kb
Host smart-7312a240-4ef5-41c9-b9c6-ccbc6ce16734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291882621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.2291882621
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.4258511626
Short name T429
Test name
Test status
Simulation time 34652928 ps
CPU time 0.83 seconds
Started Aug 05 04:50:29 PM PDT 24
Finished Aug 05 04:50:30 PM PDT 24
Peak memory 206456 kb
Host smart-fbeda1b3-833b-4d11-a5e8-9ff88289c5d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258511626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.4258511626
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.3920810820
Short name T710
Test name
Test status
Simulation time 105466527 ps
CPU time 2.55 seconds
Started Aug 05 04:50:44 PM PDT 24
Finished Aug 05 04:50:46 PM PDT 24
Peak memory 236216 kb
Host smart-8bf594ee-7423-454e-ac41-c9487a1611e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920810820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.3920810820
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.116098024
Short name T538
Test name
Test status
Simulation time 33219639 ps
CPU time 0.74 seconds
Started Aug 05 04:51:00 PM PDT 24
Finished Aug 05 04:51:00 PM PDT 24
Peak memory 205732 kb
Host smart-ad0d84c5-43c8-4ad4-bfa2-0104e458ecef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116098024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.116098024
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.3366972732
Short name T357
Test name
Test status
Simulation time 527347163 ps
CPU time 3.72 seconds
Started Aug 05 04:50:47 PM PDT 24
Finished Aug 05 04:50:51 PM PDT 24
Peak memory 233324 kb
Host smart-73097b97-7d09-453b-a616-c2ee4b544247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366972732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.3366972732
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.3397537035
Short name T644
Test name
Test status
Simulation time 15682491 ps
CPU time 0.8 seconds
Started Aug 05 04:50:39 PM PDT 24
Finished Aug 05 04:50:40 PM PDT 24
Peak memory 206944 kb
Host smart-8e6b03f5-4b39-4b8f-818e-507c1572a435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397537035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.3397537035
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.1215987276
Short name T224
Test name
Test status
Simulation time 77651385580 ps
CPU time 225.67 seconds
Started Aug 05 04:50:54 PM PDT 24
Finished Aug 05 04:54:40 PM PDT 24
Peak memory 254076 kb
Host smart-4efd1097-bed3-4596-a74a-ce1c34e24f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215987276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.1215987276
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.680654073
Short name T877
Test name
Test status
Simulation time 129734053334 ps
CPU time 307.75 seconds
Started Aug 05 04:50:48 PM PDT 24
Finished Aug 05 04:55:56 PM PDT 24
Peak memory 250880 kb
Host smart-7b6486b2-ef39-4821-a625-6a1aa5b37f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680654073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.680654073
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.2813489718
Short name T395
Test name
Test status
Simulation time 11622615438 ps
CPU time 108.38 seconds
Started Aug 05 04:50:49 PM PDT 24
Finished Aug 05 04:52:37 PM PDT 24
Peak memory 252208 kb
Host smart-7cb75e09-fe9d-4bd2-b8c5-66513fc032ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813489718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.2813489718
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.2272753015
Short name T371
Test name
Test status
Simulation time 944928873 ps
CPU time 4.93 seconds
Started Aug 05 04:50:53 PM PDT 24
Finished Aug 05 04:50:58 PM PDT 24
Peak memory 225160 kb
Host smart-3ee0bb33-f6c4-40c6-bd22-faed14f5415e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272753015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.2272753015
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.3214576909
Short name T814
Test name
Test status
Simulation time 7310380458 ps
CPU time 58.78 seconds
Started Aug 05 04:50:52 PM PDT 24
Finished Aug 05 04:51:51 PM PDT 24
Peak memory 240860 kb
Host smart-cbe97ffd-319d-423e-8d4d-7870d3cb235a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214576909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmd
s.3214576909
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_intercept.1865271946
Short name T864
Test name
Test status
Simulation time 1851719844 ps
CPU time 11.58 seconds
Started Aug 05 04:50:48 PM PDT 24
Finished Aug 05 04:51:00 PM PDT 24
Peak memory 233348 kb
Host smart-c7f1f8e2-1e0b-4606-b700-fbb949a2c798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865271946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.1865271946
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.1477260438
Short name T838
Test name
Test status
Simulation time 563825449 ps
CPU time 4.75 seconds
Started Aug 05 04:50:47 PM PDT 24
Finished Aug 05 04:50:52 PM PDT 24
Peak memory 233508 kb
Host smart-cc008c27-c62b-4387-b0c7-d9ed4f0cf182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477260438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.1477260438
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.4233729658
Short name T760
Test name
Test status
Simulation time 1130701153 ps
CPU time 6.57 seconds
Started Aug 05 04:50:46 PM PDT 24
Finished Aug 05 04:50:52 PM PDT 24
Peak memory 225128 kb
Host smart-ecb5d3d9-a908-435d-a083-379ff917dbba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233729658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.4233729658
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.2225465882
Short name T585
Test name
Test status
Simulation time 13001494546 ps
CPU time 10.89 seconds
Started Aug 05 04:50:55 PM PDT 24
Finished Aug 05 04:51:07 PM PDT 24
Peak memory 233396 kb
Host smart-47540e97-8b2d-4218-85f2-421515e87f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225465882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.2225465882
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.877556107
Short name T565
Test name
Test status
Simulation time 1886965160 ps
CPU time 18.82 seconds
Started Aug 05 04:50:53 PM PDT 24
Finished Aug 05 04:51:12 PM PDT 24
Peak memory 220848 kb
Host smart-b4fed4c0-8d04-49c1-96b3-2e8f27db4354
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=877556107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dire
ct.877556107
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.526228912
Short name T39
Test name
Test status
Simulation time 83060691407 ps
CPU time 449.27 seconds
Started Aug 05 04:50:49 PM PDT 24
Finished Aug 05 04:58:18 PM PDT 24
Peak memory 272760 kb
Host smart-76d9def9-137b-4cb1-98f1-1162ac58db3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526228912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stres
s_all.526228912
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.3337855438
Short name T744
Test name
Test status
Simulation time 6158151924 ps
CPU time 17.22 seconds
Started Aug 05 04:50:47 PM PDT 24
Finished Aug 05 04:51:04 PM PDT 24
Peak memory 217092 kb
Host smart-f3554e80-474c-47fa-bb0e-1c1f407924d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337855438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.3337855438
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.664337337
Short name T367
Test name
Test status
Simulation time 3384415205 ps
CPU time 5.78 seconds
Started Aug 05 04:50:55 PM PDT 24
Finished Aug 05 04:51:01 PM PDT 24
Peak memory 217036 kb
Host smart-b5b37cb4-c0c8-4cf5-8b3c-3bcd953cf445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664337337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.664337337
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.3859199652
Short name T925
Test name
Test status
Simulation time 20675041 ps
CPU time 1.31 seconds
Started Aug 05 04:50:33 PM PDT 24
Finished Aug 05 04:50:35 PM PDT 24
Peak memory 216828 kb
Host smart-e4c8068f-db37-488f-a7d1-a14e0c7b6164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859199652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.3859199652
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.2012752266
Short name T878
Test name
Test status
Simulation time 61590890 ps
CPU time 0.86 seconds
Started Aug 05 04:50:40 PM PDT 24
Finished Aug 05 04:50:41 PM PDT 24
Peak memory 206416 kb
Host smart-4a61b6d4-1c22-45e7-b44d-db26f0191e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012752266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.2012752266
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.1026356671
Short name T861
Test name
Test status
Simulation time 4396783092 ps
CPU time 6.62 seconds
Started Aug 05 04:50:47 PM PDT 24
Finished Aug 05 04:50:54 PM PDT 24
Peak memory 225192 kb
Host smart-47db0eea-7ee7-426e-9c2d-9fdd74218a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026356671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.1026356671
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.549178822
Short name T495
Test name
Test status
Simulation time 53822220 ps
CPU time 0.73 seconds
Started Aug 05 04:50:51 PM PDT 24
Finished Aug 05 04:50:52 PM PDT 24
Peak memory 205180 kb
Host smart-f8d61cea-e0f9-4956-8bdb-38115ea7aa3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549178822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.549178822
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.2068348535
Short name T653
Test name
Test status
Simulation time 3655309452 ps
CPU time 9.33 seconds
Started Aug 05 04:50:52 PM PDT 24
Finished Aug 05 04:51:02 PM PDT 24
Peak memory 225312 kb
Host smart-24bba202-53eb-410c-8c0e-432ea8201934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068348535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.2068348535
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.2673756355
Short name T1001
Test name
Test status
Simulation time 67569540 ps
CPU time 0.8 seconds
Started Aug 05 04:50:59 PM PDT 24
Finished Aug 05 04:51:00 PM PDT 24
Peak memory 207072 kb
Host smart-17db2ed8-1cd3-4ba7-b944-17c69a8da4fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673756355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.2673756355
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.1235535541
Short name T937
Test name
Test status
Simulation time 89077354573 ps
CPU time 169.26 seconds
Started Aug 05 04:50:49 PM PDT 24
Finished Aug 05 04:53:38 PM PDT 24
Peak memory 257028 kb
Host smart-3534a3aa-888f-415c-bd54-0270bfbaacb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235535541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.1235535541
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.2131340922
Short name T669
Test name
Test status
Simulation time 53462333213 ps
CPU time 98.65 seconds
Started Aug 05 04:50:45 PM PDT 24
Finished Aug 05 04:52:23 PM PDT 24
Peak memory 238636 kb
Host smart-abdb8761-48cd-413f-bd9c-865621797c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131340922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.2131340922
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.3643833184
Short name T596
Test name
Test status
Simulation time 2421705050 ps
CPU time 55.56 seconds
Started Aug 05 04:50:47 PM PDT 24
Finished Aug 05 04:51:43 PM PDT 24
Peak memory 249900 kb
Host smart-76954a82-3b93-46ff-9041-548fa9cfced8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643833184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.3643833184
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.1890715092
Short name T959
Test name
Test status
Simulation time 242569157 ps
CPU time 4.53 seconds
Started Aug 05 04:50:52 PM PDT 24
Finished Aug 05 04:50:56 PM PDT 24
Peak memory 233412 kb
Host smart-6ccefab5-b139-4068-be19-c14aeb25ed34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890715092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.1890715092
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.3112887757
Short name T28
Test name
Test status
Simulation time 19680699544 ps
CPU time 164.28 seconds
Started Aug 05 04:50:51 PM PDT 24
Finished Aug 05 04:53:36 PM PDT 24
Peak memory 255292 kb
Host smart-462b6a63-b3d2-4e06-8a86-84c884dea0fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112887757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmd
s.3112887757
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/27.spi_device_intercept.483817352
Short name T702
Test name
Test status
Simulation time 2322321466 ps
CPU time 5.6 seconds
Started Aug 05 04:50:49 PM PDT 24
Finished Aug 05 04:50:55 PM PDT 24
Peak memory 233440 kb
Host smart-e4429651-0050-4f40-a785-9388bbff5cd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483817352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.483817352
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.1011234512
Short name T282
Test name
Test status
Simulation time 417998151 ps
CPU time 4.04 seconds
Started Aug 05 04:50:51 PM PDT 24
Finished Aug 05 04:50:55 PM PDT 24
Peak memory 225208 kb
Host smart-0c973af6-07de-413d-9e4a-33103daae492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011234512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.1011234512
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.279987892
Short name T281
Test name
Test status
Simulation time 234759122 ps
CPU time 3.4 seconds
Started Aug 05 04:50:47 PM PDT 24
Finished Aug 05 04:50:50 PM PDT 24
Peak memory 225160 kb
Host smart-ab71ed29-32e5-406e-8df4-7742d3bd14e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279987892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swap
.279987892
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.3932475768
Short name T829
Test name
Test status
Simulation time 3868986872 ps
CPU time 6.24 seconds
Started Aug 05 04:50:51 PM PDT 24
Finished Aug 05 04:50:57 PM PDT 24
Peak memory 225172 kb
Host smart-6cb33f79-04e2-4f8b-abed-579371f4b32c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932475768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.3932475768
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.1008352093
Short name T794
Test name
Test status
Simulation time 3083533620 ps
CPU time 6.06 seconds
Started Aug 05 04:50:48 PM PDT 24
Finished Aug 05 04:50:54 PM PDT 24
Peak memory 223840 kb
Host smart-1c64ec29-fe27-4498-8d68-064f3e807709
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1008352093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.1008352093
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.2822785533
Short name T789
Test name
Test status
Simulation time 4923504482 ps
CPU time 34.87 seconds
Started Aug 05 04:50:54 PM PDT 24
Finished Aug 05 04:51:29 PM PDT 24
Peak memory 217020 kb
Host smart-a2ec014f-5ea5-47e1-a513-5bfcdce7546f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822785533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.2822785533
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.135222021
Short name T339
Test name
Test status
Simulation time 14170742 ps
CPU time 0.73 seconds
Started Aug 05 04:50:51 PM PDT 24
Finished Aug 05 04:50:57 PM PDT 24
Peak memory 206100 kb
Host smart-c2befc46-16a8-4fbc-9d07-2b4e3cda2edd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135222021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.135222021
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.2262557969
Short name T883
Test name
Test status
Simulation time 2144181051 ps
CPU time 7.66 seconds
Started Aug 05 04:50:48 PM PDT 24
Finished Aug 05 04:50:56 PM PDT 24
Peak memory 216804 kb
Host smart-3a99f182-3f1b-47b1-8f90-58a82363ed68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262557969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.2262557969
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.1617029481
Short name T417
Test name
Test status
Simulation time 71084787 ps
CPU time 0.8 seconds
Started Aug 05 04:51:01 PM PDT 24
Finished Aug 05 04:51:02 PM PDT 24
Peak memory 206472 kb
Host smart-4400f867-cd29-49ac-9c5a-9729cf6c65ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617029481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.1617029481
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.1041689675
Short name T278
Test name
Test status
Simulation time 844899281 ps
CPU time 5.73 seconds
Started Aug 05 04:51:00 PM PDT 24
Finished Aug 05 04:51:06 PM PDT 24
Peak memory 233288 kb
Host smart-6944d726-2796-4973-8208-f50e3804b4b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041689675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.1041689675
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.1950107429
Short name T851
Test name
Test status
Simulation time 43644981 ps
CPU time 0.81 seconds
Started Aug 05 04:50:49 PM PDT 24
Finished Aug 05 04:50:50 PM PDT 24
Peak memory 205136 kb
Host smart-74aefc1b-1b70-4639-a7a8-ccc284a8e9fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950107429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
1950107429
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.1731284219
Short name T597
Test name
Test status
Simulation time 464958103 ps
CPU time 2.86 seconds
Started Aug 05 04:50:44 PM PDT 24
Finished Aug 05 04:50:47 PM PDT 24
Peak memory 225108 kb
Host smart-6c83b080-7605-414b-b016-e4ef385762fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731284219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.1731284219
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.733324193
Short name T344
Test name
Test status
Simulation time 46268923 ps
CPU time 0.73 seconds
Started Aug 05 04:50:42 PM PDT 24
Finished Aug 05 04:50:43 PM PDT 24
Peak memory 207272 kb
Host smart-4fda7e2a-a6de-404e-b400-22dd7ca2bc3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733324193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.733324193
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.4203440382
Short name T328
Test name
Test status
Simulation time 653930471 ps
CPU time 13.16 seconds
Started Aug 05 04:50:50 PM PDT 24
Finished Aug 05 04:51:04 PM PDT 24
Peak memory 225348 kb
Host smart-e634a3c9-2691-46dc-bdb3-e5dcf18843ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203440382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.4203440382
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.3118064312
Short name T677
Test name
Test status
Simulation time 28085270182 ps
CPU time 184.3 seconds
Started Aug 05 04:50:57 PM PDT 24
Finished Aug 05 04:54:01 PM PDT 24
Peak memory 253244 kb
Host smart-ad838ddb-93e4-4987-8a08-d551aed4b92e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118064312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.3118064312
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.2550909320
Short name T244
Test name
Test status
Simulation time 22733726028 ps
CPU time 89.53 seconds
Started Aug 05 04:50:50 PM PDT 24
Finished Aug 05 04:52:20 PM PDT 24
Peak memory 252724 kb
Host smart-8d3f1dd9-d977-4395-a444-cfa407bd0210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550909320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmd
s.2550909320
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/28.spi_device_intercept.3030199368
Short name T405
Test name
Test status
Simulation time 2033278050 ps
CPU time 16.01 seconds
Started Aug 05 04:50:53 PM PDT 24
Finished Aug 05 04:51:09 PM PDT 24
Peak memory 225256 kb
Host smart-73561be5-cc73-4cb3-bf44-2e08919e6c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030199368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.3030199368
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.3058052333
Short name T714
Test name
Test status
Simulation time 53931695 ps
CPU time 2.17 seconds
Started Aug 05 04:50:50 PM PDT 24
Finished Aug 05 04:50:52 PM PDT 24
Peak memory 223624 kb
Host smart-c4460159-14fc-4529-a72d-48f4d8e82d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058052333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.3058052333
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.512229367
Short name T603
Test name
Test status
Simulation time 1795107019 ps
CPU time 4.21 seconds
Started Aug 05 04:50:48 PM PDT 24
Finished Aug 05 04:50:53 PM PDT 24
Peak memory 233416 kb
Host smart-bd123704-ffb4-475e-8f34-33913d9c1e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512229367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swap
.512229367
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.1322460648
Short name T700
Test name
Test status
Simulation time 1661333062 ps
CPU time 7.66 seconds
Started Aug 05 04:50:59 PM PDT 24
Finished Aug 05 04:51:07 PM PDT 24
Peak memory 233388 kb
Host smart-eb8d54b9-b0bc-49ee-860c-32b905cec944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322460648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.1322460648
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.3069062658
Short name T151
Test name
Test status
Simulation time 1528024062 ps
CPU time 7.15 seconds
Started Aug 05 04:50:58 PM PDT 24
Finished Aug 05 04:51:05 PM PDT 24
Peak memory 222836 kb
Host smart-84c37967-6a21-40c4-9dda-2c121fb49d50
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3069062658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.3069062658
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.3106066033
Short name T431
Test name
Test status
Simulation time 247583141 ps
CPU time 1.26 seconds
Started Aug 05 04:50:55 PM PDT 24
Finished Aug 05 04:50:56 PM PDT 24
Peak memory 207484 kb
Host smart-97e01193-419e-473b-8948-cae50466c29f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106066033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.3106066033
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.825597556
Short name T680
Test name
Test status
Simulation time 2734106462 ps
CPU time 8.03 seconds
Started Aug 05 04:50:48 PM PDT 24
Finished Aug 05 04:50:56 PM PDT 24
Peak memory 216892 kb
Host smart-9558ecfc-0ac3-40b3-bd70-ddf09fd0ed42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825597556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.825597556
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.7570608
Short name T363
Test name
Test status
Simulation time 20755392747 ps
CPU time 6.38 seconds
Started Aug 05 04:51:00 PM PDT 24
Finished Aug 05 04:51:07 PM PDT 24
Peak memory 216872 kb
Host smart-ee672a0f-6dc3-4141-86da-70bfb117951f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7570608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.7570608
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.318211050
Short name T803
Test name
Test status
Simulation time 57458044 ps
CPU time 2.81 seconds
Started Aug 05 04:50:46 PM PDT 24
Finished Aug 05 04:50:49 PM PDT 24
Peak memory 216876 kb
Host smart-3ecd9674-8ed1-49a6-8eb6-d2a0a2c18191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318211050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.318211050
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.1612182450
Short name T897
Test name
Test status
Simulation time 346962124 ps
CPU time 0.8 seconds
Started Aug 05 04:50:52 PM PDT 24
Finished Aug 05 04:50:53 PM PDT 24
Peak memory 206436 kb
Host smart-f3d78164-ac08-4247-a00b-3eeec8a18d97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612182450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.1612182450
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.1581654161
Short name T474
Test name
Test status
Simulation time 418073829 ps
CPU time 2.11 seconds
Started Aug 05 04:50:59 PM PDT 24
Finished Aug 05 04:51:01 PM PDT 24
Peak memory 224504 kb
Host smart-f17a771d-e2bd-46ca-ac09-8b7c9104ce05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581654161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.1581654161
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.1583081731
Short name T534
Test name
Test status
Simulation time 15022197 ps
CPU time 0.69 seconds
Started Aug 05 04:50:55 PM PDT 24
Finished Aug 05 04:50:56 PM PDT 24
Peak memory 205808 kb
Host smart-011ee24b-5b1a-441a-bbbf-2ee5f3ffd0dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583081731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
1583081731
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.2398877392
Short name T279
Test name
Test status
Simulation time 589168706 ps
CPU time 4.38 seconds
Started Aug 05 04:50:45 PM PDT 24
Finished Aug 05 04:50:49 PM PDT 24
Peak memory 233348 kb
Host smart-8a4e6488-772f-491f-8a31-07a5213572a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398877392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.2398877392
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.1403718103
Short name T341
Test name
Test status
Simulation time 82915635 ps
CPU time 0.78 seconds
Started Aug 05 04:50:53 PM PDT 24
Finished Aug 05 04:50:54 PM PDT 24
Peak memory 206064 kb
Host smart-5ecd4f98-443d-4dfb-9c6a-26ce2387986b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403718103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.1403718103
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.370606467
Short name T408
Test name
Test status
Simulation time 16389605 ps
CPU time 0.76 seconds
Started Aug 05 04:50:58 PM PDT 24
Finished Aug 05 04:50:59 PM PDT 24
Peak memory 216304 kb
Host smart-2b8c6006-5b82-4bea-b4b8-f5f5608cd023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370606467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.370606467
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.1953289445
Short name T684
Test name
Test status
Simulation time 4525643074 ps
CPU time 8.54 seconds
Started Aug 05 04:50:51 PM PDT 24
Finished Aug 05 04:51:00 PM PDT 24
Peak memory 218452 kb
Host smart-ce014746-85bb-444a-a52f-244b6d1ab1a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953289445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.1953289445
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.751145496
Short name T529
Test name
Test status
Simulation time 34510222849 ps
CPU time 132.73 seconds
Started Aug 05 04:50:52 PM PDT 24
Finished Aug 05 04:53:05 PM PDT 24
Peak memory 257880 kb
Host smart-fec8c801-e4d0-4502-b1be-e5aa784ad3c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751145496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idle
.751145496
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.992150938
Short name T372
Test name
Test status
Simulation time 36009299 ps
CPU time 2.15 seconds
Started Aug 05 04:50:58 PM PDT 24
Finished Aug 05 04:51:01 PM PDT 24
Peak memory 225136 kb
Host smart-57fff62d-3e28-4e5b-83d7-3290d9fbcc95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992150938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.992150938
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.2912074224
Short name T391
Test name
Test status
Simulation time 40602571 ps
CPU time 0.86 seconds
Started Aug 05 04:50:43 PM PDT 24
Finished Aug 05 04:50:44 PM PDT 24
Peak memory 216208 kb
Host smart-afa07ca6-c89a-408e-b150-0316e678b903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912074224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmd
s.2912074224
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/29.spi_device_intercept.2327550819
Short name T844
Test name
Test status
Simulation time 122811655 ps
CPU time 2.26 seconds
Started Aug 05 04:50:59 PM PDT 24
Finished Aug 05 04:51:01 PM PDT 24
Peak memory 232980 kb
Host smart-adaf39f1-0e92-4b3c-b5f6-3038dfc2a42c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327550819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.2327550819
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.1578269968
Short name T890
Test name
Test status
Simulation time 2515218899 ps
CPU time 29.22 seconds
Started Aug 05 04:50:55 PM PDT 24
Finished Aug 05 04:51:24 PM PDT 24
Peak memory 234332 kb
Host smart-4ab79397-f25d-4561-acd1-34e9c87e18ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578269968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.1578269968
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.1521749061
Short name T416
Test name
Test status
Simulation time 2800532284 ps
CPU time 10.03 seconds
Started Aug 05 04:50:56 PM PDT 24
Finished Aug 05 04:51:06 PM PDT 24
Peak memory 234436 kb
Host smart-acdfd05d-2021-4bde-8cdc-e3f8acff2444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521749061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.1521749061
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.3115528763
Short name T772
Test name
Test status
Simulation time 7021728931 ps
CPU time 21.21 seconds
Started Aug 05 04:50:58 PM PDT 24
Finished Aug 05 04:51:20 PM PDT 24
Peak memory 241588 kb
Host smart-ec28f7a1-2e50-473c-b630-a716087e3cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115528763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.3115528763
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.1076335371
Short name T980
Test name
Test status
Simulation time 914472789 ps
CPU time 6.98 seconds
Started Aug 05 04:51:06 PM PDT 24
Finished Aug 05 04:51:13 PM PDT 24
Peak memory 223512 kb
Host smart-bca41d63-225c-4d86-8a42-40f772d33c05
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1076335371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.1076335371
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.242632770
Short name T944
Test name
Test status
Simulation time 68606769786 ps
CPU time 69.77 seconds
Started Aug 05 04:50:50 PM PDT 24
Finished Aug 05 04:52:00 PM PDT 24
Peak memory 250344 kb
Host smart-4c07101a-9a10-4813-b543-5db3159ae0c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242632770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stres
s_all.242632770
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.3721750628
Short name T441
Test name
Test status
Simulation time 1166331009 ps
CPU time 11.24 seconds
Started Aug 05 04:50:51 PM PDT 24
Finished Aug 05 04:51:02 PM PDT 24
Peak memory 217020 kb
Host smart-f616b85e-8619-43c9-bf18-c4dc296fa7f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721750628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.3721750628
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.218330999
Short name T353
Test name
Test status
Simulation time 6932313711 ps
CPU time 19.74 seconds
Started Aug 05 04:50:54 PM PDT 24
Finished Aug 05 04:51:14 PM PDT 24
Peak memory 216764 kb
Host smart-0297260e-7106-494b-82b6-fd702db08cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218330999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.218330999
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.965643521
Short name T791
Test name
Test status
Simulation time 105784860 ps
CPU time 1.33 seconds
Started Aug 05 04:50:43 PM PDT 24
Finished Aug 05 04:50:44 PM PDT 24
Peak memory 216844 kb
Host smart-2eeb5030-ee8f-4898-86f7-f8b42f823573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965643521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.965643521
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.1314666714
Short name T373
Test name
Test status
Simulation time 1046907698 ps
CPU time 0.99 seconds
Started Aug 05 04:50:58 PM PDT 24
Finished Aug 05 04:50:59 PM PDT 24
Peak memory 206436 kb
Host smart-6ae53924-b0e2-4c97-bbd7-c100e8389add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314666714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.1314666714
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.1514226598
Short name T732
Test name
Test status
Simulation time 278969936 ps
CPU time 3.56 seconds
Started Aug 05 04:51:09 PM PDT 24
Finished Aug 05 04:51:13 PM PDT 24
Peak memory 225144 kb
Host smart-38690105-fd3a-4526-b421-94544d8f33ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514226598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.1514226598
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.2954037891
Short name T512
Test name
Test status
Simulation time 41371734 ps
CPU time 0.71 seconds
Started Aug 05 04:49:59 PM PDT 24
Finished Aug 05 04:50:00 PM PDT 24
Peak memory 205720 kb
Host smart-9080afde-60cb-4767-abe2-e29b771f3eec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954037891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.2
954037891
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.3796588906
Short name T364
Test name
Test status
Simulation time 991960425 ps
CPU time 4.5 seconds
Started Aug 05 04:49:48 PM PDT 24
Finished Aug 05 04:49:53 PM PDT 24
Peak memory 233332 kb
Host smart-6d68c82d-7657-48fe-bd8d-476ca26b8ba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796588906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.3796588906
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.839130192
Short name T523
Test name
Test status
Simulation time 42439352 ps
CPU time 0.73 seconds
Started Aug 05 04:49:55 PM PDT 24
Finished Aug 05 04:49:56 PM PDT 24
Peak memory 205864 kb
Host smart-dfc8e3f1-bdec-4f5d-9086-0703f6f3afe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839130192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.839130192
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.2749144876
Short name T26
Test name
Test status
Simulation time 2546836737 ps
CPU time 51.11 seconds
Started Aug 05 04:49:57 PM PDT 24
Finished Aug 05 04:50:48 PM PDT 24
Peak memory 251912 kb
Host smart-6caeaff0-1f20-46cc-95ef-c0dc69c749b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749144876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.2749144876
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.926610371
Short name T731
Test name
Test status
Simulation time 22941128338 ps
CPU time 29.34 seconds
Started Aug 05 04:49:54 PM PDT 24
Finished Aug 05 04:50:23 PM PDT 24
Peak memory 218368 kb
Host smart-f0b679b4-6c24-4df8-87bf-c1c0da1a7de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926610371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.926610371
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.205837302
Short name T696
Test name
Test status
Simulation time 5831639090 ps
CPU time 89.58 seconds
Started Aug 05 04:49:37 PM PDT 24
Finished Aug 05 04:51:07 PM PDT 24
Peak memory 267376 kb
Host smart-fc7399ed-835b-4de1-abd3-b1db3b0887ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205837302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle.
205837302
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.818763156
Short name T320
Test name
Test status
Simulation time 16705473309 ps
CPU time 14.96 seconds
Started Aug 05 04:49:57 PM PDT 24
Finished Aug 05 04:50:13 PM PDT 24
Peak memory 234580 kb
Host smart-a0cc70c1-bf56-44b2-b32e-9dcdc0901275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818763156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.818763156
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_intercept.1808454904
Short name T828
Test name
Test status
Simulation time 292883275 ps
CPU time 3.16 seconds
Started Aug 05 04:49:54 PM PDT 24
Finished Aug 05 04:49:57 PM PDT 24
Peak memory 233340 kb
Host smart-d09fcdf2-82f3-47b3-ae0f-c3820321b53f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808454904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.1808454904
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.2315482189
Short name T80
Test name
Test status
Simulation time 2849451026 ps
CPU time 14.58 seconds
Started Aug 05 04:49:31 PM PDT 24
Finished Aug 05 04:49:45 PM PDT 24
Peak memory 239916 kb
Host smart-e4ce1766-00f9-4038-b366-28db111e7640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315482189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.2315482189
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.3735688907
Short name T741
Test name
Test status
Simulation time 32003600 ps
CPU time 1.09 seconds
Started Aug 05 04:49:38 PM PDT 24
Finished Aug 05 04:49:40 PM PDT 24
Peak memory 217116 kb
Host smart-bbb10ca3-7cab-48de-9206-b4f921973bfa
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735688907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.spi_device_mem_parity.3735688907
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.2084511831
Short name T74
Test name
Test status
Simulation time 405240217 ps
CPU time 7.56 seconds
Started Aug 05 04:49:34 PM PDT 24
Finished Aug 05 04:49:42 PM PDT 24
Peak memory 241196 kb
Host smart-fdbfc212-7381-499c-8b13-6df03da23cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084511831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.2084511831
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.3586047262
Short name T118
Test name
Test status
Simulation time 4288627171 ps
CPU time 8.93 seconds
Started Aug 05 04:49:42 PM PDT 24
Finished Aug 05 04:49:51 PM PDT 24
Peak memory 241232 kb
Host smart-90432376-209a-4d98-af39-a0f43fe46f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586047262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.3586047262
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.3067147716
Short name T157
Test name
Test status
Simulation time 3031398178 ps
CPU time 16.71 seconds
Started Aug 05 04:49:52 PM PDT 24
Finished Aug 05 04:50:09 PM PDT 24
Peak memory 220764 kb
Host smart-146c0e4c-1bb8-48f1-9244-62fcaf080f00
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3067147716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.3067147716
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.3205449546
Short name T72
Test name
Test status
Simulation time 159866867 ps
CPU time 1.18 seconds
Started Aug 05 04:49:38 PM PDT 24
Finished Aug 05 04:49:40 PM PDT 24
Peak memory 236040 kb
Host smart-e5a20236-d5d0-484f-bc82-aa438e7233d1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205449546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.3205449546
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.2213046913
Short name T331
Test name
Test status
Simulation time 25163050807 ps
CPU time 43.93 seconds
Started Aug 05 04:49:31 PM PDT 24
Finished Aug 05 04:50:15 PM PDT 24
Peak memory 217296 kb
Host smart-25b76ad2-3051-4b90-bdb6-caa8afbbae03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213046913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.2213046913
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.779090151
Short name T440
Test name
Test status
Simulation time 34694209696 ps
CPU time 8.01 seconds
Started Aug 05 04:49:39 PM PDT 24
Finished Aug 05 04:49:48 PM PDT 24
Peak memory 217000 kb
Host smart-6043412b-7200-4957-9c27-b5be1bf4e9fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779090151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.779090151
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.2223278409
Short name T560
Test name
Test status
Simulation time 56828458 ps
CPU time 0.78 seconds
Started Aug 05 04:49:54 PM PDT 24
Finished Aug 05 04:49:55 PM PDT 24
Peak memory 206504 kb
Host smart-5b7bdcf5-6ce3-43e2-85b2-736ed11b0649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223278409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.2223278409
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.242372438
Short name T807
Test name
Test status
Simulation time 121368201 ps
CPU time 0.88 seconds
Started Aug 05 04:49:37 PM PDT 24
Finished Aug 05 04:49:38 PM PDT 24
Peak memory 206856 kb
Host smart-cb00db95-84ec-4579-bc0f-cdae21e4a7ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242372438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.242372438
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.3528471321
Short name T879
Test name
Test status
Simulation time 591335345 ps
CPU time 6.7 seconds
Started Aug 05 04:49:51 PM PDT 24
Finished Aug 05 04:49:58 PM PDT 24
Peak memory 241616 kb
Host smart-3edcc844-320a-4f44-bb71-3c7fba3d6b8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528471321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.3528471321
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.3509945364
Short name T974
Test name
Test status
Simulation time 28287357 ps
CPU time 0.7 seconds
Started Aug 05 04:50:53 PM PDT 24
Finished Aug 05 04:50:54 PM PDT 24
Peak memory 205384 kb
Host smart-38ca3970-1447-406b-b718-49ad7720d426
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509945364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
3509945364
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.2211660499
Short name T500
Test name
Test status
Simulation time 1849615779 ps
CPU time 17.38 seconds
Started Aug 05 04:50:55 PM PDT 24
Finished Aug 05 04:51:12 PM PDT 24
Peak memory 233272 kb
Host smart-7bea5ae3-3c68-4f0c-a6eb-d31c43dde679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211660499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.2211660499
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.3863541203
Short name T1009
Test name
Test status
Simulation time 18439819 ps
CPU time 0.77 seconds
Started Aug 05 04:51:01 PM PDT 24
Finished Aug 05 04:51:02 PM PDT 24
Peak memory 205940 kb
Host smart-e930eea4-deaf-4f20-a760-b2e377893c43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863541203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.3863541203
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.1973253533
Short name T197
Test name
Test status
Simulation time 11783279352 ps
CPU time 83.45 seconds
Started Aug 05 04:50:56 PM PDT 24
Finished Aug 05 04:52:19 PM PDT 24
Peak memory 252448 kb
Host smart-f30385d0-60dd-4f83-b7ab-c6f556eb8083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973253533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.1973253533
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.376695929
Short name T305
Test name
Test status
Simulation time 9096695877 ps
CPU time 106.23 seconds
Started Aug 05 04:50:57 PM PDT 24
Finished Aug 05 04:52:44 PM PDT 24
Peak memory 252860 kb
Host smart-4b27b87f-0d65-47ad-a512-e25826075bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376695929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.376695929
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.3726653224
Short name T407
Test name
Test status
Simulation time 5050245517 ps
CPU time 64.45 seconds
Started Aug 05 04:50:55 PM PDT 24
Finished Aug 05 04:52:00 PM PDT 24
Peak memory 249984 kb
Host smart-2044cd61-ff9e-476e-9831-5802d7d71921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726653224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.3726653224
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.2517783408
Short name T321
Test name
Test status
Simulation time 4432317404 ps
CPU time 21.33 seconds
Started Aug 05 04:50:51 PM PDT 24
Finished Aug 05 04:51:13 PM PDT 24
Peak memory 233428 kb
Host smart-061188e5-a3a7-4701-8aec-9f997720c8b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517783408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.2517783408
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.146376055
Short name T978
Test name
Test status
Simulation time 2050944529 ps
CPU time 46.65 seconds
Started Aug 05 04:51:03 PM PDT 24
Finished Aug 05 04:51:50 PM PDT 24
Peak memory 252236 kb
Host smart-73e6b12c-77ab-4a98-b4c7-a09d43e04962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146376055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmds
.146376055
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/30.spi_device_intercept.1378380620
Short name T385
Test name
Test status
Simulation time 7642189471 ps
CPU time 13.93 seconds
Started Aug 05 04:51:16 PM PDT 24
Finished Aug 05 04:51:30 PM PDT 24
Peak memory 225232 kb
Host smart-511f18ab-a32d-431f-9dd1-bcab3e2841ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378380620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.1378380620
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.4080463427
Short name T587
Test name
Test status
Simulation time 306863556 ps
CPU time 2.68 seconds
Started Aug 05 04:50:49 PM PDT 24
Finished Aug 05 04:50:52 PM PDT 24
Peak memory 233352 kb
Host smart-55678994-353b-4a75-95b9-fe5fcdb56908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080463427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.4080463427
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.1492426363
Short name T311
Test name
Test status
Simulation time 763610170 ps
CPU time 6.18 seconds
Started Aug 05 04:50:51 PM PDT 24
Finished Aug 05 04:50:58 PM PDT 24
Peak memory 225264 kb
Host smart-180262ac-10af-461b-82d4-a4908cc91656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492426363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.1492426363
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.1551085244
Short name T568
Test name
Test status
Simulation time 7541487465 ps
CPU time 15.99 seconds
Started Aug 05 04:50:40 PM PDT 24
Finished Aug 05 04:50:56 PM PDT 24
Peak memory 233348 kb
Host smart-ff25347f-1b32-4a46-b29c-5124886fddbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551085244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.1551085244
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.3162164452
Short name T583
Test name
Test status
Simulation time 349083716 ps
CPU time 5.37 seconds
Started Aug 05 04:50:49 PM PDT 24
Finished Aug 05 04:50:55 PM PDT 24
Peak memory 221000 kb
Host smart-0d9a181d-2c78-4e96-8439-a3997207e4d1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3162164452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.3162164452
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.855919423
Short name T240
Test name
Test status
Simulation time 239933641000 ps
CPU time 530.75 seconds
Started Aug 05 04:50:49 PM PDT 24
Finished Aug 05 04:59:40 PM PDT 24
Peak memory 273360 kb
Host smart-b15361e3-785a-4fa4-817d-d28cb89b27b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855919423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stres
s_all.855919423
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.2625895320
Short name T999
Test name
Test status
Simulation time 143835320 ps
CPU time 0.72 seconds
Started Aug 05 04:51:12 PM PDT 24
Finished Aug 05 04:51:13 PM PDT 24
Peak memory 206140 kb
Host smart-4c59b67e-88b1-4276-800b-b6a820ec92fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625895320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.2625895320
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.217279541
Short name T361
Test name
Test status
Simulation time 9010763092 ps
CPU time 7.95 seconds
Started Aug 05 04:51:01 PM PDT 24
Finished Aug 05 04:51:09 PM PDT 24
Peak memory 216904 kb
Host smart-e522082f-b1bf-49a2-ae50-991e85b112ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217279541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.217279541
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.1599644989
Short name T368
Test name
Test status
Simulation time 13579374 ps
CPU time 0.84 seconds
Started Aug 05 04:50:55 PM PDT 24
Finished Aug 05 04:50:56 PM PDT 24
Peak memory 207368 kb
Host smart-17d9184d-9779-4bc3-a4ef-5ac500d78b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599644989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.1599644989
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.1401368651
Short name T755
Test name
Test status
Simulation time 36305809 ps
CPU time 0.69 seconds
Started Aug 05 04:50:47 PM PDT 24
Finished Aug 05 04:50:48 PM PDT 24
Peak memory 206484 kb
Host smart-e64eecea-1dad-4d4b-b759-fdcb805bcc93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401368651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.1401368651
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.308478926
Short name T1025
Test name
Test status
Simulation time 1916233044 ps
CPU time 8.58 seconds
Started Aug 05 04:50:51 PM PDT 24
Finished Aug 05 04:51:00 PM PDT 24
Peak memory 233392 kb
Host smart-27d898f4-a9d7-47f4-a7cb-5160e088d8e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308478926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.308478926
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.577193112
Short name T492
Test name
Test status
Simulation time 21708582 ps
CPU time 0.72 seconds
Started Aug 05 04:50:54 PM PDT 24
Finished Aug 05 04:50:55 PM PDT 24
Peak memory 204836 kb
Host smart-907f259d-f6d4-40a5-8ab6-3b643cf732bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577193112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.577193112
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.2571903452
Short name T969
Test name
Test status
Simulation time 764593105 ps
CPU time 6.83 seconds
Started Aug 05 04:51:04 PM PDT 24
Finished Aug 05 04:51:16 PM PDT 24
Peak memory 225160 kb
Host smart-5d1c60f8-c54a-494b-9404-19e7fb1c4fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571903452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.2571903452
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.838391095
Short name T490
Test name
Test status
Simulation time 29315810 ps
CPU time 0.81 seconds
Started Aug 05 04:51:01 PM PDT 24
Finished Aug 05 04:51:02 PM PDT 24
Peak memory 206972 kb
Host smart-2c230f89-395a-4e6b-bf7e-8bd5d5202e4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838391095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.838391095
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.2994976541
Short name T456
Test name
Test status
Simulation time 329059498 ps
CPU time 7.93 seconds
Started Aug 05 04:50:59 PM PDT 24
Finished Aug 05 04:51:07 PM PDT 24
Peak memory 237260 kb
Host smart-5db6a0f2-7130-43d5-8e0c-fd252c48f017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994976541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.2994976541
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.3739732915
Short name T302
Test name
Test status
Simulation time 3261049518 ps
CPU time 91.36 seconds
Started Aug 05 04:51:00 PM PDT 24
Finished Aug 05 04:52:32 PM PDT 24
Peak memory 273748 kb
Host smart-97caeb8d-176d-4d2c-a4f3-f10f241efc41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739732915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.3739732915
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.1265588819
Short name T968
Test name
Test status
Simulation time 4824506384 ps
CPU time 60.16 seconds
Started Aug 05 04:51:18 PM PDT 24
Finished Aug 05 04:52:18 PM PDT 24
Peak memory 266224 kb
Host smart-c957f59e-cac9-4767-a9a4-d53d1928fc57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265588819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.1265588819
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.1161343028
Short name T991
Test name
Test status
Simulation time 18393368768 ps
CPU time 70.59 seconds
Started Aug 05 04:51:00 PM PDT 24
Finished Aug 05 04:52:11 PM PDT 24
Peak memory 251856 kb
Host smart-83ac983a-6222-4ee6-a631-dcef0fc01a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161343028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.1161343028
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.2118708867
Short name T284
Test name
Test status
Simulation time 110380495668 ps
CPU time 197.56 seconds
Started Aug 05 04:50:59 PM PDT 24
Finished Aug 05 04:54:17 PM PDT 24
Peak memory 250516 kb
Host smart-e3656744-93ad-4be1-9d7b-16d08b333e0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118708867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmd
s.2118708867
Directory /workspace/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/31.spi_device_intercept.499291124
Short name T215
Test name
Test status
Simulation time 857665979 ps
CPU time 10.31 seconds
Started Aug 05 04:50:59 PM PDT 24
Finished Aug 05 04:51:10 PM PDT 24
Peak memory 225124 kb
Host smart-38f664c2-01fc-4ffe-a178-556bfd8a0566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499291124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.499291124
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.39780713
Short name T61
Test name
Test status
Simulation time 32694950 ps
CPU time 2.37 seconds
Started Aug 05 04:50:54 PM PDT 24
Finished Aug 05 04:50:57 PM PDT 24
Peak memory 232940 kb
Host smart-17d2f484-d6c4-42fb-946c-7a5ec3371b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39780713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.39780713
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.776395985
Short name T987
Test name
Test status
Simulation time 21000644245 ps
CPU time 21.02 seconds
Started Aug 05 04:50:55 PM PDT 24
Finished Aug 05 04:51:16 PM PDT 24
Peak memory 225136 kb
Host smart-7b5a720e-b6c5-41a9-ae81-402c1bcf01a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776395985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swap
.776395985
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.2201795850
Short name T1018
Test name
Test status
Simulation time 22263066734 ps
CPU time 13.71 seconds
Started Aug 05 04:50:58 PM PDT 24
Finished Aug 05 04:51:12 PM PDT 24
Peak memory 233424 kb
Host smart-05566784-6809-4def-a111-dc88faed6cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201795850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.2201795850
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.4189280811
Short name T81
Test name
Test status
Simulation time 3214505475 ps
CPU time 10.28 seconds
Started Aug 05 04:51:05 PM PDT 24
Finished Aug 05 04:51:15 PM PDT 24
Peak memory 221164 kb
Host smart-7725b2ad-2578-4f26-b7b9-3d106d0c96f2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4189280811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.4189280811
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.824125822
Short name T167
Test name
Test status
Simulation time 25932045138 ps
CPU time 149.03 seconds
Started Aug 05 04:51:13 PM PDT 24
Finished Aug 05 04:53:42 PM PDT 24
Peak memory 258084 kb
Host smart-e1f81bb5-f8dd-4bbe-9859-e39129f65bdd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824125822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stres
s_all.824125822
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.4085747067
Short name T941
Test name
Test status
Simulation time 2569543511 ps
CPU time 11.61 seconds
Started Aug 05 04:50:55 PM PDT 24
Finished Aug 05 04:51:06 PM PDT 24
Peak memory 218188 kb
Host smart-2e8af765-eadd-454f-988c-5f39d2719230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085747067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.4085747067
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.682616071
Short name T928
Test name
Test status
Simulation time 1576649908 ps
CPU time 6.66 seconds
Started Aug 05 04:50:54 PM PDT 24
Finished Aug 05 04:51:00 PM PDT 24
Peak memory 216848 kb
Host smart-6e71fee8-325d-4e72-9957-7ae40c686f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682616071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.682616071
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.3162578091
Short name T434
Test name
Test status
Simulation time 15661303 ps
CPU time 0.72 seconds
Started Aug 05 04:50:53 PM PDT 24
Finished Aug 05 04:50:54 PM PDT 24
Peak memory 206456 kb
Host smart-c4087ece-58c7-4678-b4fc-f79d6235ec87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162578091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.3162578091
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.3553985241
Short name T909
Test name
Test status
Simulation time 70519115 ps
CPU time 0.79 seconds
Started Aug 05 04:51:00 PM PDT 24
Finished Aug 05 04:51:01 PM PDT 24
Peak memory 206480 kb
Host smart-c41ecc16-6d69-403d-9ffb-69a367ecf4be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553985241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.3553985241
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.1147079026
Short name T415
Test name
Test status
Simulation time 24287948410 ps
CPU time 20.16 seconds
Started Aug 05 04:51:17 PM PDT 24
Finished Aug 05 04:51:37 PM PDT 24
Peak memory 225204 kb
Host smart-e0c3c6f5-229f-4a4a-9a70-d6972a39f291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147079026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.1147079026
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.2149135979
Short name T709
Test name
Test status
Simulation time 33699984 ps
CPU time 0.73 seconds
Started Aug 05 04:50:52 PM PDT 24
Finished Aug 05 04:50:52 PM PDT 24
Peak memory 206228 kb
Host smart-b627471c-624a-477d-be26-f9238319cd87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149135979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
2149135979
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.3689657068
Short name T426
Test name
Test status
Simulation time 118007216 ps
CPU time 2.45 seconds
Started Aug 05 04:50:48 PM PDT 24
Finished Aug 05 04:50:50 PM PDT 24
Peak memory 225176 kb
Host smart-bac469e5-380c-4e0b-a6e5-c417314fb28d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689657068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.3689657068
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.3334425483
Short name T960
Test name
Test status
Simulation time 20467020 ps
CPU time 0.78 seconds
Started Aug 05 04:50:55 PM PDT 24
Finished Aug 05 04:50:56 PM PDT 24
Peak memory 207268 kb
Host smart-e5603512-c943-439b-a079-4ad0bc6b7255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334425483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.3334425483
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.2629211600
Short name T769
Test name
Test status
Simulation time 38579278253 ps
CPU time 70.29 seconds
Started Aug 05 04:50:58 PM PDT 24
Finished Aug 05 04:52:09 PM PDT 24
Peak memory 235984 kb
Host smart-b195bdbd-5b74-438a-b8c3-3c63d0c028bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629211600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.2629211600
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.130906369
Short name T977
Test name
Test status
Simulation time 4110895826 ps
CPU time 7.89 seconds
Started Aug 05 04:50:54 PM PDT 24
Finished Aug 05 04:51:01 PM PDT 24
Peak memory 225184 kb
Host smart-64e14e80-62ee-4635-9ce7-a0306ccff94f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130906369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.130906369
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.2982630035
Short name T142
Test name
Test status
Simulation time 70549320784 ps
CPU time 188.06 seconds
Started Aug 05 04:50:58 PM PDT 24
Finished Aug 05 04:54:06 PM PDT 24
Peak memory 250400 kb
Host smart-c83a8163-f891-44f9-89b3-09cbcf805ce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982630035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.2982630035
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.2201377161
Short name T915
Test name
Test status
Simulation time 2469273061 ps
CPU time 34.3 seconds
Started Aug 05 04:50:58 PM PDT 24
Finished Aug 05 04:51:33 PM PDT 24
Peak memory 225216 kb
Host smart-2912b349-01a0-46e7-9664-50a9063efde3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201377161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.2201377161
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.2975372322
Short name T77
Test name
Test status
Simulation time 83281213024 ps
CPU time 172.82 seconds
Started Aug 05 04:50:57 PM PDT 24
Finished Aug 05 04:53:50 PM PDT 24
Peak memory 266300 kb
Host smart-8d16faf2-5d82-4738-a91d-50d0d8a524ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975372322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmd
s.2975372322
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/32.spi_device_intercept.1424762269
Short name T675
Test name
Test status
Simulation time 3168337815 ps
CPU time 10.96 seconds
Started Aug 05 04:50:58 PM PDT 24
Finished Aug 05 04:51:09 PM PDT 24
Peak memory 233428 kb
Host smart-bc1c95cd-6dcc-4235-aae9-b58c51f55eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424762269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.1424762269
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.437386175
Short name T818
Test name
Test status
Simulation time 2254581742 ps
CPU time 28.88 seconds
Started Aug 05 04:50:58 PM PDT 24
Finished Aug 05 04:51:27 PM PDT 24
Peak memory 233392 kb
Host smart-152396e3-ac1b-433c-a8b0-255c35881dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437386175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.437386175
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.3496391307
Short name T540
Test name
Test status
Simulation time 945924721 ps
CPU time 5.22 seconds
Started Aug 05 04:50:55 PM PDT 24
Finished Aug 05 04:51:00 PM PDT 24
Peak memory 233400 kb
Host smart-d9623fe5-6ea3-478c-8e92-e682fb75a397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496391307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.3496391307
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.2391692731
Short name T528
Test name
Test status
Simulation time 77186718 ps
CPU time 2.13 seconds
Started Aug 05 04:51:01 PM PDT 24
Finished Aug 05 04:51:03 PM PDT 24
Peak memory 223712 kb
Host smart-fc022454-5c75-4e14-9e94-cded2a777b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391692731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.2391692731
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.3054724849
Short name T904
Test name
Test status
Simulation time 1236689340 ps
CPU time 7.9 seconds
Started Aug 05 04:50:51 PM PDT 24
Finished Aug 05 04:50:59 PM PDT 24
Peak memory 222384 kb
Host smart-d6d86f78-01b1-4a3f-b188-7900296c07ea
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3054724849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.3054724849
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.3746707228
Short name T857
Test name
Test status
Simulation time 16667388201 ps
CPU time 166.17 seconds
Started Aug 05 04:50:55 PM PDT 24
Finished Aug 05 04:53:41 PM PDT 24
Peak memory 274296 kb
Host smart-0b94f78c-c1ef-4d4f-a08f-e42696cc48a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746707228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.3746707228
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.2100819886
Short name T708
Test name
Test status
Simulation time 10416605721 ps
CPU time 17.86 seconds
Started Aug 05 04:50:51 PM PDT 24
Finished Aug 05 04:51:09 PM PDT 24
Peak memory 217080 kb
Host smart-a29e91dd-f5a2-41f3-8bf7-6d1105ad6a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100819886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.2100819886
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.473532159
Short name T561
Test name
Test status
Simulation time 4922366025 ps
CPU time 5.22 seconds
Started Aug 05 04:50:50 PM PDT 24
Finished Aug 05 04:50:55 PM PDT 24
Peak memory 216964 kb
Host smart-e6e246c8-58c7-4291-80a7-ec621d3bb1c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473532159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.473532159
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.2281309015
Short name T334
Test name
Test status
Simulation time 131129373 ps
CPU time 1.44 seconds
Started Aug 05 04:50:56 PM PDT 24
Finished Aug 05 04:50:58 PM PDT 24
Peak memory 216812 kb
Host smart-30bc315e-13d1-4f53-8cf8-b86969cc94c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281309015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.2281309015
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.233651063
Short name T739
Test name
Test status
Simulation time 20026164 ps
CPU time 0.77 seconds
Started Aug 05 04:50:54 PM PDT 24
Finished Aug 05 04:50:55 PM PDT 24
Peak memory 206524 kb
Host smart-3f7b5c36-e428-4f12-beef-f07063f1eb6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233651063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.233651063
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.2331655787
Short name T78
Test name
Test status
Simulation time 239413496 ps
CPU time 4.3 seconds
Started Aug 05 04:50:50 PM PDT 24
Finished Aug 05 04:50:55 PM PDT 24
Peak memory 235456 kb
Host smart-3758b13c-6882-4e48-a68a-54f3f5a22b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331655787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.2331655787
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.1599644342
Short name T378
Test name
Test status
Simulation time 18609917 ps
CPU time 0.71 seconds
Started Aug 05 04:50:58 PM PDT 24
Finished Aug 05 04:50:59 PM PDT 24
Peak memory 205188 kb
Host smart-d032e91d-a97c-4f42-b686-7a72f3b24b0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599644342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
1599644342
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.2792563406
Short name T3
Test name
Test status
Simulation time 476319632 ps
CPU time 6.88 seconds
Started Aug 05 04:50:54 PM PDT 24
Finished Aug 05 04:51:01 PM PDT 24
Peak memory 225244 kb
Host smart-e1f653fe-3904-43f7-ba7b-e415e79fe304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792563406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.2792563406
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.2933539950
Short name T757
Test name
Test status
Simulation time 15941274 ps
CPU time 0.8 seconds
Started Aug 05 04:51:05 PM PDT 24
Finished Aug 05 04:51:06 PM PDT 24
Peak memory 205948 kb
Host smart-fa4a05c9-3907-4239-9db1-e8e7418eafd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933539950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.2933539950
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.473187547
Short name T203
Test name
Test status
Simulation time 86757472460 ps
CPU time 351.72 seconds
Started Aug 05 04:50:58 PM PDT 24
Finished Aug 05 04:56:55 PM PDT 24
Peak memory 266308 kb
Host smart-713d1117-3f68-45d6-a7af-17837662bac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473187547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.473187547
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.2513989329
Short name T132
Test name
Test status
Simulation time 14179148038 ps
CPU time 44.52 seconds
Started Aug 05 04:51:02 PM PDT 24
Finished Aug 05 04:51:46 PM PDT 24
Peak memory 249852 kb
Host smart-347d5a77-47e6-470d-9c50-58dad2bb9058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513989329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.2513989329
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.3559259553
Short name T554
Test name
Test status
Simulation time 1388882269 ps
CPU time 35.51 seconds
Started Aug 05 04:51:14 PM PDT 24
Finished Aug 05 04:51:50 PM PDT 24
Peak memory 265384 kb
Host smart-663043c4-7767-47f9-8837-ff9dba52025a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559259553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.3559259553
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.1768983844
Short name T911
Test name
Test status
Simulation time 13045327239 ps
CPU time 83.71 seconds
Started Aug 05 04:50:58 PM PDT 24
Finished Aug 05 04:52:22 PM PDT 24
Peak memory 237388 kb
Host smart-6e39b43d-7fb9-4d9a-a4b5-9559516188e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768983844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.1768983844
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.1997944339
Short name T183
Test name
Test status
Simulation time 26363196956 ps
CPU time 133.6 seconds
Started Aug 05 04:51:05 PM PDT 24
Finished Aug 05 04:53:19 PM PDT 24
Peak memory 249788 kb
Host smart-c58e185d-12b2-4bb0-994f-c196d793d6e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997944339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmd
s.1997944339
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/33.spi_device_intercept.3234557859
Short name T966
Test name
Test status
Simulation time 402919758 ps
CPU time 2.26 seconds
Started Aug 05 04:50:59 PM PDT 24
Finished Aug 05 04:51:02 PM PDT 24
Peak memory 227200 kb
Host smart-8491bfa3-6a2c-4ca3-8e76-0c3a6ad425f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234557859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.3234557859
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.2106773819
Short name T630
Test name
Test status
Simulation time 1592141418 ps
CPU time 7.67 seconds
Started Aug 05 04:50:51 PM PDT 24
Finished Aug 05 04:50:59 PM PDT 24
Peak memory 233416 kb
Host smart-984ae447-60a2-4851-8fa0-a9867011a227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106773819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.2106773819
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.2049228669
Short name T174
Test name
Test status
Simulation time 947853761 ps
CPU time 2.84 seconds
Started Aug 05 04:50:59 PM PDT 24
Finished Aug 05 04:51:02 PM PDT 24
Peak memory 224868 kb
Host smart-3749e3f2-787c-41f8-b6dd-5571ecc61292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049228669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.2049228669
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.3147769901
Short name T133
Test name
Test status
Simulation time 25878623587 ps
CPU time 31.13 seconds
Started Aug 05 04:50:58 PM PDT 24
Finished Aug 05 04:51:30 PM PDT 24
Peak memory 233412 kb
Host smart-3d423398-9832-40f1-a7f5-0de9371a17d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147769901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.3147769901
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.503647866
Short name T983
Test name
Test status
Simulation time 1280137853 ps
CPU time 11.52 seconds
Started Aug 05 04:50:53 PM PDT 24
Finished Aug 05 04:51:05 PM PDT 24
Peak memory 219400 kb
Host smart-4f5ef3e8-6e63-4080-b1e1-24faca582f9e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=503647866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dire
ct.503647866
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.3834499306
Short name T846
Test name
Test status
Simulation time 1409610918 ps
CPU time 40.67 seconds
Started Aug 05 04:50:56 PM PDT 24
Finished Aug 05 04:51:37 PM PDT 24
Peak memory 252356 kb
Host smart-73d1dc6f-ff8c-46d0-9c83-de03bb7a99b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834499306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.3834499306
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.3870795428
Short name T330
Test name
Test status
Simulation time 3964149683 ps
CPU time 15.72 seconds
Started Aug 05 04:51:00 PM PDT 24
Finished Aug 05 04:51:16 PM PDT 24
Peak memory 216964 kb
Host smart-f1be4c91-967b-4afd-bc86-734ced7d904f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870795428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.3870795428
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.1396157495
Short name T88
Test name
Test status
Simulation time 5950741498 ps
CPU time 5.24 seconds
Started Aug 05 04:50:55 PM PDT 24
Finished Aug 05 04:51:01 PM PDT 24
Peak memory 216992 kb
Host smart-b6ccd580-d94a-4832-9b19-e488595bef24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396157495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.1396157495
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.4235174844
Short name T421
Test name
Test status
Simulation time 138500895 ps
CPU time 1.27 seconds
Started Aug 05 04:50:58 PM PDT 24
Finished Aug 05 04:51:00 PM PDT 24
Peak memory 208496 kb
Host smart-3cc5f0e3-c652-44fd-8ae5-da08a16c68f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235174844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.4235174844
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.3563472143
Short name T388
Test name
Test status
Simulation time 41582636 ps
CPU time 0.85 seconds
Started Aug 05 04:51:03 PM PDT 24
Finished Aug 05 04:51:04 PM PDT 24
Peak memory 206444 kb
Host smart-d29bff0e-c486-4cdd-a65e-4bf9fd681cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563472143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.3563472143
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.2423118983
Short name T393
Test name
Test status
Simulation time 5471903034 ps
CPU time 20.26 seconds
Started Aug 05 04:50:59 PM PDT 24
Finished Aug 05 04:51:20 PM PDT 24
Peak memory 233464 kb
Host smart-ea664c3e-7ebd-432c-82f0-257ebb1b0f21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423118983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.2423118983
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.1767628906
Short name T397
Test name
Test status
Simulation time 34670985 ps
CPU time 0.71 seconds
Started Aug 05 04:51:04 PM PDT 24
Finished Aug 05 04:51:05 PM PDT 24
Peak memory 205168 kb
Host smart-b9f0082d-d291-49ae-84d2-f6c8158b0711
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767628906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
1767628906
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.3321170632
Short name T866
Test name
Test status
Simulation time 137624382 ps
CPU time 2.58 seconds
Started Aug 05 04:51:09 PM PDT 24
Finished Aug 05 04:51:12 PM PDT 24
Peak memory 225080 kb
Host smart-f0fc5c65-c218-4e9c-b234-966b00dbdd2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321170632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.3321170632
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.3800937216
Short name T343
Test name
Test status
Simulation time 15736136 ps
CPU time 0.77 seconds
Started Aug 05 04:50:52 PM PDT 24
Finished Aug 05 04:50:53 PM PDT 24
Peak memory 207308 kb
Host smart-ea34beb1-dae5-44e3-93d9-afbfd0f984e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800937216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.3800937216
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.1343603535
Short name T299
Test name
Test status
Simulation time 31362632646 ps
CPU time 164.78 seconds
Started Aug 05 04:50:56 PM PDT 24
Finished Aug 05 04:53:41 PM PDT 24
Peak memory 251656 kb
Host smart-b9ee13b9-4fa6-4568-ad9d-af1da12610d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343603535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.1343603535
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.1458882107
Short name T180
Test name
Test status
Simulation time 74491206576 ps
CPU time 179.33 seconds
Started Aug 05 04:50:58 PM PDT 24
Finished Aug 05 04:53:58 PM PDT 24
Peak memory 249980 kb
Host smart-56fa0e23-277d-41df-9fe3-7f8908ac4921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458882107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.1458882107
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.3085841662
Short name T876
Test name
Test status
Simulation time 66922190171 ps
CPU time 153.77 seconds
Started Aug 05 04:50:58 PM PDT 24
Finished Aug 05 04:53:32 PM PDT 24
Peak memory 251188 kb
Host smart-5e742250-1665-4c70-a52b-7915f7371000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085841662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.3085841662
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.2181575285
Short name T44
Test name
Test status
Simulation time 361079541 ps
CPU time 10.87 seconds
Started Aug 05 04:51:18 PM PDT 24
Finished Aug 05 04:51:29 PM PDT 24
Peak memory 237652 kb
Host smart-7cb3bca1-9266-4714-88ce-c0fcdedb4e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181575285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.2181575285
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.1668427317
Short name T997
Test name
Test status
Simulation time 3097584431 ps
CPU time 28.3 seconds
Started Aug 05 04:50:58 PM PDT 24
Finished Aug 05 04:51:26 PM PDT 24
Peak memory 249820 kb
Host smart-f05f393f-7092-4a7e-ba00-4082a8ad6b94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668427317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmd
s.1668427317
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/34.spi_device_intercept.3979051362
Short name T798
Test name
Test status
Simulation time 1321478541 ps
CPU time 9.58 seconds
Started Aug 05 04:51:20 PM PDT 24
Finished Aug 05 04:51:30 PM PDT 24
Peak memory 220328 kb
Host smart-19ba2637-cc41-44a9-91b3-80efe0bac0ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979051362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.3979051362
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.1353785167
Short name T815
Test name
Test status
Simulation time 19989673931 ps
CPU time 23.29 seconds
Started Aug 05 04:51:19 PM PDT 24
Finished Aug 05 04:51:42 PM PDT 24
Peak memory 233348 kb
Host smart-4581ce2f-f228-4517-b660-89fff4f0e3bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353785167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.1353785167
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.945692881
Short name T220
Test name
Test status
Simulation time 7840431918 ps
CPU time 12.76 seconds
Started Aug 05 04:51:02 PM PDT 24
Finished Aug 05 04:51:15 PM PDT 24
Peak memory 237372 kb
Host smart-243a3d00-139e-4a9b-8bb8-030eacfef7d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945692881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swap
.945692881
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.60079693
Short name T567
Test name
Test status
Simulation time 4260668620 ps
CPU time 11.8 seconds
Started Aug 05 04:51:09 PM PDT 24
Finished Aug 05 04:51:21 PM PDT 24
Peak memory 225220 kb
Host smart-3ea71441-c3c4-42e6-8d40-9b0df64a3344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60079693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.60079693
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.2311477352
Short name T704
Test name
Test status
Simulation time 1558814603 ps
CPU time 10.73 seconds
Started Aug 05 04:51:09 PM PDT 24
Finished Aug 05 04:51:20 PM PDT 24
Peak memory 222104 kb
Host smart-18a6c4eb-8f80-4fd3-aa80-b67fe4bf5607
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2311477352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.2311477352
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.3610114834
Short name T786
Test name
Test status
Simulation time 123124255 ps
CPU time 1.17 seconds
Started Aug 05 04:51:01 PM PDT 24
Finished Aug 05 04:51:03 PM PDT 24
Peak memory 207288 kb
Host smart-f2a61044-5839-4c38-84e4-ba8962cc4521
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610114834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.3610114834
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.877312014
Short name T573
Test name
Test status
Simulation time 7804108556 ps
CPU time 25.44 seconds
Started Aug 05 04:51:03 PM PDT 24
Finished Aug 05 04:51:28 PM PDT 24
Peak memory 216976 kb
Host smart-0755538c-9d92-4dad-b841-dc8d21fdb1cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877312014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.877312014
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.2727911023
Short name T379
Test name
Test status
Simulation time 15453060905 ps
CPU time 20.77 seconds
Started Aug 05 04:50:52 PM PDT 24
Finished Aug 05 04:51:13 PM PDT 24
Peak memory 216880 kb
Host smart-e8d9c719-3d07-450e-9a19-bca78a75dc6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727911023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.2727911023
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.1266148894
Short name T1003
Test name
Test status
Simulation time 229625202 ps
CPU time 3.57 seconds
Started Aug 05 04:51:00 PM PDT 24
Finished Aug 05 04:51:04 PM PDT 24
Peak memory 216912 kb
Host smart-29089dab-023b-4be7-9d5e-2e7fcab1b9b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266148894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.1266148894
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.2371633537
Short name T444
Test name
Test status
Simulation time 125374821 ps
CPU time 0.95 seconds
Started Aug 05 04:50:57 PM PDT 24
Finished Aug 05 04:50:58 PM PDT 24
Peak memory 207444 kb
Host smart-360cd601-553c-4141-a3c7-cf2f4b5e2cde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371633537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.2371633537
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.2585505688
Short name T956
Test name
Test status
Simulation time 484506518 ps
CPU time 3.6 seconds
Started Aug 05 04:50:57 PM PDT 24
Finished Aug 05 04:51:01 PM PDT 24
Peak memory 233380 kb
Host smart-80516bab-c0dd-4069-aa84-1b6c306a2652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585505688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.2585505688
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.4087871181
Short name T499
Test name
Test status
Simulation time 37104824 ps
CPU time 0.75 seconds
Started Aug 05 04:51:02 PM PDT 24
Finished Aug 05 04:51:03 PM PDT 24
Peak memory 205732 kb
Host smart-71127a5a-4ae4-424f-885a-0682cb0ebc58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087871181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
4087871181
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.1775147223
Short name T532
Test name
Test status
Simulation time 345807914 ps
CPU time 2.52 seconds
Started Aug 05 04:51:12 PM PDT 24
Finished Aug 05 04:51:14 PM PDT 24
Peak memory 225116 kb
Host smart-c2b05f6e-b0e2-42ba-9162-1529cded8bc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775147223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.1775147223
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.1415704597
Short name T461
Test name
Test status
Simulation time 17367020 ps
CPU time 0.79 seconds
Started Aug 05 04:50:58 PM PDT 24
Finished Aug 05 04:50:59 PM PDT 24
Peak memory 206264 kb
Host smart-825d94cd-2ff7-4179-8a1e-2bba5797fb48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415704597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.1415704597
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.1110565023
Short name T223
Test name
Test status
Simulation time 17554707840 ps
CPU time 122.98 seconds
Started Aug 05 04:51:03 PM PDT 24
Finished Aug 05 04:53:06 PM PDT 24
Peak memory 250388 kb
Host smart-947faa40-e3e3-4762-9e32-a72df0259c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110565023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.1110565023
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.1871254982
Short name T16
Test name
Test status
Simulation time 1564745285 ps
CPU time 37.53 seconds
Started Aug 05 04:51:03 PM PDT 24
Finished Aug 05 04:51:40 PM PDT 24
Peak memory 239888 kb
Host smart-10e52748-12d3-4810-85f3-1e60ac251dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871254982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.1871254982
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.3807333438
Short name T625
Test name
Test status
Simulation time 321819487 ps
CPU time 6.32 seconds
Started Aug 05 04:51:01 PM PDT 24
Finished Aug 05 04:51:08 PM PDT 24
Peak memory 225388 kb
Host smart-5f675f96-dddb-4ced-a62b-934b30b2fcff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807333438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.3807333438
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.2196380958
Short name T51
Test name
Test status
Simulation time 10289817662 ps
CPU time 41.53 seconds
Started Aug 05 04:51:25 PM PDT 24
Finished Aug 05 04:52:06 PM PDT 24
Peak memory 249792 kb
Host smart-6bb33e86-7410-471f-b807-f3b51fe0e3d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196380958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmd
s.2196380958
Directory /workspace/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/35.spi_device_intercept.2092094965
Short name T929
Test name
Test status
Simulation time 470271874 ps
CPU time 3.14 seconds
Started Aug 05 04:50:57 PM PDT 24
Finished Aug 05 04:51:00 PM PDT 24
Peak memory 233380 kb
Host smart-937d0487-9d4a-42bc-afc1-2685f33e0b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092094965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.2092094965
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.3413759660
Short name T655
Test name
Test status
Simulation time 11051504436 ps
CPU time 133.55 seconds
Started Aug 05 04:50:55 PM PDT 24
Finished Aug 05 04:53:09 PM PDT 24
Peak memory 225176 kb
Host smart-ca37aa96-e339-4884-9b71-fe078cadb694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413759660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.3413759660
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.1818199193
Short name T1020
Test name
Test status
Simulation time 37894251 ps
CPU time 2.62 seconds
Started Aug 05 04:51:11 PM PDT 24
Finished Aug 05 04:51:14 PM PDT 24
Peak memory 233312 kb
Host smart-66075ab5-2f6f-4f52-8c81-ddb37f1a7971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818199193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.1818199193
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.993182554
Short name T506
Test name
Test status
Simulation time 672166939 ps
CPU time 3.75 seconds
Started Aug 05 04:50:57 PM PDT 24
Finished Aug 05 04:51:01 PM PDT 24
Peak memory 233380 kb
Host smart-f46c6bcc-4e0f-4cd2-acc8-464d324e567e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993182554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.993182554
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.821109007
Short name T153
Test name
Test status
Simulation time 571833758 ps
CPU time 4.88 seconds
Started Aug 05 04:51:06 PM PDT 24
Finished Aug 05 04:51:11 PM PDT 24
Peak memory 221220 kb
Host smart-b20818c8-35d6-4510-b615-1bea78e85dac
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=821109007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dire
ct.821109007
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.1074850684
Short name T989
Test name
Test status
Simulation time 3232572742 ps
CPU time 53.99 seconds
Started Aug 05 04:51:15 PM PDT 24
Finished Aug 05 04:52:09 PM PDT 24
Peak memory 249872 kb
Host smart-88e3e9d3-9881-4981-8512-00a22441771d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074850684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.1074850684
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.2403539839
Short name T324
Test name
Test status
Simulation time 4098159766 ps
CPU time 25.07 seconds
Started Aug 05 04:51:02 PM PDT 24
Finished Aug 05 04:51:27 PM PDT 24
Peak memory 216932 kb
Host smart-0afeb04c-5196-4f3c-a810-0c063090237f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403539839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.2403539839
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.3628087466
Short name T1011
Test name
Test status
Simulation time 3135984922 ps
CPU time 6.25 seconds
Started Aug 05 04:51:02 PM PDT 24
Finished Aug 05 04:51:08 PM PDT 24
Peak memory 217012 kb
Host smart-54985c8c-f89a-4c7b-adac-7f3f350ba525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628087466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.3628087466
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.675704900
Short name T614
Test name
Test status
Simulation time 111138503 ps
CPU time 1.43 seconds
Started Aug 05 04:50:58 PM PDT 24
Finished Aug 05 04:51:00 PM PDT 24
Peak memory 216888 kb
Host smart-b33651ef-340d-4318-92dd-db978ce35936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675704900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.675704900
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.908299323
Short name T918
Test name
Test status
Simulation time 105022037 ps
CPU time 0.8 seconds
Started Aug 05 04:50:55 PM PDT 24
Finished Aug 05 04:50:56 PM PDT 24
Peak memory 206464 kb
Host smart-fb0b6070-2cfb-4a76-a110-3c9453c0f911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908299323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.908299323
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.1078563723
Short name T949
Test name
Test status
Simulation time 6244446436 ps
CPU time 11.36 seconds
Started Aug 05 04:50:59 PM PDT 24
Finished Aug 05 04:51:11 PM PDT 24
Peak memory 233408 kb
Host smart-c0e6891b-fa38-4d8a-9de7-72176c41ad9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078563723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.1078563723
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.1899033938
Short name T812
Test name
Test status
Simulation time 37719669 ps
CPU time 0.68 seconds
Started Aug 05 04:51:15 PM PDT 24
Finished Aug 05 04:51:16 PM PDT 24
Peak memory 205764 kb
Host smart-d52e7efe-178d-46a6-b5d7-68c7e60a8a29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899033938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
1899033938
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.1941432192
Short name T502
Test name
Test status
Simulation time 164028830 ps
CPU time 4.61 seconds
Started Aug 05 04:51:05 PM PDT 24
Finished Aug 05 04:51:09 PM PDT 24
Peak memory 233292 kb
Host smart-d896436a-6042-4df6-9392-d83e1d2ecd49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941432192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.1941432192
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.240074028
Short name T403
Test name
Test status
Simulation time 32053742 ps
CPU time 0.76 seconds
Started Aug 05 04:51:00 PM PDT 24
Finished Aug 05 04:51:01 PM PDT 24
Peak memory 205868 kb
Host smart-1ee1ea58-2ed0-4f7b-95b2-6cbf6d943709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240074028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.240074028
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.1228614302
Short name T579
Test name
Test status
Simulation time 3329650208 ps
CPU time 11.45 seconds
Started Aug 05 04:51:05 PM PDT 24
Finished Aug 05 04:51:17 PM PDT 24
Peak memory 238472 kb
Host smart-69252f0e-cc3d-4665-901f-4cb206ba422a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228614302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.1228614302
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.4240225582
Short name T770
Test name
Test status
Simulation time 43596236518 ps
CPU time 230.39 seconds
Started Aug 05 04:50:59 PM PDT 24
Finished Aug 05 04:54:49 PM PDT 24
Peak memory 249916 kb
Host smart-27ee0aaf-6d9f-4f3a-93aa-5a3b942497f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240225582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.4240225582
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.922006363
Short name T892
Test name
Test status
Simulation time 34300818007 ps
CPU time 345.89 seconds
Started Aug 05 04:50:55 PM PDT 24
Finished Aug 05 04:56:42 PM PDT 24
Peak memory 250960 kb
Host smart-6e0210d4-3681-4ac0-930e-ded8691a4328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922006363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idle
.922006363
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.2947262578
Short name T350
Test name
Test status
Simulation time 182588581 ps
CPU time 2.76 seconds
Started Aug 05 04:51:10 PM PDT 24
Finished Aug 05 04:51:12 PM PDT 24
Peak memory 225396 kb
Host smart-9d22e147-fd85-4893-a18d-b0a9ff42f9a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947262578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.2947262578
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.1944730941
Short name T290
Test name
Test status
Simulation time 17762144132 ps
CPU time 118.16 seconds
Started Aug 05 04:50:56 PM PDT 24
Finished Aug 05 04:52:54 PM PDT 24
Peak memory 256500 kb
Host smart-ede0ad35-1f5b-4658-ba53-59556a0aed8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944730941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmd
s.1944730941
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_intercept.3876934775
Short name T868
Test name
Test status
Simulation time 1933919263 ps
CPU time 18.6 seconds
Started Aug 05 04:50:56 PM PDT 24
Finished Aug 05 04:51:15 PM PDT 24
Peak memory 233408 kb
Host smart-fd57f022-79c6-48b5-9a5a-de68a2f226f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876934775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.3876934775
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.821639626
Short name T473
Test name
Test status
Simulation time 617354702 ps
CPU time 14.54 seconds
Started Aug 05 04:51:18 PM PDT 24
Finished Aug 05 04:51:33 PM PDT 24
Peak memory 233396 kb
Host smart-8f5a098b-5202-4c4e-b914-f714f501fe22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821639626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.821639626
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.3230719022
Short name T269
Test name
Test status
Simulation time 1200543020 ps
CPU time 10.57 seconds
Started Aug 05 04:51:11 PM PDT 24
Finished Aug 05 04:51:22 PM PDT 24
Peak memory 241112 kb
Host smart-a555a645-94f2-4017-88fe-f6af93cfa0e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230719022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.3230719022
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.2929095615
Short name T453
Test name
Test status
Simulation time 1999106323 ps
CPU time 5.3 seconds
Started Aug 05 04:50:58 PM PDT 24
Finished Aug 05 04:51:03 PM PDT 24
Peak memory 233348 kb
Host smart-00b94526-0d02-43d8-8c44-d5324dd3ac7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929095615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.2929095615
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.3633925754
Short name T154
Test name
Test status
Simulation time 7556964347 ps
CPU time 11 seconds
Started Aug 05 04:51:12 PM PDT 24
Finished Aug 05 04:51:23 PM PDT 24
Peak memory 219556 kb
Host smart-cc16de35-c43f-4468-8899-02342e569987
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3633925754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.3633925754
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.308724130
Short name T950
Test name
Test status
Simulation time 16388588685 ps
CPU time 105.49 seconds
Started Aug 05 04:51:14 PM PDT 24
Finished Aug 05 04:52:59 PM PDT 24
Peak memory 250884 kb
Host smart-a7ba3a87-6b91-49b4-bf48-9475dce9c64b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308724130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stres
s_all.308724130
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.2311474144
Short name T935
Test name
Test status
Simulation time 11323310960 ps
CPU time 27.4 seconds
Started Aug 05 04:51:12 PM PDT 24
Finished Aug 05 04:51:40 PM PDT 24
Peak memory 216936 kb
Host smart-7cbc64fe-2e3b-42df-a318-12cbe56d8f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311474144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.2311474144
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.3538933510
Short name T6
Test name
Test status
Simulation time 3575103576 ps
CPU time 9.01 seconds
Started Aug 05 04:51:19 PM PDT 24
Finished Aug 05 04:51:28 PM PDT 24
Peak memory 216984 kb
Host smart-a936333d-2d63-4977-a77d-7b9e8dc36eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538933510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.3538933510
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.4289616500
Short name T606
Test name
Test status
Simulation time 146790451 ps
CPU time 1.09 seconds
Started Aug 05 04:51:17 PM PDT 24
Finished Aug 05 04:51:18 PM PDT 24
Peak memory 208604 kb
Host smart-aed7155a-c5f9-42cb-af04-308895180b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289616500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.4289616500
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.2761624526
Short name T1019
Test name
Test status
Simulation time 439006923 ps
CPU time 0.88 seconds
Started Aug 05 04:51:08 PM PDT 24
Finished Aug 05 04:51:09 PM PDT 24
Peak memory 206456 kb
Host smart-f41155f5-e687-43ea-b92e-71d94ea2a448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761624526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.2761624526
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.371662172
Short name T196
Test name
Test status
Simulation time 51757737772 ps
CPU time 22.76 seconds
Started Aug 05 04:51:08 PM PDT 24
Finished Aug 05 04:51:31 PM PDT 24
Peak memory 225320 kb
Host smart-1f21fb55-aa6e-4e4b-91c6-e6898408bc77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371662172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.371662172
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.3593516222
Short name T672
Test name
Test status
Simulation time 52230158 ps
CPU time 0.71 seconds
Started Aug 05 04:51:03 PM PDT 24
Finished Aug 05 04:51:04 PM PDT 24
Peak memory 205152 kb
Host smart-01335ecd-e1ae-45c0-8b2e-5719dd12c31e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593516222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
3593516222
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.876832074
Short name T251
Test name
Test status
Simulation time 335432533 ps
CPU time 2.31 seconds
Started Aug 05 04:51:03 PM PDT 24
Finished Aug 05 04:51:05 PM PDT 24
Peak memory 225096 kb
Host smart-8f141538-d4e9-40b2-aba5-78c83b51d7d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876832074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.876832074
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.3173474969
Short name T1006
Test name
Test status
Simulation time 21754762 ps
CPU time 0.8 seconds
Started Aug 05 04:51:17 PM PDT 24
Finished Aug 05 04:51:17 PM PDT 24
Peak memory 207060 kb
Host smart-18b87f7c-9b76-4497-9bce-16eeab600a75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173474969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.3173474969
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.1251939954
Short name T294
Test name
Test status
Simulation time 14558602455 ps
CPU time 146.01 seconds
Started Aug 05 04:51:31 PM PDT 24
Finished Aug 05 04:53:58 PM PDT 24
Peak memory 249944 kb
Host smart-45737443-0fdf-4cf7-822a-b8de511aac68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251939954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.1251939954
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.2992261234
Short name T645
Test name
Test status
Simulation time 93644896941 ps
CPU time 157.09 seconds
Started Aug 05 04:51:09 PM PDT 24
Finished Aug 05 04:53:46 PM PDT 24
Peak memory 251232 kb
Host smart-698653d9-a355-4c06-a658-243d1e036043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992261234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.2992261234
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.2165878736
Short name T489
Test name
Test status
Simulation time 1808689381 ps
CPU time 5.72 seconds
Started Aug 05 04:51:25 PM PDT 24
Finished Aug 05 04:51:31 PM PDT 24
Peak memory 218188 kb
Host smart-8fe2ce23-50ab-4d3d-8053-91dede79d941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165878736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.2165878736
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.849990440
Short name T322
Test name
Test status
Simulation time 3224479112 ps
CPU time 34.97 seconds
Started Aug 05 04:51:11 PM PDT 24
Finished Aug 05 04:51:46 PM PDT 24
Peak memory 239556 kb
Host smart-5f719f24-0097-4c39-b513-5358d20e626c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849990440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.849990440
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.1640221876
Short name T874
Test name
Test status
Simulation time 9402629108 ps
CPU time 64.17 seconds
Started Aug 05 04:51:01 PM PDT 24
Finished Aug 05 04:52:05 PM PDT 24
Peak memory 249796 kb
Host smart-b233a43f-5834-4825-8f99-2fbe0b9e1b1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640221876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmd
s.1640221876
Directory /workspace/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/37.spi_device_intercept.1750224509
Short name T46
Test name
Test status
Simulation time 700188425 ps
CPU time 8.96 seconds
Started Aug 05 04:51:03 PM PDT 24
Finished Aug 05 04:51:12 PM PDT 24
Peak memory 233376 kb
Host smart-7cbf201d-6aff-4863-997d-b8ccc3f5823f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750224509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.1750224509
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.1746386645
Short name T487
Test name
Test status
Simulation time 3105048294 ps
CPU time 16.61 seconds
Started Aug 05 04:50:59 PM PDT 24
Finished Aug 05 04:51:16 PM PDT 24
Peak memory 225260 kb
Host smart-6b0c7fda-b95b-402a-8e20-9ca61a754b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746386645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.1746386645
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.3886238903
Short name T296
Test name
Test status
Simulation time 22777900266 ps
CPU time 11.7 seconds
Started Aug 05 04:51:15 PM PDT 24
Finished Aug 05 04:51:27 PM PDT 24
Peak memory 241280 kb
Host smart-bc14c766-a9ff-4fc9-9378-389dc65d005c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886238903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.3886238903
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.3723938564
Short name T896
Test name
Test status
Simulation time 9643837848 ps
CPU time 12.77 seconds
Started Aug 05 04:50:59 PM PDT 24
Finished Aug 05 04:51:12 PM PDT 24
Peak memory 241556 kb
Host smart-edebd26f-4b5e-4e5f-a358-cebccdf8e1b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723938564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.3723938564
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.2083301394
Short name T629
Test name
Test status
Simulation time 1915259877 ps
CPU time 19.79 seconds
Started Aug 05 04:51:04 PM PDT 24
Finished Aug 05 04:51:24 PM PDT 24
Peak memory 223140 kb
Host smart-62b54c3b-a86a-401f-8627-b1fb1dc36014
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2083301394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.2083301394
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.4042538878
Short name T865
Test name
Test status
Simulation time 1922369780 ps
CPU time 29.09 seconds
Started Aug 05 04:51:03 PM PDT 24
Finished Aug 05 04:51:32 PM PDT 24
Peak memory 253892 kb
Host smart-07e945d8-82d5-4b59-bc85-4d219e80dae3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042538878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.4042538878
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.2480584267
Short name T658
Test name
Test status
Simulation time 3100174645 ps
CPU time 16.21 seconds
Started Aug 05 04:51:03 PM PDT 24
Finished Aug 05 04:51:20 PM PDT 24
Peak memory 216904 kb
Host smart-016e1e87-7e10-444f-8bd5-d78d3c0a5bb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480584267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.2480584267
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.1314157184
Short name T509
Test name
Test status
Simulation time 46984763438 ps
CPU time 17.92 seconds
Started Aug 05 04:51:09 PM PDT 24
Finished Aug 05 04:51:27 PM PDT 24
Peak memory 218192 kb
Host smart-9b922c63-86b7-4f5f-9780-4698cb268ce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314157184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.1314157184
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.2484311109
Short name T848
Test name
Test status
Simulation time 15341340 ps
CPU time 0.67 seconds
Started Aug 05 04:51:14 PM PDT 24
Finished Aug 05 04:51:15 PM PDT 24
Peak memory 206000 kb
Host smart-5feddd61-3010-4640-b6aa-adbaa7738cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484311109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.2484311109
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.3832951657
Short name T345
Test name
Test status
Simulation time 30149134 ps
CPU time 0.81 seconds
Started Aug 05 04:51:12 PM PDT 24
Finished Aug 05 04:51:13 PM PDT 24
Peak memory 206564 kb
Host smart-6bcde6ca-419d-4a85-aef7-c3c28b8ae3bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832951657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.3832951657
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.2338530600
Short name T973
Test name
Test status
Simulation time 462642043 ps
CPU time 4.76 seconds
Started Aug 05 04:51:21 PM PDT 24
Finished Aug 05 04:51:26 PM PDT 24
Peak memory 233320 kb
Host smart-cc2d8d17-4813-4c11-b6d7-1c70b4f5f6f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338530600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.2338530600
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.717701955
Short name T698
Test name
Test status
Simulation time 14592099 ps
CPU time 0.74 seconds
Started Aug 05 04:50:59 PM PDT 24
Finished Aug 05 04:51:00 PM PDT 24
Peak memory 206140 kb
Host smart-e92c9854-5427-4308-9efe-0d8ff043b66b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717701955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.717701955
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.2281072254
Short name T600
Test name
Test status
Simulation time 329605137 ps
CPU time 3.89 seconds
Started Aug 05 04:51:24 PM PDT 24
Finished Aug 05 04:51:28 PM PDT 24
Peak memory 233624 kb
Host smart-d0d9b7f4-065c-4e87-8bca-d7e77bb3d6e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281072254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.2281072254
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.3474931862
Short name T783
Test name
Test status
Simulation time 27972205 ps
CPU time 0.81 seconds
Started Aug 05 04:51:26 PM PDT 24
Finished Aug 05 04:51:27 PM PDT 24
Peak memory 207272 kb
Host smart-414cfaf4-11c2-4454-90bd-dbc189a1fde6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474931862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.3474931862
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.4273519531
Short name T519
Test name
Test status
Simulation time 56077619871 ps
CPU time 84.91 seconds
Started Aug 05 04:50:59 PM PDT 24
Finished Aug 05 04:52:24 PM PDT 24
Peak memory 249832 kb
Host smart-e3e604e1-32f7-49d3-b20c-d8597558be72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273519531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.4273519531
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.2245568376
Short name T326
Test name
Test status
Simulation time 3042352266 ps
CPU time 17.23 seconds
Started Aug 05 04:50:59 PM PDT 24
Finished Aug 05 04:51:17 PM PDT 24
Peak memory 218412 kb
Host smart-64ec4b76-5ef0-475d-99b7-dc5bc01aacfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245568376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.2245568376
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.1400168457
Short name T155
Test name
Test status
Simulation time 322939639 ps
CPU time 3.75 seconds
Started Aug 05 04:51:12 PM PDT 24
Finished Aug 05 04:51:16 PM PDT 24
Peak memory 233420 kb
Host smart-2e43fd1b-5003-4ff7-a027-41c63a2cd44c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400168457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.1400168457
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.1014338574
Short name T526
Test name
Test status
Simulation time 13162513296 ps
CPU time 91.03 seconds
Started Aug 05 04:51:01 PM PDT 24
Finished Aug 05 04:52:32 PM PDT 24
Peak memory 249792 kb
Host smart-bc6da18d-2c0e-4f19-8091-8e949bd472dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014338574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmd
s.1014338574
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/38.spi_device_intercept.1183928979
Short name T613
Test name
Test status
Simulation time 115705612 ps
CPU time 2.29 seconds
Started Aug 05 04:51:08 PM PDT 24
Finished Aug 05 04:51:11 PM PDT 24
Peak memory 233004 kb
Host smart-a0fe7849-defe-42f1-bd5e-456c887e140b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183928979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.1183928979
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.390800170
Short name T627
Test name
Test status
Simulation time 1120375236 ps
CPU time 14.33 seconds
Started Aug 05 04:51:21 PM PDT 24
Finished Aug 05 04:51:35 PM PDT 24
Peak memory 225208 kb
Host smart-e5731216-bd2b-4aa9-9806-ca99e9de04a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390800170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.390800170
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.1989047983
Short name T713
Test name
Test status
Simulation time 257555590 ps
CPU time 2.72 seconds
Started Aug 05 04:51:02 PM PDT 24
Finished Aug 05 04:51:05 PM PDT 24
Peak memory 225124 kb
Host smart-1216f7b5-1863-4982-a14e-50054ddcfd1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989047983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.1989047983
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.2675387561
Short name T699
Test name
Test status
Simulation time 13919162705 ps
CPU time 11.14 seconds
Started Aug 05 04:51:06 PM PDT 24
Finished Aug 05 04:51:17 PM PDT 24
Peak memory 225224 kb
Host smart-b6afc906-9209-45f3-a0a4-22376313ba6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675387561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.2675387561
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.554912633
Short name T849
Test name
Test status
Simulation time 2001192943 ps
CPU time 7.32 seconds
Started Aug 05 04:51:03 PM PDT 24
Finished Aug 05 04:51:11 PM PDT 24
Peak memory 222448 kb
Host smart-6a15de14-8cf7-4718-ab1e-3f9e3b86d767
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=554912633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dire
ct.554912633
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.3374344276
Short name T22
Test name
Test status
Simulation time 102499079942 ps
CPU time 279.72 seconds
Started Aug 05 04:51:02 PM PDT 24
Finished Aug 05 04:55:42 PM PDT 24
Peak memory 274316 kb
Host smart-c1dda4ca-c911-4afc-9069-5d52dac8842c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374344276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.3374344276
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.3082620582
Short name T491
Test name
Test status
Simulation time 737214519 ps
CPU time 2.24 seconds
Started Aug 05 04:51:01 PM PDT 24
Finished Aug 05 04:51:03 PM PDT 24
Peak memory 216864 kb
Host smart-72f941f6-8656-455d-b171-9eba1611e2b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082620582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.3082620582
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.4022110119
Short name T7
Test name
Test status
Simulation time 11582043 ps
CPU time 0.72 seconds
Started Aug 05 04:51:03 PM PDT 24
Finished Aug 05 04:51:04 PM PDT 24
Peak memory 206104 kb
Host smart-9e9e66c4-4e37-4189-920c-e00cda7d4fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022110119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.4022110119
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.2061961406
Short name T383
Test name
Test status
Simulation time 75207291 ps
CPU time 1.02 seconds
Started Aug 05 04:51:02 PM PDT 24
Finished Aug 05 04:51:03 PM PDT 24
Peak memory 207680 kb
Host smart-703707be-6422-4ec4-9cfc-9c69ddc477c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061961406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.2061961406
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.3204560880
Short name T683
Test name
Test status
Simulation time 22183129 ps
CPU time 0.68 seconds
Started Aug 05 04:51:06 PM PDT 24
Finished Aug 05 04:51:07 PM PDT 24
Peak memory 206140 kb
Host smart-04fffab9-20fe-463c-9269-be0d236cf067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204560880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.3204560880
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.3435501081
Short name T347
Test name
Test status
Simulation time 9833772597 ps
CPU time 11.83 seconds
Started Aug 05 04:51:08 PM PDT 24
Finished Aug 05 04:51:20 PM PDT 24
Peak memory 233416 kb
Host smart-9b2edee8-798f-40c1-8fb6-b5861df9bd3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435501081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.3435501081
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.1060588468
Short name T722
Test name
Test status
Simulation time 14610846 ps
CPU time 0.73 seconds
Started Aug 05 04:51:27 PM PDT 24
Finished Aug 05 04:51:28 PM PDT 24
Peak memory 205748 kb
Host smart-9bf8f3c5-08cc-49e8-af86-924e574d2785
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060588468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
1060588468
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.2561221262
Short name T961
Test name
Test status
Simulation time 615655505 ps
CPU time 5.72 seconds
Started Aug 05 04:51:14 PM PDT 24
Finished Aug 05 04:51:20 PM PDT 24
Peak memory 225112 kb
Host smart-38416ae4-08ee-4628-8af5-de4847ed8f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561221262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.2561221262
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.988836249
Short name T424
Test name
Test status
Simulation time 31309911 ps
CPU time 0.84 seconds
Started Aug 05 04:51:15 PM PDT 24
Finished Aug 05 04:51:16 PM PDT 24
Peak memory 207056 kb
Host smart-837114ec-b715-4037-b570-00855a2d3754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988836249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.988836249
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.657788692
Short name T889
Test name
Test status
Simulation time 2191294826 ps
CPU time 11.45 seconds
Started Aug 05 04:51:23 PM PDT 24
Finished Aug 05 04:51:35 PM PDT 24
Peak memory 225268 kb
Host smart-cf145eef-824e-474d-8a00-b63ec0002f4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657788692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.657788692
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.2860720723
Short name T192
Test name
Test status
Simulation time 9669064996 ps
CPU time 34.84 seconds
Started Aug 05 04:51:24 PM PDT 24
Finished Aug 05 04:51:59 PM PDT 24
Peak memory 249800 kb
Host smart-545a10c6-fb38-46c6-8c47-a79822ba477f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860720723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.2860720723
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.3408764567
Short name T618
Test name
Test status
Simulation time 31142871054 ps
CPU time 314.8 seconds
Started Aug 05 04:51:10 PM PDT 24
Finished Aug 05 04:56:25 PM PDT 24
Peak memory 258044 kb
Host smart-8a830d0e-989c-44ac-be18-eb064a260525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408764567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.3408764567
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.534856499
Short name T563
Test name
Test status
Simulation time 3420383890 ps
CPU time 18.31 seconds
Started Aug 05 04:51:21 PM PDT 24
Finished Aug 05 04:51:40 PM PDT 24
Peak memory 249920 kb
Host smart-a0d03f67-bb20-4689-80c6-bea21d5035b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534856499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.534856499
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_intercept.133444123
Short name T256
Test name
Test status
Simulation time 16043190819 ps
CPU time 20.63 seconds
Started Aug 05 04:51:13 PM PDT 24
Finished Aug 05 04:51:33 PM PDT 24
Peak memory 233432 kb
Host smart-d3f98917-22e2-4a8b-a12e-7bceabf735df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133444123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.133444123
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.3295124468
Short name T820
Test name
Test status
Simulation time 1753993360 ps
CPU time 18.32 seconds
Started Aug 05 04:51:11 PM PDT 24
Finished Aug 05 04:51:29 PM PDT 24
Peak memory 233388 kb
Host smart-989739c9-6f95-4a69-9a93-2186be39bef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295124468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.3295124468
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.1831761208
Short name T795
Test name
Test status
Simulation time 3326194341 ps
CPU time 11.82 seconds
Started Aug 05 04:51:12 PM PDT 24
Finished Aug 05 04:51:23 PM PDT 24
Peak memory 233420 kb
Host smart-6ad425b2-2e48-435d-9b2a-09ca0ecdb341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831761208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.1831761208
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.3401246372
Short name T273
Test name
Test status
Simulation time 597754153 ps
CPU time 2.19 seconds
Started Aug 05 04:51:16 PM PDT 24
Finished Aug 05 04:51:18 PM PDT 24
Peak memory 225128 kb
Host smart-39bbc7e5-a432-40e0-96fe-9514c1ac4e3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401246372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.3401246372
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.206353138
Short name T749
Test name
Test status
Simulation time 3309906038 ps
CPU time 9.54 seconds
Started Aug 05 04:51:09 PM PDT 24
Finished Aug 05 04:51:19 PM PDT 24
Peak memory 219928 kb
Host smart-2a7c960f-14c8-41cc-b61e-6b5592579550
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=206353138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dire
ct.206353138
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.544057356
Short name T824
Test name
Test status
Simulation time 109045279 ps
CPU time 1.14 seconds
Started Aug 05 04:51:27 PM PDT 24
Finished Aug 05 04:51:28 PM PDT 24
Peak memory 207364 kb
Host smart-86825499-7167-40b5-a8e8-a0cf8407c1c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544057356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stres
s_all.544057356
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.3781603033
Short name T522
Test name
Test status
Simulation time 3055676492 ps
CPU time 22.19 seconds
Started Aug 05 04:51:18 PM PDT 24
Finished Aug 05 04:51:40 PM PDT 24
Peak memory 216996 kb
Host smart-3e838f0e-4e20-4023-82d0-bb5c529137e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781603033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.3781603033
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.238898499
Short name T776
Test name
Test status
Simulation time 3764899248 ps
CPU time 10.34 seconds
Started Aug 05 04:51:09 PM PDT 24
Finished Aug 05 04:51:20 PM PDT 24
Peak memory 216968 kb
Host smart-a21d1e10-9167-482e-89ec-3527fd7ea30b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238898499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.238898499
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.2542368582
Short name T766
Test name
Test status
Simulation time 479987159 ps
CPU time 2.61 seconds
Started Aug 05 04:51:13 PM PDT 24
Finished Aug 05 04:51:16 PM PDT 24
Peak memory 216868 kb
Host smart-66966ecd-64f3-4ab6-a68a-77b0be946ce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542368582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.2542368582
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.3906690660
Short name T870
Test name
Test status
Simulation time 76886002 ps
CPU time 0.96 seconds
Started Aug 05 04:51:01 PM PDT 24
Finished Aug 05 04:51:02 PM PDT 24
Peak memory 207464 kb
Host smart-46a3550c-d349-4031-a285-3d5631b51d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906690660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.3906690660
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.3592388814
Short name T571
Test name
Test status
Simulation time 17882464048 ps
CPU time 8.05 seconds
Started Aug 05 04:51:20 PM PDT 24
Finished Aug 05 04:51:28 PM PDT 24
Peak memory 241496 kb
Host smart-8e1b6a0f-9e6c-4e46-b8dc-c8b8bf29dd1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592388814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.3592388814
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.3244804596
Short name T885
Test name
Test status
Simulation time 14201719 ps
CPU time 0.7 seconds
Started Aug 05 04:50:00 PM PDT 24
Finished Aug 05 04:50:01 PM PDT 24
Peak memory 205784 kb
Host smart-f1e579f8-33ab-4228-a1bc-1eee919e36f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244804596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.3
244804596
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.741195692
Short name T981
Test name
Test status
Simulation time 536228920 ps
CPU time 4.14 seconds
Started Aug 05 04:49:59 PM PDT 24
Finished Aug 05 04:50:03 PM PDT 24
Peak memory 225132 kb
Host smart-3f5cf3ac-455e-40e9-8826-ce474f37f4f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741195692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.741195692
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.3509895158
Short name T30
Test name
Test status
Simulation time 21229471 ps
CPU time 0.8 seconds
Started Aug 05 04:49:42 PM PDT 24
Finished Aug 05 04:49:42 PM PDT 24
Peak memory 207292 kb
Host smart-e180204a-62b5-43fc-b3bf-17fa62f82e88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509895158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.3509895158
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.2729148277
Short name T265
Test name
Test status
Simulation time 2541613945 ps
CPU time 51.93 seconds
Started Aug 05 04:49:45 PM PDT 24
Finished Aug 05 04:50:37 PM PDT 24
Peak memory 253132 kb
Host smart-e9bf4b8e-397a-4366-a44d-14da6a2797a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729148277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.2729148277
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.541974802
Short name T332
Test name
Test status
Simulation time 22295755826 ps
CPU time 94.88 seconds
Started Aug 05 04:49:52 PM PDT 24
Finished Aug 05 04:51:27 PM PDT 24
Peak memory 266560 kb
Host smart-024b88ec-5dee-4189-8549-4bc439e2e70c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541974802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.541974802
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.1263114510
Short name T743
Test name
Test status
Simulation time 213095728 ps
CPU time 3.95 seconds
Started Aug 05 04:49:49 PM PDT 24
Finished Aug 05 04:49:53 PM PDT 24
Peak memory 225128 kb
Host smart-6a3567ec-c966-4e8d-8541-263f88f82c75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263114510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.1263114510
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.2123660459
Short name T304
Test name
Test status
Simulation time 8353443276 ps
CPU time 46.5 seconds
Started Aug 05 04:49:59 PM PDT 24
Finished Aug 05 04:50:45 PM PDT 24
Peak memory 258012 kb
Host smart-6e4f2dc1-846a-4fb9-86f7-dbe2513462ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123660459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds
.2123660459
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/4.spi_device_intercept.3233482804
Short name T1026
Test name
Test status
Simulation time 745780105 ps
CPU time 8.68 seconds
Started Aug 05 04:49:37 PM PDT 24
Finished Aug 05 04:49:46 PM PDT 24
Peak memory 233276 kb
Host smart-e2f57188-6c80-4bfb-9d80-2b4ca71edd81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233482804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.3233482804
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.322686637
Short name T275
Test name
Test status
Simulation time 11931586814 ps
CPU time 27.98 seconds
Started Aug 05 04:49:54 PM PDT 24
Finished Aug 05 04:50:22 PM PDT 24
Peak memory 225176 kb
Host smart-23c94c61-6863-4e61-baaa-07148fe20aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322686637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.322686637
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.3850073551
Short name T637
Test name
Test status
Simulation time 45455156 ps
CPU time 1.05 seconds
Started Aug 05 04:49:52 PM PDT 24
Finished Aug 05 04:49:53 PM PDT 24
Peak memory 217096 kb
Host smart-72214909-d10b-494a-bf57-e3f1a4dffb99
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850073551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.spi_device_mem_parity.3850073551
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.1824017629
Short name T50
Test name
Test status
Simulation time 9468188740 ps
CPU time 5.94 seconds
Started Aug 05 04:49:56 PM PDT 24
Finished Aug 05 04:50:03 PM PDT 24
Peak memory 225168 kb
Host smart-b128735d-5491-44fb-b262-db3a1f8a011d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824017629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.1824017629
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.3525896045
Short name T706
Test name
Test status
Simulation time 23471841659 ps
CPU time 18.15 seconds
Started Aug 05 04:49:55 PM PDT 24
Finished Aug 05 04:50:13 PM PDT 24
Peak memory 225204 kb
Host smart-66850d48-ec46-46f4-920b-89aa001ebbe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525896045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.3525896045
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.1370624174
Short name T411
Test name
Test status
Simulation time 503857534 ps
CPU time 5.09 seconds
Started Aug 05 04:49:55 PM PDT 24
Finished Aug 05 04:50:00 PM PDT 24
Peak memory 221368 kb
Host smart-309a8b38-a7ba-45ee-8015-5c77ee045910
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1370624174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.1370624174
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.2274814494
Short name T70
Test name
Test status
Simulation time 321759003 ps
CPU time 1.19 seconds
Started Aug 05 04:49:47 PM PDT 24
Finished Aug 05 04:49:49 PM PDT 24
Peak memory 235584 kb
Host smart-2af7203a-ac9b-4cc4-a63f-2a152e594876
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274814494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.2274814494
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.854430775
Short name T1
Test name
Test status
Simulation time 2982272366 ps
CPU time 8.8 seconds
Started Aug 05 04:49:55 PM PDT 24
Finished Aug 05 04:50:04 PM PDT 24
Peak memory 216932 kb
Host smart-2a9657b8-9f4a-43b2-b73d-cbfa11d9bad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854430775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.854430775
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.3691319472
Short name T348
Test name
Test status
Simulation time 1086055708 ps
CPU time 2.84 seconds
Started Aug 05 04:49:45 PM PDT 24
Finished Aug 05 04:49:48 PM PDT 24
Peak memory 216612 kb
Host smart-6f70eb65-8b74-4328-9bbe-874a07b9a599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691319472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.3691319472
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.492945347
Short name T352
Test name
Test status
Simulation time 46417949 ps
CPU time 0.97 seconds
Started Aug 05 04:49:53 PM PDT 24
Finished Aug 05 04:49:54 PM PDT 24
Peak memory 208456 kb
Host smart-3ad4efb1-7753-43f9-9689-44f9f4ecc4ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492945347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.492945347
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.3195762398
Short name T399
Test name
Test status
Simulation time 19131017 ps
CPU time 0.75 seconds
Started Aug 05 04:49:58 PM PDT 24
Finished Aug 05 04:49:59 PM PDT 24
Peak memory 206504 kb
Host smart-a3ee44cd-5b50-4d05-b6a1-c9c110baf2f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195762398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.3195762398
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.3967494936
Short name T758
Test name
Test status
Simulation time 215824525 ps
CPU time 4.55 seconds
Started Aug 05 04:49:52 PM PDT 24
Finished Aug 05 04:49:56 PM PDT 24
Peak memory 241480 kb
Host smart-ddf19e28-aa47-4989-971a-6308a16ae525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967494936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.3967494936
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.2673484119
Short name T923
Test name
Test status
Simulation time 43428310 ps
CPU time 0.73 seconds
Started Aug 05 04:51:12 PM PDT 24
Finished Aug 05 04:51:12 PM PDT 24
Peak memory 205088 kb
Host smart-94d10622-1f91-4f32-a1c8-66e1dc38eb0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673484119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
2673484119
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.4152301660
Short name T459
Test name
Test status
Simulation time 55666602 ps
CPU time 2.42 seconds
Started Aug 05 04:51:16 PM PDT 24
Finished Aug 05 04:51:19 PM PDT 24
Peak memory 225172 kb
Host smart-8d743c43-7645-494a-a244-a5e20d9e7d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152301660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.4152301660
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.3381488971
Short name T56
Test name
Test status
Simulation time 21476213 ps
CPU time 0.75 seconds
Started Aug 05 04:51:11 PM PDT 24
Finished Aug 05 04:51:12 PM PDT 24
Peak memory 207428 kb
Host smart-ce867482-b67f-4f67-a64c-15127fbe9d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381488971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.3381488971
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.215891672
Short name T200
Test name
Test status
Simulation time 3284373873 ps
CPU time 44.72 seconds
Started Aug 05 04:51:26 PM PDT 24
Finished Aug 05 04:52:10 PM PDT 24
Peak memory 258020 kb
Host smart-3ce8d74e-719a-4275-b53f-8c19f1a3f2de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215891672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.215891672
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.3444897780
Short name T483
Test name
Test status
Simulation time 7395370109 ps
CPU time 94.15 seconds
Started Aug 05 04:51:31 PM PDT 24
Finished Aug 05 04:53:05 PM PDT 24
Peak memory 250136 kb
Host smart-dbef8b03-3efd-4da5-957c-ddf42ab02de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444897780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.3444897780
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.2184756825
Short name T184
Test name
Test status
Simulation time 4392048973 ps
CPU time 35.06 seconds
Started Aug 05 04:51:13 PM PDT 24
Finished Aug 05 04:51:48 PM PDT 24
Peak memory 236892 kb
Host smart-d6fdcd21-2db6-4752-9df5-e21b8204c38b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184756825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.2184756825
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.1668829391
Short name T665
Test name
Test status
Simulation time 219582668 ps
CPU time 7.29 seconds
Started Aug 05 04:51:18 PM PDT 24
Finished Aug 05 04:51:25 PM PDT 24
Peak memory 250064 kb
Host smart-b985d3c3-85db-4fee-bfec-4d74a0dbd5d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668829391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.1668829391
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.1512506014
Short name T884
Test name
Test status
Simulation time 16321321007 ps
CPU time 126.64 seconds
Started Aug 05 04:51:29 PM PDT 24
Finished Aug 05 04:53:36 PM PDT 24
Peak memory 252648 kb
Host smart-ea5bc21c-2e80-4d96-bafe-c6c385b16dda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512506014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmd
s.1512506014
Directory /workspace/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/40.spi_device_intercept.4270568563
Short name T986
Test name
Test status
Simulation time 131878269 ps
CPU time 3.52 seconds
Started Aug 05 04:51:23 PM PDT 24
Finished Aug 05 04:51:26 PM PDT 24
Peak memory 225032 kb
Host smart-9f2a6cc7-3084-49bb-affd-18871df5e328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270568563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.4270568563
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.1820626444
Short name T222
Test name
Test status
Simulation time 71819601591 ps
CPU time 32.09 seconds
Started Aug 05 04:51:13 PM PDT 24
Finished Aug 05 04:51:45 PM PDT 24
Peak memory 233532 kb
Host smart-b1a2d602-c4eb-4ad0-9dd0-263b290c5c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820626444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.1820626444
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.2566910179
Short name T303
Test name
Test status
Simulation time 5486948224 ps
CPU time 9.37 seconds
Started Aug 05 04:51:21 PM PDT 24
Finished Aug 05 04:51:30 PM PDT 24
Peak memory 249552 kb
Host smart-7ec0bfc2-3c4b-4f44-aa12-3bbcda89712c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566910179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.2566910179
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.2357083700
Short name T678
Test name
Test status
Simulation time 2763609343 ps
CPU time 9.08 seconds
Started Aug 05 04:51:05 PM PDT 24
Finished Aug 05 04:51:14 PM PDT 24
Peak memory 225240 kb
Host smart-ee165f21-0671-4412-a34e-457c2ce04413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357083700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.2357083700
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.1399995858
Short name T513
Test name
Test status
Simulation time 282117608 ps
CPU time 6.27 seconds
Started Aug 05 04:51:20 PM PDT 24
Finished Aug 05 04:51:26 PM PDT 24
Peak memory 222072 kb
Host smart-7563df82-b076-4390-9f7a-225dc808a983
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1399995858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.1399995858
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.2607029220
Short name T679
Test name
Test status
Simulation time 1897378953 ps
CPU time 4.65 seconds
Started Aug 05 04:51:32 PM PDT 24
Finished Aug 05 04:51:37 PM PDT 24
Peak memory 217020 kb
Host smart-96d910c4-a9f0-45ce-96d0-fe0853433fc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607029220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.2607029220
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.4261680623
Short name T963
Test name
Test status
Simulation time 13131556720 ps
CPU time 10.96 seconds
Started Aug 05 04:51:06 PM PDT 24
Finished Aug 05 04:51:17 PM PDT 24
Peak memory 216952 kb
Host smart-cc584cab-6d61-4891-aabd-54f4f25a7513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261680623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.4261680623
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.1841490379
Short name T10
Test name
Test status
Simulation time 212105001 ps
CPU time 1.79 seconds
Started Aug 05 04:51:17 PM PDT 24
Finished Aug 05 04:51:19 PM PDT 24
Peak memory 216852 kb
Host smart-e381dc5f-c52b-4588-8b1f-d45a16eb5798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841490379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.1841490379
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.2909106917
Short name T349
Test name
Test status
Simulation time 293101335 ps
CPU time 0.87 seconds
Started Aug 05 04:51:33 PM PDT 24
Finished Aug 05 04:51:34 PM PDT 24
Peak memory 206472 kb
Host smart-7855d8af-dadf-4174-942d-55516ef33721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909106917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.2909106917
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.3802433049
Short name T396
Test name
Test status
Simulation time 5203622449 ps
CPU time 24.15 seconds
Started Aug 05 04:51:25 PM PDT 24
Finished Aug 05 04:51:54 PM PDT 24
Peak memory 233564 kb
Host smart-b9db8c4b-e808-4333-b58a-d87d42ad66fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802433049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.3802433049
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.799623763
Short name T701
Test name
Test status
Simulation time 136640042 ps
CPU time 0.75 seconds
Started Aug 05 04:51:29 PM PDT 24
Finished Aug 05 04:51:30 PM PDT 24
Peak memory 205752 kb
Host smart-1b53ea42-78f1-41c0-b0ab-ab687e22f548
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799623763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.799623763
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.507184843
Short name T802
Test name
Test status
Simulation time 96414026 ps
CPU time 2.92 seconds
Started Aug 05 04:51:29 PM PDT 24
Finished Aug 05 04:51:32 PM PDT 24
Peak memory 233204 kb
Host smart-660c0706-2987-409e-8952-f2df18bac90e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507184843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.507184843
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.2328889743
Short name T873
Test name
Test status
Simulation time 61179858 ps
CPU time 0.89 seconds
Started Aug 05 04:51:11 PM PDT 24
Finished Aug 05 04:51:12 PM PDT 24
Peak memory 207240 kb
Host smart-3cdcc5bf-2c19-4b94-b0a8-e169094e8b67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328889743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.2328889743
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.968432848
Short name T312
Test name
Test status
Simulation time 3093702419 ps
CPU time 23.14 seconds
Started Aug 05 04:51:30 PM PDT 24
Finished Aug 05 04:51:53 PM PDT 24
Peak memory 234404 kb
Host smart-a82f273b-ce55-4684-b885-1bca44317542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968432848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.968432848
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.1367377239
Short name T673
Test name
Test status
Simulation time 4111776112 ps
CPU time 58.25 seconds
Started Aug 05 04:51:25 PM PDT 24
Finished Aug 05 04:52:24 PM PDT 24
Peak memory 249828 kb
Host smart-93978c76-0aa4-48f9-bcf5-3a112debe296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367377239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.1367377239
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.2066188467
Short name T954
Test name
Test status
Simulation time 30342877202 ps
CPU time 269.84 seconds
Started Aug 05 04:51:23 PM PDT 24
Finished Aug 05 04:55:53 PM PDT 24
Peak memory 256228 kb
Host smart-fd96e329-9dd8-4288-8cd7-05061a01a4dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066188467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.2066188467
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.2400171959
Short name T930
Test name
Test status
Simulation time 3056000153 ps
CPU time 16.33 seconds
Started Aug 05 04:51:28 PM PDT 24
Finished Aug 05 04:51:45 PM PDT 24
Peak memory 225172 kb
Host smart-65ed2672-ce90-46d5-8b5d-adcdf335c11c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400171959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.2400171959
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.427560573
Short name T24
Test name
Test status
Simulation time 23743249 ps
CPU time 0.75 seconds
Started Aug 05 04:51:17 PM PDT 24
Finished Aug 05 04:51:18 PM PDT 24
Peak memory 216372 kb
Host smart-cc348f74-9011-45c5-8e51-ff01968eefe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427560573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmds
.427560573
Directory /workspace/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/41.spi_device_intercept.1597213635
Short name T809
Test name
Test status
Simulation time 144443818 ps
CPU time 2.81 seconds
Started Aug 05 04:51:26 PM PDT 24
Finished Aug 05 04:51:28 PM PDT 24
Peak memory 233384 kb
Host smart-8bc96747-5789-4c3c-9c86-cabf1fc41ccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597213635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.1597213635
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.1568773337
Short name T893
Test name
Test status
Simulation time 4259039817 ps
CPU time 4.93 seconds
Started Aug 05 04:51:22 PM PDT 24
Finished Aug 05 04:51:27 PM PDT 24
Peak memory 233368 kb
Host smart-1a994c32-38c2-4e15-a194-06b25004792b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568773337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.1568773337
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.3089540269
Short name T237
Test name
Test status
Simulation time 7711905962 ps
CPU time 15.51 seconds
Started Aug 05 04:51:31 PM PDT 24
Finished Aug 05 04:51:47 PM PDT 24
Peak memory 225152 kb
Host smart-1d0cdea8-de67-453e-a853-0f6049eeef34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089540269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.3089540269
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.16264746
Short name T612
Test name
Test status
Simulation time 29158009 ps
CPU time 2.24 seconds
Started Aug 05 04:51:21 PM PDT 24
Finished Aug 05 04:51:23 PM PDT 24
Peak memory 224708 kb
Host smart-ccb952ea-1343-482b-bf53-59dcfa0f0136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16264746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.16264746
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.346939206
Short name T648
Test name
Test status
Simulation time 4400575573 ps
CPU time 4.21 seconds
Started Aug 05 04:51:25 PM PDT 24
Finished Aug 05 04:51:29 PM PDT 24
Peak memory 219916 kb
Host smart-d4d007d6-71d6-4f95-8946-1c2daeb87001
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=346939206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dire
ct.346939206
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.1413987588
Short name T621
Test name
Test status
Simulation time 37784436 ps
CPU time 1.03 seconds
Started Aug 05 04:51:26 PM PDT 24
Finished Aug 05 04:51:27 PM PDT 24
Peak memory 207532 kb
Host smart-b32fbc7c-306f-44d5-ad0b-81a7c503ad7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413987588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.1413987588
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.3745733420
Short name T333
Test name
Test status
Simulation time 2338058789 ps
CPU time 22.44 seconds
Started Aug 05 04:51:26 PM PDT 24
Finished Aug 05 04:51:49 PM PDT 24
Peak memory 216868 kb
Host smart-f1f8d582-6558-413d-ac84-52a7e7bfeb9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745733420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.3745733420
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.3117871596
Short name T546
Test name
Test status
Simulation time 9421388138 ps
CPU time 13.76 seconds
Started Aug 05 04:51:18 PM PDT 24
Finished Aug 05 04:51:32 PM PDT 24
Peak memory 216964 kb
Host smart-cc6145ac-6214-4eed-aebf-3278d7c511dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117871596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.3117871596
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.2914319381
Short name T622
Test name
Test status
Simulation time 1950080029 ps
CPU time 2.27 seconds
Started Aug 05 04:52:10 PM PDT 24
Finished Aug 05 04:52:12 PM PDT 24
Peak memory 217020 kb
Host smart-78bbb3f6-950f-4803-bf95-64da15474e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914319381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.2914319381
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.2279465814
Short name T377
Test name
Test status
Simulation time 160881806 ps
CPU time 0.87 seconds
Started Aug 05 04:51:12 PM PDT 24
Finished Aug 05 04:51:13 PM PDT 24
Peak memory 206464 kb
Host smart-63c56a6a-cb7c-4e5a-9c9e-73424d7e31f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279465814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.2279465814
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.24282026
Short name T564
Test name
Test status
Simulation time 1565137313 ps
CPU time 3.4 seconds
Started Aug 05 04:51:31 PM PDT 24
Finished Aug 05 04:51:34 PM PDT 24
Peak memory 225084 kb
Host smart-7610cd1d-e214-4ee2-bb48-22d2c088e5e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24282026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.24282026
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.2633224515
Short name T65
Test name
Test status
Simulation time 23187116 ps
CPU time 0.75 seconds
Started Aug 05 04:51:35 PM PDT 24
Finished Aug 05 04:51:36 PM PDT 24
Peak memory 206116 kb
Host smart-1e5646ba-b0ce-4b82-9334-a1d838ceddd3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633224515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
2633224515
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.1125531108
Short name T626
Test name
Test status
Simulation time 841367883 ps
CPU time 7.76 seconds
Started Aug 05 04:51:17 PM PDT 24
Finished Aug 05 04:51:24 PM PDT 24
Peak memory 225132 kb
Host smart-d61a627b-cc6f-4f54-9646-de057adecde6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125531108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.1125531108
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.3372876553
Short name T687
Test name
Test status
Simulation time 58460716 ps
CPU time 0.82 seconds
Started Aug 05 04:51:28 PM PDT 24
Finished Aug 05 04:51:29 PM PDT 24
Peak memory 207288 kb
Host smart-8d67204c-17c7-428b-8591-47b443f3df5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372876553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.3372876553
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.3522827991
Short name T641
Test name
Test status
Simulation time 113231504398 ps
CPU time 163.42 seconds
Started Aug 05 04:51:24 PM PDT 24
Finished Aug 05 04:54:07 PM PDT 24
Peak memory 250376 kb
Host smart-52fd3229-b6ea-40f6-9c7c-500d1478af8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522827991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.3522827991
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.1874169675
Short name T589
Test name
Test status
Simulation time 4340232791 ps
CPU time 52.32 seconds
Started Aug 05 04:51:39 PM PDT 24
Finished Aug 05 04:52:31 PM PDT 24
Peak memory 240248 kb
Host smart-f286a5b4-8169-4126-8a06-eddfde70c274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874169675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.1874169675
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.3604088089
Short name T481
Test name
Test status
Simulation time 328780542 ps
CPU time 2.65 seconds
Started Aug 05 04:51:30 PM PDT 24
Finished Aug 05 04:51:33 PM PDT 24
Peak memory 225112 kb
Host smart-74690e78-4c82-400c-adc5-d6f7050d9014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604088089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.3604088089
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.2215046282
Short name T27
Test name
Test status
Simulation time 42016846 ps
CPU time 0.75 seconds
Started Aug 05 04:51:30 PM PDT 24
Finished Aug 05 04:51:31 PM PDT 24
Peak memory 216332 kb
Host smart-eb6df79e-876b-4a4f-8d85-74ec7853c26b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215046282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmd
s.2215046282
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/42.spi_device_intercept.505259040
Short name T656
Test name
Test status
Simulation time 521783165 ps
CPU time 4.55 seconds
Started Aug 05 04:51:16 PM PDT 24
Finished Aug 05 04:51:21 PM PDT 24
Peak memory 233372 kb
Host smart-7ee08add-dcb4-4087-8725-de5ae314f304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505259040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.505259040
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.4067185714
Short name T539
Test name
Test status
Simulation time 31186129 ps
CPU time 2.47 seconds
Started Aug 05 04:51:31 PM PDT 24
Finished Aug 05 04:51:34 PM PDT 24
Peak memory 232940 kb
Host smart-70ea2a4c-554c-4814-ae96-47a532a54e60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067185714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.4067185714
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.2755177003
Short name T94
Test name
Test status
Simulation time 62208102921 ps
CPU time 40.32 seconds
Started Aug 05 04:51:12 PM PDT 24
Finished Aug 05 04:51:52 PM PDT 24
Peak memory 233372 kb
Host smart-9b9c784c-c82c-4e05-ba73-4ec3ce708e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755177003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.2755177003
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.1955767009
Short name T725
Test name
Test status
Simulation time 581248478 ps
CPU time 5.45 seconds
Started Aug 05 04:51:17 PM PDT 24
Finished Aug 05 04:51:22 PM PDT 24
Peak memory 241220 kb
Host smart-b3e76e8c-a1c4-4c62-aa49-0741fe0901dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955767009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.1955767009
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.4292182382
Short name T439
Test name
Test status
Simulation time 1824636943 ps
CPU time 4.2 seconds
Started Aug 05 04:51:19 PM PDT 24
Finished Aug 05 04:51:23 PM PDT 24
Peak memory 223012 kb
Host smart-1834b92c-9de3-4f4c-9e0a-34f430f5e60a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4292182382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.4292182382
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.1370222527
Short name T793
Test name
Test status
Simulation time 42560888792 ps
CPU time 58.8 seconds
Started Aug 05 04:51:37 PM PDT 24
Finished Aug 05 04:52:36 PM PDT 24
Peak memory 241276 kb
Host smart-bd331dcb-5eaf-4bba-bf19-2b17b4ed64d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370222527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.1370222527
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.2439251955
Short name T467
Test name
Test status
Simulation time 2648188113 ps
CPU time 14.18 seconds
Started Aug 05 04:51:20 PM PDT 24
Finished Aug 05 04:51:34 PM PDT 24
Peak memory 216912 kb
Host smart-acabc9e0-feb0-4ba2-be16-2714043b792d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439251955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.2439251955
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.4070914006
Short name T707
Test name
Test status
Simulation time 26275864035 ps
CPU time 9.08 seconds
Started Aug 05 04:51:17 PM PDT 24
Finished Aug 05 04:51:26 PM PDT 24
Peak memory 216924 kb
Host smart-9afafa3c-8718-41df-bb8f-db9fb15b8751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070914006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.4070914006
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.2829944581
Short name T976
Test name
Test status
Simulation time 284197085 ps
CPU time 1.12 seconds
Started Aug 05 04:51:25 PM PDT 24
Finished Aug 05 04:51:27 PM PDT 24
Peak memory 208688 kb
Host smart-ffaf51d4-a1d2-4843-aa7f-78c6a4e4a13d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829944581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.2829944581
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.3479915106
Short name T869
Test name
Test status
Simulation time 74134871 ps
CPU time 0.82 seconds
Started Aug 05 04:51:24 PM PDT 24
Finished Aug 05 04:51:25 PM PDT 24
Peak memory 206440 kb
Host smart-34581461-ab93-4a9b-bef9-64e64fed0059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479915106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.3479915106
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.2128562766
Short name T488
Test name
Test status
Simulation time 2098936087 ps
CPU time 11.35 seconds
Started Aug 05 04:51:15 PM PDT 24
Finished Aug 05 04:51:26 PM PDT 24
Peak memory 238564 kb
Host smart-8684d6fb-f93b-4056-bf4d-346ed73d7bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128562766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.2128562766
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.2920790210
Short name T1016
Test name
Test status
Simulation time 83013887 ps
CPU time 0.74 seconds
Started Aug 05 04:51:33 PM PDT 24
Finished Aug 05 04:51:34 PM PDT 24
Peak memory 205664 kb
Host smart-ef5fe561-269d-41b4-ab92-26d57198f905
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920790210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
2920790210
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.1373309662
Short name T531
Test name
Test status
Simulation time 370768343 ps
CPU time 6.65 seconds
Started Aug 05 04:51:31 PM PDT 24
Finished Aug 05 04:51:43 PM PDT 24
Peak memory 233372 kb
Host smart-82588bbe-4e01-4cc7-9521-0f45db311a6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373309662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.1373309662
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.1185715785
Short name T620
Test name
Test status
Simulation time 42899499 ps
CPU time 0.79 seconds
Started Aug 05 04:51:23 PM PDT 24
Finished Aug 05 04:51:24 PM PDT 24
Peak memory 207288 kb
Host smart-43f0c690-3393-4f9c-91c1-425b2e4f13ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185715785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.1185715785
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.607159336
Short name T186
Test name
Test status
Simulation time 106705369507 ps
CPU time 161.59 seconds
Started Aug 05 04:51:31 PM PDT 24
Finished Aug 05 04:54:12 PM PDT 24
Peak memory 251484 kb
Host smart-d89fa129-8c47-4422-b25f-9ffb19b4d7e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607159336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.607159336
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.850699567
Short name T232
Test name
Test status
Simulation time 24162896393 ps
CPU time 192.79 seconds
Started Aug 05 04:51:30 PM PDT 24
Finished Aug 05 04:54:42 PM PDT 24
Peak memory 249876 kb
Host smart-298f18fe-7ae4-4874-9745-ee558a3dc832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850699567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.850699567
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.3789583243
Short name T14
Test name
Test status
Simulation time 31466183113 ps
CPU time 115.7 seconds
Started Aug 05 04:51:32 PM PDT 24
Finished Aug 05 04:53:28 PM PDT 24
Peak memory 256004 kb
Host smart-55c71048-6a16-42c3-949c-7bbf038b7553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789583243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.3789583243
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.1935978405
Short name T43
Test name
Test status
Simulation time 1385884838 ps
CPU time 4.69 seconds
Started Aug 05 04:51:43 PM PDT 24
Finished Aug 05 04:51:48 PM PDT 24
Peak memory 225188 kb
Host smart-e9ec9c97-ad36-49c4-bffe-a480ce2cc23f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935978405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.1935978405
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.588464646
Short name T206
Test name
Test status
Simulation time 6096763615 ps
CPU time 28.11 seconds
Started Aug 05 04:51:35 PM PDT 24
Finished Aug 05 04:52:03 PM PDT 24
Peak memory 256760 kb
Host smart-c999dff9-fcb7-4d4b-9a28-6feb48f1cb47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588464646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmds
.588464646
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/43.spi_device_intercept.576273027
Short name T898
Test name
Test status
Simulation time 831596919 ps
CPU time 6.94 seconds
Started Aug 05 04:51:37 PM PDT 24
Finished Aug 05 04:51:44 PM PDT 24
Peak memory 225244 kb
Host smart-2f31464a-ccc1-4e7e-be57-8607480de95c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576273027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.576273027
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.4104702650
Short name T693
Test name
Test status
Simulation time 3541249180 ps
CPU time 14.38 seconds
Started Aug 05 04:51:42 PM PDT 24
Finished Aug 05 04:51:56 PM PDT 24
Peak memory 233376 kb
Host smart-dc2cb32b-4f68-402b-8e29-d519c4278f73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104702650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.4104702650
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.4080351895
Short name T716
Test name
Test status
Simulation time 1220185245 ps
CPU time 3.89 seconds
Started Aug 05 04:51:26 PM PDT 24
Finished Aug 05 04:51:30 PM PDT 24
Peak memory 225100 kb
Host smart-47c9afee-c2c0-4f5d-b4fc-2cd7a5fdcfc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080351895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.4080351895
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.2840189700
Short name T774
Test name
Test status
Simulation time 278444310 ps
CPU time 3.07 seconds
Started Aug 05 04:51:34 PM PDT 24
Finished Aug 05 04:51:37 PM PDT 24
Peak memory 233412 kb
Host smart-9a20788e-0cce-4f76-bf49-fbe40004954b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840189700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.2840189700
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.3574485516
Short name T521
Test name
Test status
Simulation time 508906022 ps
CPU time 6.94 seconds
Started Aug 05 04:51:38 PM PDT 24
Finished Aug 05 04:51:45 PM PDT 24
Peak memory 223652 kb
Host smart-1aaf234c-3159-47da-8429-9ddaf2fbeed6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3574485516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.3574485516
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.74918604
Short name T143
Test name
Test status
Simulation time 19806368362 ps
CPU time 234.56 seconds
Started Aug 05 04:51:27 PM PDT 24
Finished Aug 05 04:55:22 PM PDT 24
Peak memory 273852 kb
Host smart-7bc25e4b-cf10-4d9d-83e2-a5798fe4ed0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74918604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stress
_all.74918604
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.3672424262
Short name T392
Test name
Test status
Simulation time 4469576427 ps
CPU time 6.36 seconds
Started Aug 05 04:51:30 PM PDT 24
Finished Aug 05 04:51:36 PM PDT 24
Peak memory 216908 kb
Host smart-a35f0f34-20fb-468e-b96c-443e6d11ff2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672424262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.3672424262
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.1600336778
Short name T832
Test name
Test status
Simulation time 326316904 ps
CPU time 2.49 seconds
Started Aug 05 04:51:27 PM PDT 24
Finished Aug 05 04:51:29 PM PDT 24
Peak memory 216868 kb
Host smart-83a1273d-ede9-4749-82d5-332172c81983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600336778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.1600336778
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.717568341
Short name T819
Test name
Test status
Simulation time 717784649 ps
CPU time 8.07 seconds
Started Aug 05 04:51:32 PM PDT 24
Finished Aug 05 04:51:40 PM PDT 24
Peak memory 217088 kb
Host smart-5a96a388-efbb-4e2f-b630-17079f7ca8cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717568341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.717568341
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.2788885575
Short name T572
Test name
Test status
Simulation time 93945374 ps
CPU time 0.87 seconds
Started Aug 05 04:51:29 PM PDT 24
Finished Aug 05 04:51:30 PM PDT 24
Peak memory 206456 kb
Host smart-73a4c05a-67bc-4806-810f-92cf4ecf6875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788885575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.2788885575
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.376378870
Short name T537
Test name
Test status
Simulation time 5300021164 ps
CPU time 10.99 seconds
Started Aug 05 04:51:38 PM PDT 24
Finished Aug 05 04:51:49 PM PDT 24
Peak memory 225216 kb
Host smart-f3a6f2de-715f-44aa-b104-fbc95fa44fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376378870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.376378870
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.4063594766
Short name T905
Test name
Test status
Simulation time 41622754 ps
CPU time 0.72 seconds
Started Aug 05 04:51:43 PM PDT 24
Finished Aug 05 04:51:44 PM PDT 24
Peak memory 205736 kb
Host smart-42665855-6e5c-4af9-84c4-3a5b1cd33b2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063594766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
4063594766
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.2354128199
Short name T957
Test name
Test status
Simulation time 158994091 ps
CPU time 2.81 seconds
Started Aug 05 04:51:37 PM PDT 24
Finished Aug 05 04:51:40 PM PDT 24
Peak memory 225136 kb
Host smart-95198d55-8c08-4046-a185-eb8e217c3afb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354128199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.2354128199
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.408407587
Short name T931
Test name
Test status
Simulation time 36047851 ps
CPU time 0.79 seconds
Started Aug 05 04:51:39 PM PDT 24
Finished Aug 05 04:51:40 PM PDT 24
Peak memory 206960 kb
Host smart-49bfdc97-8efb-4691-afbc-79a16ebd6dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408407587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.408407587
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.154954012
Short name T198
Test name
Test status
Simulation time 111798289876 ps
CPU time 199.36 seconds
Started Aug 05 04:51:45 PM PDT 24
Finished Aug 05 04:55:05 PM PDT 24
Peak memory 241632 kb
Host smart-a97ea65c-fc2f-450d-8f27-f91541e14e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154954012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.154954012
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.3575759270
Short name T462
Test name
Test status
Simulation time 39317706090 ps
CPU time 102.06 seconds
Started Aug 05 04:51:37 PM PDT 24
Finished Aug 05 04:53:20 PM PDT 24
Peak memory 257992 kb
Host smart-4afc9407-5a38-48d4-9b69-0454fe0ac2e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575759270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.3575759270
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.3445931516
Short name T745
Test name
Test status
Simulation time 6736270449 ps
CPU time 83.11 seconds
Started Aug 05 04:51:45 PM PDT 24
Finished Aug 05 04:53:09 PM PDT 24
Peak memory 255464 kb
Host smart-26071637-a07e-4025-8085-f15fa634b64c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445931516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.3445931516
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.2515262726
Short name T939
Test name
Test status
Simulation time 4237184778 ps
CPU time 17.89 seconds
Started Aug 05 04:51:40 PM PDT 24
Finished Aug 05 04:51:58 PM PDT 24
Peak memory 234488 kb
Host smart-edfdd5de-899f-40df-b9f2-0defcbfedd40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515262726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.2515262726
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_intercept.1471191981
Short name T906
Test name
Test status
Simulation time 2168209800 ps
CPU time 6.68 seconds
Started Aug 05 04:51:42 PM PDT 24
Finished Aug 05 04:51:49 PM PDT 24
Peak memory 233416 kb
Host smart-68a5cf59-1663-4005-844a-9df127e1e2cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471191981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.1471191981
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.233530719
Short name T548
Test name
Test status
Simulation time 527503747 ps
CPU time 6.42 seconds
Started Aug 05 04:51:44 PM PDT 24
Finished Aug 05 04:51:51 PM PDT 24
Peak memory 233452 kb
Host smart-c2d9e300-dd0c-4ea9-80cf-6d5cb516be71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233530719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.233530719
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.989076404
Short name T136
Test name
Test status
Simulation time 17389596502 ps
CPU time 11.76 seconds
Started Aug 05 04:51:27 PM PDT 24
Finished Aug 05 04:51:39 PM PDT 24
Peak memory 233432 kb
Host smart-3107b7cd-0264-40f3-a5c0-11e00de5dc9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989076404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swap
.989076404
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.3742473399
Short name T674
Test name
Test status
Simulation time 83360635432 ps
CPU time 19.51 seconds
Started Aug 05 04:51:34 PM PDT 24
Finished Aug 05 04:51:53 PM PDT 24
Peak memory 241204 kb
Host smart-fc84b5b6-dc6d-43c4-b658-7302fb9be1d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742473399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.3742473399
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.3731509676
Short name T158
Test name
Test status
Simulation time 5803023072 ps
CPU time 17.9 seconds
Started Aug 05 04:51:32 PM PDT 24
Finished Aug 05 04:51:50 PM PDT 24
Peak memory 220616 kb
Host smart-e7ced752-15c9-4682-bc3d-b20b8055d188
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3731509676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.3731509676
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.1913453125
Short name T996
Test name
Test status
Simulation time 106717448522 ps
CPU time 461.97 seconds
Started Aug 05 04:51:42 PM PDT 24
Finished Aug 05 04:59:25 PM PDT 24
Peak memory 265532 kb
Host smart-fcc6a725-83e9-4b54-8201-a02d75b692f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913453125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.1913453125
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.1153139330
Short name T1012
Test name
Test status
Simulation time 1825866128 ps
CPU time 18.74 seconds
Started Aug 05 04:51:35 PM PDT 24
Finished Aug 05 04:51:54 PM PDT 24
Peak memory 217012 kb
Host smart-b1be28df-bd45-4336-ba7b-67dfeb7921fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153139330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.1153139330
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.3840824786
Short name T647
Test name
Test status
Simulation time 710216093 ps
CPU time 3.39 seconds
Started Aug 05 04:51:24 PM PDT 24
Finished Aug 05 04:51:28 PM PDT 24
Peak memory 216816 kb
Host smart-1f4f6259-0366-4041-bfde-24eac463573f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840824786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.3840824786
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.4239639557
Short name T767
Test name
Test status
Simulation time 79750131 ps
CPU time 1.53 seconds
Started Aug 05 04:51:34 PM PDT 24
Finished Aug 05 04:51:35 PM PDT 24
Peak memory 216656 kb
Host smart-e2037fcf-1f8c-4cc9-b1b8-ee2eaac35415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239639557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.4239639557
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.3825392944
Short name T482
Test name
Test status
Simulation time 123496459 ps
CPU time 0.89 seconds
Started Aug 05 04:51:28 PM PDT 24
Finished Aug 05 04:51:29 PM PDT 24
Peak memory 206976 kb
Host smart-177ffcaa-78ca-4927-9b8c-8aa60f89d1c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825392944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.3825392944
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.3450888073
Short name T423
Test name
Test status
Simulation time 37306324749 ps
CPU time 29.92 seconds
Started Aug 05 04:51:44 PM PDT 24
Finished Aug 05 04:52:15 PM PDT 24
Peak memory 225220 kb
Host smart-65f49edd-a405-4147-8eac-bfe684edb26c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450888073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.3450888073
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.1087364499
Short name T609
Test name
Test status
Simulation time 75039789 ps
CPU time 0.73 seconds
Started Aug 05 04:51:33 PM PDT 24
Finished Aug 05 04:51:34 PM PDT 24
Peak memory 205792 kb
Host smart-75fd494b-0b88-4364-b5f7-b50439b4d96b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087364499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
1087364499
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.193047547
Short name T649
Test name
Test status
Simulation time 724660220 ps
CPU time 9.17 seconds
Started Aug 05 04:51:35 PM PDT 24
Finished Aug 05 04:51:45 PM PDT 24
Peak memory 233344 kb
Host smart-5df329f7-d1ff-4781-b9f0-665251b8d3d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193047547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.193047547
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.736146898
Short name T581
Test name
Test status
Simulation time 54380977 ps
CPU time 0.82 seconds
Started Aug 05 04:51:41 PM PDT 24
Finished Aug 05 04:51:43 PM PDT 24
Peak memory 206964 kb
Host smart-d5061010-45e4-423e-af16-81628e893428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736146898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.736146898
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.3690697590
Short name T235
Test name
Test status
Simulation time 12321360527 ps
CPU time 79.12 seconds
Started Aug 05 04:51:33 PM PDT 24
Finished Aug 05 04:52:52 PM PDT 24
Peak memory 249808 kb
Host smart-468c125d-bb70-4248-b866-f3637d5d4cb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690697590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.3690697590
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.2708164660
Short name T144
Test name
Test status
Simulation time 4448032259 ps
CPU time 87.19 seconds
Started Aug 05 04:51:42 PM PDT 24
Finished Aug 05 04:53:10 PM PDT 24
Peak memory 261056 kb
Host smart-9d5d44d7-6fc0-4c7d-b07e-f0914f9da072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708164660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.2708164660
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.159953689
Short name T843
Test name
Test status
Simulation time 4437156436 ps
CPU time 57.99 seconds
Started Aug 05 04:51:45 PM PDT 24
Finished Aug 05 04:52:43 PM PDT 24
Peak memory 252168 kb
Host smart-a5daad79-05cc-4f1a-bfb0-51235f173368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159953689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idle
.159953689
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.2062565663
Short name T319
Test name
Test status
Simulation time 404847485 ps
CPU time 5.44 seconds
Started Aug 05 04:51:42 PM PDT 24
Finished Aug 05 04:51:47 PM PDT 24
Peak memory 225128 kb
Host smart-a7642c35-eee2-441b-b501-2d5f6f0c49e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062565663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.2062565663
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.2725584850
Short name T422
Test name
Test status
Simulation time 210423252664 ps
CPU time 128.17 seconds
Started Aug 05 04:51:45 PM PDT 24
Finished Aug 05 04:53:54 PM PDT 24
Peak memory 253948 kb
Host smart-96e5f42b-4486-415c-9071-734ad50bba91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725584850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmd
s.2725584850
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_intercept.294104125
Short name T787
Test name
Test status
Simulation time 773299353 ps
CPU time 6.69 seconds
Started Aug 05 04:51:30 PM PDT 24
Finished Aug 05 04:51:37 PM PDT 24
Peak memory 233304 kb
Host smart-47065765-72f2-4957-90b8-5ec199e1e2c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294104125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.294104125
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.3759450721
Short name T746
Test name
Test status
Simulation time 570350451 ps
CPU time 12.15 seconds
Started Aug 05 04:51:33 PM PDT 24
Finished Aug 05 04:51:45 PM PDT 24
Peak memory 250440 kb
Host smart-01a4cd55-3281-4ddd-a9c4-a8d85c25c669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759450721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.3759450721
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.3712422377
Short name T402
Test name
Test status
Simulation time 3134357234 ps
CPU time 6.38 seconds
Started Aug 05 04:51:41 PM PDT 24
Finished Aug 05 04:51:48 PM PDT 24
Peak memory 233412 kb
Host smart-da05949a-557b-47a6-b695-48f4658ad420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712422377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.3712422377
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.816614281
Short name T860
Test name
Test status
Simulation time 1433819017 ps
CPU time 4.19 seconds
Started Aug 05 04:51:41 PM PDT 24
Finished Aug 05 04:51:46 PM PDT 24
Peak memory 227908 kb
Host smart-210f715d-1a4a-4f4e-95b3-6c57893bed99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816614281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.816614281
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.573558131
Short name T768
Test name
Test status
Simulation time 293855651 ps
CPU time 4.04 seconds
Started Aug 05 04:51:44 PM PDT 24
Finished Aug 05 04:51:48 PM PDT 24
Peak memory 220248 kb
Host smart-ff029225-b3bd-4276-bcc7-a8d4c9d1c95f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=573558131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dire
ct.573558131
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.2094595995
Short name T286
Test name
Test status
Simulation time 13964048188 ps
CPU time 50.73 seconds
Started Aug 05 04:51:31 PM PDT 24
Finished Aug 05 04:52:21 PM PDT 24
Peak memory 252736 kb
Host smart-ff5cc0d1-2f3e-49e9-b114-c9e5073213f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094595995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.2094595995
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.704953847
Short name T52
Test name
Test status
Simulation time 3833094553 ps
CPU time 21.25 seconds
Started Aug 05 04:51:35 PM PDT 24
Finished Aug 05 04:51:56 PM PDT 24
Peak memory 217096 kb
Host smart-e2d3f752-b112-4622-9109-d933a713c1d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704953847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.704953847
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.2189235595
Short name T478
Test name
Test status
Simulation time 1586962951 ps
CPU time 6.67 seconds
Started Aug 05 04:51:32 PM PDT 24
Finished Aug 05 04:51:39 PM PDT 24
Peak memory 216776 kb
Host smart-c16574c5-1191-4646-ae77-9b7edb051f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189235595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.2189235595
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.483271425
Short name T432
Test name
Test status
Simulation time 538827887 ps
CPU time 3.57 seconds
Started Aug 05 04:51:41 PM PDT 24
Finished Aug 05 04:51:45 PM PDT 24
Peak memory 216928 kb
Host smart-0f0e7ae5-3650-434b-91ea-bf597a575dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483271425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.483271425
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.1963350248
Short name T457
Test name
Test status
Simulation time 191197211 ps
CPU time 0.94 seconds
Started Aug 05 04:51:42 PM PDT 24
Finished Aug 05 04:51:44 PM PDT 24
Peak memory 206504 kb
Host smart-62019855-056a-484f-8e32-ea621d28b853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963350248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.1963350248
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.992826788
Short name T259
Test name
Test status
Simulation time 3744362090 ps
CPU time 7.52 seconds
Started Aug 05 04:51:45 PM PDT 24
Finished Aug 05 04:51:53 PM PDT 24
Peak memory 233420 kb
Host smart-2a274bce-e01e-429f-bb12-264a75d49992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992826788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.992826788
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.734888332
Short name T412
Test name
Test status
Simulation time 123344090 ps
CPU time 0.77 seconds
Started Aug 05 04:51:45 PM PDT 24
Finished Aug 05 04:51:46 PM PDT 24
Peak memory 205868 kb
Host smart-1bd87e6d-8872-45f8-9ffc-dca591f093ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734888332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.734888332
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.955199082
Short name T967
Test name
Test status
Simulation time 531673650 ps
CPU time 5.03 seconds
Started Aug 05 04:51:42 PM PDT 24
Finished Aug 05 04:51:47 PM PDT 24
Peak memory 225108 kb
Host smart-552ab56c-928a-4ea9-9755-7b77ba1c5eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955199082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.955199082
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.1660913987
Short name T771
Test name
Test status
Simulation time 54288448 ps
CPU time 0.78 seconds
Started Aug 05 04:51:40 PM PDT 24
Finished Aug 05 04:51:41 PM PDT 24
Peak memory 206868 kb
Host smart-2a0098b0-0380-434a-a995-933131f46016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660913987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.1660913987
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.2339345957
Short name T479
Test name
Test status
Simulation time 30738293 ps
CPU time 0.76 seconds
Started Aug 05 04:51:41 PM PDT 24
Finished Aug 05 04:51:42 PM PDT 24
Peak memory 216368 kb
Host smart-08d826c1-2829-4617-839e-2d710e20aa9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339345957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.2339345957
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.2077656843
Short name T1005
Test name
Test status
Simulation time 35398902505 ps
CPU time 308.79 seconds
Started Aug 05 04:51:39 PM PDT 24
Finished Aug 05 04:56:48 PM PDT 24
Peak memory 256132 kb
Host smart-9959ffbf-a1f4-44dc-bff9-a6eba0874686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077656843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.2077656843
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.4076156956
Short name T442
Test name
Test status
Simulation time 6068333021 ps
CPU time 14.47 seconds
Started Aug 05 04:51:44 PM PDT 24
Finished Aug 05 04:51:58 PM PDT 24
Peak memory 242636 kb
Host smart-01394732-de01-4a45-b6d8-b8314ac804f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076156956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.4076156956
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.1016195671
Short name T300
Test name
Test status
Simulation time 85216956050 ps
CPU time 225.2 seconds
Started Aug 05 04:51:43 PM PDT 24
Finished Aug 05 04:55:28 PM PDT 24
Peak memory 264568 kb
Host smart-0f749237-7571-4020-8dde-23384dd146db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016195671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmd
s.1016195671
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_intercept.705817716
Short name T48
Test name
Test status
Simulation time 731721005 ps
CPU time 5.84 seconds
Started Aug 05 04:51:40 PM PDT 24
Finished Aug 05 04:51:46 PM PDT 24
Peak memory 233372 kb
Host smart-a42650b2-2048-4df2-bd8e-f9581fa914cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705817716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.705817716
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.733460462
Short name T634
Test name
Test status
Simulation time 10268384952 ps
CPU time 87.81 seconds
Started Aug 05 04:51:37 PM PDT 24
Finished Aug 05 04:53:05 PM PDT 24
Peak memory 250264 kb
Host smart-e80a054c-c0f2-42c1-ae5e-c99f0c6407f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733460462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.733460462
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.2669175564
Short name T8
Test name
Test status
Simulation time 5916385992 ps
CPU time 17.26 seconds
Started Aug 05 04:51:39 PM PDT 24
Finished Aug 05 04:51:56 PM PDT 24
Peak memory 233420 kb
Host smart-6f870896-ceec-40c8-b138-917e2cd03548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669175564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.2669175564
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.1458950362
Short name T518
Test name
Test status
Simulation time 2498118545 ps
CPU time 5.37 seconds
Started Aug 05 04:51:43 PM PDT 24
Finished Aug 05 04:51:48 PM PDT 24
Peak memory 225232 kb
Host smart-72a50b1f-4df3-4bee-9473-776b932d736b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458950362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.1458950362
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.3034694716
Short name T638
Test name
Test status
Simulation time 752311980 ps
CPU time 4.84 seconds
Started Aug 05 04:51:44 PM PDT 24
Finished Aug 05 04:51:49 PM PDT 24
Peak memory 222936 kb
Host smart-41fbca23-3b7e-4957-8626-f6c25a6a91b0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3034694716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.3034694716
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.197078907
Short name T163
Test name
Test status
Simulation time 253467119 ps
CPU time 1.2 seconds
Started Aug 05 04:51:46 PM PDT 24
Finished Aug 05 04:51:47 PM PDT 24
Peak memory 207608 kb
Host smart-a83ad5a9-0786-4e97-b08f-c7faf98f1785
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197078907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stres
s_all.197078907
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.3690739387
Short name T62
Test name
Test status
Simulation time 995303836 ps
CPU time 6.82 seconds
Started Aug 05 04:51:44 PM PDT 24
Finished Aug 05 04:51:51 PM PDT 24
Peak memory 217328 kb
Host smart-2c4174ee-429f-4d0f-b0ab-0f713e2d097c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690739387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.3690739387
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.2003041825
Short name T468
Test name
Test status
Simulation time 1711020276 ps
CPU time 4.27 seconds
Started Aug 05 04:51:26 PM PDT 24
Finished Aug 05 04:51:30 PM PDT 24
Peak memory 216804 kb
Host smart-4df2d9c4-919a-477b-b316-d2f815bdfeeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003041825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.2003041825
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.1487965722
Short name T175
Test name
Test status
Simulation time 917222560 ps
CPU time 5.75 seconds
Started Aug 05 04:51:28 PM PDT 24
Finished Aug 05 04:51:34 PM PDT 24
Peak memory 217072 kb
Host smart-c4d10301-4d63-4819-bf2e-4bd540f2b922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487965722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.1487965722
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.3871421903
Short name T409
Test name
Test status
Simulation time 442396460 ps
CPU time 0.9 seconds
Started Aug 05 04:51:44 PM PDT 24
Finished Aug 05 04:51:46 PM PDT 24
Peak memory 207428 kb
Host smart-45b7682b-ad44-4734-9fcc-d3798f0bfd93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871421903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.3871421903
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.4017354675
Short name T616
Test name
Test status
Simulation time 398796520 ps
CPU time 4.51 seconds
Started Aug 05 04:51:41 PM PDT 24
Finished Aug 05 04:51:46 PM PDT 24
Peak memory 233332 kb
Host smart-fbf7628d-9d5e-4eb0-8657-c70c9546a47e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017354675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.4017354675
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.787852459
Short name T664
Test name
Test status
Simulation time 18653081 ps
CPU time 0.72 seconds
Started Aug 05 04:51:42 PM PDT 24
Finished Aug 05 04:51:43 PM PDT 24
Peak memory 205196 kb
Host smart-ef785ce9-62d5-4467-9cf5-20a48b3271c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787852459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.787852459
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.1280614475
Short name T599
Test name
Test status
Simulation time 781177041 ps
CPU time 5.94 seconds
Started Aug 05 04:51:41 PM PDT 24
Finished Aug 05 04:51:48 PM PDT 24
Peak memory 225172 kb
Host smart-363702b9-7179-4ec5-9041-d00f8b2a7433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280614475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.1280614475
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.3718135786
Short name T376
Test name
Test status
Simulation time 15841011 ps
CPU time 0.74 seconds
Started Aug 05 04:51:44 PM PDT 24
Finished Aug 05 04:51:45 PM PDT 24
Peak memory 205932 kb
Host smart-982cefc3-cafa-4f09-a598-db33893da898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718135786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.3718135786
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.2530179772
Short name T288
Test name
Test status
Simulation time 32875191417 ps
CPU time 240.49 seconds
Started Aug 05 04:51:28 PM PDT 24
Finished Aug 05 04:55:29 PM PDT 24
Peak memory 257984 kb
Host smart-127bca61-59ba-45b2-b878-303d3f4a6eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530179772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.2530179772
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.3672011692
Short name T533
Test name
Test status
Simulation time 40383298494 ps
CPU time 261.81 seconds
Started Aug 05 04:51:31 PM PDT 24
Finished Aug 05 04:55:53 PM PDT 24
Peak memory 250044 kb
Host smart-d7296b4d-df09-48b6-be49-ee272a301242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672011692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.3672011692
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.3376599798
Short name T295
Test name
Test status
Simulation time 144787776612 ps
CPU time 356.55 seconds
Started Aug 05 04:51:42 PM PDT 24
Finished Aug 05 04:57:38 PM PDT 24
Peak memory 253584 kb
Host smart-3f377bee-7e86-4e6d-bb56-8b2233ee68dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376599798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.3376599798
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.586631695
Short name T544
Test name
Test status
Simulation time 6235950715 ps
CPU time 7.61 seconds
Started Aug 05 04:51:38 PM PDT 24
Finished Aug 05 04:51:46 PM PDT 24
Peak memory 237464 kb
Host smart-2028f300-0c8a-44e2-8680-e17a42bcf23d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586631695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.586631695
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.986932285
Short name T219
Test name
Test status
Simulation time 33169517249 ps
CPU time 166.34 seconds
Started Aug 05 04:51:38 PM PDT 24
Finished Aug 05 04:54:24 PM PDT 24
Peak memory 252660 kb
Host smart-1fe28958-03f9-4449-b9aa-9621d0441b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986932285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmds
.986932285
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/47.spi_device_intercept.628445854
Short name T608
Test name
Test status
Simulation time 32160329 ps
CPU time 2.53 seconds
Started Aug 05 04:51:42 PM PDT 24
Finished Aug 05 04:51:44 PM PDT 24
Peak memory 232992 kb
Host smart-b963e5de-dc37-48f2-8755-5cdf864bddc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628445854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.628445854
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.3162004881
Short name T227
Test name
Test status
Simulation time 330080930 ps
CPU time 4.84 seconds
Started Aug 05 04:51:46 PM PDT 24
Finished Aug 05 04:51:51 PM PDT 24
Peak memory 233408 kb
Host smart-5aa31dc7-8a60-4433-a53c-40f1a11ebea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162004881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.3162004881
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.3437292958
Short name T667
Test name
Test status
Simulation time 5249666938 ps
CPU time 13.56 seconds
Started Aug 05 04:51:42 PM PDT 24
Finished Aug 05 04:51:56 PM PDT 24
Peak memory 233420 kb
Host smart-c9fa5041-2f05-479b-9e9c-9eab9e56f479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437292958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.3437292958
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.2161991713
Short name T901
Test name
Test status
Simulation time 3905485968 ps
CPU time 7.06 seconds
Started Aug 05 04:51:43 PM PDT 24
Finished Aug 05 04:51:50 PM PDT 24
Peak memory 233380 kb
Host smart-80b13dc3-bef1-475f-bd97-7f0ba37d843b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161991713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.2161991713
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.136186071
Short name T503
Test name
Test status
Simulation time 1416203446 ps
CPU time 7.4 seconds
Started Aug 05 04:51:33 PM PDT 24
Finished Aug 05 04:51:40 PM PDT 24
Peak memory 222504 kb
Host smart-da8f898e-b5df-423a-b050-f0be6c3ad0dd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=136186071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dire
ct.136186071
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.1497197407
Short name T63
Test name
Test status
Simulation time 122627708 ps
CPU time 1.14 seconds
Started Aug 05 04:51:43 PM PDT 24
Finished Aug 05 04:51:44 PM PDT 24
Peak memory 207460 kb
Host smart-b88e8cd6-9587-4059-8fc5-9ed9b28f20f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497197407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.1497197407
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.1399685295
Short name T799
Test name
Test status
Simulation time 1879368023 ps
CPU time 5.6 seconds
Started Aug 05 04:51:33 PM PDT 24
Finished Aug 05 04:51:38 PM PDT 24
Peak memory 217144 kb
Host smart-6bb2109b-cf13-45ba-be69-49c23174949f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399685295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.1399685295
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.4035900404
Short name T401
Test name
Test status
Simulation time 22597577023 ps
CPU time 20.27 seconds
Started Aug 05 04:51:37 PM PDT 24
Finished Aug 05 04:51:58 PM PDT 24
Peak memory 217212 kb
Host smart-d1d6099c-0183-46be-8e2c-1fbfbe74d053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035900404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.4035900404
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.3319438772
Short name T907
Test name
Test status
Simulation time 67937719 ps
CPU time 1.15 seconds
Started Aug 05 04:51:40 PM PDT 24
Finished Aug 05 04:51:41 PM PDT 24
Peak memory 216900 kb
Host smart-4169c284-978d-462f-9512-a2f2376daf31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319438772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.3319438772
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.1212061257
Short name T410
Test name
Test status
Simulation time 44157314 ps
CPU time 0.75 seconds
Started Aug 05 04:51:43 PM PDT 24
Finished Aug 05 04:51:44 PM PDT 24
Peak memory 206532 kb
Host smart-797bc784-ed9c-4e55-8f1b-5347358520f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212061257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.1212061257
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.4096396743
Short name T511
Test name
Test status
Simulation time 5442676072 ps
CPU time 10.74 seconds
Started Aug 05 04:51:40 PM PDT 24
Finished Aug 05 04:51:51 PM PDT 24
Peak memory 233412 kb
Host smart-c580f478-d853-4175-a5b9-7fd76cf48d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096396743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.4096396743
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.1690017935
Short name T711
Test name
Test status
Simulation time 13558644 ps
CPU time 0.72 seconds
Started Aug 05 04:51:47 PM PDT 24
Finished Aug 05 04:51:48 PM PDT 24
Peak memory 205220 kb
Host smart-7bebc9f5-c9cb-4100-9931-6c97d0d4f744
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690017935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
1690017935
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.1070999971
Short name T1007
Test name
Test status
Simulation time 505616514 ps
CPU time 2.58 seconds
Started Aug 05 04:51:46 PM PDT 24
Finished Aug 05 04:51:48 PM PDT 24
Peak memory 225072 kb
Host smart-d16d91cd-84e5-4e8d-b3fc-762367d0859b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070999971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.1070999971
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.3113583072
Short name T859
Test name
Test status
Simulation time 15191836 ps
CPU time 0.83 seconds
Started Aug 05 04:51:50 PM PDT 24
Finished Aug 05 04:51:52 PM PDT 24
Peak memory 206948 kb
Host smart-aead69eb-096a-4130-9f74-7cfd898880a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113583072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.3113583072
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.2724957488
Short name T177
Test name
Test status
Simulation time 24214141478 ps
CPU time 101.9 seconds
Started Aug 05 04:51:54 PM PDT 24
Finished Aug 05 04:53:36 PM PDT 24
Peak memory 265852 kb
Host smart-f6f4b635-f990-4e21-914f-ba698338d50b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724957488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.2724957488
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.1442192454
Short name T796
Test name
Test status
Simulation time 7683302338 ps
CPU time 120.8 seconds
Started Aug 05 04:51:40 PM PDT 24
Finished Aug 05 04:53:41 PM PDT 24
Peak memory 263544 kb
Host smart-803ea507-5965-4b57-b7f2-63cf004a5be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442192454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.1442192454
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.275661330
Short name T633
Test name
Test status
Simulation time 13555232513 ps
CPU time 37.95 seconds
Started Aug 05 04:51:51 PM PDT 24
Finished Aug 05 04:52:29 PM PDT 24
Peak memory 233464 kb
Host smart-26f04e39-d75c-448b-8d9b-d083b1a71234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275661330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idle
.275661330
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.1143087955
Short name T135
Test name
Test status
Simulation time 3005810764 ps
CPU time 45.92 seconds
Started Aug 05 04:51:53 PM PDT 24
Finished Aug 05 04:52:39 PM PDT 24
Peak memory 233364 kb
Host smart-ffec5a4c-b558-4570-a99c-810acb06b06a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143087955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.1143087955
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.2428207422
Short name T369
Test name
Test status
Simulation time 76754950 ps
CPU time 0.81 seconds
Started Aug 05 04:51:45 PM PDT 24
Finished Aug 05 04:51:46 PM PDT 24
Peak memory 216592 kb
Host smart-5e10be5a-f30f-480c-b0eb-7b459c2f6c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428207422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmd
s.2428207422
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/48.spi_device_intercept.1356401653
Short name T207
Test name
Test status
Simulation time 658483386 ps
CPU time 7.94 seconds
Started Aug 05 04:51:51 PM PDT 24
Finished Aug 05 04:51:59 PM PDT 24
Peak memory 225120 kb
Host smart-8a068401-b4e6-4d0f-a600-2de9deac98b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356401653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.1356401653
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.1574520470
Short name T788
Test name
Test status
Simulation time 3852800223 ps
CPU time 9.97 seconds
Started Aug 05 04:51:37 PM PDT 24
Finished Aug 05 04:51:47 PM PDT 24
Peak memory 233548 kb
Host smart-f03cd62f-c393-41a2-a70e-d80071074b27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574520470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.1574520470
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.754349991
Short name T264
Test name
Test status
Simulation time 32898266082 ps
CPU time 24.79 seconds
Started Aug 05 04:51:45 PM PDT 24
Finished Aug 05 04:52:10 PM PDT 24
Peak memory 233392 kb
Host smart-83eb12cb-a516-4672-b961-b4cef5ecf3d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754349991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swap
.754349991
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.980251235
Short name T663
Test name
Test status
Simulation time 7778952417 ps
CPU time 23.43 seconds
Started Aug 05 04:51:53 PM PDT 24
Finished Aug 05 04:52:17 PM PDT 24
Peak memory 242556 kb
Host smart-aa16a2a3-4725-4ba2-a094-b6c6e044ef95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980251235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.980251235
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.3505680664
Short name T817
Test name
Test status
Simulation time 7141831525 ps
CPU time 5.29 seconds
Started Aug 05 04:51:41 PM PDT 24
Finished Aug 05 04:51:46 PM PDT 24
Peak memory 221388 kb
Host smart-82fc0302-4580-4730-90f7-419266d780fe
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3505680664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.3505680664
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.2545036319
Short name T808
Test name
Test status
Simulation time 147252527239 ps
CPU time 311.92 seconds
Started Aug 05 04:51:51 PM PDT 24
Finished Aug 05 04:57:03 PM PDT 24
Peak memory 258040 kb
Host smart-a42e7c21-2b87-4d00-81c5-b1e3afecad76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545036319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.2545036319
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.1860916899
Short name T336
Test name
Test status
Simulation time 3954222608 ps
CPU time 29.54 seconds
Started Aug 05 04:51:44 PM PDT 24
Finished Aug 05 04:52:14 PM PDT 24
Peak memory 217044 kb
Host smart-5726b776-5840-455e-80c3-5e661e83af50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860916899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.1860916899
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.3278963488
Short name T781
Test name
Test status
Simulation time 1399043293 ps
CPU time 5.24 seconds
Started Aug 05 04:51:45 PM PDT 24
Finished Aug 05 04:51:51 PM PDT 24
Peak memory 216880 kb
Host smart-ddcee8f9-b482-4792-a52e-4f6278551f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278963488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.3278963488
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.2879863345
Short name T661
Test name
Test status
Simulation time 17214701 ps
CPU time 0.76 seconds
Started Aug 05 04:51:50 PM PDT 24
Finished Aug 05 04:51:52 PM PDT 24
Peak memory 206504 kb
Host smart-0b0c9580-0ce9-4e74-aef6-225205f870b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879863345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.2879863345
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.968326675
Short name T727
Test name
Test status
Simulation time 29099359 ps
CPU time 0.68 seconds
Started Aug 05 04:51:44 PM PDT 24
Finished Aug 05 04:51:45 PM PDT 24
Peak memory 206492 kb
Host smart-9814c66b-edea-48b7-b0de-93bc4e6f0ec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968326675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.968326675
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.2464853769
Short name T601
Test name
Test status
Simulation time 174507819 ps
CPU time 2.27 seconds
Started Aug 05 04:51:46 PM PDT 24
Finished Aug 05 04:51:48 PM PDT 24
Peak memory 225052 kb
Host smart-c274de19-8a7a-4acd-aa07-862a562489bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464853769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.2464853769
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.2528691681
Short name T682
Test name
Test status
Simulation time 30609686 ps
CPU time 0.72 seconds
Started Aug 05 04:51:44 PM PDT 24
Finished Aug 05 04:51:45 PM PDT 24
Peak memory 206120 kb
Host smart-da3c9383-93bc-4ed0-ab18-a408d8408d06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528691681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
2528691681
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.2694119914
Short name T830
Test name
Test status
Simulation time 110637556 ps
CPU time 3.57 seconds
Started Aug 05 04:51:44 PM PDT 24
Finished Aug 05 04:51:48 PM PDT 24
Peak memory 233264 kb
Host smart-c3ae0a95-a85f-4196-b0ce-de8d984d60fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694119914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.2694119914
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.4038877566
Short name T979
Test name
Test status
Simulation time 225155084 ps
CPU time 0.78 seconds
Started Aug 05 04:51:50 PM PDT 24
Finished Aug 05 04:51:51 PM PDT 24
Peak memory 207244 kb
Host smart-87aaa275-25ba-42ca-8d36-878e2cdb1c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038877566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.4038877566
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.2834527128
Short name T241
Test name
Test status
Simulation time 244108596796 ps
CPU time 306.9 seconds
Started Aug 05 04:51:41 PM PDT 24
Finished Aug 05 04:56:49 PM PDT 24
Peak memory 263436 kb
Host smart-743dfbf1-36fb-432a-ad3e-53bc1214e623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834527128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.2834527128
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.526412244
Short name T168
Test name
Test status
Simulation time 10639135181 ps
CPU time 65.23 seconds
Started Aug 05 04:51:45 PM PDT 24
Finished Aug 05 04:52:50 PM PDT 24
Peak memory 233384 kb
Host smart-2123885b-7540-4a81-8284-31689a4c2cc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526412244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.526412244
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.2871460623
Short name T913
Test name
Test status
Simulation time 121919461495 ps
CPU time 291.34 seconds
Started Aug 05 04:51:41 PM PDT 24
Finished Aug 05 04:56:32 PM PDT 24
Peak memory 250052 kb
Host smart-7c930b91-6fb9-49a1-8fb0-f75c3ad0ae03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871460623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.2871460623
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.2273884481
Short name T555
Test name
Test status
Simulation time 8681763866 ps
CPU time 19.78 seconds
Started Aug 05 04:51:48 PM PDT 24
Finished Aug 05 04:52:08 PM PDT 24
Peak memory 225212 kb
Host smart-e5d798b0-0cde-435b-bfa6-5749fc7912ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273884481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.2273884481
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.2417683448
Short name T724
Test name
Test status
Simulation time 16209511089 ps
CPU time 46.59 seconds
Started Aug 05 04:51:44 PM PDT 24
Finished Aug 05 04:52:31 PM PDT 24
Peak memory 257128 kb
Host smart-f4f52170-6864-4ec4-8a85-19eec7a12a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417683448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmd
s.2417683448
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/49.spi_device_intercept.3908635521
Short name T210
Test name
Test status
Simulation time 272709456 ps
CPU time 5.08 seconds
Started Aug 05 04:51:43 PM PDT 24
Finished Aug 05 04:51:48 PM PDT 24
Peak memory 221352 kb
Host smart-2069afab-b157-4127-b12b-3b389bc12005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908635521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.3908635521
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.3391067232
Short name T785
Test name
Test status
Simulation time 12669968101 ps
CPU time 78.36 seconds
Started Aug 05 04:51:46 PM PDT 24
Finished Aug 05 04:53:05 PM PDT 24
Peak memory 230832 kb
Host smart-b1eb84ca-91e0-4203-80f5-06b64af1ef40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391067232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.3391067232
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.1697346738
Short name T266
Test name
Test status
Simulation time 947953680 ps
CPU time 2.66 seconds
Started Aug 05 04:51:51 PM PDT 24
Finished Aug 05 04:51:54 PM PDT 24
Peak memory 233348 kb
Host smart-4ec886c0-385a-45d9-becd-c20ba0920345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697346738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.1697346738
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.2070819967
Short name T895
Test name
Test status
Simulation time 3940947183 ps
CPU time 12.45 seconds
Started Aug 05 04:51:46 PM PDT 24
Finished Aug 05 04:51:59 PM PDT 24
Peak memory 225184 kb
Host smart-dcf3839e-1e80-428d-9f49-c9747575e6ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070819967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.2070819967
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.826437809
Short name T902
Test name
Test status
Simulation time 251646361 ps
CPU time 5.76 seconds
Started Aug 05 04:51:37 PM PDT 24
Finished Aug 05 04:51:43 PM PDT 24
Peak memory 220300 kb
Host smart-813729ec-48c1-447b-b945-0dfeb9e4e3b0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=826437809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dire
ct.826437809
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.2431066507
Short name T20
Test name
Test status
Simulation time 378871366 ps
CPU time 1.15 seconds
Started Aug 05 04:51:40 PM PDT 24
Finished Aug 05 04:51:41 PM PDT 24
Peak memory 207384 kb
Host smart-14d9a6dd-7782-4837-a3ec-d6a40e89a41c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431066507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.2431066507
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.3073693239
Short name T173
Test name
Test status
Simulation time 3024776977 ps
CPU time 31.44 seconds
Started Aug 05 04:51:39 PM PDT 24
Finished Aug 05 04:52:10 PM PDT 24
Peak memory 216928 kb
Host smart-34955e09-228e-441b-a4db-7debbf432bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073693239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.3073693239
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.3099863595
Short name T35
Test name
Test status
Simulation time 22634092 ps
CPU time 0.7 seconds
Started Aug 05 04:51:50 PM PDT 24
Finished Aug 05 04:51:51 PM PDT 24
Peak memory 206092 kb
Host smart-d292edbd-061c-4c5b-8f26-c7daa1df2424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099863595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.3099863595
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.3509395576
Short name T530
Test name
Test status
Simulation time 1485842746 ps
CPU time 5.28 seconds
Started Aug 05 04:51:44 PM PDT 24
Finished Aug 05 04:51:49 PM PDT 24
Peak memory 216872 kb
Host smart-59e740d5-056a-4da2-b3b3-7fdddaf42a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509395576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.3509395576
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.507997987
Short name T804
Test name
Test status
Simulation time 71577833 ps
CPU time 0.71 seconds
Started Aug 05 04:51:53 PM PDT 24
Finished Aug 05 04:51:54 PM PDT 24
Peak memory 206456 kb
Host smart-a0d94176-ecdd-419d-900e-fb78f4900365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507997987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.507997987
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.2171426305
Short name T853
Test name
Test status
Simulation time 5591473190 ps
CPU time 13.01 seconds
Started Aug 05 04:51:44 PM PDT 24
Finished Aug 05 04:51:57 PM PDT 24
Peak memory 235656 kb
Host smart-6f83ae2b-40dd-4bde-838d-c28e3dd20dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171426305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.2171426305
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.2847489003
Short name T66
Test name
Test status
Simulation time 11431334 ps
CPU time 0.73 seconds
Started Aug 05 04:49:48 PM PDT 24
Finished Aug 05 04:49:49 PM PDT 24
Peak memory 205192 kb
Host smart-c0564cd4-f308-4a34-b0f1-705b4482631c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847489003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.2
847489003
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.4225409904
Short name T689
Test name
Test status
Simulation time 2046786459 ps
CPU time 26.98 seconds
Started Aug 05 04:49:48 PM PDT 24
Finished Aug 05 04:50:15 PM PDT 24
Peak memory 225088 kb
Host smart-096728ea-4f6e-4b38-9bec-704d21c0cd97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225409904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.4225409904
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.2377884516
Short name T64
Test name
Test status
Simulation time 174961889 ps
CPU time 0.78 seconds
Started Aug 05 04:49:56 PM PDT 24
Finished Aug 05 04:49:57 PM PDT 24
Peak memory 207424 kb
Host smart-b76de448-6d49-4c07-8c8e-9242d111ca3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377884516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.2377884516
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.2329086403
Short name T834
Test name
Test status
Simulation time 60355555115 ps
CPU time 120.2 seconds
Started Aug 05 04:49:53 PM PDT 24
Finished Aug 05 04:51:54 PM PDT 24
Peak memory 250184 kb
Host smart-c03288a2-4df5-453e-ae33-5eb78349a007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329086403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.2329086403
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.809665733
Short name T40
Test name
Test status
Simulation time 255805950780 ps
CPU time 281.84 seconds
Started Aug 05 04:49:46 PM PDT 24
Finished Aug 05 04:54:28 PM PDT 24
Peak memory 255252 kb
Host smart-fdc49f1c-f9de-4bfe-b599-5c9bc99f7938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809665733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.809665733
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.5740747
Short name T346
Test name
Test status
Simulation time 673035458 ps
CPU time 3.93 seconds
Started Aug 05 04:49:57 PM PDT 24
Finished Aug 05 04:50:01 PM PDT 24
Peak memory 225112 kb
Host smart-28a2dc24-4a34-4477-bdf4-0784c6b2177b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5740747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.5740747
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.3041825823
Short name T733
Test name
Test status
Simulation time 3768364016 ps
CPU time 45.27 seconds
Started Aug 05 04:49:58 PM PDT 24
Finished Aug 05 04:50:43 PM PDT 24
Peak memory 250992 kb
Host smart-8eca580d-896a-4c4f-9414-b7188491878f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041825823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds
.3041825823
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/5.spi_device_intercept.942285680
Short name T498
Test name
Test status
Simulation time 656692722 ps
CPU time 8.62 seconds
Started Aug 05 04:49:47 PM PDT 24
Finished Aug 05 04:49:55 PM PDT 24
Peak memory 233352 kb
Host smart-2b612f5b-cc33-466e-b961-8abbf030660d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942285680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.942285680
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.1558100962
Short name T90
Test name
Test status
Simulation time 1567535065 ps
CPU time 7.27 seconds
Started Aug 05 04:50:08 PM PDT 24
Finished Aug 05 04:50:15 PM PDT 24
Peak memory 225176 kb
Host smart-b1cd65e9-dab7-4719-b545-421fe22c3b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558100962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.1558100962
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.3006814573
Short name T924
Test name
Test status
Simulation time 55538935 ps
CPU time 1.08 seconds
Started Aug 05 04:49:57 PM PDT 24
Finished Aug 05 04:49:59 PM PDT 24
Peak memory 217140 kb
Host smart-e427d9d5-afb2-46af-89d3-e69ec58dd2c0
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006814573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.spi_device_mem_parity.3006814573
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.4050930890
Short name T517
Test name
Test status
Simulation time 2779063214 ps
CPU time 6.67 seconds
Started Aug 05 04:49:44 PM PDT 24
Finished Aug 05 04:49:51 PM PDT 24
Peak memory 233716 kb
Host smart-537ab9c2-69fa-4062-b060-9b82c31cc96b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050930890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.4050930890
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.405897354
Short name T1014
Test name
Test status
Simulation time 1718035373 ps
CPU time 12.4 seconds
Started Aug 05 04:49:57 PM PDT 24
Finished Aug 05 04:50:10 PM PDT 24
Peak memory 234400 kb
Host smart-f54ab024-fc01-4ddf-9c56-792442587dd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405897354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.405897354
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.3961070116
Short name T936
Test name
Test status
Simulation time 2125633608 ps
CPU time 9.04 seconds
Started Aug 05 04:49:49 PM PDT 24
Finished Aug 05 04:49:58 PM PDT 24
Peak memory 222636 kb
Host smart-a8ebec2f-4bbf-4a18-b1e8-c7dc10485dd1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3961070116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.3961070116
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.3700533914
Short name T33
Test name
Test status
Simulation time 104735568 ps
CPU time 0.99 seconds
Started Aug 05 04:49:58 PM PDT 24
Finished Aug 05 04:49:59 PM PDT 24
Peak memory 207060 kb
Host smart-8a00b521-e42b-4d2b-ada0-1c2ed4df6223
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700533914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.3700533914
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.1248131641
Short name T59
Test name
Test status
Simulation time 3949219749 ps
CPU time 22.96 seconds
Started Aug 05 04:49:43 PM PDT 24
Finished Aug 05 04:50:06 PM PDT 24
Peak memory 217004 kb
Host smart-a7d49c4b-dd07-46c7-bee7-7a803f759df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248131641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.1248131641
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.1049141697
Short name T1004
Test name
Test status
Simulation time 509999312 ps
CPU time 3.3 seconds
Started Aug 05 04:49:57 PM PDT 24
Finished Aug 05 04:50:00 PM PDT 24
Peak memory 216868 kb
Host smart-27e5faf7-57eb-43e2-8ad3-54e51f680ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049141697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.1049141697
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.3259585418
Short name T703
Test name
Test status
Simulation time 23317860 ps
CPU time 0.94 seconds
Started Aug 05 04:49:55 PM PDT 24
Finished Aug 05 04:49:56 PM PDT 24
Peak memory 208460 kb
Host smart-82518a0f-2ad8-4706-b3f5-4bb70c26bb04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259585418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.3259585418
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.739976261
Short name T718
Test name
Test status
Simulation time 64053141 ps
CPU time 0.77 seconds
Started Aug 05 04:49:55 PM PDT 24
Finished Aug 05 04:49:56 PM PDT 24
Peak memory 206444 kb
Host smart-8c26098c-5192-478f-999b-8cea929652c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739976261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.739976261
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.4216312667
Short name T720
Test name
Test status
Simulation time 40861410801 ps
CPU time 34.31 seconds
Started Aug 05 04:50:04 PM PDT 24
Finished Aug 05 04:50:38 PM PDT 24
Peak memory 234408 kb
Host smart-e2c5b0fb-9cc1-4435-b589-27e6987009ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216312667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.4216312667
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.3583477154
Short name T862
Test name
Test status
Simulation time 31183237 ps
CPU time 0.7 seconds
Started Aug 05 04:49:46 PM PDT 24
Finished Aug 05 04:49:47 PM PDT 24
Peak memory 205780 kb
Host smart-9ac183ba-b7b1-49fa-92a8-edcfdb2deceb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583477154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.3
583477154
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.3349849243
Short name T247
Test name
Test status
Simulation time 1009729533 ps
CPU time 11.59 seconds
Started Aug 05 04:50:02 PM PDT 24
Finished Aug 05 04:50:13 PM PDT 24
Peak memory 233456 kb
Host smart-80cb171f-12fa-4b83-8005-1e5421a01b20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349849243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.3349849243
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.2221319485
Short name T169
Test name
Test status
Simulation time 59533202 ps
CPU time 0.77 seconds
Started Aug 05 04:49:48 PM PDT 24
Finished Aug 05 04:49:48 PM PDT 24
Peak memory 207256 kb
Host smart-6bf6b3bf-2b32-49b1-8ce6-36fe3e64e4d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221319485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.2221319485
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.882482093
Short name T1002
Test name
Test status
Simulation time 2020327737 ps
CPU time 15.16 seconds
Started Aug 05 04:49:57 PM PDT 24
Finished Aug 05 04:50:12 PM PDT 24
Peak memory 225172 kb
Host smart-759efde6-edf5-4424-9b1c-f5f97281c638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882482093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.882482093
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.1233746725
Short name T580
Test name
Test status
Simulation time 29466666701 ps
CPU time 274.33 seconds
Started Aug 05 04:49:47 PM PDT 24
Finished Aug 05 04:54:21 PM PDT 24
Peak memory 250860 kb
Host smart-4984a28e-227d-400b-a733-297a9f6aa55e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233746725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.1233746725
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.961094311
Short name T310
Test name
Test status
Simulation time 34443357627 ps
CPU time 128.47 seconds
Started Aug 05 04:50:00 PM PDT 24
Finished Aug 05 04:52:09 PM PDT 24
Peak memory 257268 kb
Host smart-ad78f159-d714-43ef-9639-5867f9a065b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961094311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle.
961094311
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.962307048
Short name T855
Test name
Test status
Simulation time 9207264153 ps
CPU time 28.89 seconds
Started Aug 05 04:49:59 PM PDT 24
Finished Aug 05 04:50:38 PM PDT 24
Peak memory 225212 kb
Host smart-2b45331d-c72d-4bb9-b029-60413b8058bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962307048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds.
962307048
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/6.spi_device_intercept.1167937572
Short name T212
Test name
Test status
Simulation time 736488934 ps
CPU time 6.83 seconds
Started Aug 05 04:50:06 PM PDT 24
Finished Aug 05 04:50:13 PM PDT 24
Peak memory 225096 kb
Host smart-c715ad2c-d990-45fa-b115-85962d18e236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167937572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.1167937572
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.3144865604
Short name T272
Test name
Test status
Simulation time 11261037403 ps
CPU time 90.24 seconds
Started Aug 05 04:49:47 PM PDT 24
Finished Aug 05 04:51:17 PM PDT 24
Peak memory 229392 kb
Host smart-601e0635-fa49-4a9d-ace4-dafe651b8f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144865604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.3144865604
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.344695433
Short name T543
Test name
Test status
Simulation time 265724378 ps
CPU time 1.11 seconds
Started Aug 05 04:49:45 PM PDT 24
Finished Aug 05 04:49:46 PM PDT 24
Peak memory 218392 kb
Host smart-dd86600c-c5b9-45d1-87f1-75ed776c1654
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344695433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.spi_device_mem_parity.344695433
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.267596436
Short name T839
Test name
Test status
Simulation time 950441239 ps
CPU time 4.06 seconds
Started Aug 05 04:49:58 PM PDT 24
Finished Aug 05 04:50:02 PM PDT 24
Peak memory 233372 kb
Host smart-0517b1db-21f0-4f16-8aef-36d2e43a72ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267596436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap.
267596436
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.1126443250
Short name T524
Test name
Test status
Simulation time 599020078 ps
CPU time 7.99 seconds
Started Aug 05 04:50:00 PM PDT 24
Finished Aug 05 04:50:08 PM PDT 24
Peak memory 233364 kb
Host smart-d5473fde-967e-4140-b78e-5a325743434e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126443250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.1126443250
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.3021800507
Short name T574
Test name
Test status
Simulation time 634382284 ps
CPU time 5.33 seconds
Started Aug 05 04:49:56 PM PDT 24
Finished Aug 05 04:50:01 PM PDT 24
Peak memory 223084 kb
Host smart-9d14ec6f-39ad-452f-b2c1-0759bdfee476
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3021800507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.3021800507
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.2350322785
Short name T146
Test name
Test status
Simulation time 122767380291 ps
CPU time 105.88 seconds
Started Aug 05 04:50:11 PM PDT 24
Finished Aug 05 04:51:57 PM PDT 24
Peak memory 265200 kb
Host smart-d72eb803-15ca-489f-95e5-7c10d2820fd7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350322785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.2350322785
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.1049341044
Short name T921
Test name
Test status
Simulation time 3284754883 ps
CPU time 20.45 seconds
Started Aug 05 04:49:54 PM PDT 24
Finished Aug 05 04:50:15 PM PDT 24
Peak memory 217012 kb
Host smart-f2df372f-130a-4c6d-8e95-e464ff02fb69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049341044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.1049341044
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.904256092
Short name T631
Test name
Test status
Simulation time 5826170488 ps
CPU time 13.2 seconds
Started Aug 05 04:49:57 PM PDT 24
Finished Aug 05 04:50:11 PM PDT 24
Peak memory 216956 kb
Host smart-988b73b5-5ff3-4992-82b2-2c49f6f0c822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904256092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.904256092
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.1188708554
Short name T854
Test name
Test status
Simulation time 70919814 ps
CPU time 1.28 seconds
Started Aug 05 04:50:03 PM PDT 24
Finished Aug 05 04:50:04 PM PDT 24
Peak memory 216900 kb
Host smart-cc543463-845a-4b60-8d0c-354a8a08e96e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188708554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.1188708554
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.2809851530
Short name T659
Test name
Test status
Simulation time 121528389 ps
CPU time 0.8 seconds
Started Aug 05 04:49:48 PM PDT 24
Finished Aug 05 04:49:49 PM PDT 24
Peak memory 206480 kb
Host smart-82792602-47c1-406e-ab46-e37fc9243628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809851530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.2809851530
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.2637021609
Short name T856
Test name
Test status
Simulation time 97532454289 ps
CPU time 21.79 seconds
Started Aug 05 04:50:00 PM PDT 24
Finished Aug 05 04:50:32 PM PDT 24
Peak memory 233456 kb
Host smart-2123f109-9482-4dee-a02c-5e1d098c4a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637021609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.2637021609
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.436297734
Short name T754
Test name
Test status
Simulation time 13062415 ps
CPU time 0.72 seconds
Started Aug 05 04:49:57 PM PDT 24
Finished Aug 05 04:49:57 PM PDT 24
Peak memory 205180 kb
Host smart-7bac99d7-81ba-4c7e-943a-e570c24ec846
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436297734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.436297734
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.2985435698
Short name T280
Test name
Test status
Simulation time 1537119183 ps
CPU time 8.66 seconds
Started Aug 05 04:49:56 PM PDT 24
Finished Aug 05 04:50:05 PM PDT 24
Peak memory 225032 kb
Host smart-bcc11469-e626-4e82-9172-86e6f7d66b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985435698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.2985435698
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.2872323589
Short name T773
Test name
Test status
Simulation time 35260239 ps
CPU time 0.75 seconds
Started Aug 05 04:49:44 PM PDT 24
Finished Aug 05 04:49:45 PM PDT 24
Peak memory 206228 kb
Host smart-787a2d9a-929c-4324-956f-e7102a203123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872323589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.2872323589
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.1472979669
Short name T375
Test name
Test status
Simulation time 1912780993 ps
CPU time 10.7 seconds
Started Aug 05 04:49:54 PM PDT 24
Finished Aug 05 04:50:05 PM PDT 24
Peak memory 235168 kb
Host smart-45fac13e-0408-4066-bd7d-c6b070bb7b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472979669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.1472979669
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.1852010492
Short name T309
Test name
Test status
Simulation time 9675834418 ps
CPU time 89.66 seconds
Started Aug 05 04:50:16 PM PDT 24
Finished Aug 05 04:51:46 PM PDT 24
Peak memory 249948 kb
Host smart-41a8f49f-21b9-4610-a723-7d89234b3f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852010492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.1852010492
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.3800568166
Short name T728
Test name
Test status
Simulation time 50701389671 ps
CPU time 28.37 seconds
Started Aug 05 04:49:57 PM PDT 24
Finished Aug 05 04:50:26 PM PDT 24
Peak memory 221480 kb
Host smart-779327e7-4b27-4969-995f-306dcf2f99b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800568166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.3800568166
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.1300632340
Short name T735
Test name
Test status
Simulation time 155831162 ps
CPU time 4.59 seconds
Started Aug 05 04:49:54 PM PDT 24
Finished Aug 05 04:49:59 PM PDT 24
Peak memory 225088 kb
Host smart-5a340256-f0fa-4b71-965d-ff9f0b22e12f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300632340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.1300632340
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.1683250150
Short name T919
Test name
Test status
Simulation time 85535436 ps
CPU time 0.79 seconds
Started Aug 05 04:50:35 PM PDT 24
Finished Aug 05 04:50:36 PM PDT 24
Peak memory 216348 kb
Host smart-d87aad19-dd27-47ce-a620-c1300a87b4b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683250150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds
.1683250150
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_intercept.3021624394
Short name T623
Test name
Test status
Simulation time 8791691579 ps
CPU time 18.33 seconds
Started Aug 05 04:50:00 PM PDT 24
Finished Aug 05 04:50:18 PM PDT 24
Peak memory 228168 kb
Host smart-f1157de8-a129-43fc-a963-7ea486dbce5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021624394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.3021624394
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.2562014524
Short name T948
Test name
Test status
Simulation time 30068600866 ps
CPU time 57.71 seconds
Started Aug 05 04:50:01 PM PDT 24
Finished Aug 05 04:50:59 PM PDT 24
Peak memory 250372 kb
Host smart-5854f0b8-b6e4-4f08-b408-c5780818a60a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562014524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.2562014524
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.3385509477
Short name T1023
Test name
Test status
Simulation time 59518381 ps
CPU time 1.07 seconds
Started Aug 05 04:49:57 PM PDT 24
Finished Aug 05 04:49:58 PM PDT 24
Peak memory 217140 kb
Host smart-5f5cc356-c943-4822-8fdb-4eda414fa870
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385509477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.spi_device_mem_parity.3385509477
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.2730560345
Short name T263
Test name
Test status
Simulation time 1085266631 ps
CPU time 8.94 seconds
Started Aug 05 04:50:00 PM PDT 24
Finished Aug 05 04:50:09 PM PDT 24
Peak memory 233348 kb
Host smart-48455d0d-3e9a-4e76-97ea-90d5a3275430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730560345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.2730560345
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.1748593626
Short name T975
Test name
Test status
Simulation time 101189934 ps
CPU time 2.47 seconds
Started Aug 05 04:49:59 PM PDT 24
Finished Aug 05 04:50:02 PM PDT 24
Peak memory 233008 kb
Host smart-646f36f8-1e4e-4259-a1dd-fc5f4e71f911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748593626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.1748593626
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.3410260207
Short name T25
Test name
Test status
Simulation time 6892118642 ps
CPU time 14.87 seconds
Started Aug 05 04:50:03 PM PDT 24
Finished Aug 05 04:50:18 PM PDT 24
Peak memory 220316 kb
Host smart-94767398-cc0d-485c-94f4-8cdeddcc8fff
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3410260207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.3410260207
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.2139097338
Short name T837
Test name
Test status
Simulation time 8084486361 ps
CPU time 133.92 seconds
Started Aug 05 04:50:11 PM PDT 24
Finished Aug 05 04:52:25 PM PDT 24
Peak memory 254216 kb
Host smart-2addbf87-3b70-4158-90d7-582aea677e76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139097338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.2139097338
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.755848209
Short name T927
Test name
Test status
Simulation time 3210995523 ps
CPU time 27.49 seconds
Started Aug 05 04:49:56 PM PDT 24
Finished Aug 05 04:50:24 PM PDT 24
Peak memory 217056 kb
Host smart-07308307-a5fb-47b8-ac99-6458ea6a5970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755848209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.755848209
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.2016919595
Short name T438
Test name
Test status
Simulation time 22289123920 ps
CPU time 8.69 seconds
Started Aug 05 04:50:07 PM PDT 24
Finished Aug 05 04:50:15 PM PDT 24
Peak memory 216940 kb
Host smart-5fff60cd-01d6-48e8-830e-223665a5862c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016919595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.2016919595
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.1375157449
Short name T662
Test name
Test status
Simulation time 1468794798 ps
CPU time 4.73 seconds
Started Aug 05 04:50:03 PM PDT 24
Finished Aug 05 04:50:08 PM PDT 24
Peak memory 216788 kb
Host smart-b365e54c-e475-475e-9cc6-9af89a721d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375157449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.1375157449
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.3831354184
Short name T89
Test name
Test status
Simulation time 66157385 ps
CPU time 0.85 seconds
Started Aug 05 04:50:00 PM PDT 24
Finished Aug 05 04:50:01 PM PDT 24
Peak memory 207484 kb
Host smart-50f25ece-6599-492e-82cd-06d7b8876d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831354184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.3831354184
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.3314426629
Short name T171
Test name
Test status
Simulation time 934661200 ps
CPU time 8.01 seconds
Started Aug 05 04:49:49 PM PDT 24
Finished Aug 05 04:49:57 PM PDT 24
Peak memory 240112 kb
Host smart-19fcc542-e5dc-4845-a2bc-853b926c8a3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314426629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.3314426629
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.4245719856
Short name T449
Test name
Test status
Simulation time 33988882 ps
CPU time 0.75 seconds
Started Aug 05 04:50:00 PM PDT 24
Finished Aug 05 04:50:00 PM PDT 24
Peak memory 205884 kb
Host smart-f237f7fa-cfb2-48bb-9a22-07ad9d155ba2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245719856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.4
245719856
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.785698389
Short name T514
Test name
Test status
Simulation time 465568166 ps
CPU time 5.73 seconds
Started Aug 05 04:50:05 PM PDT 24
Finished Aug 05 04:50:11 PM PDT 24
Peak memory 225128 kb
Host smart-37bb317c-0908-4488-a730-cc9eaf69c26d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785698389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.785698389
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.1664985469
Short name T552
Test name
Test status
Simulation time 16965039 ps
CPU time 0.8 seconds
Started Aug 05 04:49:46 PM PDT 24
Finished Aug 05 04:49:47 PM PDT 24
Peak memory 206892 kb
Host smart-bdd5db08-32be-4c7d-8654-3a3c7b240d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664985469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.1664985469
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.3564636948
Short name T705
Test name
Test status
Simulation time 3445745774 ps
CPU time 48.13 seconds
Started Aug 05 04:50:42 PM PDT 24
Finished Aug 05 04:51:30 PM PDT 24
Peak memory 249832 kb
Host smart-0ba4bed1-d1cf-4db2-817c-42317bad653c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564636948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.3564636948
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.918764419
Short name T291
Test name
Test status
Simulation time 7442931606 ps
CPU time 49.95 seconds
Started Aug 05 04:50:23 PM PDT 24
Finished Aug 05 04:51:13 PM PDT 24
Peak memory 255976 kb
Host smart-a01906e4-42e4-4895-b618-ec5f5c239e3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918764419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.918764419
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.1843934402
Short name T1013
Test name
Test status
Simulation time 5662203220 ps
CPU time 26.32 seconds
Started Aug 05 04:49:59 PM PDT 24
Finished Aug 05 04:50:25 PM PDT 24
Peak memory 218584 kb
Host smart-08ea5fed-eadf-4a95-840c-7da26f22ce1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843934402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.1843934402
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.1997157418
Short name T566
Test name
Test status
Simulation time 1202739965 ps
CPU time 4.5 seconds
Started Aug 05 04:50:07 PM PDT 24
Finished Aug 05 04:50:11 PM PDT 24
Peak memory 233384 kb
Host smart-58bb8c5c-ea32-4ab4-9800-3dd5cd94e4e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997157418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.1997157418
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.3396759681
Short name T202
Test name
Test status
Simulation time 107590758915 ps
CPU time 198.92 seconds
Started Aug 05 04:50:03 PM PDT 24
Finished Aug 05 04:53:22 PM PDT 24
Peak memory 252812 kb
Host smart-8eb6a2e4-b302-4636-b1b5-3324cae76a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396759681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds
.3396759681
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/8.spi_device_intercept.1744474199
Short name T271
Test name
Test status
Simulation time 1608491543 ps
CPU time 4.03 seconds
Started Aug 05 04:50:01 PM PDT 24
Finished Aug 05 04:50:05 PM PDT 24
Peak memory 225180 kb
Host smart-94506b7e-631e-4205-a54b-78bef2e38779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744474199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.1744474199
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.241502312
Short name T365
Test name
Test status
Simulation time 12820670220 ps
CPU time 54.18 seconds
Started Aug 05 04:49:53 PM PDT 24
Finished Aug 05 04:50:52 PM PDT 24
Peak memory 239784 kb
Host smart-dc05bc44-a61c-4adf-bfde-6c63fa99949c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241502312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.241502312
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.2643741351
Short name T955
Test name
Test status
Simulation time 46688046 ps
CPU time 1.01 seconds
Started Aug 05 04:49:58 PM PDT 24
Finished Aug 05 04:49:59 PM PDT 24
Peak memory 218512 kb
Host smart-1681e1da-03d8-4841-b7da-34fc31339d90
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643741351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.spi_device_mem_parity.2643741351
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.3868561812
Short name T229
Test name
Test status
Simulation time 31752218850 ps
CPU time 18.03 seconds
Started Aug 05 04:50:02 PM PDT 24
Finished Aug 05 04:50:20 PM PDT 24
Peak memory 225148 kb
Host smart-c5f71848-2174-4e6e-a08f-9b9657601851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868561812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.3868561812
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.1103243627
Short name T964
Test name
Test status
Simulation time 20154968587 ps
CPU time 16.08 seconds
Started Aug 05 04:49:57 PM PDT 24
Finished Aug 05 04:50:13 PM PDT 24
Peak memory 233416 kb
Host smart-ecd65535-3703-4ad8-bb70-5ca1f198a053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103243627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.1103243627
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.3341563869
Short name T990
Test name
Test status
Simulation time 1293143088 ps
CPU time 8.94 seconds
Started Aug 05 04:50:00 PM PDT 24
Finished Aug 05 04:50:14 PM PDT 24
Peak memory 223360 kb
Host smart-84c57579-6ac6-45a2-8f03-f4963c61b750
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3341563869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.3341563869
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.1074868752
Short name T932
Test name
Test status
Simulation time 54594858 ps
CPU time 1.05 seconds
Started Aug 05 04:49:57 PM PDT 24
Finished Aug 05 04:49:58 PM PDT 24
Peak memory 208336 kb
Host smart-c794afcd-60af-467a-bcfb-9bf34fe56874
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074868752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.1074868752
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.462487011
Short name T425
Test name
Test status
Simulation time 2512089254 ps
CPU time 14.75 seconds
Started Aug 05 04:49:56 PM PDT 24
Finished Aug 05 04:50:11 PM PDT 24
Peak memory 216908 kb
Host smart-ce95e4a9-0753-4871-a046-ced33d26b76f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462487011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.462487011
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.1165331390
Short name T842
Test name
Test status
Simulation time 716246051 ps
CPU time 1.82 seconds
Started Aug 05 04:49:52 PM PDT 24
Finished Aug 05 04:49:54 PM PDT 24
Peak memory 208424 kb
Host smart-cc462041-3531-4a8c-866a-1a966a9496ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165331390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.1165331390
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.2877358686
Short name T816
Test name
Test status
Simulation time 264373880 ps
CPU time 2.93 seconds
Started Aug 05 04:50:00 PM PDT 24
Finished Aug 05 04:50:03 PM PDT 24
Peak memory 216848 kb
Host smart-442c03f0-94fe-4aeb-95ec-7013db9d0ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877358686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.2877358686
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.380265037
Short name T576
Test name
Test status
Simulation time 105341183 ps
CPU time 0.78 seconds
Started Aug 05 04:50:06 PM PDT 24
Finished Aug 05 04:50:07 PM PDT 24
Peak memory 206432 kb
Host smart-e0ac67f1-f7a7-459f-a280-9ebf72c4d777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380265037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.380265037
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.2530970816
Short name T738
Test name
Test status
Simulation time 884801709 ps
CPU time 5.92 seconds
Started Aug 05 04:50:07 PM PDT 24
Finished Aug 05 04:50:13 PM PDT 24
Peak memory 233320 kb
Host smart-29e1bb95-7a5e-4c73-af6e-b2f0f9be8bfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530970816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.2530970816
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.405805792
Short name T67
Test name
Test status
Simulation time 32710891 ps
CPU time 0.71 seconds
Started Aug 05 04:49:53 PM PDT 24
Finished Aug 05 04:49:54 PM PDT 24
Peak memory 205800 kb
Host smart-a7766559-e7f5-43a9-9f88-97b59bc48d43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405805792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.405805792
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.1387696191
Short name T628
Test name
Test status
Simulation time 3434940224 ps
CPU time 11.47 seconds
Started Aug 05 04:50:03 PM PDT 24
Finished Aug 05 04:50:14 PM PDT 24
Peak memory 233444 kb
Host smart-eaf8b0dc-6605-4634-958b-f8947c32a74b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387696191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.1387696191
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.2102203517
Short name T867
Test name
Test status
Simulation time 47205341 ps
CPU time 0.82 seconds
Started Aug 05 04:49:56 PM PDT 24
Finished Aug 05 04:50:02 PM PDT 24
Peak memory 206952 kb
Host smart-9220af5f-bf71-4365-aec2-8a31b4008298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102203517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.2102203517
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.3293256417
Short name T1024
Test name
Test status
Simulation time 5479303840 ps
CPU time 63.07 seconds
Started Aug 05 04:50:20 PM PDT 24
Finished Aug 05 04:51:29 PM PDT 24
Peak memory 267600 kb
Host smart-30a4fff4-e200-4c94-aaf6-d478f8a2779c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293256417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.3293256417
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.2026744612
Short name T611
Test name
Test status
Simulation time 65844325494 ps
CPU time 124.36 seconds
Started Aug 05 04:49:47 PM PDT 24
Finished Aug 05 04:51:51 PM PDT 24
Peak memory 250104 kb
Host smart-3410d56b-b2a5-4a7c-8f2a-420e11bd7038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026744612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.2026744612
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.1439173611
Short name T238
Test name
Test status
Simulation time 36300775793 ps
CPU time 166.95 seconds
Started Aug 05 04:49:58 PM PDT 24
Finished Aug 05 04:52:45 PM PDT 24
Peak memory 249896 kb
Host smart-4762e0e3-0b25-4954-bca7-4f7874562a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439173611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.1439173611
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.915727544
Short name T450
Test name
Test status
Simulation time 4232672376 ps
CPU time 53.21 seconds
Started Aug 05 04:50:03 PM PDT 24
Finished Aug 05 04:50:56 PM PDT 24
Peak memory 241604 kb
Host smart-09ba082d-7874-40eb-8c5a-ec9e32bf771c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915727544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.915727544
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.3030361726
Short name T762
Test name
Test status
Simulation time 6019549915 ps
CPU time 40.2 seconds
Started Aug 05 04:49:56 PM PDT 24
Finished Aug 05 04:50:37 PM PDT 24
Peak memory 241636 kb
Host smart-42dd5db1-4f5a-4e04-9d1d-b4ef3d5cd8b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030361726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds
.3030361726
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/9.spi_device_intercept.3054686921
Short name T938
Test name
Test status
Simulation time 2633350456 ps
CPU time 5.06 seconds
Started Aug 05 04:50:00 PM PDT 24
Finished Aug 05 04:50:05 PM PDT 24
Peak memory 233460 kb
Host smart-dc2b83d1-d980-40ae-8ec0-916b98fe85ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054686921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.3054686921
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.2536245737
Short name T134
Test name
Test status
Simulation time 26784935712 ps
CPU time 56.1 seconds
Started Aug 05 04:49:51 PM PDT 24
Finished Aug 05 04:50:47 PM PDT 24
Peak memory 233472 kb
Host smart-4309e077-83ba-4003-b04c-32a8ba92845c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536245737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.2536245737
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.204469448
Short name T42
Test name
Test status
Simulation time 28393682 ps
CPU time 1 seconds
Started Aug 05 04:50:01 PM PDT 24
Finished Aug 05 04:50:02 PM PDT 24
Peak memory 217120 kb
Host smart-06873794-ad37-4321-8e32-0f17ce27c8c2
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204469448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.spi_device_mem_parity.204469448
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.2189314616
Short name T455
Test name
Test status
Simulation time 15777843616 ps
CPU time 12.13 seconds
Started Aug 05 04:49:46 PM PDT 24
Finished Aug 05 04:49:58 PM PDT 24
Peak memory 225148 kb
Host smart-2f0484ca-3b57-4810-9baf-ae641b9d4007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189314616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.2189314616
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.1093651436
Short name T775
Test name
Test status
Simulation time 5418655167 ps
CPU time 15.86 seconds
Started Aug 05 04:49:58 PM PDT 24
Finished Aug 05 04:50:14 PM PDT 24
Peak memory 233408 kb
Host smart-b6896513-9e08-4065-b448-bd83ac2d493e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093651436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.1093651436
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.732330579
Short name T435
Test name
Test status
Simulation time 685522869 ps
CPU time 4.76 seconds
Started Aug 05 04:49:58 PM PDT 24
Finished Aug 05 04:50:03 PM PDT 24
Peak memory 223260 kb
Host smart-d3a11b74-9ebc-4efc-8c65-5d4e65694c26
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=732330579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_direc
t.732330579
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.3065333848
Short name T19
Test name
Test status
Simulation time 51681847 ps
CPU time 1.03 seconds
Started Aug 05 04:50:12 PM PDT 24
Finished Aug 05 04:50:13 PM PDT 24
Peak memory 207132 kb
Host smart-6f514061-ef11-471c-8295-353b08214e7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065333848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.3065333848
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.1835285418
Short name T549
Test name
Test status
Simulation time 24428506889 ps
CPU time 33.53 seconds
Started Aug 05 04:50:12 PM PDT 24
Finished Aug 05 04:50:46 PM PDT 24
Peak memory 216952 kb
Host smart-3215e18b-3cf6-4186-b16d-1bfe43f4f5b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835285418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.1835285418
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.40213672
Short name T734
Test name
Test status
Simulation time 778258105 ps
CPU time 5.34 seconds
Started Aug 05 04:50:26 PM PDT 24
Finished Aug 05 04:50:32 PM PDT 24
Peak memory 216836 kb
Host smart-3f52d4c4-de34-48a0-bf02-fabce28d5052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40213672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.40213672
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.845502344
Short name T926
Test name
Test status
Simulation time 54244481 ps
CPU time 0.83 seconds
Started Aug 05 04:49:52 PM PDT 24
Finished Aug 05 04:49:52 PM PDT 24
Peak memory 206484 kb
Host smart-7142e295-57d8-43f7-becb-b1c857b57510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845502344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.845502344
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.3613930409
Short name T811
Test name
Test status
Simulation time 35359938 ps
CPU time 0.79 seconds
Started Aug 05 04:49:59 PM PDT 24
Finished Aug 05 04:50:00 PM PDT 24
Peak memory 206440 kb
Host smart-a65e9cb2-bcde-4ddc-b2c4-be12ca5cc0fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613930409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.3613930409
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.3428323982
Short name T119
Test name
Test status
Simulation time 65680098 ps
CPU time 2.61 seconds
Started Aug 05 04:49:58 PM PDT 24
Finished Aug 05 04:50:01 PM PDT 24
Peak memory 232884 kb
Host smart-0602d1cc-1684-423f-b63d-98e0cee37da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428323982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.3428323982
Directory /workspace/9.spi_device_upload/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%