Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2590976	1			T1	3244		T2	1265		T3	7175
all_values[1]	2590976	1			T1	3244		T2	1265		T3	7175
all_values[2]	2590976	1			T1	3244		T2	1265		T3	7175
all_values[3]	2590976	1			T1	3244		T2	1265		T3	7175
all_values[4]	2590976	1			T1	3244		T2	1265		T3	7175
all_values[5]	2590976	1			T1	3244		T2	1265		T3	7175
all_values[6]	2590976	1			T1	3244		T2	1265		T3	7175
all_values[7]	2590976	1			T1	3244		T2	1265		T3	7175

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20097187

1

T1

25952

T2

10120

T3

57350

auto[1]

630621

1

T3

50

T13

6370

T15

68

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20703122

1

T1

25952

T2

10120

T3

57302

auto[1]

24686

1

T3

98

T6

227

T11

124

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2518478	1			T1	3244		T2	1265		T3	7145
all_values[0]	auto[0]	auto[1]	11855	1			T3	26		T6	154		T11	62
all_values[0]	auto[1]	auto[0]	60091	1			T3	2		T13	2		T15	4
all_values[0]	auto[1]	auto[1]	552	1			T3	2		T13	4		T15	1
all_values[1]	auto[0]	auto[0]	2501373	1			T1	3244		T2	1265		T3	7142
all_values[1]	auto[0]	auto[1]	7014	1			T3	24		T6	63		T11	62
all_values[1]	auto[1]	auto[0]	82020	1			T3	4		T13	1		T15	7
all_values[1]	auto[1]	auto[1]	569	1			T3	5		T13	3		T15	5
all_values[2]	auto[0]	auto[0]	2494941	1			T1	3244		T2	1265		T3	7156
all_values[2]	auto[0]	auto[1]	2252	1			T3	12		T6	10		T13	4
all_values[2]	auto[1]	auto[0]	93352	1			T3	4		T13	2107		T15	5
all_values[2]	auto[1]	auto[1]	431	1			T3	3		T13	4		T15	2
all_values[3]	auto[0]	auto[0]	2497102	1			T1	3244		T2	1265		T3	7165
all_values[3]	auto[0]	auto[1]	203	1			T3	3		T13	1		T15	6
all_values[3]	auto[1]	auto[0]	93479	1			T3	4		T13	2112		T15	2
all_values[3]	auto[1]	auto[1]	192	1			T3	3		T13	2		T17	2
all_values[4]	auto[0]	auto[0]	2545015	1			T1	3244		T2	1265		T3	7167
all_values[4]	auto[0]	auto[1]	195	1			T3	3		T13	1		T15	2
all_values[4]	auto[1]	auto[0]	45537	1			T3	2		T13	2111		T15	7
all_values[4]	auto[1]	auto[1]	229	1			T3	3		T13	3		T15	5
all_values[5]	auto[0]	auto[0]	2460652	1			T1	3244		T2	1265		T3	7167
all_values[5]	auto[0]	auto[1]	199	1			T3	1		T13	3		T15	2
all_values[5]	auto[1]	auto[0]	129950	1			T3	3		T13	4		T15	6
all_values[5]	auto[1]	auto[1]	175	1			T3	4		T13	4		T15	6
all_values[6]	auto[0]	auto[0]	2540208	1			T1	3244		T2	1265		T3	7170
all_values[6]	auto[0]	auto[1]	208	1			T3	1		T13	4		T15	5
all_values[6]	auto[1]	auto[0]	50383	1			T3	3		T13	4		T15	3
all_values[6]	auto[1]	auto[1]	177	1			T3	1		T15	6		T18	2
all_values[7]	auto[0]	auto[0]	2517267	1			T1	3244		T2	1265		T3	7164
all_values[7]	auto[0]	auto[1]	225	1			T3	4		T13	4		T15	4
all_values[7]	auto[1]	auto[0]	73274	1			T3	4		T13	8		T15	8
all_values[7]	auto[1]	auto[1]	210	1			T3	3		T13	1		T15	1