Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	35550	1			T1	86		T2	270		T3	98
auto[SpiFlashAddrCfg]	7661	1			T1	43		T2	51		T3	13
auto[SpiFlashAddr3b]	9269	1			T1	47		T2	56		T3	16
auto[SpiFlashAddr4b]	7606	1			T1	24		T2	38		T3	6

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34401

1

T1

103

T2

249

T3

89

auto[1]

25685

1

T1

97

T2

166

T3

44

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32052

1

T1

115

T2

179

T3

41

auto[1]

28034

1

T1

85

T2

236

T3

92

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	40140	1			T1	105		T2	300		T3	99
values[1]	1115	1			T1	10		T2	10		T3	3
values[2]	1440	1			T1	5		T2	9		T3	2
values[3]	1462	1			T1	3		T2	13		T4	8
values[4]	1467	1			T1	5		T2	5		T3	1
values[5]	1405	1			T1	11		T2	7		T4	7
values[6]	1485	1			T1	4		T2	10		T3	5
values[7]	1627	1			T1	10		T2	5		T4	11
values[8]	9945	1			T1	47		T2	56		T3	23

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30721

1

T2

415

T3

133

T6

175

auto[1]

29365

1

T1

200

T4

579

T5

9

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

56831

1

T1

178

T2

401

T3

127

write

3255

1

T1

22

T2

14

T3

6

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

19524

1

T1

86

T2

110

T3

24

valids[0x1]

40562

1

T1

114

T2

305

T3

109

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1539	1			T1	7		T2	4		T3	1
internal_process_ops[0x5a]	1674	1			T1	15		T2	9		T3	4
internal_process_ops[0x05]	21539	1			T1	6		T2	203		T3	74
internal_process_ops[0x35]	1554	1			T1	9		T2	7		T3	2
internal_process_ops[0x15]	1564	1			T1	7		T2	12		T3	6
internal_process_ops[0x03]	993	1			T1	3		T2	6		T3	2
internal_process_ops[0x0b]	1064	1			T1	1		T2	7		T4	5
internal_process_ops[0x3b]	1079	1			T1	1		T2	6		T3	4
internal_process_ops[0x6b]	1065	1			T1	5		T2	2		T4	4
internal_process_ops[0xbb]	1114	1			T1	1		T2	7		T3	1
internal_process_ops[0xeb]	1064	1			T1	1		T2	9		T3	3

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

58512

1

T1

190

T2

409

T3

131

auto[1]

1574

1

T1

10

T2

6

T3

2

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

57684

1

T1

188

T2

408

T3

127

auto[1]

2402

1

T1

12

T2

7

T3

6

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10729

1

T2

173

T3

80

T6

60

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6150

1

T2

96

T3

18

T6

36

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1993

1

T2

20

T3

3

T6

13

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1861

1

T2

24

T3

5

T6

9

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2444

1

T2

26

T3

2

T6

9

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2166

1

T2

29

T3

13

T6

10

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1958

1

T2

23

T3

3

T6

17

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1761

1

T2

10

T3

3

T6

12

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

111

1

T11

3

T26

4

T37

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

90

1

T11

3

T13

1

T14

6

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

89

1

T25

1

T26

1

T14

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

121

1

T2

1

T6

3

T11

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

128

1

T2

2

T26

1

T14

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

95

1

T3

1

T26

1

T40

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

97

1

T2

3

T3

4

T25

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

109

1

T2

2

T11

3

T25

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

123

1

T2

1

T40

3

T160

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

86

1

T25

3

T14

1

T40

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

104

1

T11

2

T25

1

T40

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

96

1

T3

1

T6

1

T25

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

115

1

T2

1

T6

3

T11

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

91

1

T2

3

T11

2

T26

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

110

1

T2

1

T13

1

T37

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

94

1

T6

2

T38

2

T14

2

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10510

1

T1

48

T4

221

T34

205

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7359

1

T1

34

T4

234

T34

268

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1534

1

T1

11

T4

19

T5

3

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1432

1

T1

22

T4

20

T34

18

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1982

1

T1

25

T4

24

T5

3

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1869

1

T1

18

T4

18

T34

15

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1592

1

T1

6

T4

9

T5

3

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1491

1

T1

14

T4

10

T34

21

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

99

1

T34

5

T27

1

T14

4

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

92

1

T1

3

T14

2

T161

4

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

95

1

T1

1

T34

1

T27

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

105

1

T4

1

T34

2

T27

4

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

110

1

T1

5

T4

1

T161

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

89

1

T4

3

T36

1

T116

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

117

1

T1

3

T27

8

T14

4

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

96

1

T1

2

T4

1

T34

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

99

1

T4

2

T27

2

T88

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

111

1

T1

2

T34

1

T27

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

96

1

T4

2

T34

3

T27

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

93

1

T1

2

T116

1

T16

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

115

1

T1

2

T4

6

T34

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

105

1

T1

1

T4

2

T27

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

73

1

T1

1

T4

3

T34

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

101

1

T4

3

T34

5

T14

1

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3876	1			T2	39		T3	10		T6	34
auto[0]	values[0]	valids[0x1]	15812	1			T2	261		T3	89		T6	79
auto[0]	values[1]	valids[0x1]	544	1			T2	10		T3	3		T6	2
auto[0]	values[2]	valids[0x0]	490	1			T2	3		T3	1		T11	1
auto[0]	values[2]	valids[0x1]	290	1			T2	6		T3	1		T6	6
auto[0]	values[3]	valids[0x0]	513	1			T2	10		T6	4		T11	6
auto[0]	values[3]	valids[0x1]	300	1			T2	3		T6	1		T11	3
auto[0]	values[4]	valids[0x0]	523	1			T2	3		T6	4		T11	3
auto[0]	values[4]	valids[0x1]	296	1			T2	2		T3	1		T11	1
auto[0]	values[5]	valids[0x0]	512	1			T2	6		T11	6		T25	3
auto[0]	values[5]	valids[0x1]	277	1			T2	1		T11	2		T26	2
auto[0]	values[6]	valids[0x0]	548	1			T2	7		T3	3		T6	4
auto[0]	values[6]	valids[0x1]	286	1			T2	3		T3	2		T6	3
auto[0]	values[7]	valids[0x0]	582	1			T2	5		T6	4		T11	2
auto[0]	values[7]	valids[0x1]	310	1			T6	1		T11	2		T25	1
auto[0]	values[8]	valids[0x0]	3451	1			T2	37		T3	10		T6	24
auto[0]	values[8]	valids[0x1]	2111	1			T2	19		T3	13		T6	9
auto[1]	values[0]	valids[0x0]	4070	1			T1	42		T4	43		T34	55
auto[1]	values[0]	valids[0x1]	16382	1			T1	63		T4	444		T34	456
auto[1]	values[1]	valids[0x1]	571	1			T1	10		T4	2		T34	2
auto[1]	values[2]	valids[0x0]	430	1			T1	3		T4	3		T5	3
auto[1]	values[2]	valids[0x1]	230	1			T1	2		T4	1		T5	2
auto[1]	values[3]	valids[0x0]	398	1			T1	1		T4	7		T5	3
auto[1]	values[3]	valids[0x1]	251	1			T1	2		T4	1		T34	3
auto[1]	values[4]	valids[0x0]	391	1			T1	3		T4	8		T34	3
auto[1]	values[4]	valids[0x1]	257	1			T1	2		T4	3		T14	2
auto[1]	values[5]	valids[0x0]	349	1			T1	8		T4	2		T8	1
auto[1]	values[5]	valids[0x1]	267	1			T1	3		T4	5		T34	1
auto[1]	values[6]	valids[0x0]	371	1			T1	2		T4	4		T34	5
auto[1]	values[6]	valids[0x1]	280	1			T1	2		T4	3		T34	1
auto[1]	values[7]	valids[0x0]	456	1			T1	4		T4	10		T129	4
auto[1]	values[7]	valids[0x1]	279	1			T1	6		T4	1		T34	2
auto[1]	values[8]	valids[0x0]	2564	1			T1	23		T4	30		T5	1
auto[1]	values[8]	valids[0x1]	1819	1			T1	24		T4	12		T8	1