Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3537983

1

T1

15931

T2

19286

T3

4625

auto[1]

31603

1

T1

47

T2

195

T3

73

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1134213

1

T1

462

T2

59

T3

29

auto[1]

2435373

1

T1

15516

T2

19422

T3

4669

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	673112	1			T1	709		T2	1054		T3	2
auto[524288:1048575]	437686	1			T1	288		T2	2607		T3	1
auto[1048576:1572863]	374865	1			T1	27		T2	1067		T4	820
auto[1572864:2097151]	361830	1			T1	448		T2	531		T3	10
auto[2097152:2621439]	474494	1			T1	1702		T2	5206		T3	3387
auto[2621440:3145727]	417142	1			T1	542		T2	2023		T3	1
auto[3145728:3670015]	453146	1			T1	5861		T2	6933		T3	781
auto[3670016:4194303]	377311	1			T1	6401		T2	60		T3	516

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2472291

1

T1

15967

T2

19475

T3

4695

auto[1]

1097295

1

T1

11

T2

6

T3

3

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3159610

1

T1

15766

T2

15667

T3

1440

auto[1]

409976

1

T1

212

T2

3814

T3

3258

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	234395	1			T1	62		T2	15		T3	1
auto[0]	auto[0]	auto[0:524287]	auto[1]	378066	1			T1	628		T2	912		T6	2650
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	117018	1			T1	32		T2	3		T3	1
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	259440	1			T1	256		T2	2596		T6	640
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	95888	1			T1	22		T2	8		T4	4
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	232421	1			T2	289		T4	513		T6	3
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	100990	1			T1	42		T2	6		T3	2
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	210453	1			T1	385		T2	513		T3	1
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	146546	1			T1	61		T2	3		T3	1
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	267981	1			T1	1615		T2	5203		T3	131
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	158946	1			T1	26		T2	2		T3	1
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	213524	1			T1	513		T2	2018		T4	1484
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	148950	1			T1	33		T2	4		T3	9
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	232367	1			T1	5656		T2	3895		T3	711
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	116087	1			T1	65		T2	4		T3	2
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	220263	1			T1	6332		T2	1		T3	512
auto[0]	auto[1]	auto[0:524287]	auto[0]	1485	1			T1	7		T2	1		T3	1
auto[0]	auto[1]	auto[0:524287]	auto[1]	54669	1			T2	5		T34	4		T26	1
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	2700	1			T4	7		T6	1		T14	3
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	51356	1			T4	131		T6	1142		T14	284
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	2209	1			T1	5		T2	2		T11	10
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	41008	1			T2	768		T4	258		T11	1455
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	1019	1			T1	15		T2	1		T4	1
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	46052	1			T27	770		T14	2		T161	704
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	548	1			T1	20		T3	3		T4	3
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	56189	1			T3	3247		T4	2		T11	1
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	1554	1			T2	3		T6	9		T34	5
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	39292	1			T4	1		T6	5		T34	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	678	1			T1	28		T4	4		T34	5
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	67829	1			T1	128		T2	3034		T4	6
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	1035	1			T3	2		T4	9		T6	1
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	37025	1			T4	257		T6	1		T27	128
auto[1]	auto[0]	auto[0:524287]	auto[0]	531	1			T1	9		T2	4		T6	2
auto[1]	auto[0]	auto[0:524287]	auto[1]	3364	1			T1	3		T2	117		T6	6
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	365	1			T2	1		T11	3		T27	3
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	6045	1			T2	7		T11	30		T27	43
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	439	1			T4	1		T25	5		T26	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	2110	1			T4	44		T25	5		T26	33
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	410	1			T1	3		T2	1		T3	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	2413	1			T2	10		T3	6		T4	74
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	386	1			T1	3		T4	1		T6	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	2169	1			T4	32		T34	169		T26	2
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	413	1			T1	3		T4	6		T34	4
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	2758	1			T4	80		T34	59		T25	2
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	451	1			T1	13		T3	3		T4	2
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	2098	1			T3	58		T4	9		T34	79
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	409	1			T1	4		T2	1		T4	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	1914	1			T2	54		T4	15		T6	13
auto[1]	auto[1]	auto[0:524287]	auto[0]	89	1			T26	1		T14	1		T194	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	513	1			T26	28		T14	2		T194	3
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	102	1			T4	3		T14	4		T161	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	660	1			T4	41		T161	44		T210	45
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	100	1			T11	1		T26	1		T188	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	690	1			T26	22		T193	56		T77	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	114	1			T1	3		T27	2		T14	2
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	379	1			T27	16		T14	37		T18	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	108	1			T1	3		T3	2		T4	2
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	567	1			T3	3		T4	23		T11	2
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	88	1			T6	5		T34	1		T188	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	567	1			T6	3		T34	25		T188	8
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	92	1			T1	3		T4	1		T27	2
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	681	1			T4	26		T27	36		T14	32
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	68	1			T4	1		T14	2		T88	4
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	510	1			T4	12		T14	39		T88	4

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	2042748	1			T1	15728		T2	15469		T3	1370
auto[0]	auto[0]	auto[1]	1090587	1			T2	3		T3	2		T4	6
auto[0]	auto[1]	auto[0]	398684	1			T1	203		T2	3814		T3	3253
auto[0]	auto[1]	auto[1]	5964	1			T4	3		T34	1		T26	1
auto[1]	auto[0]	auto[0]	25658	1			T1	30		T2	192		T3	67
auto[1]	auto[0]	auto[1]	617	1			T1	8		T2	3		T3	1
auto[1]	auto[1]	auto[0]	5201	1			T1	6		T3	5		T4	107
auto[1]	auto[1]	auto[1]	127	1			T1	3		T4	2		T27	1