Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2590976	1			T1	3244		T2	1265		T3	7175
all_pins[1]	2590976	1			T1	3244		T2	1265		T3	7175
all_pins[2]	2590976	1			T1	3244		T2	1265		T3	7175
all_pins[3]	2590976	1			T1	3244		T2	1265		T3	7175
all_pins[4]	2590976	1			T1	3244		T2	1265		T3	7175
all_pins[5]	2590976	1			T1	3244		T2	1265		T3	7175
all_pins[6]	2590976	1			T1	3244		T2	1265		T3	7175
all_pins[7]	2590976	1			T1	3244		T2	1265		T3	7175

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	20676423	1			T1	25952		T2	10120		T3	57376
values[0x1]	51385	1			T3	24		T13	21		T15	26
transitions[0x0=>0x1]	49547	1			T3	20		T13	13		T15	21
transitions[0x1=>0x0]	49562	1			T3	20		T13	13		T15	21

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2590382	1			T1	3244		T2	1265		T3	7173
all_pins[0]	values[0x1]	594	1			T3	2		T13	4		T15	1
all_pins[0]	transitions[0x0=>0x1]	392	1			T3	1		T13	3		T15	1
all_pins[0]	transitions[0x1=>0x0]	418	1			T3	4		T13	2		T15	5
all_pins[1]	values[0x0]	2590356	1			T1	3244		T2	1265		T3	7170
all_pins[1]	values[0x1]	620	1			T3	5		T13	3		T15	5
all_pins[1]	transitions[0x0=>0x1]	365	1			T3	4		T13	1		T15	4
all_pins[1]	transitions[0x1=>0x0]	205	1			T3	2		T13	2		T15	1
all_pins[2]	values[0x0]	2590516	1			T1	3244		T2	1265		T3	7172
all_pins[2]	values[0x1]	460	1			T3	3		T13	4		T15	2
all_pins[2]	transitions[0x0=>0x1]	413	1			T3	3		T13	2		T15	2
all_pins[2]	transitions[0x1=>0x0]	145	1			T3	3		T17	2		T18	1
all_pins[3]	values[0x0]	2590784	1			T1	3244		T2	1265		T3	7172
all_pins[3]	values[0x1]	192	1			T3	3		T13	2		T17	2
all_pins[3]	transitions[0x0=>0x1]	144	1			T3	3		T17	2		T18	2
all_pins[3]	transitions[0x1=>0x0]	181	1			T3	3		T13	1		T15	5
all_pins[4]	values[0x0]	2590747	1			T1	3244		T2	1265		T3	7172
all_pins[4]	values[0x1]	229	1			T3	3		T13	3		T15	5
all_pins[4]	transitions[0x0=>0x1]	182	1			T3	2		T13	2		T15	4
all_pins[4]	transitions[0x1=>0x0]	2700	1			T3	3		T13	3		T15	5
all_pins[5]	values[0x0]	2588229	1			T1	3244		T2	1265		T3	7171
all_pins[5]	values[0x1]	2747	1			T3	4		T13	4		T15	6
all_pins[5]	transitions[0x0=>0x1]	1605	1			T3	4		T13	4		T15	4
all_pins[5]	transitions[0x1=>0x0]	45191	1			T3	1		T15	4		T18	10965
all_pins[6]	values[0x0]	2544643	1			T1	3244		T2	1265		T3	7174
all_pins[6]	values[0x1]	46333	1			T3	1		T15	6		T18	11349
all_pins[6]	transitions[0x0=>0x1]	46285	1			T3	1		T15	5		T18	11347
all_pins[6]	transitions[0x1=>0x0]	162	1			T3	3		T13	1		T18	1
all_pins[7]	values[0x0]	2590766	1			T1	3244		T2	1265		T3	7172
all_pins[7]	values[0x1]	210	1			T3	3		T13	1		T15	1
all_pins[7]	transitions[0x0=>0x1]	161	1			T3	2		T13	1		T15	1
all_pins[7]	transitions[0x1=>0x0]	560	1			T3	1		T13	4		T15	1