Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17963

1

T2

249

T3

89

T6

102

auto[1]

12758

1

T2

166

T3

44

T6

73

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4162	1			T2	136		T6	69		T11	73
values[1]	3718	1			T3	77		T11	23		T78	2
values[2]	3577	1			T2	20		T13	20		T25	50
values[3]	4733	1			T2	151		T11	40		T70	4
values[4]	2958	1			T3	36		T11	21		T26	20
values[5]	3726	1			T2	40		T26	57		T38	8
values[6]	3683	1			T2	48		T6	63		T11	40
values[7]	4164	1			T2	20		T3	20		T6	43

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4449	1			T2	40		T3	77		T25	47
values[1]	3091	1			T2	20		T3	20		T6	63
values[2]	3636	1			T2	48		T3	36		T6	20
values[3]	3496	1			T6	20		T35	6		T13	20
values[4]	4321	1			T2	78		T6	49		T11	76
values[5]	3856	1			T2	209		T6	23		T11	20
values[6]	4161	1			T2	20		T11	20		T73	4
values[7]	3711	1			T11	20		T14	41		T39	26

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	248	1			T225	2		T181	9		T196	12
auto[0]	values[0]	values[1]	197	1			T6	11		T11	16		T184	18
auto[0]	values[0]	values[2]	241	1			T172	10		T173	17		T20	8
auto[0]	values[0]	values[3]	320	1			T25	19		T69	14		T172	12
auto[0]	values[0]	values[4]	601	1			T6	25		T11	14		T223	8
auto[0]	values[0]	values[5]	423	1			T2	131		T40	32		T226	2
auto[0]	values[0]	values[6]	266	1			T193	15		T224	11		T214	10
auto[0]	values[0]	values[7]	338	1			T40	10		T187	20		T224	12
auto[0]	values[1]	values[0]	398	1			T3	67		T189	9		T19	12
auto[0]	values[1]	values[1]	198	1			T180	12		T76	16		T227	11
auto[0]	values[1]	values[2]	225	1			T194	12		T210	100		T228	2
auto[0]	values[1]	values[3]	214	1			T213	15		T229	2		T230	9
auto[0]	values[1]	values[4]	299	1			T11	16		T194	63		T210	14
auto[0]	values[1]	values[5]	213	1			T78	2		T37	14		T181	11
auto[0]	values[1]	values[6]	478	1			T187	14		T160	13		T231	6
auto[0]	values[1]	values[7]	264	1			T40	22		T188	23		T232	12
auto[0]	values[2]	values[0]	399	1			T25	21		T187	13		T160	12
auto[0]	values[2]	values[1]	210	1			T25	15		T181	16		T185	22
auto[0]	values[2]	values[2]	185	1			T2	11		T40	14		T75	12
auto[0]	values[2]	values[3]	285	1			T13	12		T14	33		T210	14
auto[0]	values[2]	values[4]	201	1			T172	8		T211	11		T233	6
auto[0]	values[2]	values[5]	189	1			T193	7		T234	13		T123	4
auto[0]	values[2]	values[6]	281	1			T172	9		T60	8		T235	6
auto[0]	values[2]	values[7]	139	1			T187	17		T236	2		T237	4
auto[0]	values[3]	values[0]	442	1			T2	11		T187	16		T172	9
auto[0]	values[3]	values[1]	263	1			T238	6		T179	13		T239	12
auto[0]	values[3]	values[2]	391	1			T172	10		T173	21		T19	24
auto[0]	values[3]	values[3]	294	1			T71	6		T26	15		T216	6
auto[0]	values[3]	values[4]	336	1			T2	13		T70	4		T26	9
auto[0]	values[3]	values[5]	258	1			T2	20		T240	5		T210	12
auto[0]	values[3]	values[6]	261	1			T11	4		T73	4		T40	13
auto[0]	values[3]	values[7]	275	1			T11	16		T188	4		T224	32
auto[0]	values[4]	values[0]	225	1			T172	12		T194	23		T196	11
auto[0]	values[4]	values[1]	322	1			T11	10		T14	11		T118	24
auto[0]	values[4]	values[2]	310	1			T3	12		T241	16		T194	10
auto[0]	values[4]	values[3]	161	1			T172	23		T30	20		T227	10
auto[0]	values[4]	values[4]	176	1			T26	11		T187	10		T172	10
auto[0]	values[4]	values[5]	197	1			T40	12		T173	13		T189	15
auto[0]	values[4]	values[6]	180	1			T40	14		T221	2		T194	10
auto[0]	values[4]	values[7]	124	1			T14	11		T206	13		T31	14
auto[0]	values[5]	values[0]	293	1			T2	14		T193	88		T181	6
auto[0]	values[5]	values[1]	300	1			T2	7		T14	54		T120	14
auto[0]	values[5]	values[2]	194	1			T26	11		T40	8		T188	10
auto[0]	values[5]	values[3]	309	1			T179	15		T210	5		T189	14
auto[0]	values[5]	values[4]	161	1			T40	14		T206	16		T242	11
auto[0]	values[5]	values[5]	335	1			T187	11		T243	20		T211	12
auto[0]	values[5]	values[6]	131	1			T244	12		T245	29		T60	24
auto[0]	values[5]	values[7]	439	1			T173	8		T189	31		T196	12
auto[0]	values[6]	values[0]	223	1			T25	16		T246	12		T247	2
auto[0]	values[6]	values[1]	175	1			T11	10		T74	14		T181	9
auto[0]	values[6]	values[2]	149	1			T2	21		T193	15		T173	12
auto[0]	values[6]	values[3]	381	1			T6	13		T35	6		T26	62
auto[0]	values[6]	values[4]	316	1			T6	11		T14	7		T188	19
auto[0]	values[6]	values[5]	318	1			T6	13		T11	12		T248	6
auto[0]	values[6]	values[6]	346	1			T2	10		T69	11		T193	14
auto[0]	values[6]	values[7]	231	1			T194	17		T201	13		T249	11
auto[0]	values[7]	values[0]	540	1			T194	32		T202	69		T213	22
auto[0]	values[7]	values[1]	160	1			T3	10		T6	17		T173	4
auto[0]	values[7]	values[2]	373	1			T6	12		T100	4		T14	86
auto[0]	values[7]	values[3]	139	1			T187	15		T184	17		T121	14
auto[0]	values[7]	values[4]	130	1			T187	8		T196	13		T250	8
auto[0]	values[7]	values[5]	469	1			T2	11		T26	54		T181	15
auto[0]	values[7]	values[6]	574	1			T40	13		T69	15		T194	23
auto[0]	values[7]	values[7]	250	1			T218	7		T251	13		T227	10
auto[1]	values[0]	values[0]	202	1			T181	11		T196	8		T234	9
auto[1]	values[0]	values[1]	166	1			T6	29		T11	4		T184	6
auto[1]	values[0]	values[2]	146	1			T172	10		T173	3		T252	16
auto[1]	values[0]	values[3]	118	1			T25	5		T69	6		T172	8
auto[1]	values[0]	values[4]	369	1			T6	4		T11	39		T160	13
auto[1]	values[0]	values[5]	108	1			T2	5		T40	8		T206	12
auto[1]	values[0]	values[6]	219	1			T193	11		T224	14		T155	10
auto[1]	values[0]	values[7]	200	1			T40	10		T187	9		T224	9
auto[1]	values[1]	values[0]	167	1			T3	10		T189	11		T19	8
auto[1]	values[1]	values[1]	169	1			T180	8		T76	4		T227	9
auto[1]	values[1]	values[2]	246	1			T194	11		T210	9		T253	15
auto[1]	values[1]	values[3]	120	1			T213	5		T230	11		T251	11
auto[1]	values[1]	values[4]	194	1			T11	7		T194	17		T210	6
auto[1]	values[1]	values[5]	150	1			T37	7		T181	10		T254	6
auto[1]	values[1]	values[6]	213	1			T187	6		T160	19		T181	19
auto[1]	values[1]	values[7]	170	1			T40	18		T188	10		T206	8
auto[1]	values[2]	values[0]	365	1			T25	5		T187	19		T160	8
auto[1]	values[2]	values[1]	51	1			T25	9		T181	4		T213	6
auto[1]	values[2]	values[2]	187	1			T2	9		T40	6		T160	6
auto[1]	values[2]	values[3]	232	1			T13	8		T14	11		T210	22
auto[1]	values[2]	values[4]	127	1			T172	12		T211	9		T255	10
auto[1]	values[2]	values[5]	211	1			T193	59		T234	7		T123	70
auto[1]	values[2]	values[6]	335	1			T172	11		T60	12		T121	12
auto[1]	values[2]	values[7]	180	1			T187	5		T256	20		T257	15
auto[1]	values[3]	values[0]	238	1			T2	9		T187	17		T172	11
auto[1]	values[3]	values[1]	81	1			T179	7		T20	6		T211	7
auto[1]	values[3]	values[2]	276	1			T172	10		T173	19		T209	12
auto[1]	values[3]	values[3]	354	1			T26	39		T193	12		T189	63
auto[1]	values[3]	values[4]	591	1			T2	65		T26	64		T14	31
auto[1]	values[3]	values[5]	275	1			T2	33		T240	16		T210	22
auto[1]	values[3]	values[6]	167	1			T11	16		T40	7		T188	21
auto[1]	values[3]	values[7]	231	1			T11	4		T39	26		T188	43
auto[1]	values[4]	values[0]	221	1			T172	8		T194	3		T196	83
auto[1]	values[4]	values[1]	197	1			T11	11		T14	50		T172	8
auto[1]	values[4]	values[2]	199	1			T3	24		T194	22		T173	11
auto[1]	values[4]	values[3]	142	1			T172	17		T30	4		T258	10
auto[1]	values[4]	values[4]	172	1			T26	9		T187	10		T172	10
auto[1]	values[4]	values[5]	102	1			T40	8		T173	7		T189	7
auto[1]	values[4]	values[6]	173	1			T40	6		T194	12		T179	8
auto[1]	values[4]	values[7]	57	1			T14	30		T206	7		T31	6
auto[1]	values[5]	values[0]	174	1			T2	6		T193	11		T181	14
auto[1]	values[5]	values[1]	200	1			T2	13		T38	8		T14	8
auto[1]	values[5]	values[2]	191	1			T26	46		T40	12		T188	10
auto[1]	values[5]	values[3]	165	1			T179	5		T210	15		T189	6
auto[1]	values[5]	values[4]	184	1			T40	6		T222	24		T206	9
auto[1]	values[5]	values[5]	143	1			T187	11		T211	8		T206	14
auto[1]	values[5]	values[6]	66	1			T60	16		T259	13		T260	10
auto[1]	values[5]	values[7]	441	1			T173	12		T189	8		T196	88
auto[1]	values[6]	values[0]	119	1			T25	5		T195	15		T184	18
auto[1]	values[6]	values[1]	203	1			T11	10		T181	22		T206	11
auto[1]	values[6]	values[2]	198	1			T2	7		T193	62		T173	8
auto[1]	values[6]	values[3]	153	1			T6	7		T26	10		T193	7
auto[1]	values[6]	values[4]	306	1			T6	9		T14	13		T215	18
auto[1]	values[6]	values[5]	157	1			T6	10		T11	8		T173	6
auto[1]	values[6]	values[6]	239	1			T2	10		T69	9		T193	57
auto[1]	values[6]	values[7]	169	1			T194	6		T261	14		T201	7
auto[1]	values[7]	values[0]	195	1			T194	7		T202	12		T213	18
auto[1]	values[7]	values[1]	199	1			T3	10		T6	6		T173	16
auto[1]	values[7]	values[2]	125	1			T6	8		T14	8		T179	5
auto[1]	values[7]	values[3]	109	1			T187	5		T184	3		T121	6
auto[1]	values[7]	values[4]	158	1			T187	32		T196	15		T262	8
auto[1]	values[7]	values[5]	308	1			T2	9		T26	21		T181	5
auto[1]	values[7]	values[6]	232	1			T40	7		T69	10		T194	9
auto[1]	values[7]	values[7]	203	1			T218	13		T263	10		T251	90