Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	66	0	66	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	64	0	64	100.00	100	1	1	64

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

14945

1

T2

177

T3

84

T6

91

auto[1]

45141

1

T1

200

T2

238

T3

49

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	64	0	64	100.00

Automatically Generated Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:3]	1230	1			T1	4		T2	6		T3	2
auto[4:7]	24782	1			T1	20		T2	218		T3	79
auto[8:11]	1301	1			T1	1		T2	9		T4	5
auto[12:15]	348	1			T1	1		T2	4		T3	1
auto[16:19]	347	1			T1	3		T2	2		T4	2
auto[20:23]	1825	1			T1	7		T2	12		T3	6
auto[24:27]	368	1			T1	2		T2	1		T3	1
auto[28:31]	351	1			T1	2		T2	2		T11	4
auto[32:35]	300	1			T1	1		T4	3		T6	1
auto[36:39]	326	1			T2	1		T4	2		T6	1
auto[40:43]	352	1			T1	2		T3	1		T4	2
auto[44:47]	283	1			T1	7		T2	1		T4	3
auto[48:51]	282	1			T1	2		T2	2		T4	2
auto[52:55]	1804	1			T1	11		T2	8		T3	2
auto[56:59]	1354	1			T1	3		T2	9		T3	4
auto[60:63]	337	1			T2	3		T4	5		T6	3
auto[64:67]	345	1			T1	3		T2	2		T4	1
auto[68:71]	323	1			T2	3		T4	2		T6	3
auto[72:75]	302	1			T1	2		T2	2		T3	3
auto[76:79]	328	1			T1	1		T3	1		T11	2
auto[80:83]	362	1			T2	2		T4	3		T34	1
auto[84:87]	274	1			T2	2		T13	1		T14	5
auto[88:91]	1947	1			T1	16		T2	10		T3	4
auto[92:95]	320	1			T1	3		T2	2		T4	1
auto[96:99]	267	1			T1	3		T2	2		T6	5
auto[100:103]	310	1			T1	2		T2	1		T4	2
auto[104:107]	1296	1			T1	6		T2	2		T4	5
auto[108:111]	333	1			T1	5		T2	1		T3	1
auto[112:115]	361	1			T1	2		T2	1		T4	5
auto[116:119]	358	1			T1	2		T2	2		T3	1
auto[120:123]	314	1			T1	3		T2	1		T11	4
auto[124:127]	356	1			T2	2		T4	5		T11	1
auto[128:131]	374	1			T2	2		T11	1		T26	1
auto[132:135]	307	1			T1	3		T2	2		T3	2
auto[136:139]	338	1			T1	4		T2	3		T4	5
auto[140:143]	262	1			T1	4		T2	5		T4	4
auto[144:147]	319	1			T1	1		T2	2		T4	4
auto[148:151]	313	1			T1	4		T3	1		T4	2
auto[152:155]	296	1			T1	1		T2	4		T3	1
auto[156:159]	1761	1			T1	8		T2	7		T3	1
auto[160:163]	296	1			T1	2		T2	5		T4	2
auto[164:167]	336	1			T1	2		T2	1		T3	1
auto[168:171]	349	1			T1	1		T4	1		T34	1
auto[172:175]	342	1			T1	1		T2	2		T3	1
auto[176:179]	325	1			T2	2		T3	1		T6	1
auto[180:183]	1841	1			T1	10		T2	8		T3	1
auto[184:187]	1377	1			T1	2		T2	8		T3	1
auto[188:191]	314	1			T1	1		T3	2		T11	1
auto[192:195]	331	1			T1	4		T2	2		T11	3
auto[196:199]	322	1			T3	1		T4	3		T34	4
auto[200:203]	308	1			T1	2		T2	2		T25	3
auto[204:207]	333	1			T2	3		T4	1		T6	1
auto[208:211]	332	1			T2	3		T4	1		T11	4
auto[212:215]	315	1			T1	4		T2	4		T4	1
auto[216:219]	310	1			T1	2		T2	1		T3	4
auto[220:223]	309	1			T1	2		T2	4		T4	1
auto[224:227]	317	1			T1	1		T6	1		T11	1
auto[228:231]	335	1			T2	1		T4	2		T34	2
auto[232:235]	2756	1			T1	14		T2	21		T3	7
auto[236:239]	296	1			T1	2		T2	3		T3	1
auto[240:243]	329	1			T1	2		T3	1		T6	1
auto[244:247]	304	1			T1	2		T2	3		T4	1
auto[248:251]	329	1			T1	4		T2	4		T3	1
auto[252:255]	324	1			T1	3		T4	4		T34	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:3]	auto[0]	430	1			T2	3		T3	2		T6	6
auto[0:3]	auto[1]	800	1			T1	4		T2	3		T4	5
auto[4:7]	auto[0]	5374	1			T2	93		T3	63		T6	30
auto[4:7]	auto[1]	19408	1			T1	20		T2	125		T3	16
auto[8:11]	auto[0]	427	1			T2	4		T6	4		T11	5
auto[8:11]	auto[1]	874	1			T1	1		T2	5		T4	5
auto[12:15]	auto[0]	93	1			T2	2		T3	1		T6	2
auto[12:15]	auto[1]	255	1			T1	1		T2	2		T4	1
auto[16:19]	auto[0]	88	1			T26	2		T14	1		T69	4
auto[16:19]	auto[1]	259	1			T1	3		T2	2		T4	2
auto[20:23]	auto[0]	457	1			T2	8		T6	2		T11	4
auto[20:23]	auto[1]	1368	1			T1	7		T2	4		T3	6
auto[24:27]	auto[0]	93	1			T2	1		T3	1		T11	3
auto[24:27]	auto[1]	275	1			T1	2		T4	1		T34	6
auto[28:31]	auto[0]	76	1			T11	1		T25	1		T38	1
auto[28:31]	auto[1]	275	1			T1	2		T2	2		T11	3
auto[32:35]	auto[0]	72	1			T14	2		T40	1		T187	1
auto[32:35]	auto[1]	228	1			T1	1		T4	3		T6	1
auto[36:39]	auto[0]	72	1			T2	1		T6	1		T11	1
auto[36:39]	auto[1]	254	1			T4	2		T34	1		T26	5
auto[40:43]	auto[0]	98	1			T3	1		T26	1		T188	1
auto[40:43]	auto[1]	254	1			T1	2		T4	2		T11	1
auto[44:47]	auto[0]	47	1			T2	1		T6	1		T193	1
auto[44:47]	auto[1]	236	1			T1	7		T4	3		T11	1
auto[48:51]	auto[0]	63	1			T11	2		T25	1		T39	2
auto[48:51]	auto[1]	219	1			T1	2		T2	2		T4	2
auto[52:55]	auto[0]	469	1			T2	2		T11	7		T70	1
auto[52:55]	auto[1]	1335	1			T1	11		T2	6		T3	2
auto[56:59]	auto[0]	490	1			T2	4		T3	2		T11	6
auto[56:59]	auto[1]	864	1			T1	3		T2	5		T3	2
auto[60:63]	auto[0]	82	1			T2	1		T6	3		T14	2
auto[60:63]	auto[1]	255	1			T2	2		T4	5		T34	4
auto[64:67]	auto[0]	85	1			T2	1		T26	1		T14	2
auto[64:67]	auto[1]	260	1			T1	3		T2	1		T4	1
auto[68:71]	auto[0]	68	1			T2	1		T6	3		T26	2
auto[68:71]	auto[1]	255	1			T2	2		T4	2		T34	2
auto[72:75]	auto[0]	67	1			T2	2		T3	1		T6	1
auto[72:75]	auto[1]	235	1			T1	2		T3	2		T4	4
auto[76:79]	auto[0]	76	1			T3	1		T11	1		T14	2
auto[76:79]	auto[1]	252	1			T1	1		T11	1		T34	1
auto[80:83]	auto[0]	90	1			T25	3		T26	2		T14	1
auto[80:83]	auto[1]	272	1			T2	2		T4	3		T34	1
auto[84:87]	auto[0]	80	1			T2	2		T13	1		T193	3
auto[84:87]	auto[1]	194	1			T14	5		T161	4		T193	3
auto[88:91]	auto[0]	468	1			T2	5		T3	3		T6	1
auto[88:91]	auto[1]	1479	1			T1	16		T2	5		T3	1
auto[92:95]	auto[0]	86	1			T2	2		T11	5		T14	1
auto[92:95]	auto[1]	234	1			T1	3		T4	1		T34	1
auto[96:99]	auto[0]	60	1			T6	2		T25	1		T188	1
auto[96:99]	auto[1]	207	1			T1	3		T2	2		T6	3
auto[100:103]	auto[0]	91	1			T6	1		T11	4		T26	1
auto[100:103]	auto[1]	219	1			T1	2		T2	1		T4	2
auto[104:107]	auto[0]	465	1			T2	1		T6	2		T11	5
auto[104:107]	auto[1]	831	1			T1	6		T2	1		T4	5
auto[108:111]	auto[0]	83	1			T2	1		T26	1		T215	1
auto[108:111]	auto[1]	250	1			T1	5		T3	1		T34	3
auto[112:115]	auto[0]	79	1			T6	2		T118	3		T193	2
auto[112:115]	auto[1]	282	1			T1	2		T2	1		T4	5
auto[116:119]	auto[0]	95	1			T11	1		T26	1		T14	1
auto[116:119]	auto[1]	263	1			T1	2		T2	2		T3	1
auto[120:123]	auto[0]	70	1			T2	1		T11	1		T14	2
auto[120:123]	auto[1]	244	1			T1	3		T11	3		T34	2
auto[124:127]	auto[0]	80	1			T11	1		T193	1		T184	2
auto[124:127]	auto[1]	276	1			T2	2		T4	5		T34	1
auto[128:131]	auto[0]	87	1			T11	1		T14	2		T172	3
auto[128:131]	auto[1]	287	1			T2	2		T26	1		T27	2
auto[132:135]	auto[0]	83	1			T2	1		T11	1		T246	2
auto[132:135]	auto[1]	224	1			T1	3		T2	1		T3	2
auto[136:139]	auto[0]	93	1			T13	1		T25	1		T40	1
auto[136:139]	auto[1]	245	1			T1	4		T2	3		T4	5
auto[140:143]	auto[0]	64	1			T2	1		T14	1		T37	1
auto[140:143]	auto[1]	198	1			T1	4		T2	4		T4	4
auto[144:147]	auto[0]	80	1			T11	1		T71	2		T188	2
auto[144:147]	auto[1]	239	1			T1	1		T2	2		T4	4
auto[148:151]	auto[0]	80	1			T6	1		T193	1		T172	1
auto[148:151]	auto[1]	233	1			T1	4		T3	1		T4	2
auto[152:155]	auto[0]	76	1			T26	1		T14	1		T40	1
auto[152:155]	auto[1]	220	1			T1	1		T2	4		T3	1
auto[156:159]	auto[0]	458	1			T2	3		T3	1		T6	8
auto[156:159]	auto[1]	1303	1			T1	8		T2	4		T4	9
auto[160:163]	auto[0]	60	1			T2	3		T6	1		T26	2
auto[160:163]	auto[1]	236	1			T1	2		T2	2		T4	2
auto[164:167]	auto[0]	73	1			T3	1		T25	1		T14	1
auto[164:167]	auto[1]	263	1			T1	2		T2	1		T34	5
auto[168:171]	auto[0]	100	1			T172	2		T224	2		T248	1
auto[168:171]	auto[1]	249	1			T1	1		T4	1		T34	1
auto[172:175]	auto[0]	79	1			T3	1		T40	1		T172	1
auto[172:175]	auto[1]	263	1			T1	1		T2	2		T6	4
auto[176:179]	auto[0]	95	1			T2	1		T3	1		T11	3
auto[176:179]	auto[1]	230	1			T2	1		T6	1		T27	3
auto[180:183]	auto[0]	467	1			T2	3		T6	3		T11	4
auto[180:183]	auto[1]	1374	1			T1	10		T2	5		T3	1
auto[184:187]	auto[0]	462	1			T2	2		T3	1		T6	1
auto[184:187]	auto[1]	915	1			T1	2		T2	6		T4	9
auto[188:191]	auto[0]	74	1			T11	1		T26	2		T14	2
auto[188:191]	auto[1]	240	1			T1	1		T3	2		T34	1
auto[192:195]	auto[0]	96	1			T2	2		T40	3		T37	1
auto[192:195]	auto[1]	235	1			T1	4		T11	3		T34	5
auto[196:199]	auto[0]	66	1			T26	1		T40	2		T194	1
auto[196:199]	auto[1]	256	1			T3	1		T4	3		T34	4
auto[200:203]	auto[0]	74	1			T2	2		T14	2		T193	2
auto[200:203]	auto[1]	234	1			T1	2		T25	3		T27	2
auto[204:207]	auto[0]	88	1			T2	3		T26	1		T40	1
auto[204:207]	auto[1]	245	1			T4	1		T6	1		T11	4
auto[208:211]	auto[0]	86	1			T11	4		T216	1		T40	1
auto[208:211]	auto[1]	246	1			T2	3		T4	1		T34	2
auto[212:215]	auto[0]	84	1			T6	3		T11	1		T187	4
auto[212:215]	auto[1]	231	1			T1	4		T2	4		T4	1
auto[216:219]	auto[0]	82	1			T6	4		T11	2		T40	3
auto[216:219]	auto[1]	228	1			T1	2		T2	1		T3	4
auto[220:223]	auto[0]	81	1			T2	1		T193	3		T172	1
auto[220:223]	auto[1]	228	1			T1	2		T2	3		T4	1
auto[224:227]	auto[0]	67	1			T6	1		T26	1		T216	1
auto[224:227]	auto[1]	250	1			T1	1		T11	1		T25	1
auto[228:231]	auto[0]	81	1			T188	2		T193	3		T224	3
auto[228:231]	auto[1]	254	1			T2	1		T4	2		T34	2
auto[232:235]	auto[0]	846	1			T2	11		T3	2		T6	6
auto[232:235]	auto[1]	1910	1			T1	14		T2	10		T3	5
auto[236:239]	auto[0]	74	1			T2	3		T3	1		T6	1
auto[236:239]	auto[1]	222	1			T1	2		T34	3		T26	3
auto[240:243]	auto[0]	67	1			T3	1		T25	1		T26	1
auto[240:243]	auto[1]	262	1			T1	2		T6	1		T11	2
auto[244:247]	auto[0]	96	1			T2	2		T6	1		T11	2
auto[244:247]	auto[1]	208	1			T1	2		T2	1		T4	1
auto[248:251]	auto[0]	73	1			T2	3		T25	1		T26	1
auto[248:251]	auto[1]	256	1			T1	4		T2	1		T3	1
auto[252:255]	auto[0]	79	1			T26	1		T187	1		T188	2
auto[252:255]	auto[1]	245	1			T1	3		T4	4		T34	2