Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	363	1			T2	2		T6	4		T11	2
auto[ReadAddrCrossIntoMailbox]	272	1			T2	3		T6	1		T11	2
auto[ReadAddrCrossOutOfMailbox]	263	1			T2	4		T6	1		T11	2
auto[ReadAddrCrossAllMailbox]	202	1			T2	4		T11	2		T25	1
auto[ReadAddrOutsideMailbox]	3583	1			T2	24		T3	10		T6	20

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2351

1

T2

17

T3

6

T6

15

auto[1]

2332

1

T2

20

T3

4

T6

11

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	738	1			T2	6		T3	2		T6	5
read_ops[0x0b]	740	1			T2	7		T6	3		T11	5
read_ops[0x3b]	804	1			T2	6		T3	4		T6	2
read_ops[0x6b]	796	1			T2	2		T6	5		T11	12
read_ops[0xbb]	836	1			T2	7		T3	1		T6	5
read_ops[0xeb]	769	1			T2	9		T3	3		T6	6

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	25	1			T187	1		T188	2		T189	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	21	1			T181	1		T189	1		T211	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	21	1			T2	1		T264	3		T189	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	27	1			T26	2		T40	1		T188	2
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	20	1			T11	1		T244	1		T240	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	25	1			T2	1		T14	2		T244	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	14	1			T2	1		T172	1		T240	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T14	1		T40	1		T264	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	297	1			T2	1		T3	2		T6	5
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	272	1			T2	2		T11	2		T35	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	25	1			T2	1		T11	1		T25	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	35	1			T14	1		T40	1		T160	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	16	1			T2	1		T26	2		T193	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	21	1			T40	1		T181	1		T189	2
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	23	1			T40	1		T172	1		T224	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	17	1			T2	1		T172	2		T60	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	19	1			T11	1		T69	1		T193	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	14	1			T40	2		T179	2		T196	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	280	1			T2	1		T6	3		T11	2
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	290	1			T2	3		T11	1		T26	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	24	1			T40	2		T160	1		T194	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	16	1			T69	1		T195	1		T196	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	30	1			T40	1		T173	1		T212	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	25	1			T26	1		T40	1		T188	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	22	1			T26	1		T40	1		T193	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	27	1			T26	1		T40	2		T187	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	20	1			T2	1		T160	1		T172	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	18	1			T40	1		T69	1		T264	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	318	1			T2	2		T3	2		T11	2
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	304	1			T2	3		T3	2		T6	2
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	29	1			T40	2		T172	1		T181	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	43	1			T6	2		T11	1		T69	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	30	1			T40	2		T187	1		T194	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	19	1			T172	1		T60	1		T211	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	21	1			T40	1		T210	1		T264	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	21	1			T6	1		T69	2		T173	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T11	1		T172	1		T180	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	13	1			T179	1		T212	1		T211	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	289	1			T2	1		T6	2		T11	4
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	316	1			T2	1		T11	6		T14	5
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	29	1			T40	1		T69	1		T221	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	49	1			T6	1		T25	1		T40	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	24	1			T11	1		T40	1		T172	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	28	1			T2	1		T6	1		T40	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	28	1			T2	1		T11	1		T193	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	25	1			T160	1		T181	1		T60	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T25	1		T187	1		T195	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	23	1			T2	1		T26	1		T40	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	302	1			T3	1		T6	1		T11	5
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	311	1			T2	4		T6	2		T71	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	33	1			T2	1		T35	1		T40	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	34	1			T6	1		T35	1		T25	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	22	1			T26	1		T40	2		T160	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	9	1			T11	1		T194	1		T173	2
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	16	1			T2	1		T14	1		T40	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	18	1			T40	1		T194	1		T206	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	22	1			T2	1		T40	3		T179	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	11	1			T40	1		T69	1		T194	2
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	320	1			T2	3		T3	1		T6	4
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	284	1			T2	3		T3	2		T6	1