Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	854	1			T3	10		T13	11		T15	14
all_values[1]	854	1			T3	10		T13	11		T15	14
all_values[2]	854	1			T3	10		T13	11		T15	14
all_values[3]	854	1			T3	10		T13	11		T15	14
all_values[4]	854	1			T3	10		T13	11		T15	14
all_values[5]	854	1			T3	10		T13	11		T15	14
all_values[6]	854	1			T3	10		T13	11		T15	14
all_values[7]	854	1			T3	10		T13	11		T15	14

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3618

1

T3

42

T13

36

T15

52

auto[1]

3214

1

T3

38

T13

52

T15

60

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2766

1

T3

26

T13

34

T15

41

auto[1]

4066

1

T3

54

T13

54

T15

71

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3929

1

T3

44

T13

51

T15

60

auto[1]

2903

1

T3

36

T13

37

T15

52

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	184	1			T3	1		T13	3		T15	4
all_values[0]	auto[0]	auto[0]	auto[1]	76	1			T3	1		T13	1		T15	2
all_values[0]	auto[0]	auto[1]	auto[0]	155	1			T3	2		T15	3		T17	1
all_values[0]	auto[0]	auto[1]	auto[1]	84	1			T3	1		T13	2		T15	1
all_values[0]	auto[1]	auto[0]	auto[1]	197	1			T3	2		T13	4		T15	2
all_values[0]	auto[1]	auto[1]	auto[1]	158	1			T3	3		T13	1		T15	2
all_values[1]	auto[0]	auto[0]	auto[0]	178	1			T3	2		T13	2		T15	3
all_values[1]	auto[0]	auto[0]	auto[1]	98	1			T13	1		T15	1		T17	1
all_values[1]	auto[0]	auto[1]	auto[0]	161	1			T3	1		T13	1		T15	3
all_values[1]	auto[0]	auto[1]	auto[1]	78	1			T3	3		T13	2		T15	1
all_values[1]	auto[1]	auto[0]	auto[1]	183	1			T3	3		T13	2		T15	1
all_values[1]	auto[1]	auto[1]	auto[1]	156	1			T3	1		T13	3		T15	5
all_values[2]	auto[0]	auto[0]	auto[0]	184	1			T3	1		T17	3		T19	2
all_values[2]	auto[0]	auto[0]	auto[1]	82	1			T3	2		T13	2		T15	3
all_values[2]	auto[0]	auto[1]	auto[0]	154	1			T3	2		T13	2		T15	4
all_values[2]	auto[0]	auto[1]	auto[1]	72	1			T3	1		T13	2		T15	1
all_values[2]	auto[1]	auto[0]	auto[1]	184	1			T3	1		T13	1		T15	4
all_values[2]	auto[1]	auto[1]	auto[1]	178	1			T3	3		T13	4		T15	2
all_values[3]	auto[0]	auto[0]	auto[0]	176	1			T3	1		T13	1		T15	5
all_values[3]	auto[0]	auto[0]	auto[1]	81	1			T3	2		T15	2		T19	2
all_values[3]	auto[0]	auto[1]	auto[0]	152	1			T3	1		T13	5		T15	1
all_values[3]	auto[0]	auto[1]	auto[1]	89	1			T3	1		T13	2		T17	1
all_values[3]	auto[1]	auto[0]	auto[1]	198	1			T3	3		T13	2		T15	6
all_values[3]	auto[1]	auto[1]	auto[1]	158	1			T3	2		T13	1		T17	1
all_values[4]	auto[0]	auto[0]	auto[0]	180	1			T3	1		T13	3		T15	2
all_values[4]	auto[0]	auto[0]	auto[1]	74	1			T3	3		T19	1		T20	2
all_values[4]	auto[0]	auto[1]	auto[0]	135	1			T3	1		T13	2		T15	3
all_values[4]	auto[0]	auto[1]	auto[1]	95	1			T3	1		T13	2		T15	3
all_values[4]	auto[1]	auto[0]	auto[1]	178	1			T3	2		T13	1		T15	2
all_values[4]	auto[1]	auto[1]	auto[1]	192	1			T3	2		T13	3		T15	4
all_values[5]	auto[0]	auto[0]	auto[0]	271	1			T3	3		T13	2		T15	2
all_values[5]	auto[0]	auto[1]	auto[0]	209	1			T3	2		T13	2		T15	4
all_values[5]	auto[1]	auto[0]	auto[1]	207	1			T3	2		T13	2		T15	2
all_values[5]	auto[1]	auto[1]	auto[1]	167	1			T3	3		T13	5		T15	6
all_values[6]	auto[0]	auto[0]	auto[0]	172	1			T3	4		T13	3		T17	1
all_values[6]	auto[0]	auto[0]	auto[1]	84	1			T13	1		T15	1		T18	1
all_values[6]	auto[0]	auto[1]	auto[0]	160	1			T3	2		T13	4		T15	1
all_values[6]	auto[0]	auto[1]	auto[1]	66	1			T15	3		T18	1		T19	2
all_values[6]	auto[1]	auto[0]	auto[1]	210	1			T3	4		T13	1		T15	4
all_values[6]	auto[1]	auto[1]	auto[1]	162	1			T13	2		T15	5		T19	6
all_values[7]	auto[0]	auto[0]	auto[0]	133	1			T15	1		T18	1		T19	9
all_values[7]	auto[0]	auto[0]	auto[1]	95	1			T3	1		T13	2		T15	1
all_values[7]	auto[0]	auto[1]	auto[0]	162	1			T3	2		T13	4		T15	5
all_values[7]	auto[0]	auto[1]	auto[1]	89	1			T3	2		T18	1		T19	3
all_values[7]	auto[1]	auto[0]	auto[1]	193	1			T3	3		T13	2		T15	4
all_values[7]	auto[1]	auto[1]	auto[1]	182	1			T3	2		T13	3		T15	3

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal