Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1760

1

T3

1

T6

2

T11

2

auto[1]

1780

1

T3

1

T11

2

T12

21

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1786

1

T3

2

T6

2

T11

3

auto[1]

1754

1

T11

1

T12

35

T24

41

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2839

1

T3

2

T6

1

T11

4

auto[1]

701

1

T6

1

T13

3

T25

2

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	700	1			T12	8		T13	1		T24	8
valid[1]	689	1			T12	7		T13	2		T24	9
valid[2]	717	1			T3	1		T11	2		T12	8
valid[3]	693	1			T6	1		T12	6		T13	1
valid[4]	741	1			T3	1		T6	1		T11	2

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	112	1			T25	1		T14	2		T37	3
auto[0]	auto[0]	valid[0]	auto[1]	188	1			T12	5		T24	2		T14	2
auto[0]	auto[0]	valid[1]	auto[0]	106	1			T13	1		T14	2		T37	2
auto[0]	auto[0]	valid[1]	auto[1]	161	1			T12	3		T24	3		T25	1
auto[0]	auto[0]	valid[2]	auto[0]	102	1			T3	1		T37	1		T187	1
auto[0]	auto[0]	valid[2]	auto[1]	174	1			T11	1		T12	2		T24	3
auto[0]	auto[0]	valid[3]	auto[0]	111	1			T6	1		T25	1		T14	1
auto[0]	auto[0]	valid[3]	auto[1]	160	1			T12	3		T24	8		T25	2
auto[0]	auto[0]	valid[4]	auto[0]	106	1			T11	1		T14	3		T36	2
auto[0]	auto[0]	valid[4]	auto[1]	176	1			T12	1		T24	3		T66	1
auto[0]	auto[1]	valid[0]	auto[0]	95	1			T14	2		T37	1		T187	1
auto[0]	auto[1]	valid[0]	auto[1]	181	1			T12	3		T24	6		T67	4
auto[0]	auto[1]	valid[1]	auto[0]	103	1			T13	1		T25	1		T36	1
auto[0]	auto[1]	valid[1]	auto[1]	183	1			T12	4		T24	6		T14	1
auto[0]	auto[1]	valid[2]	auto[0]	119	1			T11	1		T13	1		T25	1
auto[0]	auto[1]	valid[2]	auto[1]	177	1			T12	6		T24	6		T25	1
auto[0]	auto[1]	valid[3]	auto[0]	118	1			T14	2		T36	1		T69	1
auto[0]	auto[1]	valid[3]	auto[1]	164	1			T12	3		T24	2		T67	6
auto[0]	auto[1]	valid[4]	auto[0]	113	1			T3	1		T11	1		T13	1
auto[0]	auto[1]	valid[4]	auto[1]	190	1			T12	5		T24	2		T25	1
auto[1]	auto[0]	valid[0]	auto[0]	66	1			T13	1		T14	1		T68	1
auto[1]	auto[0]	valid[1]	auto[0]	74	1			T14	2		T37	1		T68	1
auto[1]	auto[0]	valid[2]	auto[0]	71	1			T13	1		T14	2		T314	1
auto[1]	auto[0]	valid[3]	auto[0]	72	1			T14	1		T36	1		T37	1
auto[1]	auto[0]	valid[4]	auto[0]	81	1			T6	1		T14	1		T116	1
auto[1]	auto[1]	valid[0]	auto[0]	58	1			T14	1		T37	1		T187	1
auto[1]	auto[1]	valid[1]	auto[0]	62	1			T25	1		T36	1		T37	1
auto[1]	auto[1]	valid[2]	auto[0]	74	1			T14	1		T36	2		T160	1
auto[1]	auto[1]	valid[3]	auto[0]	68	1			T13	1		T25	1		T14	1
auto[1]	auto[1]	valid[4]	auto[0]	75	1			T14	1		T36	1		T68	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal