Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

48108

1

T3

38

T6

82

T11

94

auto[1]

17325

1

T6

10

T11

28

T12

397

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

47910

1

T3

27

T6

56

T11

82

auto[1]

17523

1

T3

11

T6

36

T11

40

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	33901	1			T3	24		T6	49		T11	59
others[1]	5536	1			T3	4		T6	10		T11	12
others[2]	5561	1			T3	2		T6	4		T11	13
others[3]	6237	1			T3	2		T6	10		T11	11
interest[1]	3496	1			T3	1		T6	5		T11	7
interest[4]	22139	1			T3	16		T6	37		T11	42
interest[64]	10702	1			T3	5		T6	14		T11	20

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	15678	1			T3	17		T6	27		T11	27
auto[0]	auto[0]	others[1]	2614	1			T3	2		T6	6		T11	4
auto[0]	auto[0]	others[2]	2635	1			T3	1		T6	1		T11	4
auto[0]	auto[0]	others[3]	2966	1			T3	2		T6	2		T11	6
auto[0]	auto[0]	interest[1]	1652	1			T3	1		T6	3		T11	3
auto[0]	auto[0]	interest[4]	10218	1			T3	11		T6	21		T11	20
auto[0]	auto[0]	interest[64]	5040	1			T3	4		T6	7		T11	10
auto[0]	auto[1]	others[0]	9161	1			T6	2		T11	13		T12	195
auto[0]	auto[1]	others[1]	1412	1			T11	3		T12	33		T24	35
auto[0]	auto[1]	others[2]	1411	1			T6	2		T11	3		T12	42
auto[0]	auto[1]	others[3]	1675	1			T6	4		T11	2		T12	39
auto[0]	auto[1]	interest[1]	913	1			T11	3		T12	22		T24	17
auto[0]	auto[1]	interest[4]	6082	1			T6	2		T11	8		T12	127
auto[0]	auto[1]	interest[64]	2753	1			T6	2		T11	4		T12	66
auto[1]	auto[0]	others[0]	9062	1			T3	7		T6	20		T11	19
auto[1]	auto[0]	others[1]	1510	1			T3	2		T6	4		T11	5
auto[1]	auto[0]	others[2]	1515	1			T3	1		T6	1		T11	6
auto[1]	auto[0]	others[3]	1596	1			T6	4		T11	3		T13	7
auto[1]	auto[0]	interest[1]	931	1			T6	2		T11	1		T13	5
auto[1]	auto[0]	interest[4]	5839	1			T3	5		T6	14		T11	14
auto[1]	auto[0]	interest[64]	2909	1			T3	1		T6	5		T11	6

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal