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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.05 98.44 94.10 98.62 89.36 97.28 95.29 99.26


Total test records in report: 1149
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T104 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.3243809311 Aug 06 04:29:07 PM PDT 24 Aug 06 04:29:08 PM PDT 24 112416114 ps
T61 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.4081336470 Aug 06 04:27:48 PM PDT 24 Aug 06 04:27:49 PM PDT 24 82088682 ps
T83 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.3464761195 Aug 06 04:28:12 PM PDT 24 Aug 06 04:28:30 PM PDT 24 1239087035 ps
T1048 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.535960250 Aug 06 04:27:45 PM PDT 24 Aug 06 04:27:46 PM PDT 24 14945027 ps
T1049 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.1861711752 Aug 06 04:27:50 PM PDT 24 Aug 06 04:27:51 PM PDT 24 47095497 ps
T1050 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.3168650257 Aug 06 04:28:11 PM PDT 24 Aug 06 04:28:12 PM PDT 24 15902909 ps
T84 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.389887253 Aug 06 04:27:37 PM PDT 24 Aug 06 04:27:44 PM PDT 24 383664019 ps
T62 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1239787029 Aug 06 04:27:34 PM PDT 24 Aug 06 04:27:35 PM PDT 24 39178904 ps
T99 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.511119213 Aug 06 04:27:50 PM PDT 24 Aug 06 04:27:53 PM PDT 24 86985718 ps
T89 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.2349538749 Aug 06 04:27:45 PM PDT 24 Aug 06 04:27:49 PM PDT 24 668866319 ps
T90 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.3118170373 Aug 06 04:27:50 PM PDT 24 Aug 06 04:27:54 PM PDT 24 2140870849 ps
T1051 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.453038410 Aug 06 04:27:46 PM PDT 24 Aug 06 04:27:47 PM PDT 24 41008576 ps
T91 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.730655370 Aug 06 04:27:46 PM PDT 24 Aug 06 04:27:51 PM PDT 24 196757432 ps
T1052 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.2756042471 Aug 06 04:28:05 PM PDT 24 Aug 06 04:28:06 PM PDT 24 18204650 ps
T105 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.3212312792 Aug 06 04:27:28 PM PDT 24 Aug 06 04:27:36 PM PDT 24 453505919 ps
T1053 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.3135482169 Aug 06 04:28:02 PM PDT 24 Aug 06 04:28:02 PM PDT 24 11112820 ps
T1054 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.1770083548 Aug 06 04:27:40 PM PDT 24 Aug 06 04:27:41 PM PDT 24 23085835 ps
T97 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.4154271249 Aug 06 04:28:04 PM PDT 24 Aug 06 04:28:07 PM PDT 24 1455957784 ps
T106 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.51390279 Aug 06 04:27:34 PM PDT 24 Aug 06 04:27:37 PM PDT 24 970138658 ps
T92 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.1217341053 Aug 06 04:29:08 PM PDT 24 Aug 06 04:29:10 PM PDT 24 355136284 ps
T85 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.3572059904 Aug 06 04:28:07 PM PDT 24 Aug 06 04:28:22 PM PDT 24 1144144053 ps
T107 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.3345175013 Aug 06 04:27:51 PM PDT 24 Aug 06 04:27:53 PM PDT 24 33607559 ps
T1055 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.3801373796 Aug 06 04:27:32 PM PDT 24 Aug 06 04:27:55 PM PDT 24 4630717242 ps
T1056 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1063408512 Aug 06 04:27:37 PM PDT 24 Aug 06 04:27:49 PM PDT 24 1044914511 ps
T1057 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.3368432551 Aug 06 04:27:51 PM PDT 24 Aug 06 04:27:52 PM PDT 24 43079412 ps
T1058 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.1391914516 Aug 06 04:27:50 PM PDT 24 Aug 06 04:27:54 PM PDT 24 62262389 ps
T1059 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.2728589033 Aug 06 04:28:11 PM PDT 24 Aug 06 04:28:15 PM PDT 24 240768113 ps
T108 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.958835965 Aug 06 04:28:12 PM PDT 24 Aug 06 04:28:13 PM PDT 24 19633404 ps
T135 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.2091463810 Aug 06 04:27:52 PM PDT 24 Aug 06 04:27:53 PM PDT 24 77408590 ps
T1060 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.1264369440 Aug 06 04:27:49 PM PDT 24 Aug 06 04:27:50 PM PDT 24 27919841 ps
T1061 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.146740605 Aug 06 04:28:09 PM PDT 24 Aug 06 04:28:10 PM PDT 24 19251775 ps
T94 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2167999797 Aug 06 04:27:50 PM PDT 24 Aug 06 04:27:54 PM PDT 24 135598259 ps
T1062 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3247874624 Aug 06 04:27:31 PM PDT 24 Aug 06 04:27:34 PM PDT 24 41194505 ps
T93 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3616103509 Aug 06 04:27:48 PM PDT 24 Aug 06 04:27:52 PM PDT 24 712590668 ps
T1063 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.2943184294 Aug 06 04:27:57 PM PDT 24 Aug 06 04:27:58 PM PDT 24 43643933 ps
T1064 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.3410310455 Aug 06 04:27:34 PM PDT 24 Aug 06 04:27:38 PM PDT 24 63426493 ps
T63 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.287209107 Aug 06 04:28:01 PM PDT 24 Aug 06 04:28:02 PM PDT 24 56751563 ps
T136 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.845837363 Aug 06 04:28:17 PM PDT 24 Aug 06 04:28:21 PM PDT 24 224954878 ps
T95 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.835064848 Aug 06 04:27:32 PM PDT 24 Aug 06 04:27:36 PM PDT 24 497461418 ps
T1065 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.113059957 Aug 06 04:27:45 PM PDT 24 Aug 06 04:27:46 PM PDT 24 83723696 ps
T1066 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.2011363614 Aug 06 04:28:12 PM PDT 24 Aug 06 04:28:12 PM PDT 24 11725459 ps
T109 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.4087508245 Aug 06 04:27:31 PM PDT 24 Aug 06 04:27:32 PM PDT 24 162213769 ps
T162 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3959581420 Aug 06 04:27:37 PM PDT 24 Aug 06 04:27:50 PM PDT 24 414791304 ps
T137 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.1572721443 Aug 06 04:27:46 PM PDT 24 Aug 06 04:27:48 PM PDT 24 78814645 ps
T96 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.1059610618 Aug 06 04:27:50 PM PDT 24 Aug 06 04:28:00 PM PDT 24 197011120 ps
T1067 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1838026830 Aug 06 04:27:51 PM PDT 24 Aug 06 04:27:54 PM PDT 24 38682453 ps
T138 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2109610052 Aug 06 04:27:48 PM PDT 24 Aug 06 04:27:50 PM PDT 24 73870582 ps
T1068 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.3547645519 Aug 06 04:28:12 PM PDT 24 Aug 06 04:28:13 PM PDT 24 102590465 ps
T1069 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.147661535 Aug 06 04:28:28 PM PDT 24 Aug 06 04:28:32 PM PDT 24 97502331 ps
T1070 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.609193690 Aug 06 04:29:08 PM PDT 24 Aug 06 04:29:12 PM PDT 24 41983886 ps
T64 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.2677082345 Aug 06 04:27:39 PM PDT 24 Aug 06 04:27:40 PM PDT 24 151063232 ps
T1071 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.2038680381 Aug 06 04:27:47 PM PDT 24 Aug 06 04:27:50 PM PDT 24 60615960 ps
T1072 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.356886752 Aug 06 04:27:30 PM PDT 24 Aug 06 04:27:30 PM PDT 24 11634931 ps
T1073 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.1554297183 Aug 06 04:27:34 PM PDT 24 Aug 06 04:27:37 PM PDT 24 61259480 ps
T1074 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3280292762 Aug 06 04:27:57 PM PDT 24 Aug 06 04:27:58 PM PDT 24 45850037 ps
T1075 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.2087257444 Aug 06 04:27:50 PM PDT 24 Aug 06 04:27:51 PM PDT 24 22745503 ps
T1076 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.1346414700 Aug 06 04:27:52 PM PDT 24 Aug 06 04:27:55 PM PDT 24 237423565 ps
T1077 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.2204896499 Aug 06 04:27:46 PM PDT 24 Aug 06 04:27:47 PM PDT 24 63436571 ps
T1078 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.932016087 Aug 06 04:27:49 PM PDT 24 Aug 06 04:27:51 PM PDT 24 154063799 ps
T110 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.2872075622 Aug 06 04:27:37 PM PDT 24 Aug 06 04:27:40 PM PDT 24 79100787 ps
T1079 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.3212350594 Aug 06 04:27:37 PM PDT 24 Aug 06 04:27:38 PM PDT 24 14422603 ps
T1080 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.1576476011 Aug 06 04:28:12 PM PDT 24 Aug 06 04:28:13 PM PDT 24 14874815 ps
T159 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.1782128795 Aug 06 04:27:43 PM PDT 24 Aug 06 04:27:48 PM PDT 24 212841631 ps
T1081 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.3520126845 Aug 06 04:28:00 PM PDT 24 Aug 06 04:28:02 PM PDT 24 143107986 ps
T1082 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2028339775 Aug 06 04:28:04 PM PDT 24 Aug 06 04:28:05 PM PDT 24 11352669 ps
T1083 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.1788690823 Aug 06 04:27:31 PM PDT 24 Aug 06 04:27:34 PM PDT 24 40695823 ps
T1084 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.1562652155 Aug 06 04:28:04 PM PDT 24 Aug 06 04:28:05 PM PDT 24 32472264 ps
T1085 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.3491083443 Aug 06 04:29:08 PM PDT 24 Aug 06 04:29:15 PM PDT 24 697870703 ps
T1086 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3022943604 Aug 06 04:28:10 PM PDT 24 Aug 06 04:28:10 PM PDT 24 33038540 ps
T163 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.503792954 Aug 06 04:27:31 PM PDT 24 Aug 06 04:27:53 PM PDT 24 2577770023 ps
T139 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3892658805 Aug 06 04:27:47 PM PDT 24 Aug 06 04:27:51 PM PDT 24 798221396 ps
T1087 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.2008415924 Aug 06 04:28:01 PM PDT 24 Aug 06 04:28:02 PM PDT 24 23102270 ps
T1088 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.3108967721 Aug 06 04:27:33 PM PDT 24 Aug 06 04:27:34 PM PDT 24 20395325 ps
T1089 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.1934677375 Aug 06 04:27:44 PM PDT 24 Aug 06 04:27:51 PM PDT 24 291533462 ps
T168 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.3137193984 Aug 06 04:27:34 PM PDT 24 Aug 06 04:27:42 PM PDT 24 110284319 ps
T140 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2621388418 Aug 06 04:27:32 PM PDT 24 Aug 06 04:27:34 PM PDT 24 741861105 ps
T1090 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.1163624221 Aug 06 04:27:47 PM PDT 24 Aug 06 04:27:48 PM PDT 24 28713845 ps
T1091 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.825178878 Aug 06 04:28:12 PM PDT 24 Aug 06 04:28:14 PM PDT 24 1148713535 ps
T141 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.217187259 Aug 06 04:27:50 PM PDT 24 Aug 06 04:27:52 PM PDT 24 159881745 ps
T1092 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.1182015281 Aug 06 04:28:01 PM PDT 24 Aug 06 04:28:02 PM PDT 24 12601439 ps
T1093 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.1230398120 Aug 06 04:28:17 PM PDT 24 Aug 06 04:28:18 PM PDT 24 29898741 ps
T1094 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.1893053890 Aug 06 04:28:09 PM PDT 24 Aug 06 04:28:10 PM PDT 24 24496338 ps
T1095 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.416571912 Aug 06 04:27:29 PM PDT 24 Aug 06 04:27:30 PM PDT 24 33765383 ps
T164 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.3330350776 Aug 06 04:27:50 PM PDT 24 Aug 06 04:28:09 PM PDT 24 304870966 ps
T1096 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.2925109038 Aug 06 04:28:07 PM PDT 24 Aug 06 04:28:08 PM PDT 24 31057530 ps
T1097 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.1124905012 Aug 06 04:28:04 PM PDT 24 Aug 06 04:28:05 PM PDT 24 96690770 ps
T1098 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3838461219 Aug 06 04:27:50 PM PDT 24 Aug 06 04:27:52 PM PDT 24 88854750 ps
T1099 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.3474966741 Aug 06 04:27:44 PM PDT 24 Aug 06 04:27:46 PM PDT 24 164772853 ps
T1100 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.1801722918 Aug 06 04:27:52 PM PDT 24 Aug 06 04:27:55 PM PDT 24 1719257699 ps
T1101 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.3482167168 Aug 06 04:27:47 PM PDT 24 Aug 06 04:27:49 PM PDT 24 284199670 ps
T1102 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3510152914 Aug 06 04:27:32 PM PDT 24 Aug 06 04:27:33 PM PDT 24 17930745 ps
T1103 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.1821020686 Aug 06 04:27:47 PM PDT 24 Aug 06 04:27:49 PM PDT 24 174430577 ps
T1104 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.2290780074 Aug 06 04:27:32 PM PDT 24 Aug 06 04:27:33 PM PDT 24 13695147 ps
T1105 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3693043410 Aug 06 04:27:39 PM PDT 24 Aug 06 04:27:40 PM PDT 24 112463655 ps
T1106 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.1780288493 Aug 06 04:27:58 PM PDT 24 Aug 06 04:28:03 PM PDT 24 152235430 ps
T1107 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.3781511658 Aug 06 04:27:36 PM PDT 24 Aug 06 04:27:38 PM PDT 24 882510479 ps
T165 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.2233012643 Aug 06 04:27:48 PM PDT 24 Aug 06 04:28:05 PM PDT 24 307211425 ps
T1108 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.4074771977 Aug 06 04:28:14 PM PDT 24 Aug 06 04:28:14 PM PDT 24 11908230 ps
T1109 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1132971484 Aug 06 04:27:40 PM PDT 24 Aug 06 04:27:44 PM PDT 24 353269308 ps
T1110 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.2568266743 Aug 06 04:27:44 PM PDT 24 Aug 06 04:27:47 PM PDT 24 208540611 ps
T166 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.860026631 Aug 06 04:27:50 PM PDT 24 Aug 06 04:27:57 PM PDT 24 548127516 ps
T1111 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.1166570775 Aug 06 04:28:08 PM PDT 24 Aug 06 04:28:08 PM PDT 24 99894398 ps
T1112 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.1953863924 Aug 06 04:27:43 PM PDT 24 Aug 06 04:27:44 PM PDT 24 14459555 ps
T1113 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3132502740 Aug 06 04:27:49 PM PDT 24 Aug 06 04:27:52 PM PDT 24 43788308 ps
T111 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.2020587492 Aug 06 04:27:31 PM PDT 24 Aug 06 04:27:48 PM PDT 24 4137303966 ps
T1114 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.969822257 Aug 06 04:28:02 PM PDT 24 Aug 06 04:28:04 PM PDT 24 30055513 ps
T1115 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.633537285 Aug 06 04:27:46 PM PDT 24 Aug 06 04:27:48 PM PDT 24 33797385 ps
T1116 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.3993178662 Aug 06 04:27:57 PM PDT 24 Aug 06 04:27:58 PM PDT 24 14124965 ps
T171 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.426682717 Aug 06 04:27:47 PM PDT 24 Aug 06 04:28:05 PM PDT 24 296721117 ps
T1117 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2230642903 Aug 06 04:27:34 PM PDT 24 Aug 06 04:27:36 PM PDT 24 419148160 ps
T1118 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.165752464 Aug 06 04:27:44 PM PDT 24 Aug 06 04:27:48 PM PDT 24 165401603 ps
T1119 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.1593145430 Aug 06 04:28:01 PM PDT 24 Aug 06 04:28:04 PM PDT 24 129752959 ps
T1120 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2192681227 Aug 06 04:27:23 PM PDT 24 Aug 06 04:27:23 PM PDT 24 12651078 ps
T1121 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.1233607685 Aug 06 04:27:57 PM PDT 24 Aug 06 04:27:58 PM PDT 24 206021701 ps
T1122 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.2395242196 Aug 06 04:27:30 PM PDT 24 Aug 06 04:27:34 PM PDT 24 155508040 ps
T1123 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3161055849 Aug 06 04:27:35 PM PDT 24 Aug 06 04:27:58 PM PDT 24 590696398 ps
T112 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.1943503401 Aug 06 04:27:30 PM PDT 24 Aug 06 04:27:32 PM PDT 24 65746568 ps
T1124 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.856209042 Aug 06 04:27:51 PM PDT 24 Aug 06 04:27:52 PM PDT 24 29629656 ps
T1125 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.2550767606 Aug 06 04:28:02 PM PDT 24 Aug 06 04:28:02 PM PDT 24 18087849 ps
T1126 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3157666988 Aug 06 04:27:32 PM PDT 24 Aug 06 04:27:35 PM PDT 24 415801452 ps
T1127 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.1107689740 Aug 06 04:28:07 PM PDT 24 Aug 06 04:28:08 PM PDT 24 19153736 ps
T1128 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.3980015229 Aug 06 04:28:12 PM PDT 24 Aug 06 04:28:13 PM PDT 24 50089057 ps
T1129 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.3410625545 Aug 06 04:28:16 PM PDT 24 Aug 06 04:28:17 PM PDT 24 11316970 ps
T1130 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.3838553690 Aug 06 04:27:47 PM PDT 24 Aug 06 04:27:53 PM PDT 24 102060724 ps
T1131 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3519758224 Aug 06 04:27:31 PM PDT 24 Aug 06 04:27:35 PM PDT 24 218099278 ps
T1132 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.3167249851 Aug 06 04:28:08 PM PDT 24 Aug 06 04:28:08 PM PDT 24 28324825 ps
T1133 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.833917803 Aug 06 04:28:15 PM PDT 24 Aug 06 04:28:15 PM PDT 24 30490490 ps
T169 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.2919429934 Aug 06 04:27:45 PM PDT 24 Aug 06 04:27:52 PM PDT 24 226584776 ps
T1134 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.561044931 Aug 06 04:27:47 PM PDT 24 Aug 06 04:27:48 PM PDT 24 60776704 ps
T1135 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.827821714 Aug 06 04:28:17 PM PDT 24 Aug 06 04:28:17 PM PDT 24 24047818 ps
T1136 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.633487052 Aug 06 04:28:09 PM PDT 24 Aug 06 04:28:10 PM PDT 24 24198503 ps
T170 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.2099018551 Aug 06 04:27:44 PM PDT 24 Aug 06 04:27:56 PM PDT 24 383681845 ps
T1137 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.3495348464 Aug 06 04:28:05 PM PDT 24 Aug 06 04:28:20 PM PDT 24 684541739 ps
T167 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.3772160234 Aug 06 04:27:52 PM PDT 24 Aug 06 04:28:13 PM PDT 24 838225308 ps
T1138 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.223194258 Aug 06 04:27:50 PM PDT 24 Aug 06 04:27:53 PM PDT 24 113154881 ps
T1139 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.3077466076 Aug 06 04:27:51 PM PDT 24 Aug 06 04:28:04 PM PDT 24 2114799145 ps
T1140 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.1540883009 Aug 06 04:27:48 PM PDT 24 Aug 06 04:27:51 PM PDT 24 339809230 ps
T98 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1355794190 Aug 06 04:27:34 PM PDT 24 Aug 06 04:27:47 PM PDT 24 1336025522 ps
T113 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2684797690 Aug 06 04:27:30 PM PDT 24 Aug 06 04:27:32 PM PDT 24 35159338 ps
T1141 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.3333647893 Aug 06 04:27:50 PM PDT 24 Aug 06 04:27:56 PM PDT 24 1005489172 ps
T114 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.3984567558 Aug 06 04:28:06 PM PDT 24 Aug 06 04:28:09 PM PDT 24 71030376 ps
T1142 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.2874645547 Aug 06 04:28:05 PM PDT 24 Aug 06 04:28:08 PM PDT 24 225383916 ps
T1143 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.284650059 Aug 06 04:27:44 PM PDT 24 Aug 06 04:27:50 PM PDT 24 127052279 ps
T1144 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.1428459552 Aug 06 04:28:10 PM PDT 24 Aug 06 04:28:11 PM PDT 24 22969373 ps
T1145 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.1116330631 Aug 06 04:27:34 PM PDT 24 Aug 06 04:27:49 PM PDT 24 1123760012 ps
T1146 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.1139937665 Aug 06 04:27:59 PM PDT 24 Aug 06 04:28:02 PM PDT 24 86478180 ps
T1147 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.780091676 Aug 06 04:28:00 PM PDT 24 Aug 06 04:28:01 PM PDT 24 34234471 ps
T1148 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.1143366261 Aug 06 04:27:49 PM PDT 24 Aug 06 04:28:12 PM PDT 24 2066595943 ps
T1149 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.4103003756 Aug 06 04:27:48 PM PDT 24 Aug 06 04:27:52 PM PDT 24 585939177 ps

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.2207877649
Short name T6
Test name
Test status
Simulation time 85454799872 ps
CPU time 167.4 seconds
Started Aug 06 04:47:16 PM PDT 24
Finished Aug 06 04:50:04 PM PDT 24
Peak memory 251416 kb
Host smart-d4ff33e9-dba0-49b6-93ec-94d10e96248a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207877649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.2207877649
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.3677299905
Short name T14
Test name
Test status
Simulation time 277142535460 ps
CPU time 603.36 seconds
Started Aug 06 04:47:00 PM PDT 24
Finished Aug 06 04:57:04 PM PDT 24
Peak memory 279824 kb
Host smart-d99a0e9b-5ac2-4326-a41b-c3b125315fea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677299905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.3677299905
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.195414995
Short name T2
Test name
Test status
Simulation time 34227278978 ps
CPU time 112.12 seconds
Started Aug 06 04:47:03 PM PDT 24
Finished Aug 06 04:48:55 PM PDT 24
Peak memory 254004 kb
Host smart-a90c5943-7661-49b7-8b2c-3907afd77d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195414995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.195414995
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.1278509504
Short name T20
Test name
Test status
Simulation time 67659594843 ps
CPU time 658.49 seconds
Started Aug 06 04:47:30 PM PDT 24
Finished Aug 06 04:58:28 PM PDT 24
Peak memory 271696 kb
Host smart-43553cd5-d2af-4269-a35e-5f0c283e4618
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278509504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.1278509504
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3011745808
Short name T81
Test name
Test status
Simulation time 126658581 ps
CPU time 1.84 seconds
Started Aug 06 04:27:50 PM PDT 24
Finished Aug 06 04:27:52 PM PDT 24
Peak memory 215416 kb
Host smart-94cad068-9928-4a2f-84e9-213411035a9a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011745808 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.3011745808
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.660446303
Short name T184
Test name
Test status
Simulation time 26338306342 ps
CPU time 65.09 seconds
Started Aug 06 04:46:42 PM PDT 24
Finished Aug 06 04:47:47 PM PDT 24
Peak memory 257464 kb
Host smart-1226cb49-84cd-4185-a665-3371167960cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660446303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.660446303
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.1054334835
Short name T45
Test name
Test status
Simulation time 17503442 ps
CPU time 0.8 seconds
Started Aug 06 04:44:27 PM PDT 24
Finished Aug 06 04:44:28 PM PDT 24
Peak memory 216520 kb
Host smart-63bb16d4-8f88-4435-88b3-fcec3a44a77c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054334835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.1054334835
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.1340409834
Short name T16
Test name
Test status
Simulation time 571215618634 ps
CPU time 317.17 seconds
Started Aug 06 04:45:46 PM PDT 24
Finished Aug 06 04:51:03 PM PDT 24
Peak memory 256040 kb
Host smart-bfd6ba6d-98fd-46f8-80d2-94edc9b440af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340409834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.1340409834
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.884042596
Short name T60
Test name
Test status
Simulation time 11874370616 ps
CPU time 87.29 seconds
Started Aug 06 04:44:32 PM PDT 24
Finished Aug 06 04:46:00 PM PDT 24
Peak memory 269308 kb
Host smart-db2cc790-8473-4bad-82cb-3b53a7a1e9d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884042596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds.
884042596
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.547842984
Short name T206
Test name
Test status
Simulation time 51544036728 ps
CPU time 521.76 seconds
Started Aug 06 04:46:57 PM PDT 24
Finished Aug 06 04:55:39 PM PDT 24
Peak memory 267496 kb
Host smart-957732d3-ce15-483e-b5ca-1565ec0b402b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547842984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.547842984
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.423070656
Short name T289
Test name
Test status
Simulation time 6068570848 ps
CPU time 112.39 seconds
Started Aug 06 04:46:59 PM PDT 24
Finished Aug 06 04:48:52 PM PDT 24
Peak memory 251740 kb
Host smart-0f665ef1-2444-4449-ac68-ef9a5939088b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423070656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.423070656
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.3464761195
Short name T83
Test name
Test status
Simulation time 1239087035 ps
CPU time 18.69 seconds
Started Aug 06 04:28:12 PM PDT 24
Finished Aug 06 04:28:30 PM PDT 24
Peak memory 215624 kb
Host smart-98927644-6ade-4ad7-a1fb-00eb424f43a2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464761195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.3464761195
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.781651009
Short name T8
Test name
Test status
Simulation time 647401262 ps
CPU time 6.41 seconds
Started Aug 06 04:44:37 PM PDT 24
Finished Aug 06 04:44:44 PM PDT 24
Peak memory 225244 kb
Host smart-a6228b94-eece-47b8-a69d-fb50f8c002bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781651009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.781651009
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.1984887505
Short name T44
Test name
Test status
Simulation time 15143868 ps
CPU time 0.71 seconds
Started Aug 06 04:45:38 PM PDT 24
Finished Aug 06 04:45:39 PM PDT 24
Peak memory 205248 kb
Host smart-2694f3da-e10c-4543-b134-fb2a83797529
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984887505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
1984887505
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.3115971658
Short name T194
Test name
Test status
Simulation time 77710681253 ps
CPU time 142.13 seconds
Started Aug 06 04:45:47 PM PDT 24
Finished Aug 06 04:48:09 PM PDT 24
Peak memory 258144 kb
Host smart-9f4bb9e7-7898-40ff-8966-740578a0e2b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115971658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.3115971658
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.921852048
Short name T102
Test name
Test status
Simulation time 222815890 ps
CPU time 2.88 seconds
Started Aug 06 04:27:30 PM PDT 24
Finished Aug 06 04:27:33 PM PDT 24
Peak memory 207240 kb
Host smart-f87c6a73-922b-4dd9-8d7d-e198c073934a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921852048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.921852048
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.730655370
Short name T91
Test name
Test status
Simulation time 196757432 ps
CPU time 5.29 seconds
Started Aug 06 04:27:46 PM PDT 24
Finished Aug 06 04:27:51 PM PDT 24
Peak memory 215816 kb
Host smart-87d11de2-61ce-4b03-bbeb-9ac46c1961af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730655370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.730655370
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.4192585809
Short name T187
Test name
Test status
Simulation time 119174680486 ps
CPU time 188.85 seconds
Started Aug 06 04:45:49 PM PDT 24
Finished Aug 06 04:48:58 PM PDT 24
Peak memory 273836 kb
Host smart-a97b05a8-ddf9-4dbf-8a8c-87f80d16e23a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192585809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.4192585809
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.2256801907
Short name T189
Test name
Test status
Simulation time 3314448689 ps
CPU time 91.04 seconds
Started Aug 06 04:47:18 PM PDT 24
Finished Aug 06 04:48:49 PM PDT 24
Peak memory 257396 kb
Host smart-900f2c32-b3d7-4bc3-b65d-93edc553baa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256801907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.2256801907
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.2602658503
Short name T234
Test name
Test status
Simulation time 236025067000 ps
CPU time 318.21 seconds
Started Aug 06 04:47:10 PM PDT 24
Finished Aug 06 04:52:29 PM PDT 24
Peak memory 268200 kb
Host smart-82d2e2ee-5396-4676-913a-ad13848094de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602658503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.2602658503
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.994146633
Short name T251
Test name
Test status
Simulation time 2380699254 ps
CPU time 47.2 seconds
Started Aug 06 04:46:38 PM PDT 24
Finished Aug 06 04:47:25 PM PDT 24
Peak memory 249780 kb
Host smart-5b198041-9edd-4421-b54b-fb1146d15af7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994146633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.994146633
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.3464636711
Short name T333
Test name
Test status
Simulation time 92667988 ps
CPU time 0.99 seconds
Started Aug 06 04:44:16 PM PDT 24
Finished Aug 06 04:44:17 PM PDT 24
Peak memory 218308 kb
Host smart-f4f0525c-606c-4ba8-a712-d6cb2e59640d
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464636711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.spi_device_mem_parity.3464636711
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.3148752060
Short name T172
Test name
Test status
Simulation time 39284849534 ps
CPU time 196.22 seconds
Started Aug 06 04:44:51 PM PDT 24
Finished Aug 06 04:48:07 PM PDT 24
Peak memory 255300 kb
Host smart-fa3981b7-8b34-4273-beba-46beabb25ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148752060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds
.3148752060
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.2419424495
Short name T177
Test name
Test status
Simulation time 40804587530 ps
CPU time 413.11 seconds
Started Aug 06 04:46:43 PM PDT 24
Finished Aug 06 04:53:37 PM PDT 24
Peak memory 265596 kb
Host smart-6f369f13-d4fe-483d-90eb-3ef59adba25c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419424495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.2419424495
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.2954625001
Short name T47
Test name
Test status
Simulation time 98985970 ps
CPU time 1.12 seconds
Started Aug 06 04:44:14 PM PDT 24
Finished Aug 06 04:44:15 PM PDT 24
Peak memory 235436 kb
Host smart-fab9a0fc-ffe7-4f53-868a-0e9998f15cc0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954625001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.2954625001
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.3804614486
Short name T230
Test name
Test status
Simulation time 18932675893 ps
CPU time 192.25 seconds
Started Aug 06 04:45:40 PM PDT 24
Finished Aug 06 04:48:52 PM PDT 24
Peak memory 254420 kb
Host smart-37abd67c-5ef9-4121-87cd-172fdc8001de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804614486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmd
s.3804614486
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.358372604
Short name T27
Test name
Test status
Simulation time 49708245046 ps
CPU time 217.05 seconds
Started Aug 06 04:47:28 PM PDT 24
Finished Aug 06 04:51:05 PM PDT 24
Peak memory 257172 kb
Host smart-4872af01-38c0-439d-9034-d1bf51798b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358372604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.358372604
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.223138479
Short name T193
Test name
Test status
Simulation time 15407769245 ps
CPU time 158.99 seconds
Started Aug 06 04:45:15 PM PDT 24
Finished Aug 06 04:47:55 PM PDT 24
Peak memory 263724 kb
Host smart-089ee82f-d6b8-49d6-a8e8-52754e02d9eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223138479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.223138479
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.3365280385
Short name T875
Test name
Test status
Simulation time 120065571258 ps
CPU time 101.19 seconds
Started Aug 06 04:47:15 PM PDT 24
Finished Aug 06 04:48:56 PM PDT 24
Peak memory 263460 kb
Host smart-435f0dcc-daef-4345-9e59-b8578df02d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365280385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.3365280385
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.2171705727
Short name T819
Test name
Test status
Simulation time 15620339253 ps
CPU time 224.93 seconds
Started Aug 06 04:45:49 PM PDT 24
Finished Aug 06 04:49:35 PM PDT 24
Peak memory 274160 kb
Host smart-51b25519-15cb-42bd-8f8c-b3d54b64958a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171705727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.2171705727
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.1123522147
Short name T462
Test name
Test status
Simulation time 10600010700 ps
CPU time 62.03 seconds
Started Aug 06 04:45:50 PM PDT 24
Finished Aug 06 04:46:52 PM PDT 24
Peak memory 257336 kb
Host smart-b95fefd4-b682-41eb-9013-b4bde7b950bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123522147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.1123522147
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.3340203448
Short name T180
Test name
Test status
Simulation time 5429039136 ps
CPU time 44.15 seconds
Started Aug 06 04:44:35 PM PDT 24
Finished Aug 06 04:45:20 PM PDT 24
Peak memory 241668 kb
Host smart-6d074024-5f4e-4870-9f60-dce39eb1554d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340203448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.3340203448
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3959581420
Short name T162
Test name
Test status
Simulation time 414791304 ps
CPU time 12.54 seconds
Started Aug 06 04:27:37 PM PDT 24
Finished Aug 06 04:27:50 PM PDT 24
Peak memory 215612 kb
Host smart-de0bcb54-0d88-47c9-bdca-55443e5bf88b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959581420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.3959581420
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.1435110448
Short name T69
Test name
Test status
Simulation time 83970892633 ps
CPU time 207.73 seconds
Started Aug 06 04:45:51 PM PDT 24
Finished Aug 06 04:49:19 PM PDT 24
Peak memory 249876 kb
Host smart-ff0fac01-e5b6-4d1e-9193-0e0e188d98aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435110448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.1435110448
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3616103509
Short name T93
Test name
Test status
Simulation time 712590668 ps
CPU time 4.74 seconds
Started Aug 06 04:27:48 PM PDT 24
Finished Aug 06 04:27:52 PM PDT 24
Peak memory 216712 kb
Host smart-f556823c-ce15-4a7a-b51d-00777159cbe8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616103509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
3616103509
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.3772160234
Short name T167
Test name
Test status
Simulation time 838225308 ps
CPU time 21.06 seconds
Started Aug 06 04:27:52 PM PDT 24
Finished Aug 06 04:28:13 PM PDT 24
Peak memory 215700 kb
Host smart-03bdb75b-6a2c-435a-b823-5724a546792f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772160234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.3772160234
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.3858742374
Short name T204
Test name
Test status
Simulation time 34160455563 ps
CPU time 114.29 seconds
Started Aug 06 04:45:17 PM PDT 24
Finished Aug 06 04:47:11 PM PDT 24
Peak memory 254896 kb
Host smart-4bea4782-46c4-46c7-b8a2-be9b5fa3eca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858742374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.3858742374
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.1459579403
Short name T296
Test name
Test status
Simulation time 37270929061 ps
CPU time 356.1 seconds
Started Aug 06 04:44:27 PM PDT 24
Finished Aug 06 04:50:23 PM PDT 24
Peak memory 264580 kb
Host smart-b246c015-0de8-44fd-9c54-bd561fe096a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459579403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.1459579403
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.2720328522
Short name T688
Test name
Test status
Simulation time 12241436894 ps
CPU time 45.8 seconds
Started Aug 06 04:45:54 PM PDT 24
Finished Aug 06 04:46:40 PM PDT 24
Peak memory 225268 kb
Host smart-32625b32-4015-4115-ae1c-5ba98b7b5a55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720328522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.2720328522
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.3845643491
Short name T292
Test name
Test status
Simulation time 4981018796 ps
CPU time 83.97 seconds
Started Aug 06 04:45:47 PM PDT 24
Finished Aug 06 04:47:11 PM PDT 24
Peak memory 258000 kb
Host smart-a09cfd90-6f67-4610-b6e1-cf9d31e5cd58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845643491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmd
s.3845643491
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.1202692848
Short name T191
Test name
Test status
Simulation time 3441147177 ps
CPU time 78.72 seconds
Started Aug 06 04:45:56 PM PDT 24
Finished Aug 06 04:47:15 PM PDT 24
Peak memory 255492 kb
Host smart-2b9978ec-7785-45b8-8fcb-1680ae547e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202692848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.1202692848
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.1158747125
Short name T76
Test name
Test status
Simulation time 24978992989 ps
CPU time 172.18 seconds
Started Aug 06 04:44:49 PM PDT 24
Finished Aug 06 04:47:41 PM PDT 24
Peak memory 249784 kb
Host smart-0d104077-6008-4999-a911-268b256e1790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158747125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds
.1158747125
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.2800891130
Short name T5
Test name
Test status
Simulation time 170041401 ps
CPU time 8.09 seconds
Started Aug 06 04:45:39 PM PDT 24
Finished Aug 06 04:45:48 PM PDT 24
Peak memory 241628 kb
Host smart-d56be19e-3e70-4507-9762-cc015db7b5c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800891130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.2800891130
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.1423227408
Short name T242
Test name
Test status
Simulation time 110987711845 ps
CPU time 927.67 seconds
Started Aug 06 04:44:11 PM PDT 24
Finished Aug 06 04:59:39 PM PDT 24
Peak memory 266228 kb
Host smart-7b8dfb86-657f-4553-a6ee-c1cf0748fa46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423227408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.1423227408
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.1560546981
Short name T497
Test name
Test status
Simulation time 16541674520 ps
CPU time 13.29 seconds
Started Aug 06 04:45:21 PM PDT 24
Finished Aug 06 04:45:35 PM PDT 24
Peak memory 233452 kb
Host smart-9c3d6a41-e589-4749-a261-5a6f33a9acff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560546981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.1560546981
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.696389564
Short name T122
Test name
Test status
Simulation time 43423455318 ps
CPU time 281.18 seconds
Started Aug 06 04:45:00 PM PDT 24
Finished Aug 06 04:49:42 PM PDT 24
Peak memory 275544 kb
Host smart-9624f95b-9c65-4acc-9479-c9230d10f68c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696389564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stress
_all.696389564
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.3580284146
Short name T155
Test name
Test status
Simulation time 993712874 ps
CPU time 5.96 seconds
Started Aug 06 04:45:17 PM PDT 24
Finished Aug 06 04:45:24 PM PDT 24
Peak memory 233088 kb
Host smart-312417b7-4d84-4df2-ba08-72ff23c854a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580284146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.3580284146
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.4081336470
Short name T61
Test name
Test status
Simulation time 82088682 ps
CPU time 1.36 seconds
Started Aug 06 04:27:48 PM PDT 24
Finished Aug 06 04:27:49 PM PDT 24
Peak memory 216600 kb
Host smart-55109f79-a214-4a4c-ba93-efb9d87e0e0f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081336470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.4081336470
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.3491083443
Short name T1085
Test name
Test status
Simulation time 697870703 ps
CPU time 4.23 seconds
Started Aug 06 04:29:08 PM PDT 24
Finished Aug 06 04:29:15 PM PDT 24
Peak memory 215396 kb
Host smart-8205c838-c224-4297-8386-7b91a7d410b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491083443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.3
491083443
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1355794190
Short name T98
Test name
Test status
Simulation time 1336025522 ps
CPU time 13.04 seconds
Started Aug 06 04:27:34 PM PDT 24
Finished Aug 06 04:27:47 PM PDT 24
Peak memory 217324 kb
Host smart-f0d03acf-d504-46b6-a735-45449b096873
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355794190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.1355794190
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.2738855608
Short name T15
Test name
Test status
Simulation time 34352026 ps
CPU time 0.99 seconds
Started Aug 06 04:44:33 PM PDT 24
Finished Aug 06 04:44:34 PM PDT 24
Peak memory 207252 kb
Host smart-d624c214-7a73-427b-907a-869db466c409
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738855608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.2738855608
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.2623192951
Short name T133
Test name
Test status
Simulation time 438668655 ps
CPU time 9.63 seconds
Started Aug 06 04:27:48 PM PDT 24
Finished Aug 06 04:27:58 PM PDT 24
Peak memory 207772 kb
Host smart-dac1644d-9aa0-40fb-a397-5b688e994bba
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623192951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.2623192951
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.2661896938
Short name T134
Test name
Test status
Simulation time 6437959039 ps
CPU time 25 seconds
Started Aug 06 04:27:30 PM PDT 24
Finished Aug 06 04:27:56 PM PDT 24
Peak memory 207456 kb
Host smart-b8c74958-82a3-4cfd-a85c-1e8885e67b20
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661896938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.2661896938
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.714937101
Short name T80
Test name
Test status
Simulation time 58270291 ps
CPU time 3.92 seconds
Started Aug 06 04:27:19 PM PDT 24
Finished Aug 06 04:27:23 PM PDT 24
Peak memory 217308 kb
Host smart-2554fd15-7cd3-4562-ac87-e17eedb392f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714937101 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.714937101
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.1943503401
Short name T112
Test name
Test status
Simulation time 65746568 ps
CPU time 1.26 seconds
Started Aug 06 04:27:30 PM PDT 24
Finished Aug 06 04:27:32 PM PDT 24
Peak memory 215628 kb
Host smart-7a35b68f-a6df-40d2-aa5c-94d60826ac4f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943503401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.1
943503401
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2192681227
Short name T1120
Test name
Test status
Simulation time 12651078 ps
CPU time 0.78 seconds
Started Aug 06 04:27:23 PM PDT 24
Finished Aug 06 04:27:23 PM PDT 24
Peak memory 204128 kb
Host smart-8d8d5ed4-7c7b-4a69-bc61-cf01cc5b6a8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192681227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.2
192681227
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.3243809311
Short name T104
Test name
Test status
Simulation time 112416114 ps
CPU time 1.16 seconds
Started Aug 06 04:29:07 PM PDT 24
Finished Aug 06 04:29:08 PM PDT 24
Peak memory 215188 kb
Host smart-af79fc09-506f-4ae4-a3bc-998f025aad02
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243809311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.3243809311
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.356886752
Short name T1072
Test name
Test status
Simulation time 11634931 ps
CPU time 0.64 seconds
Started Aug 06 04:27:30 PM PDT 24
Finished Aug 06 04:27:30 PM PDT 24
Peak memory 204272 kb
Host smart-87fb296d-02ed-4738-8dc6-54ef5245035f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356886752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_mem
_walk.356886752
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1782585348
Short name T1036
Test name
Test status
Simulation time 219260528 ps
CPU time 2.86 seconds
Started Aug 06 04:27:37 PM PDT 24
Finished Aug 06 04:27:40 PM PDT 24
Peak memory 215616 kb
Host smart-03e94ab1-d52d-4fa6-a1b8-07c00956a44b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782585348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.1782585348
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.1217341053
Short name T92
Test name
Test status
Simulation time 355136284 ps
CPU time 2.29 seconds
Started Aug 06 04:29:08 PM PDT 24
Finished Aug 06 04:29:10 PM PDT 24
Peak memory 215592 kb
Host smart-c6f4b1ac-82f7-47a6-b184-8da9920b1b64
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217341053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.1
217341053
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.3802052952
Short name T1045
Test name
Test status
Simulation time 415675758 ps
CPU time 7.16 seconds
Started Aug 06 04:28:15 PM PDT 24
Finished Aug 06 04:28:23 PM PDT 24
Peak memory 207396 kb
Host smart-1f97bc75-82d8-4821-ba91-65121ae79fdc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802052952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.3802052952
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.1143366261
Short name T1148
Test name
Test status
Simulation time 2066595943 ps
CPU time 22.45 seconds
Started Aug 06 04:27:49 PM PDT 24
Finished Aug 06 04:28:12 PM PDT 24
Peak memory 207324 kb
Host smart-a5c1bc85-4262-4406-b3e7-db7d3fefe198
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143366261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.1143366261
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.287209107
Short name T63
Test name
Test status
Simulation time 56751563 ps
CPU time 0.93 seconds
Started Aug 06 04:28:01 PM PDT 24
Finished Aug 06 04:28:02 PM PDT 24
Peak memory 207140 kb
Host smart-d530889c-4a12-42b4-a4ea-b0321696c3c0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287209107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_hw_reset.287209107
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3157666988
Short name T1126
Test name
Test status
Simulation time 415801452 ps
CPU time 2.72 seconds
Started Aug 06 04:27:32 PM PDT 24
Finished Aug 06 04:27:35 PM PDT 24
Peak memory 217040 kb
Host smart-ac6c9cc9-48d7-473c-8d1a-d161f22c4418
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157666988 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.3157666988
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.609193690
Short name T1070
Test name
Test status
Simulation time 41983886 ps
CPU time 1.28 seconds
Started Aug 06 04:29:08 PM PDT 24
Finished Aug 06 04:29:12 PM PDT 24
Peak memory 215308 kb
Host smart-1fa85bef-c18c-4535-9a6d-da30f0ed37c1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609193690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.609193690
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.2008415924
Short name T1087
Test name
Test status
Simulation time 23102270 ps
CPU time 0.85 seconds
Started Aug 06 04:28:01 PM PDT 24
Finished Aug 06 04:28:02 PM PDT 24
Peak memory 204364 kb
Host smart-939038b3-10eb-4cd4-98e1-670efa92340a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008415924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.2
008415924
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2684797690
Short name T113
Test name
Test status
Simulation time 35159338 ps
CPU time 1.23 seconds
Started Aug 06 04:27:30 PM PDT 24
Finished Aug 06 04:27:32 PM PDT 24
Peak memory 215644 kb
Host smart-0aa2d904-76e8-4e3a-a746-41a47180dce1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684797690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.2684797690
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.416571912
Short name T1095
Test name
Test status
Simulation time 33765383 ps
CPU time 0.63 seconds
Started Aug 06 04:27:29 PM PDT 24
Finished Aug 06 04:27:30 PM PDT 24
Peak memory 204300 kb
Host smart-7f599830-ac53-4eeb-ad96-024bbb8c45f1
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416571912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_mem
_walk.416571912
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3519758224
Short name T1131
Test name
Test status
Simulation time 218099278 ps
CPU time 3.72 seconds
Started Aug 06 04:27:31 PM PDT 24
Finished Aug 06 04:27:35 PM PDT 24
Peak memory 215472 kb
Host smart-ba195e38-bf7c-4a63-8a94-7a488328288c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519758224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.3519758224
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.389887253
Short name T84
Test name
Test status
Simulation time 383664019 ps
CPU time 6.16 seconds
Started Aug 06 04:27:37 PM PDT 24
Finished Aug 06 04:27:44 PM PDT 24
Peak memory 215836 kb
Host smart-f2f9ad3f-8a8d-490e-8b05-7a3c107537ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389887253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_
tl_intg_err.389887253
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.4103003756
Short name T1149
Test name
Test status
Simulation time 585939177 ps
CPU time 3.39 seconds
Started Aug 06 04:27:48 PM PDT 24
Finished Aug 06 04:27:52 PM PDT 24
Peak memory 217568 kb
Host smart-c7ce0795-248b-4c48-9f1a-7360b434d180
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103003756 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.4103003756
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.932016087
Short name T1078
Test name
Test status
Simulation time 154063799 ps
CPU time 1.85 seconds
Started Aug 06 04:27:49 PM PDT 24
Finished Aug 06 04:27:51 PM PDT 24
Peak memory 215512 kb
Host smart-d7360f94-d00b-4277-98f1-57ad266cd04f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932016087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.932016087
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.3762825637
Short name T1047
Test name
Test status
Simulation time 48633351 ps
CPU time 0.74 seconds
Started Aug 06 04:27:50 PM PDT 24
Finished Aug 06 04:27:51 PM PDT 24
Peak memory 204104 kb
Host smart-c9b5cace-e7c8-4325-8af5-1d8e855670b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762825637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
3762825637
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.2038680381
Short name T1071
Test name
Test status
Simulation time 60615960 ps
CPU time 3.69 seconds
Started Aug 06 04:27:47 PM PDT 24
Finished Aug 06 04:27:50 PM PDT 24
Peak memory 215400 kb
Host smart-afbeaf06-4d34-41a9-9006-7229fc62da97
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038680381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.2038680381
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.1782128795
Short name T159
Test name
Test status
Simulation time 212841631 ps
CPU time 4.84 seconds
Started Aug 06 04:27:43 PM PDT 24
Finished Aug 06 04:27:48 PM PDT 24
Peak memory 215804 kb
Host smart-e119d1b1-2c09-4cd1-96d1-bdac9bf814b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782128795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
1782128795
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.1934677375
Short name T1089
Test name
Test status
Simulation time 291533462 ps
CPU time 6.93 seconds
Started Aug 06 04:27:44 PM PDT 24
Finished Aug 06 04:27:51 PM PDT 24
Peak memory 215588 kb
Host smart-6c345b26-4eb1-4fa2-973c-c390e093a9a1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934677375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.1934677375
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.511119213
Short name T99
Test name
Test status
Simulation time 86985718 ps
CPU time 2.64 seconds
Started Aug 06 04:27:50 PM PDT 24
Finished Aug 06 04:27:53 PM PDT 24
Peak memory 216600 kb
Host smart-ea30c9b1-a618-4f78-91ef-baeefa55a9b2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511119213 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.511119213
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.3368432551
Short name T1057
Test name
Test status
Simulation time 43079412 ps
CPU time 1.44 seconds
Started Aug 06 04:27:51 PM PDT 24
Finished Aug 06 04:27:52 PM PDT 24
Peak memory 207356 kb
Host smart-086a1f6a-fbc4-4703-9f80-fc2145437fa4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368432551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
3368432551
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.2943184294
Short name T1063
Test name
Test status
Simulation time 43643933 ps
CPU time 0.72 seconds
Started Aug 06 04:27:57 PM PDT 24
Finished Aug 06 04:27:58 PM PDT 24
Peak memory 204088 kb
Host smart-3051d932-3a8f-4211-8d73-8eaf2f77fbaf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943184294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
2943184294
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.856209042
Short name T1124
Test name
Test status
Simulation time 29629656 ps
CPU time 1.7 seconds
Started Aug 06 04:27:51 PM PDT 24
Finished Aug 06 04:27:52 PM PDT 24
Peak memory 215476 kb
Host smart-0833029b-86f2-4bb8-af51-01fe2861aae5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856209042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.s
pi_device_same_csr_outstanding.856209042
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.1593145430
Short name T1119
Test name
Test status
Simulation time 129752959 ps
CPU time 3.49 seconds
Started Aug 06 04:28:01 PM PDT 24
Finished Aug 06 04:28:04 PM PDT 24
Peak memory 215960 kb
Host smart-847fce98-df28-4b67-bc17-9fcfc79fda7d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593145430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
1593145430
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.2099018551
Short name T170
Test name
Test status
Simulation time 383681845 ps
CPU time 12.34 seconds
Started Aug 06 04:27:44 PM PDT 24
Finished Aug 06 04:27:56 PM PDT 24
Peak memory 215584 kb
Host smart-a9725ecd-dd28-4b5a-a658-e9e4e7f79d76
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099018551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.2099018551
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3838461219
Short name T1098
Test name
Test status
Simulation time 88854750 ps
CPU time 1.85 seconds
Started Aug 06 04:27:50 PM PDT 24
Finished Aug 06 04:27:52 PM PDT 24
Peak memory 215680 kb
Host smart-da3b42c4-1097-4bbb-b137-8f3339fa4a14
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838461219 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.3838461219
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.3345175013
Short name T107
Test name
Test status
Simulation time 33607559 ps
CPU time 1.77 seconds
Started Aug 06 04:27:51 PM PDT 24
Finished Aug 06 04:27:53 PM PDT 24
Peak memory 215536 kb
Host smart-f040876b-ad88-4bf0-ac69-f1d4ac86c7a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345175013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
3345175013
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.1953863924
Short name T1112
Test name
Test status
Simulation time 14459555 ps
CPU time 0.74 seconds
Started Aug 06 04:27:43 PM PDT 24
Finished Aug 06 04:27:44 PM PDT 24
Peak memory 204020 kb
Host smart-c7f85f32-fe4a-4c8b-a1a5-d78df342a6d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953863924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
1953863924
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.2568266743
Short name T1110
Test name
Test status
Simulation time 208540611 ps
CPU time 2.61 seconds
Started Aug 06 04:27:44 PM PDT 24
Finished Aug 06 04:27:47 PM PDT 24
Peak memory 215616 kb
Host smart-a329077f-0ff9-44f4-a7b5-d33bed7de20e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568266743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.2568266743
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.3333647893
Short name T1141
Test name
Test status
Simulation time 1005489172 ps
CPU time 5.8 seconds
Started Aug 06 04:27:50 PM PDT 24
Finished Aug 06 04:27:56 PM PDT 24
Peak memory 215488 kb
Host smart-a3e22503-db44-4566-8252-649a36e9a338
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333647893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.3333647893
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2167999797
Short name T94
Test name
Test status
Simulation time 135598259 ps
CPU time 3.93 seconds
Started Aug 06 04:27:50 PM PDT 24
Finished Aug 06 04:27:54 PM PDT 24
Peak memory 217608 kb
Host smart-777be326-cd48-4205-9ff6-f7ab2bd3c478
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167999797 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.2167999797
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.217187259
Short name T141
Test name
Test status
Simulation time 159881745 ps
CPU time 1.32 seconds
Started Aug 06 04:27:50 PM PDT 24
Finished Aug 06 04:27:52 PM PDT 24
Peak memory 207400 kb
Host smart-fedefed3-eaf7-4ba5-88b2-141f012afd7b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217187259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.217187259
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.1264369440
Short name T1060
Test name
Test status
Simulation time 27919841 ps
CPU time 0.75 seconds
Started Aug 06 04:27:49 PM PDT 24
Finished Aug 06 04:27:50 PM PDT 24
Peak memory 204276 kb
Host smart-b4300523-d9ee-42d3-af0f-909116d26ffb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264369440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
1264369440
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.2727165004
Short name T1040
Test name
Test status
Simulation time 518195326 ps
CPU time 3.16 seconds
Started Aug 06 04:27:47 PM PDT 24
Finished Aug 06 04:27:50 PM PDT 24
Peak memory 215532 kb
Host smart-32f0a0b3-d55c-4ffc-8795-83bdd6e51d94
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727165004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.2727165004
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.633537285
Short name T1115
Test name
Test status
Simulation time 33797385 ps
CPU time 1.96 seconds
Started Aug 06 04:27:46 PM PDT 24
Finished Aug 06 04:27:48 PM PDT 24
Peak memory 216784 kb
Host smart-41f630b4-496e-4acc-be64-9389faacf6dc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633537285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.633537285
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.860026631
Short name T166
Test name
Test status
Simulation time 548127516 ps
CPU time 7.2 seconds
Started Aug 06 04:27:50 PM PDT 24
Finished Aug 06 04:27:57 PM PDT 24
Peak memory 215400 kb
Host smart-3aae3179-6abf-41e2-b86e-37a962335af5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860026631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device
_tl_intg_err.860026631
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.1821020686
Short name T1103
Test name
Test status
Simulation time 174430577 ps
CPU time 1.78 seconds
Started Aug 06 04:27:47 PM PDT 24
Finished Aug 06 04:27:49 PM PDT 24
Peak memory 215572 kb
Host smart-09389488-2be3-4508-862f-f666a9e71f7d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821020686 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.1821020686
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.1588469995
Short name T128
Test name
Test status
Simulation time 129250845 ps
CPU time 1.26 seconds
Started Aug 06 04:28:04 PM PDT 24
Finished Aug 06 04:28:05 PM PDT 24
Peak memory 215580 kb
Host smart-ec5181c8-9dca-4c88-a4c8-ca8b6160910e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588469995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
1588469995
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.535960250
Short name T1048
Test name
Test status
Simulation time 14945027 ps
CPU time 0.69 seconds
Started Aug 06 04:27:45 PM PDT 24
Finished Aug 06 04:27:46 PM PDT 24
Peak memory 204400 kb
Host smart-08da6c13-d87a-437e-9fb1-601b40c9b71b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535960250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.535960250
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3132502740
Short name T1113
Test name
Test status
Simulation time 43788308 ps
CPU time 2.67 seconds
Started Aug 06 04:27:49 PM PDT 24
Finished Aug 06 04:27:52 PM PDT 24
Peak memory 215604 kb
Host smart-f15ca330-7ca1-4cb2-9223-86b2d9c77969
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132502740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.3132502740
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.2349538749
Short name T89
Test name
Test status
Simulation time 668866319 ps
CPU time 3.8 seconds
Started Aug 06 04:27:45 PM PDT 24
Finished Aug 06 04:27:49 PM PDT 24
Peak memory 215636 kb
Host smart-9f02db00-0c1f-4241-8cf3-5bd2c4af8977
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349538749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
2349538749
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.3495348464
Short name T1137
Test name
Test status
Simulation time 684541739 ps
CPU time 14.85 seconds
Started Aug 06 04:28:05 PM PDT 24
Finished Aug 06 04:28:20 PM PDT 24
Peak memory 215904 kb
Host smart-c2dc64ab-744a-43d5-b866-4fdd3c25cc20
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495348464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.3495348464
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1838026830
Short name T1067
Test name
Test status
Simulation time 38682453 ps
CPU time 2.69 seconds
Started Aug 06 04:27:51 PM PDT 24
Finished Aug 06 04:27:54 PM PDT 24
Peak memory 217756 kb
Host smart-530e82ee-2884-495a-9f3e-bb4b930caf99
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838026830 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.1838026830
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.2091463810
Short name T135
Test name
Test status
Simulation time 77408590 ps
CPU time 1.19 seconds
Started Aug 06 04:27:52 PM PDT 24
Finished Aug 06 04:27:53 PM PDT 24
Peak memory 207336 kb
Host smart-ba550950-52be-4dde-8b39-d559f75a4788
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091463810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
2091463810
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.2804054438
Short name T1039
Test name
Test status
Simulation time 18383599 ps
CPU time 0.79 seconds
Started Aug 06 04:27:45 PM PDT 24
Finished Aug 06 04:27:46 PM PDT 24
Peak memory 204100 kb
Host smart-d40bbed9-544f-47a4-9c9e-cec4176534b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804054438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
2804054438
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.1391914516
Short name T1058
Test name
Test status
Simulation time 62262389 ps
CPU time 3.79 seconds
Started Aug 06 04:27:50 PM PDT 24
Finished Aug 06 04:27:54 PM PDT 24
Peak memory 215524 kb
Host smart-e1988b2f-bf85-4087-a687-7d89ddfe7226
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391914516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.1391914516
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.284650059
Short name T1143
Test name
Test status
Simulation time 127052279 ps
CPU time 5.25 seconds
Started Aug 06 04:27:44 PM PDT 24
Finished Aug 06 04:27:50 PM PDT 24
Peak memory 215816 kb
Host smart-8d0f06b1-ff40-4db5-b6d3-3233d790d466
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284650059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.284650059
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.3838553690
Short name T1130
Test name
Test status
Simulation time 102060724 ps
CPU time 6.26 seconds
Started Aug 06 04:27:47 PM PDT 24
Finished Aug 06 04:27:53 PM PDT 24
Peak memory 215616 kb
Host smart-85a5eeed-9666-4c9f-9454-ecde5e8faa10
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838553690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.3838553690
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.2938668889
Short name T86
Test name
Test status
Simulation time 97070217 ps
CPU time 3.86 seconds
Started Aug 06 04:28:09 PM PDT 24
Finished Aug 06 04:28:18 PM PDT 24
Peak memory 218648 kb
Host smart-78855758-4fa7-4ad2-954c-b3a100ddfe0b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938668889 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.2938668889
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.561044931
Short name T1134
Test name
Test status
Simulation time 60776704 ps
CPU time 1.3 seconds
Started Aug 06 04:27:47 PM PDT 24
Finished Aug 06 04:27:48 PM PDT 24
Peak memory 215616 kb
Host smart-ab773cea-1585-453a-a6a4-b5bb43950b0e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561044931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.561044931
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.2221225994
Short name T1042
Test name
Test status
Simulation time 15047472 ps
CPU time 0.74 seconds
Started Aug 06 04:28:04 PM PDT 24
Finished Aug 06 04:28:05 PM PDT 24
Peak memory 204100 kb
Host smart-832ae7b4-4436-44ec-912c-bad09b049d8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221225994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
2221225994
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.165752464
Short name T1118
Test name
Test status
Simulation time 165401603 ps
CPU time 3.7 seconds
Started Aug 06 04:27:44 PM PDT 24
Finished Aug 06 04:27:48 PM PDT 24
Peak memory 215592 kb
Host smart-28f4c0d7-10ca-4d0c-9ab8-5fa0846fe0bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165752464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.s
pi_device_same_csr_outstanding.165752464
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.1139937665
Short name T1146
Test name
Test status
Simulation time 86478180 ps
CPU time 2.78 seconds
Started Aug 06 04:27:59 PM PDT 24
Finished Aug 06 04:28:02 PM PDT 24
Peak memory 215812 kb
Host smart-debc6288-6f79-4eb6-b304-40c459b2319a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139937665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
1139937665
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.4154271249
Short name T97
Test name
Test status
Simulation time 1455957784 ps
CPU time 3.34 seconds
Started Aug 06 04:28:04 PM PDT 24
Finished Aug 06 04:28:07 PM PDT 24
Peak memory 218288 kb
Host smart-ad602651-dec8-4fbd-8851-c0ba1f703830
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154271249 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.4154271249
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.3984567558
Short name T114
Test name
Test status
Simulation time 71030376 ps
CPU time 2.24 seconds
Started Aug 06 04:28:06 PM PDT 24
Finished Aug 06 04:28:09 PM PDT 24
Peak memory 215576 kb
Host smart-8b32a59a-d227-4b58-a4c2-f47ea380a965
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984567558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
3984567558
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.453038410
Short name T1051
Test name
Test status
Simulation time 41008576 ps
CPU time 0.79 seconds
Started Aug 06 04:27:46 PM PDT 24
Finished Aug 06 04:27:47 PM PDT 24
Peak memory 204076 kb
Host smart-7e579063-b453-48d3-b750-c94aae238915
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453038410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.453038410
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.969822257
Short name T1114
Test name
Test status
Simulation time 30055513 ps
CPU time 1.71 seconds
Started Aug 06 04:28:02 PM PDT 24
Finished Aug 06 04:28:04 PM PDT 24
Peak memory 215604 kb
Host smart-55f33079-f726-4d52-ad5b-8db46c4b3a59
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969822257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.s
pi_device_same_csr_outstanding.969822257
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.1346414700
Short name T1076
Test name
Test status
Simulation time 237423565 ps
CPU time 3.29 seconds
Started Aug 06 04:27:52 PM PDT 24
Finished Aug 06 04:27:55 PM PDT 24
Peak memory 215828 kb
Host smart-1442d1d2-772c-4499-9903-980675210c67
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346414700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
1346414700
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.3077466076
Short name T1139
Test name
Test status
Simulation time 2114799145 ps
CPU time 13.1 seconds
Started Aug 06 04:27:51 PM PDT 24
Finished Aug 06 04:28:04 PM PDT 24
Peak memory 215888 kb
Host smart-4b7fb441-03ad-411f-ad48-76611af3a6bf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077466076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.3077466076
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.3520126845
Short name T1081
Test name
Test status
Simulation time 143107986 ps
CPU time 2.5 seconds
Started Aug 06 04:28:00 PM PDT 24
Finished Aug 06 04:28:02 PM PDT 24
Peak memory 218060 kb
Host smart-9e61129a-e19b-434b-9078-b33a61969ddd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520126845 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.3520126845
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.2874645547
Short name T1142
Test name
Test status
Simulation time 225383916 ps
CPU time 2.63 seconds
Started Aug 06 04:28:05 PM PDT 24
Finished Aug 06 04:28:08 PM PDT 24
Peak memory 215604 kb
Host smart-085ccbbb-6f6c-4ab4-8b27-eda04e977f38
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874645547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
2874645547
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.1230398120
Short name T1093
Test name
Test status
Simulation time 29898741 ps
CPU time 0.68 seconds
Started Aug 06 04:28:17 PM PDT 24
Finished Aug 06 04:28:18 PM PDT 24
Peak memory 204092 kb
Host smart-84100d65-122f-4e65-8b1a-a12b52819408
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230398120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
1230398120
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.1829688124
Short name T127
Test name
Test status
Simulation time 739701233 ps
CPU time 3.47 seconds
Started Aug 06 04:27:56 PM PDT 24
Finished Aug 06 04:28:00 PM PDT 24
Peak memory 215604 kb
Host smart-c8ace096-afd1-4103-949b-c320dc0833da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829688124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.1829688124
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.825178878
Short name T1091
Test name
Test status
Simulation time 1148713535 ps
CPU time 2.12 seconds
Started Aug 06 04:28:12 PM PDT 24
Finished Aug 06 04:28:14 PM PDT 24
Peak memory 215788 kb
Host smart-313c5f4e-6ac0-4803-8a0f-e61ff2b4cc90
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825178878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.825178878
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.845837363
Short name T136
Test name
Test status
Simulation time 224954878 ps
CPU time 3.47 seconds
Started Aug 06 04:28:17 PM PDT 24
Finished Aug 06 04:28:21 PM PDT 24
Peak memory 218584 kb
Host smart-84463cf3-70b8-4027-9a0d-bfd7dc4671b2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845837363 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.845837363
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.958835965
Short name T108
Test name
Test status
Simulation time 19633404 ps
CPU time 1.23 seconds
Started Aug 06 04:28:12 PM PDT 24
Finished Aug 06 04:28:13 PM PDT 24
Peak memory 215536 kb
Host smart-4fe73a10-3094-4899-8cbe-bab44a2746ec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958835965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.958835965
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.2011363614
Short name T1066
Test name
Test status
Simulation time 11725459 ps
CPU time 0.68 seconds
Started Aug 06 04:28:12 PM PDT 24
Finished Aug 06 04:28:12 PM PDT 24
Peak memory 204444 kb
Host smart-dcfba415-c655-4ba7-ae56-80a01834ec5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011363614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
2011363614
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.2728589033
Short name T1059
Test name
Test status
Simulation time 240768113 ps
CPU time 3.68 seconds
Started Aug 06 04:28:11 PM PDT 24
Finished Aug 06 04:28:15 PM PDT 24
Peak memory 215988 kb
Host smart-5825f9ab-1202-402c-bb8b-7d105a205882
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728589033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.2728589033
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.1780288493
Short name T1106
Test name
Test status
Simulation time 152235430 ps
CPU time 5.13 seconds
Started Aug 06 04:27:58 PM PDT 24
Finished Aug 06 04:28:03 PM PDT 24
Peak memory 215932 kb
Host smart-4ec96cf8-fdbd-4f3c-8163-ca23483f206f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780288493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
1780288493
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.3572059904
Short name T85
Test name
Test status
Simulation time 1144144053 ps
CPU time 15.13 seconds
Started Aug 06 04:28:07 PM PDT 24
Finished Aug 06 04:28:22 PM PDT 24
Peak memory 215712 kb
Host smart-0102faee-3d69-4d7f-a874-1165468c6c93
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572059904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.3572059904
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.3821112696
Short name T1037
Test name
Test status
Simulation time 133548839 ps
CPU time 8.18 seconds
Started Aug 06 04:27:31 PM PDT 24
Finished Aug 06 04:27:39 PM PDT 24
Peak memory 215608 kb
Host smart-9c005632-580c-458a-aef8-e905f73e4cb7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821112696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.3821112696
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.3801373796
Short name T1055
Test name
Test status
Simulation time 4630717242 ps
CPU time 22.77 seconds
Started Aug 06 04:27:32 PM PDT 24
Finished Aug 06 04:27:55 PM PDT 24
Peak memory 207392 kb
Host smart-2efedf82-1fec-4dcb-8d77-72ca4d957de4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801373796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.3801373796
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1239787029
Short name T62
Test name
Test status
Simulation time 39178904 ps
CPU time 0.94 seconds
Started Aug 06 04:27:34 PM PDT 24
Finished Aug 06 04:27:35 PM PDT 24
Peak memory 206984 kb
Host smart-107d778f-20ac-4d0b-8d81-472f6c043d56
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239787029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.1239787029
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.1788690823
Short name T1083
Test name
Test status
Simulation time 40695823 ps
CPU time 2.66 seconds
Started Aug 06 04:27:31 PM PDT 24
Finished Aug 06 04:27:34 PM PDT 24
Peak memory 216932 kb
Host smart-ca031dbf-4903-41fb-b604-52787f16d871
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788690823 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.1788690823
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.51390279
Short name T106
Test name
Test status
Simulation time 970138658 ps
CPU time 2.61 seconds
Started Aug 06 04:27:34 PM PDT 24
Finished Aug 06 04:27:37 PM PDT 24
Peak memory 215400 kb
Host smart-88cdac63-5512-4da3-ae5e-34e5e0da2b01
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51390279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.51390279
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.3212350594
Short name T1079
Test name
Test status
Simulation time 14422603 ps
CPU time 0.68 seconds
Started Aug 06 04:27:37 PM PDT 24
Finished Aug 06 04:27:38 PM PDT 24
Peak memory 204424 kb
Host smart-70e6aa30-e5ae-4ea2-842b-c1884bdcbe09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212350594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.3
212350594
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2230642903
Short name T1117
Test name
Test status
Simulation time 419148160 ps
CPU time 1.3 seconds
Started Aug 06 04:27:34 PM PDT 24
Finished Aug 06 04:27:36 PM PDT 24
Peak memory 215556 kb
Host smart-3bb578c0-677c-4f54-b590-e0fec8492d56
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230642903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.2230642903
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.625232172
Short name T1034
Test name
Test status
Simulation time 11860413 ps
CPU time 0.69 seconds
Started Aug 06 04:27:33 PM PDT 24
Finished Aug 06 04:27:34 PM PDT 24
Peak memory 203736 kb
Host smart-a0a601e5-7b54-4c46-adab-07b5d678a95e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625232172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_mem
_walk.625232172
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1132971484
Short name T1109
Test name
Test status
Simulation time 353269308 ps
CPU time 3.91 seconds
Started Aug 06 04:27:40 PM PDT 24
Finished Aug 06 04:27:44 PM PDT 24
Peak memory 215600 kb
Host smart-243f952f-47d9-4a6d-9865-8a80b191dd60
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132971484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.1132971484
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1969798973
Short name T79
Test name
Test status
Simulation time 304406467 ps
CPU time 4.93 seconds
Started Aug 06 04:27:33 PM PDT 24
Finished Aug 06 04:27:38 PM PDT 24
Peak memory 215784 kb
Host smart-df45e598-b6f4-4ec3-b88c-cb0b45d324cf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969798973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.1
969798973
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.503792954
Short name T163
Test name
Test status
Simulation time 2577770023 ps
CPU time 21.65 seconds
Started Aug 06 04:27:31 PM PDT 24
Finished Aug 06 04:27:53 PM PDT 24
Peak memory 215764 kb
Host smart-7cdc749d-8e07-48e9-9720-08ed30bbc3cf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503792954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_
tl_intg_err.503792954
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.2925109038
Short name T1096
Test name
Test status
Simulation time 31057530 ps
CPU time 0.75 seconds
Started Aug 06 04:28:07 PM PDT 24
Finished Aug 06 04:28:08 PM PDT 24
Peak memory 204040 kb
Host smart-f108d4ca-739a-4b2b-92f0-bed4d1901ffa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925109038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
2925109038
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.4074771977
Short name T1108
Test name
Test status
Simulation time 11908230 ps
CPU time 0.7 seconds
Started Aug 06 04:28:14 PM PDT 24
Finished Aug 06 04:28:14 PM PDT 24
Peak memory 204092 kb
Host smart-f59bf09c-c71e-4cfd-ab41-7356d462cb82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074771977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
4074771977
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3280292762
Short name T1074
Test name
Test status
Simulation time 45850037 ps
CPU time 0.73 seconds
Started Aug 06 04:27:57 PM PDT 24
Finished Aug 06 04:27:58 PM PDT 24
Peak memory 204024 kb
Host smart-a20e8c3e-2aa1-4beb-a6ae-9f26f4c30084
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280292762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
3280292762
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.3993178662
Short name T1116
Test name
Test status
Simulation time 14124965 ps
CPU time 0.7 seconds
Started Aug 06 04:27:57 PM PDT 24
Finished Aug 06 04:27:58 PM PDT 24
Peak memory 204008 kb
Host smart-878fa74a-ec04-401b-9a46-7306c96650d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993178662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
3993178662
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1651600891
Short name T1035
Test name
Test status
Simulation time 26821365 ps
CPU time 0.7 seconds
Started Aug 06 04:27:56 PM PDT 24
Finished Aug 06 04:27:57 PM PDT 24
Peak memory 204120 kb
Host smart-e15c9889-a5d0-42a2-b457-b42b9e73c499
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651600891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
1651600891
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.3135482169
Short name T1053
Test name
Test status
Simulation time 11112820 ps
CPU time 0.71 seconds
Started Aug 06 04:28:02 PM PDT 24
Finished Aug 06 04:28:02 PM PDT 24
Peak memory 204428 kb
Host smart-b07beb0e-00d0-45e6-b430-0308524ee466
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135482169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
3135482169
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.3547645519
Short name T1068
Test name
Test status
Simulation time 102590465 ps
CPU time 0.74 seconds
Started Aug 06 04:28:12 PM PDT 24
Finished Aug 06 04:28:13 PM PDT 24
Peak memory 204116 kb
Host smart-22e23f0a-0200-4484-a0a9-af416502b66b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547645519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
3547645519
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.1182015281
Short name T1092
Test name
Test status
Simulation time 12601439 ps
CPU time 0.73 seconds
Started Aug 06 04:28:01 PM PDT 24
Finished Aug 06 04:28:02 PM PDT 24
Peak memory 204412 kb
Host smart-4d7ff3f9-5d98-48d1-adb4-b290b656ae9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182015281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
1182015281
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.827821714
Short name T1135
Test name
Test status
Simulation time 24047818 ps
CPU time 0.74 seconds
Started Aug 06 04:28:17 PM PDT 24
Finished Aug 06 04:28:17 PM PDT 24
Peak memory 204108 kb
Host smart-e77a49f1-46a3-4804-8b19-1878a07f2aae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827821714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.827821714
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.1576476011
Short name T1080
Test name
Test status
Simulation time 14874815 ps
CPU time 0.71 seconds
Started Aug 06 04:28:12 PM PDT 24
Finished Aug 06 04:28:13 PM PDT 24
Peak memory 204080 kb
Host smart-ee133995-c5a2-442f-b434-4c093a7b4870
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576476011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
1576476011
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.3212312792
Short name T105
Test name
Test status
Simulation time 453505919 ps
CPU time 7.42 seconds
Started Aug 06 04:27:28 PM PDT 24
Finished Aug 06 04:27:36 PM PDT 24
Peak memory 207348 kb
Host smart-0451c37f-9f12-4c14-88fb-067554d6937f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212312792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.3212312792
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1063408512
Short name T1056
Test name
Test status
Simulation time 1044914511 ps
CPU time 11.21 seconds
Started Aug 06 04:27:37 PM PDT 24
Finished Aug 06 04:27:49 PM PDT 24
Peak memory 207276 kb
Host smart-7ef978a9-4ca8-4f85-a829-b83249d05673
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063408512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.1063408512
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.2677082345
Short name T64
Test name
Test status
Simulation time 151063232 ps
CPU time 1.17 seconds
Started Aug 06 04:27:39 PM PDT 24
Finished Aug 06 04:27:40 PM PDT 24
Peak memory 207376 kb
Host smart-42507ea1-b710-4a74-9ae0-0ad5e9c59607
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677082345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.2677082345
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2621388418
Short name T140
Test name
Test status
Simulation time 741861105 ps
CPU time 1.73 seconds
Started Aug 06 04:27:32 PM PDT 24
Finished Aug 06 04:27:34 PM PDT 24
Peak memory 215616 kb
Host smart-10dd69c2-0c51-4b35-bb1c-526a9d96832c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621388418 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.2621388418
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.1770083548
Short name T1054
Test name
Test status
Simulation time 23085835 ps
CPU time 0.72 seconds
Started Aug 06 04:27:40 PM PDT 24
Finished Aug 06 04:27:41 PM PDT 24
Peak memory 203992 kb
Host smart-89d5a577-7876-4cb2-ac15-9072d7c9b1f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770083548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.1
770083548
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.2458039133
Short name T103
Test name
Test status
Simulation time 101182939 ps
CPU time 1.89 seconds
Started Aug 06 04:27:31 PM PDT 24
Finished Aug 06 04:27:33 PM PDT 24
Peak memory 215488 kb
Host smart-7fd4ba4b-4a20-415e-ba6d-b20a879e1f50
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458039133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.2458039133
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.3108967721
Short name T1088
Test name
Test status
Simulation time 20395325 ps
CPU time 0.69 seconds
Started Aug 06 04:27:33 PM PDT 24
Finished Aug 06 04:27:34 PM PDT 24
Peak memory 203748 kb
Host smart-16d2a573-51bd-4d01-b821-95a339263603
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108967721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.3108967721
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.1554297183
Short name T1073
Test name
Test status
Simulation time 61259480 ps
CPU time 1.85 seconds
Started Aug 06 04:27:34 PM PDT 24
Finished Aug 06 04:27:37 PM PDT 24
Peak memory 215524 kb
Host smart-9886991d-d086-46d6-8bf2-c22368da34ad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554297183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.1554297183
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.2395242196
Short name T1122
Test name
Test status
Simulation time 155508040 ps
CPU time 3.87 seconds
Started Aug 06 04:27:30 PM PDT 24
Finished Aug 06 04:27:34 PM PDT 24
Peak memory 215880 kb
Host smart-58d0f7ea-1387-4933-980c-760fddc7f9ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395242196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.2
395242196
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.1116330631
Short name T1145
Test name
Test status
Simulation time 1123760012 ps
CPU time 14.93 seconds
Started Aug 06 04:27:34 PM PDT 24
Finished Aug 06 04:27:49 PM PDT 24
Peak memory 216016 kb
Host smart-d71c02d5-736a-4f87-aee5-11badc26740a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116330631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.1116330631
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.3168650257
Short name T1050
Test name
Test status
Simulation time 15902909 ps
CPU time 0.73 seconds
Started Aug 06 04:28:11 PM PDT 24
Finished Aug 06 04:28:12 PM PDT 24
Peak memory 204084 kb
Host smart-b196ec1f-d048-44ce-af0b-4110fb9bdeda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168650257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
3168650257
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.3167249851
Short name T1132
Test name
Test status
Simulation time 28324825 ps
CPU time 0.78 seconds
Started Aug 06 04:28:08 PM PDT 24
Finished Aug 06 04:28:08 PM PDT 24
Peak memory 204108 kb
Host smart-7cdc1c49-d44c-47d5-845c-d23455402dd5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167249851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
3167249851
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.780091676
Short name T1147
Test name
Test status
Simulation time 34234471 ps
CPU time 0.73 seconds
Started Aug 06 04:28:00 PM PDT 24
Finished Aug 06 04:28:01 PM PDT 24
Peak memory 204072 kb
Host smart-54cd6727-314d-4982-bfc1-60db24566f51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780091676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.780091676
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.1428459552
Short name T1144
Test name
Test status
Simulation time 22969373 ps
CPU time 0.69 seconds
Started Aug 06 04:28:10 PM PDT 24
Finished Aug 06 04:28:11 PM PDT 24
Peak memory 204076 kb
Host smart-d4c4fb65-57fa-4130-8473-5cccb804eee3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428459552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
1428459552
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.3980015229
Short name T1128
Test name
Test status
Simulation time 50089057 ps
CPU time 0.7 seconds
Started Aug 06 04:28:12 PM PDT 24
Finished Aug 06 04:28:13 PM PDT 24
Peak memory 204084 kb
Host smart-71125505-7b73-4292-b71d-0e50b58b48f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980015229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
3980015229
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.2756042471
Short name T1052
Test name
Test status
Simulation time 18204650 ps
CPU time 0.75 seconds
Started Aug 06 04:28:05 PM PDT 24
Finished Aug 06 04:28:06 PM PDT 24
Peak memory 204116 kb
Host smart-c94be915-1a0e-4c84-b25a-068712948945
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756042471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
2756042471
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.1893053890
Short name T1094
Test name
Test status
Simulation time 24496338 ps
CPU time 0.67 seconds
Started Aug 06 04:28:09 PM PDT 24
Finished Aug 06 04:28:10 PM PDT 24
Peak memory 204436 kb
Host smart-8b3e98a3-351b-4df1-a14b-89ab90992137
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893053890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
1893053890
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.247959896
Short name T1043
Test name
Test status
Simulation time 22040861 ps
CPU time 0.74 seconds
Started Aug 06 04:28:07 PM PDT 24
Finished Aug 06 04:28:08 PM PDT 24
Peak memory 204080 kb
Host smart-2a950543-2f23-4c2c-b485-e291e5535896
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247959896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.247959896
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.2288072978
Short name T1046
Test name
Test status
Simulation time 25055528 ps
CPU time 0.74 seconds
Started Aug 06 04:28:09 PM PDT 24
Finished Aug 06 04:28:10 PM PDT 24
Peak memory 204108 kb
Host smart-f7126b5d-1d06-4f33-8c19-d74124301848
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288072978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
2288072978
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.1166570775
Short name T1111
Test name
Test status
Simulation time 99894398 ps
CPU time 0.66 seconds
Started Aug 06 04:28:08 PM PDT 24
Finished Aug 06 04:28:08 PM PDT 24
Peak memory 204076 kb
Host smart-9a132727-4360-4a03-8162-d1cc965e6898
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166570775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
1166570775
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.2020587492
Short name T111
Test name
Test status
Simulation time 4137303966 ps
CPU time 16.72 seconds
Started Aug 06 04:27:31 PM PDT 24
Finished Aug 06 04:27:48 PM PDT 24
Peak memory 215568 kb
Host smart-9ea0404a-c667-4d3f-81c6-526796dfab10
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020587492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.2020587492
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3161055849
Short name T1123
Test name
Test status
Simulation time 590696398 ps
CPU time 22.77 seconds
Started Aug 06 04:27:35 PM PDT 24
Finished Aug 06 04:27:58 PM PDT 24
Peak memory 207344 kb
Host smart-47a18d32-d04f-41f7-980b-c920dae70a6a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161055849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.3161055849
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3693043410
Short name T1105
Test name
Test status
Simulation time 112463655 ps
CPU time 1.18 seconds
Started Aug 06 04:27:39 PM PDT 24
Finished Aug 06 04:27:40 PM PDT 24
Peak memory 207712 kb
Host smart-4fa64605-7360-472b-83aa-e54d86810036
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693043410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.3693043410
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3247874624
Short name T1062
Test name
Test status
Simulation time 41194505 ps
CPU time 3.01 seconds
Started Aug 06 04:27:31 PM PDT 24
Finished Aug 06 04:27:34 PM PDT 24
Peak memory 216684 kb
Host smart-15463659-d4ae-4940-b709-8536a87f93ce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247874624 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.3247874624
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.3635101584
Short name T101
Test name
Test status
Simulation time 32074649 ps
CPU time 1.87 seconds
Started Aug 06 04:27:40 PM PDT 24
Finished Aug 06 04:27:42 PM PDT 24
Peak memory 215588 kb
Host smart-b85c7360-8cc1-4785-949c-9b6fd0e91cb1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635101584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.3
635101584
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3510152914
Short name T1102
Test name
Test status
Simulation time 17930745 ps
CPU time 0.77 seconds
Started Aug 06 04:27:32 PM PDT 24
Finished Aug 06 04:27:33 PM PDT 24
Peak memory 203968 kb
Host smart-fa62dfa5-2902-4627-a120-c60bf19a8c89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510152914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.3
510152914
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.4087508245
Short name T109
Test name
Test status
Simulation time 162213769 ps
CPU time 1.41 seconds
Started Aug 06 04:27:31 PM PDT 24
Finished Aug 06 04:27:32 PM PDT 24
Peak memory 215516 kb
Host smart-4988eb0d-a641-440c-b74f-03d05b7ea4de
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087508245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.4087508245
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.2290780074
Short name T1104
Test name
Test status
Simulation time 13695147 ps
CPU time 0.69 seconds
Started Aug 06 04:27:32 PM PDT 24
Finished Aug 06 04:27:33 PM PDT 24
Peak memory 203940 kb
Host smart-43de3681-cc57-4502-8cf1-11f7ae1f3d8a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290780074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.2290780074
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.147661535
Short name T1069
Test name
Test status
Simulation time 97502331 ps
CPU time 3.53 seconds
Started Aug 06 04:28:28 PM PDT 24
Finished Aug 06 04:28:32 PM PDT 24
Peak memory 215580 kb
Host smart-43970938-f418-4f89-b5e4-a55a1876e8b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147661535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sp
i_device_same_csr_outstanding.147661535
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.835064848
Short name T95
Test name
Test status
Simulation time 497461418 ps
CPU time 3.67 seconds
Started Aug 06 04:27:32 PM PDT 24
Finished Aug 06 04:27:36 PM PDT 24
Peak memory 215648 kb
Host smart-33e3341a-2339-4d9f-8c8f-dcba2a43b021
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835064848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.835064848
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.3137193984
Short name T168
Test name
Test status
Simulation time 110284319 ps
CPU time 7.03 seconds
Started Aug 06 04:27:34 PM PDT 24
Finished Aug 06 04:27:42 PM PDT 24
Peak memory 215552 kb
Host smart-4830d405-7c5e-4048-9735-bb8e8f178dd4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137193984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.3137193984
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.3410625545
Short name T1129
Test name
Test status
Simulation time 11316970 ps
CPU time 0.76 seconds
Started Aug 06 04:28:16 PM PDT 24
Finished Aug 06 04:28:17 PM PDT 24
Peak memory 204108 kb
Host smart-890bea17-ac7f-4d82-9457-9ec7e35c517d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410625545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
3410625545
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.146740605
Short name T1061
Test name
Test status
Simulation time 19251775 ps
CPU time 0.74 seconds
Started Aug 06 04:28:09 PM PDT 24
Finished Aug 06 04:28:10 PM PDT 24
Peak memory 204448 kb
Host smart-96d42757-90d7-4a30-90ed-2523f7c396dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146740605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.146740605
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.1107689740
Short name T1127
Test name
Test status
Simulation time 19153736 ps
CPU time 0.76 seconds
Started Aug 06 04:28:07 PM PDT 24
Finished Aug 06 04:28:08 PM PDT 24
Peak memory 204104 kb
Host smart-094cb70f-4f4c-4901-ad3d-57a1750db9cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107689740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
1107689740
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.2550767606
Short name T1125
Test name
Test status
Simulation time 18087849 ps
CPU time 0.76 seconds
Started Aug 06 04:28:02 PM PDT 24
Finished Aug 06 04:28:02 PM PDT 24
Peak memory 204104 kb
Host smart-915c1de6-5281-4ddf-accf-1ab190da90fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550767606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
2550767606
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.205284722
Short name T1041
Test name
Test status
Simulation time 17695805 ps
CPU time 0.81 seconds
Started Aug 06 04:27:58 PM PDT 24
Finished Aug 06 04:27:59 PM PDT 24
Peak memory 204544 kb
Host smart-73e505bb-931a-4a0f-8993-fecdcf1c4b4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205284722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.205284722
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3022943604
Short name T1086
Test name
Test status
Simulation time 33038540 ps
CPU time 0.68 seconds
Started Aug 06 04:28:10 PM PDT 24
Finished Aug 06 04:28:10 PM PDT 24
Peak memory 204104 kb
Host smart-261883e7-2f77-4deb-acc8-ed13b7efbb27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022943604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
3022943604
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.633487052
Short name T1136
Test name
Test status
Simulation time 24198503 ps
CPU time 0.73 seconds
Started Aug 06 04:28:09 PM PDT 24
Finished Aug 06 04:28:10 PM PDT 24
Peak memory 204124 kb
Host smart-2c10931e-b70a-403c-ac5c-4bb1da779260
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633487052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.633487052
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.1562652155
Short name T1084
Test name
Test status
Simulation time 32472264 ps
CPU time 0.74 seconds
Started Aug 06 04:28:04 PM PDT 24
Finished Aug 06 04:28:05 PM PDT 24
Peak memory 204120 kb
Host smart-3259c73d-de53-4ebd-b37b-51af0d56e87b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562652155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
1562652155
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2028339775
Short name T1082
Test name
Test status
Simulation time 11352669 ps
CPU time 0.79 seconds
Started Aug 06 04:28:04 PM PDT 24
Finished Aug 06 04:28:05 PM PDT 24
Peak memory 204044 kb
Host smart-30e4a2fa-972f-43a2-9891-1ab002fc5f2a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028339775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
2028339775
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.404185506
Short name T1044
Test name
Test status
Simulation time 13852426 ps
CPU time 0.74 seconds
Started Aug 06 04:28:09 PM PDT 24
Finished Aug 06 04:28:10 PM PDT 24
Peak memory 204448 kb
Host smart-3e550587-dca4-440b-a1be-f4ccf68bd2a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404185506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.404185506
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.3781511658
Short name T1107
Test name
Test status
Simulation time 882510479 ps
CPU time 2.64 seconds
Started Aug 06 04:27:36 PM PDT 24
Finished Aug 06 04:27:38 PM PDT 24
Peak memory 218336 kb
Host smart-0586afd7-c373-484c-9822-4d4358843a41
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781511658 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.3781511658
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.2872075622
Short name T110
Test name
Test status
Simulation time 79100787 ps
CPU time 2.34 seconds
Started Aug 06 04:27:37 PM PDT 24
Finished Aug 06 04:27:40 PM PDT 24
Peak memory 215540 kb
Host smart-ebbc3edf-0fb2-432d-8a5e-2ffb3465b36b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872075622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.2
872075622
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.833917803
Short name T1133
Test name
Test status
Simulation time 30490490 ps
CPU time 0.69 seconds
Started Aug 06 04:28:15 PM PDT 24
Finished Aug 06 04:28:15 PM PDT 24
Peak memory 203908 kb
Host smart-4f4d24ea-90ed-456e-a457-73ad3d1a3e40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833917803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.833917803
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.3410310455
Short name T1064
Test name
Test status
Simulation time 63426493 ps
CPU time 4.24 seconds
Started Aug 06 04:27:34 PM PDT 24
Finished Aug 06 04:27:38 PM PDT 24
Peak memory 215400 kb
Host smart-45e5829e-3d85-4d54-9ea2-3112b007511d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410310455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.3410310455
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.1784294552
Short name T82
Test name
Test status
Simulation time 59301836 ps
CPU time 1.77 seconds
Started Aug 06 04:27:32 PM PDT 24
Finished Aug 06 04:27:34 PM PDT 24
Peak memory 215880 kb
Host smart-d9c155c2-546a-40f2-b243-04c190a5b077
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784294552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.1
784294552
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.113059957
Short name T1065
Test name
Test status
Simulation time 83723696 ps
CPU time 1.38 seconds
Started Aug 06 04:27:45 PM PDT 24
Finished Aug 06 04:27:46 PM PDT 24
Peak memory 215304 kb
Host smart-f3b014d8-4159-451c-b2ca-36d13e1a7217
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113059957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.113059957
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.1861711752
Short name T1049
Test name
Test status
Simulation time 47095497 ps
CPU time 0.79 seconds
Started Aug 06 04:27:50 PM PDT 24
Finished Aug 06 04:27:51 PM PDT 24
Peak memory 204088 kb
Host smart-82cc8e12-3e15-4bac-a462-72a95c02b4c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861711752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.1
861711752
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.1572721443
Short name T137
Test name
Test status
Simulation time 78814645 ps
CPU time 2.15 seconds
Started Aug 06 04:27:46 PM PDT 24
Finished Aug 06 04:27:48 PM PDT 24
Peak memory 215600 kb
Host smart-3ba6a4c9-b148-4019-9971-e3dfd7f6bf8d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572721443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.1572721443
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.426682717
Short name T171
Test name
Test status
Simulation time 296721117 ps
CPU time 18.51 seconds
Started Aug 06 04:27:47 PM PDT 24
Finished Aug 06 04:28:05 PM PDT 24
Peak memory 215472 kb
Host smart-99ce52ad-9aa3-4e20-882d-276326ae0502
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426682717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_
tl_intg_err.426682717
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3892658805
Short name T139
Test name
Test status
Simulation time 798221396 ps
CPU time 3.82 seconds
Started Aug 06 04:27:47 PM PDT 24
Finished Aug 06 04:27:51 PM PDT 24
Peak memory 217712 kb
Host smart-2ac5c9de-a7da-4331-85cf-7b50091aaf34
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892658805 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.3892658805
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.2087257444
Short name T1075
Test name
Test status
Simulation time 22745503 ps
CPU time 1.45 seconds
Started Aug 06 04:27:50 PM PDT 24
Finished Aug 06 04:27:51 PM PDT 24
Peak memory 215572 kb
Host smart-d54c10c0-6980-41f3-8734-d275a1b442dc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087257444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.2
087257444
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.1930428869
Short name T1038
Test name
Test status
Simulation time 13072056 ps
CPU time 0.73 seconds
Started Aug 06 04:27:50 PM PDT 24
Finished Aug 06 04:27:51 PM PDT 24
Peak memory 204080 kb
Host smart-957194a9-36fb-4579-88e9-3bf49d5c0a76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930428869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.1
930428869
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.3482167168
Short name T1101
Test name
Test status
Simulation time 284199670 ps
CPU time 1.61 seconds
Started Aug 06 04:27:47 PM PDT 24
Finished Aug 06 04:27:49 PM PDT 24
Peak memory 215996 kb
Host smart-323a98b6-9f6b-49de-90aa-871a696bbe75
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482167168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.3482167168
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.1059610618
Short name T96
Test name
Test status
Simulation time 197011120 ps
CPU time 5.08 seconds
Started Aug 06 04:27:50 PM PDT 24
Finished Aug 06 04:28:00 PM PDT 24
Peak memory 215724 kb
Host smart-b39daea3-e380-439f-bcf5-008919b4ca51
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059610618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.1
059610618
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.2233012643
Short name T165
Test name
Test status
Simulation time 307211425 ps
CPU time 16.07 seconds
Started Aug 06 04:27:48 PM PDT 24
Finished Aug 06 04:28:05 PM PDT 24
Peak memory 215964 kb
Host smart-95aef7ad-f5ec-4ee6-a5ba-4c017c9a508a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233012643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.2233012643
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.1233607685
Short name T1121
Test name
Test status
Simulation time 206021701 ps
CPU time 1.69 seconds
Started Aug 06 04:27:57 PM PDT 24
Finished Aug 06 04:27:58 PM PDT 24
Peak memory 215816 kb
Host smart-74a2d74a-36a2-423c-b265-34c0bf1efcc6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233607685 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.1233607685
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.1124905012
Short name T1097
Test name
Test status
Simulation time 96690770 ps
CPU time 1.33 seconds
Started Aug 06 04:28:04 PM PDT 24
Finished Aug 06 04:28:05 PM PDT 24
Peak memory 207324 kb
Host smart-b2fea9d8-c39e-4aa8-80e4-877de38870f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124905012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.1
124905012
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.1163624221
Short name T1090
Test name
Test status
Simulation time 28713845 ps
CPU time 0.71 seconds
Started Aug 06 04:27:47 PM PDT 24
Finished Aug 06 04:27:48 PM PDT 24
Peak memory 204428 kb
Host smart-8e96d4ea-e299-48d4-8e54-a9832c5e7d78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163624221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.1
163624221
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.1540883009
Short name T1140
Test name
Test status
Simulation time 339809230 ps
CPU time 3.78 seconds
Started Aug 06 04:27:48 PM PDT 24
Finished Aug 06 04:27:51 PM PDT 24
Peak memory 215588 kb
Host smart-d8c0b748-1bf6-44c3-af59-94e5237a80b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540883009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.1540883009
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.1801722918
Short name T1100
Test name
Test status
Simulation time 1719257699 ps
CPU time 2.9 seconds
Started Aug 06 04:27:52 PM PDT 24
Finished Aug 06 04:27:55 PM PDT 24
Peak memory 215812 kb
Host smart-52844704-9473-4441-a38c-257234dcb039
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801722918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.1
801722918
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.3330350776
Short name T164
Test name
Test status
Simulation time 304870966 ps
CPU time 17.95 seconds
Started Aug 06 04:27:50 PM PDT 24
Finished Aug 06 04:28:09 PM PDT 24
Peak memory 215572 kb
Host smart-bf195c74-9738-411f-aafb-45a4e8fd71a2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330350776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.3330350776
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.223194258
Short name T1138
Test name
Test status
Simulation time 113154881 ps
CPU time 2.76 seconds
Started Aug 06 04:27:50 PM PDT 24
Finished Aug 06 04:27:53 PM PDT 24
Peak memory 216608 kb
Host smart-f18ca606-2826-404a-90f1-b4f2c9935612
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223194258 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.223194258
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.3474966741
Short name T1099
Test name
Test status
Simulation time 164772853 ps
CPU time 2.43 seconds
Started Aug 06 04:27:44 PM PDT 24
Finished Aug 06 04:27:46 PM PDT 24
Peak memory 215544 kb
Host smart-5c691b72-2435-4e5d-8fdd-752c2e9bd2dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474966741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.3
474966741
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.2204896499
Short name T1077
Test name
Test status
Simulation time 63436571 ps
CPU time 0.81 seconds
Started Aug 06 04:27:46 PM PDT 24
Finished Aug 06 04:27:47 PM PDT 24
Peak memory 204120 kb
Host smart-79c8db75-70a5-47df-9418-f1f3c8eff2b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204896499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.2
204896499
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2109610052
Short name T138
Test name
Test status
Simulation time 73870582 ps
CPU time 1.81 seconds
Started Aug 06 04:27:48 PM PDT 24
Finished Aug 06 04:27:50 PM PDT 24
Peak memory 215540 kb
Host smart-ed093c7c-79de-4b68-8fb3-14176fcde583
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109610052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.2109610052
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.3118170373
Short name T90
Test name
Test status
Simulation time 2140870849 ps
CPU time 3.83 seconds
Started Aug 06 04:27:50 PM PDT 24
Finished Aug 06 04:27:54 PM PDT 24
Peak memory 215796 kb
Host smart-f72c7de6-7743-4682-b91a-c4c5e6e091ed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118170373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.3
118170373
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.2919429934
Short name T169
Test name
Test status
Simulation time 226584776 ps
CPU time 6.91 seconds
Started Aug 06 04:27:45 PM PDT 24
Finished Aug 06 04:27:52 PM PDT 24
Peak memory 215612 kb
Host smart-f49fb5aa-93c8-4233-8a6d-2063ed269a34
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919429934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.2919429934
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.2002505480
Short name T785
Test name
Test status
Simulation time 21799821 ps
CPU time 0.72 seconds
Started Aug 06 04:44:10 PM PDT 24
Finished Aug 06 04:44:11 PM PDT 24
Peak memory 206020 kb
Host smart-0694fc6d-d53e-4472-b2fa-f9b5231f773f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002505480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.2
002505480
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.1489467753
Short name T983
Test name
Test status
Simulation time 417059503 ps
CPU time 2.36 seconds
Started Aug 06 04:44:12 PM PDT 24
Finished Aug 06 04:44:15 PM PDT 24
Peak memory 225084 kb
Host smart-91cf289f-5aa4-42ef-9dcd-ace7d4a16afd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489467753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.1489467753
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.3404038139
Short name T579
Test name
Test status
Simulation time 12321811 ps
CPU time 0.75 seconds
Started Aug 06 04:44:23 PM PDT 24
Finished Aug 06 04:44:24 PM PDT 24
Peak memory 205428 kb
Host smart-60b89f68-0280-4d40-9500-44de6ac7ff01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404038139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.3404038139
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.1941144509
Short name T773
Test name
Test status
Simulation time 138311245527 ps
CPU time 243.06 seconds
Started Aug 06 04:44:17 PM PDT 24
Finished Aug 06 04:48:20 PM PDT 24
Peak memory 251956 kb
Host smart-bddb9172-5af2-4a7f-837b-f4800742f83d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941144509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.1941144509
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.3502817423
Short name T290
Test name
Test status
Simulation time 23513247153 ps
CPU time 235.14 seconds
Started Aug 06 04:44:09 PM PDT 24
Finished Aug 06 04:48:05 PM PDT 24
Peak memory 252908 kb
Host smart-c7500992-7cf6-4e05-bc95-a0b345fe52ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502817423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.3502817423
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.3234196813
Short name T259
Test name
Test status
Simulation time 20697222342 ps
CPU time 160.55 seconds
Started Aug 06 04:44:17 PM PDT 24
Finished Aug 06 04:46:58 PM PDT 24
Peak memory 255380 kb
Host smart-3d0f8c37-f692-4137-bdef-0fd82381bdda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234196813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.3234196813
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.2665673714
Short name T115
Test name
Test status
Simulation time 3134895165 ps
CPU time 11.62 seconds
Started Aug 06 04:44:16 PM PDT 24
Finished Aug 06 04:44:28 PM PDT 24
Peak memory 233364 kb
Host smart-2a3e96c4-e988-494a-b5f4-1e7613c1646d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665673714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.2665673714
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.3742648202
Short name T547
Test name
Test status
Simulation time 13822713 ps
CPU time 0.76 seconds
Started Aug 06 04:44:17 PM PDT 24
Finished Aug 06 04:44:17 PM PDT 24
Peak memory 216296 kb
Host smart-a3fb1169-12fd-4bf4-8195-70f9b3a1bf48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742648202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds
.3742648202
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_intercept.38166887
Short name T548
Test name
Test status
Simulation time 4826659745 ps
CPU time 14 seconds
Started Aug 06 04:44:16 PM PDT 24
Finished Aug 06 04:44:30 PM PDT 24
Peak memory 225172 kb
Host smart-e040fd51-feee-4e6f-8131-5f845e715387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38166887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.38166887
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.1559593711
Short name T868
Test name
Test status
Simulation time 6978568561 ps
CPU time 14.12 seconds
Started Aug 06 04:44:14 PM PDT 24
Finished Aug 06 04:44:28 PM PDT 24
Peak memory 233360 kb
Host smart-2717d09b-3d37-4880-bc6f-323d7470b519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559593711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.1559593711
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.2836588583
Short name T862
Test name
Test status
Simulation time 67510724 ps
CPU time 1.04 seconds
Started Aug 06 04:44:13 PM PDT 24
Finished Aug 06 04:44:14 PM PDT 24
Peak memory 218356 kb
Host smart-4d65d91b-b642-4c97-ab51-a6e9c657130b
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836588583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.spi_device_mem_parity.2836588583
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.1240267937
Short name T252
Test name
Test status
Simulation time 1793543134 ps
CPU time 6.37 seconds
Started Aug 06 04:44:09 PM PDT 24
Finished Aug 06 04:44:16 PM PDT 24
Peak memory 225100 kb
Host smart-8f7dcccf-e8bb-4a24-ae15-514304718672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240267937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.1240267937
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.2549449847
Short name T863
Test name
Test status
Simulation time 3628874461 ps
CPU time 11.17 seconds
Started Aug 06 04:44:20 PM PDT 24
Finished Aug 06 04:44:31 PM PDT 24
Peak memory 233384 kb
Host smart-23c35212-8b5f-440b-b227-a534707f9dbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549449847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.2549449847
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.902616961
Short name T619
Test name
Test status
Simulation time 1113806196 ps
CPU time 9.02 seconds
Started Aug 06 04:44:17 PM PDT 24
Finished Aug 06 04:44:26 PM PDT 24
Peak memory 221116 kb
Host smart-3cc00289-0839-49ab-9f1f-bc318ba20bec
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=902616961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_direc
t.902616961
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.4040930617
Short name T65
Test name
Test status
Simulation time 1670449876 ps
CPU time 22.65 seconds
Started Aug 06 04:44:16 PM PDT 24
Finished Aug 06 04:44:39 PM PDT 24
Peak memory 216856 kb
Host smart-5cc13162-860d-476c-b73d-df388007dd87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040930617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.4040930617
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.2198586571
Short name T335
Test name
Test status
Simulation time 13680700 ps
CPU time 0.72 seconds
Started Aug 06 04:44:11 PM PDT 24
Finished Aug 06 04:44:12 PM PDT 24
Peak memory 206132 kb
Host smart-d6f314d0-67e4-4ab7-bc35-b7902ed3dff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198586571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.2198586571
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.801313149
Short name T799
Test name
Test status
Simulation time 60635308 ps
CPU time 1.03 seconds
Started Aug 06 04:44:14 PM PDT 24
Finished Aug 06 04:44:15 PM PDT 24
Peak memory 208240 kb
Host smart-d5874d7f-070c-49f6-8089-1e78fc8d8b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801313149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.801313149
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.2732079808
Short name T942
Test name
Test status
Simulation time 564384620 ps
CPU time 0.94 seconds
Started Aug 06 04:44:15 PM PDT 24
Finished Aug 06 04:44:16 PM PDT 24
Peak memory 206376 kb
Host smart-af0e54be-9c68-4312-b50f-d240ccfb2edd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732079808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.2732079808
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.3579126178
Short name T934
Test name
Test status
Simulation time 1346612086 ps
CPU time 4.82 seconds
Started Aug 06 04:44:16 PM PDT 24
Finished Aug 06 04:44:20 PM PDT 24
Peak memory 233300 kb
Host smart-dfba9b2f-67a9-4425-bed2-d6cb350e401c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579126178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.3579126178
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.2288194363
Short name T515
Test name
Test status
Simulation time 26074160 ps
CPU time 0.67 seconds
Started Aug 06 04:44:39 PM PDT 24
Finished Aug 06 04:44:39 PM PDT 24
Peak memory 205844 kb
Host smart-2239ae1f-f3ee-450e-9653-6cf782bc6706
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288194363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.2
288194363
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.3748553860
Short name T660
Test name
Test status
Simulation time 334440449 ps
CPU time 2.3 seconds
Started Aug 06 04:44:33 PM PDT 24
Finished Aug 06 04:44:35 PM PDT 24
Peak memory 225104 kb
Host smart-fe030f98-44bc-431a-aee7-e37d042630e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748553860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.3748553860
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.4136299942
Short name T804
Test name
Test status
Simulation time 48230789 ps
CPU time 0.72 seconds
Started Aug 06 04:44:12 PM PDT 24
Finished Aug 06 04:44:13 PM PDT 24
Peak memory 205876 kb
Host smart-629ae0c6-6e8c-49e2-bdb7-437c01afba96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136299942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.4136299942
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.3494039066
Short name T562
Test name
Test status
Simulation time 203121671231 ps
CPU time 265.92 seconds
Started Aug 06 04:44:39 PM PDT 24
Finished Aug 06 04:49:05 PM PDT 24
Peak memory 252784 kb
Host smart-f3f901fa-3fb9-4183-92cf-b0ad98020735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494039066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.3494039066
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.1575421347
Short name T411
Test name
Test status
Simulation time 11079018340 ps
CPU time 83.58 seconds
Started Aug 06 04:44:30 PM PDT 24
Finished Aug 06 04:45:53 PM PDT 24
Peak memory 233564 kb
Host smart-b2c604e3-a654-4ef0-8735-e1c15ff94479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575421347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.1575421347
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.1198284904
Short name T715
Test name
Test status
Simulation time 5869457541 ps
CPU time 89.04 seconds
Started Aug 06 04:44:40 PM PDT 24
Finished Aug 06 04:46:09 PM PDT 24
Peak memory 253560 kb
Host smart-7425ffe0-4d0f-4fe5-a74f-91625063d44e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198284904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.1198284904
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.3298446985
Short name T504
Test name
Test status
Simulation time 477774034 ps
CPU time 8.32 seconds
Started Aug 06 04:44:27 PM PDT 24
Finished Aug 06 04:44:35 PM PDT 24
Peak memory 241428 kb
Host smart-c12cbabb-d49c-472f-8d3b-4aa85752b064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298446985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.3298446985
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.3714978510
Short name T179
Test name
Test status
Simulation time 42340435728 ps
CPU time 257.87 seconds
Started Aug 06 04:44:30 PM PDT 24
Finished Aug 06 04:48:48 PM PDT 24
Peak memory 252868 kb
Host smart-92bf3088-74df-4a02-bc2a-a72012bf760a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714978510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds
.3714978510
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/1.spi_device_intercept.3188778264
Short name T736
Test name
Test status
Simulation time 428595888 ps
CPU time 7.8 seconds
Started Aug 06 04:44:34 PM PDT 24
Finished Aug 06 04:44:42 PM PDT 24
Peak memory 225188 kb
Host smart-e0d122ea-f60e-4be2-9e7e-cbca9e5d3a20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188778264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.3188778264
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.716123669
Short name T1013
Test name
Test status
Simulation time 37276961477 ps
CPU time 24.67 seconds
Started Aug 06 04:44:39 PM PDT 24
Finished Aug 06 04:45:04 PM PDT 24
Peak memory 239608 kb
Host smart-49d3b4df-da72-43ca-ad9e-151ecfcd663b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716123669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.716123669
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.1406923248
Short name T267
Test name
Test status
Simulation time 21798383341 ps
CPU time 33.97 seconds
Started Aug 06 04:44:13 PM PDT 24
Finished Aug 06 04:44:47 PM PDT 24
Peak memory 249912 kb
Host smart-1eabae2d-8417-412d-acc6-9ddccbbb0b49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406923248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.1406923248
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.2867886852
Short name T1005
Test name
Test status
Simulation time 1140623829 ps
CPU time 6.52 seconds
Started Aug 06 04:44:13 PM PDT 24
Finished Aug 06 04:44:20 PM PDT 24
Peak memory 241884 kb
Host smart-7f523b13-cd92-43ec-a6dc-f670ef1eff58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867886852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.2867886852
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.1105364616
Short name T821
Test name
Test status
Simulation time 834037358 ps
CPU time 7.22 seconds
Started Aug 06 04:44:33 PM PDT 24
Finished Aug 06 04:44:40 PM PDT 24
Peak memory 222492 kb
Host smart-3de985c3-b46e-42c3-bacd-1aec9e7d54de
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1105364616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.1105364616
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.866438514
Short name T48
Test name
Test status
Simulation time 57804321 ps
CPU time 1.15 seconds
Started Aug 06 04:44:41 PM PDT 24
Finished Aug 06 04:44:42 PM PDT 24
Peak memory 235584 kb
Host smart-8dc3382f-1dfb-4e03-a0a7-e0a9e8995dda
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866438514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.866438514
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.4112168657
Short name T663
Test name
Test status
Simulation time 25314343 ps
CPU time 0.75 seconds
Started Aug 06 04:44:16 PM PDT 24
Finished Aug 06 04:44:16 PM PDT 24
Peak memory 206040 kb
Host smart-5f59b971-edf5-4e81-914b-0633b1ce5879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112168657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.4112168657
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.1653861378
Short name T834
Test name
Test status
Simulation time 7511239388 ps
CPU time 20.47 seconds
Started Aug 06 04:44:16 PM PDT 24
Finished Aug 06 04:44:37 PM PDT 24
Peak memory 216876 kb
Host smart-0947d214-966d-4cfe-ad7f-e31180ee59dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653861378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.1653861378
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.472853475
Short name T827
Test name
Test status
Simulation time 263136106 ps
CPU time 1.4 seconds
Started Aug 06 04:44:16 PM PDT 24
Finished Aug 06 04:44:17 PM PDT 24
Peak memory 208720 kb
Host smart-f0fffb33-1239-4b89-b843-2aabb6e96eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472853475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.472853475
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.1430666488
Short name T626
Test name
Test status
Simulation time 88730346 ps
CPU time 0.98 seconds
Started Aug 06 04:44:13 PM PDT 24
Finished Aug 06 04:44:14 PM PDT 24
Peak memory 207448 kb
Host smart-3b3163b1-3dfd-4d77-9464-55304e1f1251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430666488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.1430666488
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.3713410411
Short name T844
Test name
Test status
Simulation time 707802328 ps
CPU time 6.21 seconds
Started Aug 06 04:44:29 PM PDT 24
Finished Aug 06 04:44:35 PM PDT 24
Peak memory 225244 kb
Host smart-08d43f95-dbc3-48f8-8b41-aa2082d5d7fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713410411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.3713410411
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.161277085
Short name T758
Test name
Test status
Simulation time 35985906 ps
CPU time 0.74 seconds
Started Aug 06 04:45:14 PM PDT 24
Finished Aug 06 04:45:15 PM PDT 24
Peak memory 205472 kb
Host smart-d2f8a675-0145-4453-9bfb-7a2fb2af0174
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161277085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.161277085
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.3452579691
Short name T880
Test name
Test status
Simulation time 133061920 ps
CPU time 2.65 seconds
Started Aug 06 04:45:12 PM PDT 24
Finished Aug 06 04:45:15 PM PDT 24
Peak memory 233380 kb
Host smart-ab07f828-9373-488f-8e04-49e805af15d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452579691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.3452579691
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.2791302362
Short name T979
Test name
Test status
Simulation time 74572992 ps
CPU time 0.78 seconds
Started Aug 06 04:44:51 PM PDT 24
Finished Aug 06 04:44:51 PM PDT 24
Peak memory 206900 kb
Host smart-12ea682a-0084-4f0d-bd9e-7ff27ddf0f4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791302362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.2791302362
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.2938279738
Short name T644
Test name
Test status
Simulation time 1311962872 ps
CPU time 10.41 seconds
Started Aug 06 04:45:14 PM PDT 24
Finished Aug 06 04:45:25 PM PDT 24
Peak memory 225244 kb
Host smart-86d73589-c92f-42b8-86b7-fa1650cb1d70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938279738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.2938279738
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.2512178734
Short name T208
Test name
Test status
Simulation time 3523370240 ps
CPU time 65.98 seconds
Started Aug 06 04:45:17 PM PDT 24
Finished Aug 06 04:46:23 PM PDT 24
Peak memory 249792 kb
Host smart-237cbb30-d805-4baa-a499-8be82e610e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512178734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.2512178734
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.987201051
Short name T696
Test name
Test status
Simulation time 6409683009 ps
CPU time 75.61 seconds
Started Aug 06 04:45:11 PM PDT 24
Finished Aug 06 04:46:27 PM PDT 24
Peak memory 263364 kb
Host smart-50278a45-ff16-4d81-a3e5-3edbbf35879f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987201051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idle
.987201051
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.1558003695
Short name T666
Test name
Test status
Simulation time 599024576 ps
CPU time 4.32 seconds
Started Aug 06 04:45:12 PM PDT 24
Finished Aug 06 04:45:16 PM PDT 24
Peak memory 225216 kb
Host smart-dfb3f5ee-d016-48ec-aeeb-dd366c5821f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558003695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.1558003695
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_intercept.3298219090
Short name T905
Test name
Test status
Simulation time 535904827 ps
CPU time 5.82 seconds
Started Aug 06 04:45:12 PM PDT 24
Finished Aug 06 04:45:18 PM PDT 24
Peak memory 233436 kb
Host smart-c1a51dc2-ffa6-4c01-bbc5-2c433d3be1d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298219090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.3298219090
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.3978378818
Short name T237
Test name
Test status
Simulation time 3239628956 ps
CPU time 14.05 seconds
Started Aug 06 04:45:12 PM PDT 24
Finished Aug 06 04:45:27 PM PDT 24
Peak memory 225152 kb
Host smart-cb8bf18a-91d2-4c10-a315-3912096d4cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978378818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.3978378818
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.280227994
Short name T10
Test name
Test status
Simulation time 27241605 ps
CPU time 1.04 seconds
Started Aug 06 04:44:53 PM PDT 24
Finished Aug 06 04:44:54 PM PDT 24
Peak memory 217132 kb
Host smart-1de93892-93b6-408c-aeab-61279877bab6
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280227994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.spi_device_mem_parity.280227994
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.127153160
Short name T496
Test name
Test status
Simulation time 31420892 ps
CPU time 2.44 seconds
Started Aug 06 04:45:13 PM PDT 24
Finished Aug 06 04:45:15 PM PDT 24
Peak memory 232980 kb
Host smart-a6bcd906-0c58-4583-96a1-138e31ccce7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127153160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swap
.127153160
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.705595932
Short name T246
Test name
Test status
Simulation time 1424965228 ps
CPU time 5.29 seconds
Started Aug 06 04:45:13 PM PDT 24
Finished Aug 06 04:45:18 PM PDT 24
Peak memory 225200 kb
Host smart-7c22b079-bcd7-408c-9bd0-ddfbc4cbec31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705595932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.705595932
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.2993449190
Short name T132
Test name
Test status
Simulation time 5318718495 ps
CPU time 9.62 seconds
Started Aug 06 04:45:14 PM PDT 24
Finished Aug 06 04:45:24 PM PDT 24
Peak memory 219572 kb
Host smart-34742b23-4e78-4a99-8fd8-9ea03a4be3f8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2993449190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.2993449190
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.2800989771
Short name T809
Test name
Test status
Simulation time 116750671584 ps
CPU time 179.47 seconds
Started Aug 06 04:45:12 PM PDT 24
Finished Aug 06 04:48:12 PM PDT 24
Peak memory 249924 kb
Host smart-00bc204f-3943-4587-bcea-54ddfd749ba6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800989771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.2800989771
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.1617050536
Short name T311
Test name
Test status
Simulation time 6280321227 ps
CPU time 31.54 seconds
Started Aug 06 04:44:54 PM PDT 24
Finished Aug 06 04:45:26 PM PDT 24
Peak memory 216972 kb
Host smart-23cbc9d2-ad23-46dd-9d87-bf23378ec384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617050536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.1617050536
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.3443591393
Short name T338
Test name
Test status
Simulation time 8761694148 ps
CPU time 9.3 seconds
Started Aug 06 04:44:50 PM PDT 24
Finished Aug 06 04:44:59 PM PDT 24
Peak memory 217240 kb
Host smart-48715051-cd67-407c-97d7-6f4ffbd051b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443591393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.3443591393
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.137133106
Short name T765
Test name
Test status
Simulation time 549265908 ps
CPU time 1.7 seconds
Started Aug 06 04:45:13 PM PDT 24
Finished Aug 06 04:45:15 PM PDT 24
Peak memory 216964 kb
Host smart-e37d8cc5-db86-45e4-bc99-e1ac5f724b20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137133106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.137133106
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.1743897316
Short name T154
Test name
Test status
Simulation time 84923829 ps
CPU time 0.91 seconds
Started Aug 06 04:45:16 PM PDT 24
Finished Aug 06 04:45:17 PM PDT 24
Peak memory 206544 kb
Host smart-dfa42758-dde0-4cd2-a39a-08b00f2360d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743897316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.1743897316
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.1179789004
Short name T989
Test name
Test status
Simulation time 1836079607 ps
CPU time 3.5 seconds
Started Aug 06 04:45:12 PM PDT 24
Finished Aug 06 04:45:15 PM PDT 24
Peak memory 225216 kb
Host smart-71e5a099-7718-4c4c-8ac0-daa933fd0dac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179789004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.1179789004
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.3753946604
Short name T569
Test name
Test status
Simulation time 35188969 ps
CPU time 0.71 seconds
Started Aug 06 04:45:17 PM PDT 24
Finished Aug 06 04:45:19 PM PDT 24
Peak memory 205972 kb
Host smart-ebf5faf6-98f5-47bb-beb7-8d88d21e2054
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753946604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
3753946604
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.3687263580
Short name T100
Test name
Test status
Simulation time 726723779 ps
CPU time 4.3 seconds
Started Aug 06 04:45:14 PM PDT 24
Finished Aug 06 04:45:19 PM PDT 24
Peak memory 233412 kb
Host smart-289bf4ca-480f-44fe-a3fa-89fd6d16f270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687263580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.3687263580
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.1501683374
Short name T551
Test name
Test status
Simulation time 15293475 ps
CPU time 0.78 seconds
Started Aug 06 04:45:13 PM PDT 24
Finished Aug 06 04:45:14 PM PDT 24
Peak memory 206976 kb
Host smart-e9ca26d5-a721-49dc-a236-9f37663a4862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501683374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.1501683374
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.4032209900
Short name T11
Test name
Test status
Simulation time 164401286662 ps
CPU time 310.18 seconds
Started Aug 06 04:45:17 PM PDT 24
Finished Aug 06 04:50:27 PM PDT 24
Peak memory 258084 kb
Host smart-40a2d0c3-e621-40a4-b2b9-3f5d20c31622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032209900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.4032209900
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.1694695532
Short name T454
Test name
Test status
Simulation time 769449395 ps
CPU time 4.84 seconds
Started Aug 06 04:45:13 PM PDT 24
Finished Aug 06 04:45:18 PM PDT 24
Peak memory 233276 kb
Host smart-ed6e9427-e9bb-43fc-bd3c-a2089c06ce92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694695532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.1694695532
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.204644211
Short name T450
Test name
Test status
Simulation time 4645083713 ps
CPU time 29.39 seconds
Started Aug 06 04:45:22 PM PDT 24
Finished Aug 06 04:45:51 PM PDT 24
Peak memory 238960 kb
Host smart-4a28c13f-7f44-45e1-bc75-9b1b67dcb14a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204644211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmds
.204644211
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_intercept.1919515287
Short name T461
Test name
Test status
Simulation time 1832051008 ps
CPU time 5.68 seconds
Started Aug 06 04:45:15 PM PDT 24
Finished Aug 06 04:45:21 PM PDT 24
Peak memory 233332 kb
Host smart-06023d16-7a4e-479d-a671-930ec17815c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919515287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.1919515287
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.3652193671
Short name T269
Test name
Test status
Simulation time 1314011904 ps
CPU time 10.11 seconds
Started Aug 06 04:45:13 PM PDT 24
Finished Aug 06 04:45:23 PM PDT 24
Peak memory 233296 kb
Host smart-2979807b-8f82-4520-b810-1686c2f1fef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652193671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.3652193671
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.1122785663
Short name T806
Test name
Test status
Simulation time 135843122 ps
CPU time 1.06 seconds
Started Aug 06 04:45:17 PM PDT 24
Finished Aug 06 04:45:18 PM PDT 24
Peak memory 217004 kb
Host smart-b72175a3-6371-4cc8-a47e-348bda9f1d2b
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122785663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.spi_device_mem_parity.1122785663
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.464435827
Short name T256
Test name
Test status
Simulation time 492023817 ps
CPU time 9.8 seconds
Started Aug 06 04:45:17 PM PDT 24
Finished Aug 06 04:45:27 PM PDT 24
Peak memory 225108 kb
Host smart-2a0398fd-d35b-4634-811c-ce0c201c36c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464435827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swap
.464435827
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.375995545
Short name T928
Test name
Test status
Simulation time 12399906542 ps
CPU time 10.05 seconds
Started Aug 06 04:45:17 PM PDT 24
Finished Aug 06 04:45:27 PM PDT 24
Peak memory 225268 kb
Host smart-bac0aa4b-f00d-4530-8716-d1a3a50109d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375995545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.375995545
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.1953104383
Short name T559
Test name
Test status
Simulation time 864770504 ps
CPU time 12.14 seconds
Started Aug 06 04:45:17 PM PDT 24
Finished Aug 06 04:45:30 PM PDT 24
Peak memory 222604 kb
Host smart-48688d93-77da-47a1-90e3-e8f560610f38
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1953104383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.1953104383
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.3247957434
Short name T142
Test name
Test status
Simulation time 8216917754 ps
CPU time 48.68 seconds
Started Aug 06 04:45:21 PM PDT 24
Finished Aug 06 04:46:10 PM PDT 24
Peak memory 249896 kb
Host smart-1439f7a7-a0cd-42af-9685-e9d15b6c44c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247957434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.3247957434
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.1007114218
Short name T991
Test name
Test status
Simulation time 2683828027 ps
CPU time 6.74 seconds
Started Aug 06 04:45:14 PM PDT 24
Finished Aug 06 04:45:21 PM PDT 24
Peak memory 217040 kb
Host smart-b8901b50-6a5c-4aba-9d31-e36d6fd98960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007114218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.1007114218
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.807548046
Short name T386
Test name
Test status
Simulation time 2098664820 ps
CPU time 2 seconds
Started Aug 06 04:45:11 PM PDT 24
Finished Aug 06 04:45:13 PM PDT 24
Peak memory 216640 kb
Host smart-a0f44e81-8d8e-46ac-badc-2d97464df4f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807548046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.807548046
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.492790363
Short name T432
Test name
Test status
Simulation time 124632458 ps
CPU time 1.45 seconds
Started Aug 06 04:45:13 PM PDT 24
Finished Aug 06 04:45:15 PM PDT 24
Peak memory 216780 kb
Host smart-de14bb2a-996c-46f3-8233-ea1f000354e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492790363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.492790363
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.2006219956
Short name T1019
Test name
Test status
Simulation time 162808182 ps
CPU time 0.86 seconds
Started Aug 06 04:45:12 PM PDT 24
Finished Aug 06 04:45:13 PM PDT 24
Peak memory 206460 kb
Host smart-25820b91-ea8a-4a19-a88a-265d98b3dc75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006219956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.2006219956
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.354834320
Short name T655
Test name
Test status
Simulation time 1538289236 ps
CPU time 8.39 seconds
Started Aug 06 04:45:13 PM PDT 24
Finished Aug 06 04:45:21 PM PDT 24
Peak memory 233392 kb
Host smart-4fee2cc2-f487-4002-9a8a-e46278a29312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354834320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.354834320
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.810361410
Short name T1006
Test name
Test status
Simulation time 22453849 ps
CPU time 0.68 seconds
Started Aug 06 04:45:20 PM PDT 24
Finished Aug 06 04:45:21 PM PDT 24
Peak memory 205144 kb
Host smart-351a55da-fcb8-445d-9b43-1420983b109c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810361410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.810361410
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.2989659577
Short name T75
Test name
Test status
Simulation time 2028272266 ps
CPU time 13.92 seconds
Started Aug 06 04:45:22 PM PDT 24
Finished Aug 06 04:45:36 PM PDT 24
Peak memory 233384 kb
Host smart-f5bc6011-8f10-422e-905f-ed77fcc580b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989659577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.2989659577
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.82977264
Short name T341
Test name
Test status
Simulation time 19349645 ps
CPU time 0.74 seconds
Started Aug 06 04:45:18 PM PDT 24
Finished Aug 06 04:45:19 PM PDT 24
Peak memory 207008 kb
Host smart-13de2082-1b65-4076-a671-2579a8a7fcc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82977264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.82977264
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.987443373
Short name T529
Test name
Test status
Simulation time 5984520617 ps
CPU time 54.43 seconds
Started Aug 06 04:45:21 PM PDT 24
Finished Aug 06 04:46:16 PM PDT 24
Peak memory 254644 kb
Host smart-0169227a-9032-4326-8401-e2c203012a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987443373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.987443373
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.570671388
Short name T59
Test name
Test status
Simulation time 25802890821 ps
CPU time 88.24 seconds
Started Aug 06 04:45:22 PM PDT 24
Finished Aug 06 04:46:51 PM PDT 24
Peak memory 258012 kb
Host smart-a08df001-e29d-4ffb-b54a-1bdf4277ebe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570671388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.570671388
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.1313282598
Short name T227
Test name
Test status
Simulation time 23960761869 ps
CPU time 73.49 seconds
Started Aug 06 04:45:21 PM PDT 24
Finished Aug 06 04:46:35 PM PDT 24
Peak memory 249836 kb
Host smart-1810312c-514e-474a-811d-7bc6325a76d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313282598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.1313282598
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.128428091
Short name T914
Test name
Test status
Simulation time 718289290 ps
CPU time 7.4 seconds
Started Aug 06 04:45:22 PM PDT 24
Finished Aug 06 04:45:30 PM PDT 24
Peak memory 233432 kb
Host smart-7aa6e5c1-b751-4dd3-bb9b-03149e2c6e2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128428091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.128428091
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.505481752
Short name T598
Test name
Test status
Simulation time 4161515026 ps
CPU time 23.29 seconds
Started Aug 06 04:45:19 PM PDT 24
Finished Aug 06 04:45:42 PM PDT 24
Peak memory 240540 kb
Host smart-24648e11-4dd8-4713-876e-90250b798fd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505481752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmds
.505481752
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_intercept.2272711026
Short name T1004
Test name
Test status
Simulation time 1691269896 ps
CPU time 6.01 seconds
Started Aug 06 04:45:17 PM PDT 24
Finished Aug 06 04:45:23 PM PDT 24
Peak memory 225068 kb
Host smart-30e4dd5a-aff1-4feb-bd5e-03f27a967621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272711026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.2272711026
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.3816991603
Short name T525
Test name
Test status
Simulation time 2517719695 ps
CPU time 12.46 seconds
Started Aug 06 04:45:21 PM PDT 24
Finished Aug 06 04:45:34 PM PDT 24
Peak memory 225192 kb
Host smart-c8702b1c-a22d-4e7a-9237-0100518c11d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816991603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.3816991603
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.218006328
Short name T351
Test name
Test status
Simulation time 212921218 ps
CPU time 0.96 seconds
Started Aug 06 04:45:18 PM PDT 24
Finished Aug 06 04:45:19 PM PDT 24
Peak memory 218444 kb
Host smart-ffbd40d9-dee9-43f3-859d-ee5dac90e47f
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218006328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.spi_device_mem_parity.218006328
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.483440339
Short name T435
Test name
Test status
Simulation time 1239159562 ps
CPU time 5.73 seconds
Started Aug 06 04:45:17 PM PDT 24
Finished Aug 06 04:45:24 PM PDT 24
Peak memory 241648 kb
Host smart-7de48463-2922-4e09-b6f2-6a0caf05e413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483440339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.483440339
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.4286257571
Short name T348
Test name
Test status
Simulation time 710358728 ps
CPU time 4.84 seconds
Started Aug 06 04:45:19 PM PDT 24
Finished Aug 06 04:45:24 PM PDT 24
Peak memory 223368 kb
Host smart-2941fc95-7a4c-4928-88a4-745a9e880c55
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4286257571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.4286257571
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.2576975405
Short name T487
Test name
Test status
Simulation time 3820981027 ps
CPU time 23.52 seconds
Started Aug 06 04:45:22 PM PDT 24
Finished Aug 06 04:45:46 PM PDT 24
Peak memory 225148 kb
Host smart-82857e4e-600b-4f40-b851-f211187c619b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576975405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.2576975405
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.3088574206
Short name T901
Test name
Test status
Simulation time 5364429986 ps
CPU time 26.63 seconds
Started Aug 06 04:45:18 PM PDT 24
Finished Aug 06 04:45:45 PM PDT 24
Peak memory 216876 kb
Host smart-9d34bb05-e81f-4c22-a619-31c77163071d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088574206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.3088574206
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.3735687820
Short name T891
Test name
Test status
Simulation time 1318665159 ps
CPU time 3.23 seconds
Started Aug 06 04:45:18 PM PDT 24
Finished Aug 06 04:45:22 PM PDT 24
Peak memory 216864 kb
Host smart-5144b163-87c7-48e0-8abe-391b87ed0c3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735687820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.3735687820
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.1138612855
Short name T648
Test name
Test status
Simulation time 323362971 ps
CPU time 1.91 seconds
Started Aug 06 04:45:18 PM PDT 24
Finished Aug 06 04:45:20 PM PDT 24
Peak memory 216764 kb
Host smart-40207921-bd01-4389-bb1e-499f92029069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138612855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.1138612855
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.1683748642
Short name T726
Test name
Test status
Simulation time 48255630 ps
CPU time 0.82 seconds
Started Aug 06 04:45:19 PM PDT 24
Finished Aug 06 04:45:19 PM PDT 24
Peak memory 206496 kb
Host smart-eedde2c7-5e66-4e75-a45b-100cd5d556dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683748642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.1683748642
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.2411796860
Short name T883
Test name
Test status
Simulation time 66758588 ps
CPU time 2.79 seconds
Started Aug 06 04:45:17 PM PDT 24
Finished Aug 06 04:45:21 PM PDT 24
Peak memory 233336 kb
Host smart-7065b2aa-782f-4786-8e8f-646f9bf16e05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411796860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.2411796860
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.916985757
Short name T642
Test name
Test status
Simulation time 22602082 ps
CPU time 0.72 seconds
Started Aug 06 04:45:13 PM PDT 24
Finished Aug 06 04:45:14 PM PDT 24
Peak memory 205252 kb
Host smart-1f4e52f6-d9b0-480a-ba5d-5302a7aa8052
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916985757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.916985757
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.610092300
Short name T73
Test name
Test status
Simulation time 240702211 ps
CPU time 3.38 seconds
Started Aug 06 04:45:25 PM PDT 24
Finished Aug 06 04:45:28 PM PDT 24
Peak memory 233264 kb
Host smart-b1e84ce8-1b53-4d4a-9165-8762a5dce683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610092300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.610092300
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.4072673876
Short name T544
Test name
Test status
Simulation time 44963620 ps
CPU time 0.77 seconds
Started Aug 06 04:45:23 PM PDT 24
Finished Aug 06 04:45:24 PM PDT 24
Peak memory 205836 kb
Host smart-f19474ee-a803-4e48-b635-95cfe697a170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072673876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.4072673876
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.2380281081
Short name T818
Test name
Test status
Simulation time 123330032772 ps
CPU time 116.58 seconds
Started Aug 06 04:45:19 PM PDT 24
Finished Aug 06 04:47:16 PM PDT 24
Peak memory 250052 kb
Host smart-59931cbf-12cf-47e0-8bd9-d8e9f5eb49ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380281081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.2380281081
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.3789587909
Short name T125
Test name
Test status
Simulation time 18379529701 ps
CPU time 80.23 seconds
Started Aug 06 04:45:16 PM PDT 24
Finished Aug 06 04:46:36 PM PDT 24
Peak memory 258056 kb
Host smart-3c709248-19d5-448d-b370-02f92b895c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789587909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.3789587909
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.2383023546
Short name T26
Test name
Test status
Simulation time 15199194424 ps
CPU time 142.23 seconds
Started Aug 06 04:45:15 PM PDT 24
Finished Aug 06 04:47:37 PM PDT 24
Peak memory 257996 kb
Host smart-5e8fd068-2b7c-40c1-a5dd-d1507dcf1614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383023546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.2383023546
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.3838708484
Short name T481
Test name
Test status
Simulation time 756575640 ps
CPU time 7.82 seconds
Started Aug 06 04:45:22 PM PDT 24
Finished Aug 06 04:45:30 PM PDT 24
Peak memory 233340 kb
Host smart-f27deec8-e1de-46ae-ae64-54f24a5be3c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838708484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.3838708484
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.2582397668
Short name T965
Test name
Test status
Simulation time 16061208022 ps
CPU time 145.03 seconds
Started Aug 06 04:45:20 PM PDT 24
Finished Aug 06 04:47:45 PM PDT 24
Peak memory 254096 kb
Host smart-e14422a3-14cf-4da3-b40a-11311236ddbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582397668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmd
s.2582397668
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/13.spi_device_intercept.3562482678
Short name T550
Test name
Test status
Simulation time 3453562323 ps
CPU time 12.95 seconds
Started Aug 06 04:45:25 PM PDT 24
Finished Aug 06 04:45:38 PM PDT 24
Peak memory 233372 kb
Host smart-0fbf37f7-9110-4b14-be13-2156a2c39985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562482678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.3562482678
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.3312766593
Short name T763
Test name
Test status
Simulation time 47982989402 ps
CPU time 112.39 seconds
Started Aug 06 04:45:22 PM PDT 24
Finished Aug 06 04:47:14 PM PDT 24
Peak memory 225308 kb
Host smart-54453395-6ba9-4500-8f24-4d4b24a4f602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312766593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.3312766593
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.1803473986
Short name T361
Test name
Test status
Simulation time 35819504 ps
CPU time 1.05 seconds
Started Aug 06 04:45:20 PM PDT 24
Finished Aug 06 04:45:21 PM PDT 24
Peak memory 217060 kb
Host smart-4b7df208-6074-4675-8093-9c07f4916edf
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803473986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.spi_device_mem_parity.1803473986
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.930769616
Short name T974
Test name
Test status
Simulation time 373467829 ps
CPU time 4.36 seconds
Started Aug 06 04:45:22 PM PDT 24
Finished Aug 06 04:45:26 PM PDT 24
Peak memory 233436 kb
Host smart-0dfedfd6-0eae-408d-9699-20065c5e8913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930769616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.930769616
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.1431980446
Short name T512
Test name
Test status
Simulation time 2535583183 ps
CPU time 14.36 seconds
Started Aug 06 04:45:25 PM PDT 24
Finished Aug 06 04:45:39 PM PDT 24
Peak memory 222692 kb
Host smart-b46fc610-dc3a-447b-8c2b-2eba57202c1a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1431980446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.1431980446
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.277731264
Short name T18
Test name
Test status
Simulation time 9964402375 ps
CPU time 123.44 seconds
Started Aug 06 04:45:14 PM PDT 24
Finished Aug 06 04:47:18 PM PDT 24
Peak memory 250896 kb
Host smart-2a6b1154-bb95-4a8a-9aa6-c6b76ca5761c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277731264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stres
s_all.277731264
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.3503865662
Short name T347
Test name
Test status
Simulation time 14123051098 ps
CPU time 20.11 seconds
Started Aug 06 04:45:22 PM PDT 24
Finished Aug 06 04:45:43 PM PDT 24
Peak memory 216668 kb
Host smart-94a888c2-f64d-49aa-a7f6-6c27071e47ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503865662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.3503865662
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.2630358380
Short name T117
Test name
Test status
Simulation time 16267155510 ps
CPU time 14.71 seconds
Started Aug 06 04:45:22 PM PDT 24
Finished Aug 06 04:45:36 PM PDT 24
Peak memory 216980 kb
Host smart-351472ed-be7e-433a-81cd-641b2998e4ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630358380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.2630358380
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.2300189276
Short name T375
Test name
Test status
Simulation time 106710086 ps
CPU time 0.96 seconds
Started Aug 06 04:45:21 PM PDT 24
Finished Aug 06 04:45:23 PM PDT 24
Peak memory 207592 kb
Host smart-38e99b9a-b4de-45f2-be17-5a7f28032b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300189276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.2300189276
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.1265680259
Short name T388
Test name
Test status
Simulation time 274319956 ps
CPU time 0.77 seconds
Started Aug 06 04:45:25 PM PDT 24
Finished Aug 06 04:45:26 PM PDT 24
Peak memory 206420 kb
Host smart-4d3ebb98-e14b-4ac4-8d36-d06e3d40e3cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265680259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.1265680259
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.2469295581
Short name T232
Test name
Test status
Simulation time 28991395336 ps
CPU time 12.07 seconds
Started Aug 06 04:45:25 PM PDT 24
Finished Aug 06 04:45:37 PM PDT 24
Peak memory 225128 kb
Host smart-0e539c93-63de-4c7f-9d06-cabc84c49e4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469295581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.2469295581
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.3273690385
Short name T53
Test name
Test status
Simulation time 49697578 ps
CPU time 0.74 seconds
Started Aug 06 04:45:18 PM PDT 24
Finished Aug 06 04:45:19 PM PDT 24
Peak memory 205148 kb
Host smart-edf755a8-8c4e-475b-96a5-73b0783aa8df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273690385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
3273690385
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.1016789596
Short name T403
Test name
Test status
Simulation time 76665973 ps
CPU time 2.65 seconds
Started Aug 06 04:45:16 PM PDT 24
Finished Aug 06 04:45:19 PM PDT 24
Peak memory 233264 kb
Host smart-dbe8730b-d044-4210-9710-1720cbd550cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016789596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.1016789596
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.510820313
Short name T493
Test name
Test status
Simulation time 22117129 ps
CPU time 0.81 seconds
Started Aug 06 04:45:20 PM PDT 24
Finished Aug 06 04:45:20 PM PDT 24
Peak memory 207032 kb
Host smart-c62478b4-5a89-4cfb-97ae-f580f46079b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510820313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.510820313
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.649656266
Short name T262
Test name
Test status
Simulation time 264025139652 ps
CPU time 173.7 seconds
Started Aug 06 04:45:14 PM PDT 24
Finished Aug 06 04:48:08 PM PDT 24
Peak memory 249852 kb
Host smart-1f2a4962-c036-4b3a-901f-67c273de0ec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649656266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.649656266
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.22352644
Short name T980
Test name
Test status
Simulation time 30397778153 ps
CPU time 299.87 seconds
Started Aug 06 04:45:17 PM PDT 24
Finished Aug 06 04:50:18 PM PDT 24
Peak memory 255868 kb
Host smart-5c97fed7-a9f9-4b9b-b256-4b0419b270c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22352644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.22352644
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.1948151684
Short name T30
Test name
Test status
Simulation time 80875561711 ps
CPU time 226.04 seconds
Started Aug 06 04:45:18 PM PDT 24
Finished Aug 06 04:49:04 PM PDT 24
Peak memory 255280 kb
Host smart-937b0e52-641d-410a-a88e-f37554a3d522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948151684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.1948151684
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.3283583227
Short name T881
Test name
Test status
Simulation time 149538840 ps
CPU time 4 seconds
Started Aug 06 04:45:15 PM PDT 24
Finished Aug 06 04:45:19 PM PDT 24
Peak memory 233716 kb
Host smart-680c29d2-9f73-4ff7-9a9f-db205dda7726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283583227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.3283583227
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.2928983557
Short name T599
Test name
Test status
Simulation time 8671663176 ps
CPU time 32.19 seconds
Started Aug 06 04:45:18 PM PDT 24
Finished Aug 06 04:45:51 PM PDT 24
Peak memory 250864 kb
Host smart-ff4182f3-192b-40dc-9c59-0d7d7087609a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928983557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmd
s.2928983557
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/14.spi_device_intercept.3102218105
Short name T811
Test name
Test status
Simulation time 2309074190 ps
CPU time 12.54 seconds
Started Aug 06 04:45:15 PM PDT 24
Finished Aug 06 04:45:28 PM PDT 24
Peak memory 225168 kb
Host smart-bd645652-2a8d-4c12-8584-96013abe5d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102218105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.3102218105
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.1677033739
Short name T618
Test name
Test status
Simulation time 1056168682 ps
CPU time 14.57 seconds
Started Aug 06 04:45:15 PM PDT 24
Finished Aug 06 04:45:29 PM PDT 24
Peak memory 233376 kb
Host smart-35d4f5a7-051a-4ed7-b334-9daadf35baee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677033739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.1677033739
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.1891297047
Short name T832
Test name
Test status
Simulation time 88988174 ps
CPU time 1.1 seconds
Started Aug 06 04:45:20 PM PDT 24
Finished Aug 06 04:45:21 PM PDT 24
Peak memory 217176 kb
Host smart-7fce9def-9c05-4461-b8b6-1d3059faab2c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891297047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.spi_device_mem_parity.1891297047
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.2355210004
Short name T281
Test name
Test status
Simulation time 3151122180 ps
CPU time 11.17 seconds
Started Aug 06 04:45:23 PM PDT 24
Finished Aug 06 04:45:34 PM PDT 24
Peak memory 233372 kb
Host smart-d608b53d-6cba-4575-b7ad-86d4f0a0bca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355210004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.2355210004
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.3342177833
Short name T602
Test name
Test status
Simulation time 10986361278 ps
CPU time 16.21 seconds
Started Aug 06 04:45:16 PM PDT 24
Finished Aug 06 04:45:33 PM PDT 24
Peak memory 225216 kb
Host smart-c962d49c-e739-45db-bfc2-7b0d7da79144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342177833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.3342177833
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.2609818315
Short name T777
Test name
Test status
Simulation time 144636857 ps
CPU time 4.35 seconds
Started Aug 06 04:45:18 PM PDT 24
Finished Aug 06 04:45:23 PM PDT 24
Peak memory 223620 kb
Host smart-9b20ca01-9025-4948-ae04-1e7bb351e032
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2609818315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.2609818315
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.790024319
Short name T13
Test name
Test status
Simulation time 9000148676 ps
CPU time 29.77 seconds
Started Aug 06 04:45:22 PM PDT 24
Finished Aug 06 04:45:53 PM PDT 24
Peak memory 237844 kb
Host smart-e2d19b97-f624-46ea-8435-a472b38d3e2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790024319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stres
s_all.790024319
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.3076436989
Short name T786
Test name
Test status
Simulation time 1692007919 ps
CPU time 3.36 seconds
Started Aug 06 04:45:21 PM PDT 24
Finished Aug 06 04:45:25 PM PDT 24
Peak memory 216936 kb
Host smart-b87466bc-d220-4ce4-90f0-4350f843b8b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076436989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.3076436989
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.2226311596
Short name T920
Test name
Test status
Simulation time 17487068205 ps
CPU time 13.85 seconds
Started Aug 06 04:45:15 PM PDT 24
Finished Aug 06 04:45:29 PM PDT 24
Peak memory 217048 kb
Host smart-10e2df0c-8604-475d-891d-c7cdce5feffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226311596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.2226311596
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.1757620285
Short name T152
Test name
Test status
Simulation time 88441331 ps
CPU time 3.12 seconds
Started Aug 06 04:45:20 PM PDT 24
Finished Aug 06 04:45:23 PM PDT 24
Peak memory 216996 kb
Host smart-d6ae431c-38b3-4eb6-b0ec-b055e084a8b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757620285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.1757620285
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.3165163728
Short name T780
Test name
Test status
Simulation time 49526203 ps
CPU time 0.76 seconds
Started Aug 06 04:45:13 PM PDT 24
Finished Aug 06 04:45:14 PM PDT 24
Peak memory 206452 kb
Host smart-3c7780bd-c643-4698-bdfd-18157679a11b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165163728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.3165163728
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.1161634332
Short name T950
Test name
Test status
Simulation time 187564049 ps
CPU time 2.86 seconds
Started Aug 06 04:45:16 PM PDT 24
Finished Aug 06 04:45:19 PM PDT 24
Peak memory 225064 kb
Host smart-ebe824b0-0fec-4381-95cd-38146d18d51e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161634332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.1161634332
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.4251209382
Short name T972
Test name
Test status
Simulation time 44386414 ps
CPU time 0.74 seconds
Started Aug 06 04:45:38 PM PDT 24
Finished Aug 06 04:45:39 PM PDT 24
Peak memory 205748 kb
Host smart-a0246f4e-13ad-4406-beca-71409f760f8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251209382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
4251209382
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.33680769
Short name T178
Test name
Test status
Simulation time 2238982459 ps
CPU time 4.82 seconds
Started Aug 06 04:45:21 PM PDT 24
Finished Aug 06 04:45:26 PM PDT 24
Peak memory 233516 kb
Host smart-4e8fd1f5-0f15-4b8c-93e2-6bc02c111f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33680769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.33680769
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.506001077
Short name T812
Test name
Test status
Simulation time 42189858 ps
CPU time 0.81 seconds
Started Aug 06 04:45:17 PM PDT 24
Finished Aug 06 04:45:18 PM PDT 24
Peak memory 206988 kb
Host smart-b2700341-19b2-40bb-9041-d64892a92981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506001077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.506001077
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.2933200516
Short name T802
Test name
Test status
Simulation time 1625749165 ps
CPU time 32.24 seconds
Started Aug 06 04:45:37 PM PDT 24
Finished Aug 06 04:46:10 PM PDT 24
Peak memory 249904 kb
Host smart-de7b3e3d-f422-4db2-b4e4-f0bd3644582a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933200516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.2933200516
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.103537356
Short name T25
Test name
Test status
Simulation time 41869052770 ps
CPU time 210.48 seconds
Started Aug 06 04:45:38 PM PDT 24
Finished Aug 06 04:49:08 PM PDT 24
Peak memory 257432 kb
Host smart-52f04dd5-1d56-4fcc-bd7f-3237e664a51e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103537356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.103537356
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.2497838505
Short name T1000
Test name
Test status
Simulation time 1828165537 ps
CPU time 21.48 seconds
Started Aug 06 04:45:42 PM PDT 24
Finished Aug 06 04:46:04 PM PDT 24
Peak memory 233472 kb
Host smart-f8c64a75-4797-4a6c-93e2-e6ca84b96d15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497838505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.2497838505
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.3054041363
Short name T977
Test name
Test status
Simulation time 142297779 ps
CPU time 6.65 seconds
Started Aug 06 04:45:35 PM PDT 24
Finished Aug 06 04:45:42 PM PDT 24
Peak memory 241592 kb
Host smart-9336e637-fd1a-42f9-b2e2-6ffa42ee2ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054041363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.3054041363
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.1177869646
Short name T750
Test name
Test status
Simulation time 2306852823 ps
CPU time 50.29 seconds
Started Aug 06 04:45:44 PM PDT 24
Finished Aug 06 04:46:34 PM PDT 24
Peak memory 250224 kb
Host smart-ae78ff9b-8cbf-4f83-b965-b01014a79b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177869646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmd
s.1177869646
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/15.spi_device_intercept.351387902
Short name T78
Test name
Test status
Simulation time 308776217 ps
CPU time 3.16 seconds
Started Aug 06 04:45:20 PM PDT 24
Finished Aug 06 04:45:23 PM PDT 24
Peak memory 233280 kb
Host smart-f5526b66-7605-4c62-8b4a-b2945a20b088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351387902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.351387902
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.2719058619
Short name T437
Test name
Test status
Simulation time 2091481525 ps
CPU time 19.78 seconds
Started Aug 06 04:45:22 PM PDT 24
Finished Aug 06 04:45:43 PM PDT 24
Peak memory 241472 kb
Host smart-6783597f-1edc-4fa2-acf4-b51e9ab024d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719058619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.2719058619
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.4041934443
Short name T387
Test name
Test status
Simulation time 86585322 ps
CPU time 0.99 seconds
Started Aug 06 04:45:19 PM PDT 24
Finished Aug 06 04:45:20 PM PDT 24
Peak memory 218376 kb
Host smart-6d1c17cd-b6de-4819-af97-aa8725509bbc
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041934443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.spi_device_mem_parity.4041934443
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.3400876907
Short name T447
Test name
Test status
Simulation time 42454231 ps
CPU time 2.82 seconds
Started Aug 06 04:45:21 PM PDT 24
Finished Aug 06 04:45:24 PM PDT 24
Peak memory 233232 kb
Host smart-ff7aa9c1-57e3-44cc-8df0-00b08e22f759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400876907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.3400876907
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.2561289949
Short name T803
Test name
Test status
Simulation time 132540100 ps
CPU time 3.16 seconds
Started Aug 06 04:45:20 PM PDT 24
Finished Aug 06 04:45:23 PM PDT 24
Peak memory 233272 kb
Host smart-a26336f0-3a8e-418b-a425-b0b306699ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561289949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.2561289949
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.2877980424
Short name T992
Test name
Test status
Simulation time 268335838 ps
CPU time 5.09 seconds
Started Aug 06 04:45:41 PM PDT 24
Finished Aug 06 04:45:46 PM PDT 24
Peak memory 219456 kb
Host smart-a6f7bee5-f0e4-4ed2-8917-62f1bda9127f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2877980424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.2877980424
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.3603975543
Short name T293
Test name
Test status
Simulation time 25849067133 ps
CPU time 139.31 seconds
Started Aug 06 04:45:37 PM PDT 24
Finished Aug 06 04:47:56 PM PDT 24
Peak memory 266236 kb
Host smart-17dcb1c5-100c-464c-9eb5-15647e0d361b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603975543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.3603975543
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.2401231374
Short name T314
Test name
Test status
Simulation time 682857693 ps
CPU time 7.12 seconds
Started Aug 06 04:45:17 PM PDT 24
Finished Aug 06 04:45:25 PM PDT 24
Peak memory 216784 kb
Host smart-6f74620e-74cf-4225-b23d-19bd69588fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401231374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.2401231374
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.2270891051
Short name T752
Test name
Test status
Simulation time 1601480171 ps
CPU time 5.7 seconds
Started Aug 06 04:45:19 PM PDT 24
Finished Aug 06 04:45:25 PM PDT 24
Peak memory 216880 kb
Host smart-853efa68-2f75-4ec2-9f82-686373f55dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270891051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.2270891051
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.2255689309
Short name T485
Test name
Test status
Simulation time 30082565 ps
CPU time 1.53 seconds
Started Aug 06 04:45:19 PM PDT 24
Finished Aug 06 04:45:20 PM PDT 24
Peak memory 208800 kb
Host smart-41b985a8-31ba-4bbf-a97e-a2aad699f42a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255689309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.2255689309
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.614351105
Short name T66
Test name
Test status
Simulation time 104207652 ps
CPU time 0.74 seconds
Started Aug 06 04:45:19 PM PDT 24
Finished Aug 06 04:45:20 PM PDT 24
Peak memory 206604 kb
Host smart-2e87c379-d47c-40f4-a5fb-55c6ed495b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614351105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.614351105
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.589358748
Short name T582
Test name
Test status
Simulation time 290107636 ps
CPU time 2.41 seconds
Started Aug 06 04:45:23 PM PDT 24
Finished Aug 06 04:45:25 PM PDT 24
Peak memory 225024 kb
Host smart-18bdb8bc-fffd-48b4-bfe7-0c16e5ac6bd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589358748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.589358748
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.3713790312
Short name T415
Test name
Test status
Simulation time 15461057 ps
CPU time 0.72 seconds
Started Aug 06 04:45:47 PM PDT 24
Finished Aug 06 04:45:48 PM PDT 24
Peak memory 205792 kb
Host smart-083c3d94-0cf7-4eb2-ad4c-0f40a781bad2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713790312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
3713790312
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.677293834
Short name T325
Test name
Test status
Simulation time 87788460 ps
CPU time 2.3 seconds
Started Aug 06 04:45:37 PM PDT 24
Finished Aug 06 04:45:40 PM PDT 24
Peak memory 233412 kb
Host smart-8d24aa93-279c-438d-9351-b7619bd7cb6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677293834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.677293834
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.354638624
Short name T665
Test name
Test status
Simulation time 25410117 ps
CPU time 0.74 seconds
Started Aug 06 04:45:49 PM PDT 24
Finished Aug 06 04:45:50 PM PDT 24
Peak memory 206212 kb
Host smart-04e9577c-e99b-44ee-9065-4783b942aee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354638624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.354638624
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.2690025632
Short name T996
Test name
Test status
Simulation time 268569482791 ps
CPU time 438.48 seconds
Started Aug 06 04:45:38 PM PDT 24
Finished Aug 06 04:52:57 PM PDT 24
Peak memory 249908 kb
Host smart-6db6c5ab-b09d-41be-a142-fed1131347a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690025632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.2690025632
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.4244489342
Short name T810
Test name
Test status
Simulation time 104943360482 ps
CPU time 420.38 seconds
Started Aug 06 04:45:37 PM PDT 24
Finished Aug 06 04:52:38 PM PDT 24
Peak memory 249812 kb
Host smart-96820565-200e-4563-87ad-9f6aade0fbca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244489342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.4244489342
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.323951995
Short name T201
Test name
Test status
Simulation time 35226906455 ps
CPU time 228.73 seconds
Started Aug 06 04:45:38 PM PDT 24
Finished Aug 06 04:49:27 PM PDT 24
Peak memory 254972 kb
Host smart-6f3f9c52-a7a8-40cf-85bd-9269800794b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323951995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmds
.323951995
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/16.spi_device_intercept.1733915876
Short name T513
Test name
Test status
Simulation time 37468975 ps
CPU time 2.64 seconds
Started Aug 06 04:45:41 PM PDT 24
Finished Aug 06 04:45:44 PM PDT 24
Peak memory 233060 kb
Host smart-724af693-0f9f-4a73-be5b-4b4dac5994f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733915876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.1733915876
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.2223281090
Short name T729
Test name
Test status
Simulation time 642084452 ps
CPU time 8.65 seconds
Started Aug 06 04:45:41 PM PDT 24
Finished Aug 06 04:45:50 PM PDT 24
Peak memory 233392 kb
Host smart-bd9c10d8-8f5e-4468-8b22-b2a3fc8d4f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223281090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.2223281090
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.3958499698
Short name T727
Test name
Test status
Simulation time 94959167 ps
CPU time 1.01 seconds
Started Aug 06 04:45:37 PM PDT 24
Finished Aug 06 04:45:39 PM PDT 24
Peak memory 217076 kb
Host smart-f56eb2d9-b119-446a-9ae1-d7d23b449901
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958499698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.spi_device_mem_parity.3958499698
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.3614987296
Short name T925
Test name
Test status
Simulation time 17801903147 ps
CPU time 10.99 seconds
Started Aug 06 04:45:39 PM PDT 24
Finished Aug 06 04:45:50 PM PDT 24
Peak memory 225132 kb
Host smart-6925ec12-a3cf-4fe4-b4e0-ca6bec43c517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614987296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.3614987296
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.4078221286
Short name T71
Test name
Test status
Simulation time 6487176677 ps
CPU time 6.73 seconds
Started Aug 06 04:45:38 PM PDT 24
Finished Aug 06 04:45:45 PM PDT 24
Peak memory 225104 kb
Host smart-a8b9efe7-05a0-423a-ac1e-5bf9afe86356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078221286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.4078221286
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.3819475096
Short name T635
Test name
Test status
Simulation time 704052444 ps
CPU time 5.46 seconds
Started Aug 06 04:45:38 PM PDT 24
Finished Aug 06 04:45:44 PM PDT 24
Peak memory 220588 kb
Host smart-4af29306-a3fd-4c18-9b84-239e420461ad
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3819475096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.3819475096
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.34979107
Short name T1018
Test name
Test status
Simulation time 48486066 ps
CPU time 1.02 seconds
Started Aug 06 04:45:39 PM PDT 24
Finished Aug 06 04:45:40 PM PDT 24
Peak memory 208304 kb
Host smart-c225ca79-1f68-4672-9e73-ffb55640955c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34979107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stress
_all.34979107
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.1911524503
Short name T684
Test name
Test status
Simulation time 1403516814 ps
CPU time 7.4 seconds
Started Aug 06 04:45:40 PM PDT 24
Finished Aug 06 04:45:48 PM PDT 24
Peak memory 216816 kb
Host smart-79ce9afb-ef5f-436f-a37e-356400bfe4a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911524503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.1911524503
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.1289636638
Short name T911
Test name
Test status
Simulation time 1370761454 ps
CPU time 3.32 seconds
Started Aug 06 04:45:36 PM PDT 24
Finished Aug 06 04:45:40 PM PDT 24
Peak memory 216904 kb
Host smart-b2e149cf-7470-4ba2-8a0c-f7a7eb66f350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289636638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.1289636638
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.3078586319
Short name T524
Test name
Test status
Simulation time 145652099 ps
CPU time 2.14 seconds
Started Aug 06 04:45:40 PM PDT 24
Finished Aug 06 04:45:42 PM PDT 24
Peak memory 216968 kb
Host smart-623785d3-8bf7-4a50-83d8-cc1b17e522b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078586319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.3078586319
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.205869245
Short name T523
Test name
Test status
Simulation time 32772011 ps
CPU time 0.74 seconds
Started Aug 06 04:45:40 PM PDT 24
Finished Aug 06 04:45:41 PM PDT 24
Peak memory 206548 kb
Host smart-773da2b3-de11-4fc3-ad06-6a29874869d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205869245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.205869245
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.1199548815
Short name T372
Test name
Test status
Simulation time 9620423033 ps
CPU time 12.47 seconds
Started Aug 06 04:45:41 PM PDT 24
Finished Aug 06 04:45:53 PM PDT 24
Peak memory 236772 kb
Host smart-fc8808cb-72b5-4d66-a912-0123f91bb93c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199548815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.1199548815
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.1447316921
Short name T945
Test name
Test status
Simulation time 44586819 ps
CPU time 0.85 seconds
Started Aug 06 04:45:41 PM PDT 24
Finished Aug 06 04:45:42 PM PDT 24
Peak memory 205808 kb
Host smart-6de278e3-b17e-4ef6-bf88-f5f8790daf23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447316921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
1447316921
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.3975935800
Short name T617
Test name
Test status
Simulation time 675287065 ps
CPU time 9.87 seconds
Started Aug 06 04:45:42 PM PDT 24
Finished Aug 06 04:45:52 PM PDT 24
Peak memory 233396 kb
Host smart-c5e81679-049b-48e8-8e51-b6b51e0ae287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975935800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.3975935800
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.2724543980
Short name T463
Test name
Test status
Simulation time 23043377 ps
CPU time 0.77 seconds
Started Aug 06 04:45:38 PM PDT 24
Finished Aug 06 04:45:39 PM PDT 24
Peak memory 207008 kb
Host smart-0ca466f6-7b81-4267-8f96-cdcdb84cb74b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724543980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.2724543980
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.909379958
Short name T188
Test name
Test status
Simulation time 65652757549 ps
CPU time 222.16 seconds
Started Aug 06 04:45:37 PM PDT 24
Finished Aug 06 04:49:20 PM PDT 24
Peak memory 256660 kb
Host smart-11c1ea37-6ea8-4ddd-88a8-49366aa9105e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909379958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.909379958
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.3941201176
Short name T916
Test name
Test status
Simulation time 106036075544 ps
CPU time 201.43 seconds
Started Aug 06 04:45:38 PM PDT 24
Finished Aug 06 04:49:00 PM PDT 24
Peak memory 256432 kb
Host smart-443dfa0f-55ab-43cf-8bb0-1cfd674799c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941201176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.3941201176
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.1589402852
Short name T291
Test name
Test status
Simulation time 9042469363 ps
CPU time 43.99 seconds
Started Aug 06 04:45:41 PM PDT 24
Finished Aug 06 04:46:25 PM PDT 24
Peak memory 257700 kb
Host smart-a842f171-8311-45f2-abde-4b0cba672a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589402852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.1589402852
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.2269159794
Short name T627
Test name
Test status
Simulation time 868170762 ps
CPU time 6.87 seconds
Started Aug 06 04:45:39 PM PDT 24
Finished Aug 06 04:45:46 PM PDT 24
Peak memory 237004 kb
Host smart-0fbf27c3-dc6f-498a-b6dd-cf2e6d8f7ad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269159794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.2269159794
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.1038749327
Short name T358
Test name
Test status
Simulation time 10793228 ps
CPU time 0.75 seconds
Started Aug 06 04:45:38 PM PDT 24
Finished Aug 06 04:45:39 PM PDT 24
Peak memory 216300 kb
Host smart-47e68ccf-331e-4544-aef3-0eb555b1b453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038749327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmd
s.1038749327
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/17.spi_device_intercept.861440440
Short name T553
Test name
Test status
Simulation time 14321115462 ps
CPU time 39.82 seconds
Started Aug 06 04:45:39 PM PDT 24
Finished Aug 06 04:46:19 PM PDT 24
Peak memory 225196 kb
Host smart-311f4ad1-e2fe-4495-9d5d-1bed8a48ee86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861440440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.861440440
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.995201714
Short name T367
Test name
Test status
Simulation time 31539802 ps
CPU time 2.14 seconds
Started Aug 06 04:45:37 PM PDT 24
Finished Aug 06 04:45:39 PM PDT 24
Peak memory 224496 kb
Host smart-c7a92ee2-7669-4fa1-924d-603c85d5571e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995201714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.995201714
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.327767585
Short name T900
Test name
Test status
Simulation time 15571314 ps
CPU time 1.02 seconds
Started Aug 06 04:45:37 PM PDT 24
Finished Aug 06 04:45:39 PM PDT 24
Peak memory 217076 kb
Host smart-640be3c7-ecfd-4958-981b-21e1152dea89
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327767585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.spi_device_mem_parity.327767585
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.4212926477
Short name T1028
Test name
Test status
Simulation time 238439162 ps
CPU time 2.45 seconds
Started Aug 06 04:45:38 PM PDT 24
Finished Aug 06 04:45:40 PM PDT 24
Peak memory 225000 kb
Host smart-c9d253e5-bd52-4316-9df4-e2c13ff3e9bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212926477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.4212926477
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.2617051252
Short name T404
Test name
Test status
Simulation time 20134526698 ps
CPU time 9.94 seconds
Started Aug 06 04:45:41 PM PDT 24
Finished Aug 06 04:45:51 PM PDT 24
Peak memory 225248 kb
Host smart-11543b7b-8e9d-4f2f-b02c-498d8f79e823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617051252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.2617051252
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.779004984
Short name T327
Test name
Test status
Simulation time 285381268 ps
CPU time 4.23 seconds
Started Aug 06 04:45:37 PM PDT 24
Finished Aug 06 04:45:42 PM PDT 24
Peak memory 223444 kb
Host smart-72ed61ca-6347-4aba-830a-dfc99ec63343
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=779004984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dire
ct.779004984
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.1995344789
Short name T126
Test name
Test status
Simulation time 60472554918 ps
CPU time 273.68 seconds
Started Aug 06 04:45:38 PM PDT 24
Finished Aug 06 04:50:12 PM PDT 24
Peak memory 285352 kb
Host smart-a05ce8d1-1c64-474b-aba9-06d18b02249b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995344789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.1995344789
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.1472911899
Short name T423
Test name
Test status
Simulation time 23994542470 ps
CPU time 19.64 seconds
Started Aug 06 04:45:40 PM PDT 24
Finished Aug 06 04:46:00 PM PDT 24
Peak memory 217040 kb
Host smart-8a143407-2ba2-48a6-85b9-810983d60c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472911899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.1472911899
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.2381810135
Short name T723
Test name
Test status
Simulation time 1434057688 ps
CPU time 7.26 seconds
Started Aug 06 04:45:38 PM PDT 24
Finished Aug 06 04:45:46 PM PDT 24
Peak memory 216916 kb
Host smart-1275a84b-aec2-4c91-bca5-1c20e0bd3dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381810135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.2381810135
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.3403797241
Short name T345
Test name
Test status
Simulation time 529591591 ps
CPU time 2.44 seconds
Started Aug 06 04:45:38 PM PDT 24
Finished Aug 06 04:45:40 PM PDT 24
Peak memory 216912 kb
Host smart-80251c53-eb32-4476-b169-0ed21ea5ca23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403797241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.3403797241
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.2513392897
Short name T489
Test name
Test status
Simulation time 430718076 ps
CPU time 0.86 seconds
Started Aug 06 04:45:36 PM PDT 24
Finished Aug 06 04:45:37 PM PDT 24
Peak memory 206524 kb
Host smart-18319a35-4ab2-4359-8321-bf70b4f2b6c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513392897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.2513392897
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.312170712
Short name T628
Test name
Test status
Simulation time 4584885820 ps
CPU time 6.11 seconds
Started Aug 06 04:45:41 PM PDT 24
Finished Aug 06 04:45:47 PM PDT 24
Peak memory 225220 kb
Host smart-d584a74e-f1c7-4b80-a409-8f0a0cac142c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312170712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.312170712
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.2270083603
Short name T250
Test name
Test status
Simulation time 197798130 ps
CPU time 3.59 seconds
Started Aug 06 04:45:41 PM PDT 24
Finished Aug 06 04:45:45 PM PDT 24
Peak memory 233368 kb
Host smart-06369631-1a72-493d-9380-d8bad3e7ac0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270083603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.2270083603
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.411390903
Short name T469
Test name
Test status
Simulation time 21731475 ps
CPU time 0.81 seconds
Started Aug 06 04:45:38 PM PDT 24
Finished Aug 06 04:45:39 PM PDT 24
Peak memory 206940 kb
Host smart-0eee2006-b6e4-41d9-ba57-a5203db8f8dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411390903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.411390903
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.146465672
Short name T855
Test name
Test status
Simulation time 2500698096 ps
CPU time 35.63 seconds
Started Aug 06 04:45:40 PM PDT 24
Finished Aug 06 04:46:15 PM PDT 24
Peak memory 238648 kb
Host smart-f8cf97a3-62f6-49bd-b84e-c18b502eb3d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146465672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.146465672
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.3975945138
Short name T751
Test name
Test status
Simulation time 6525734068 ps
CPU time 75.44 seconds
Started Aug 06 04:45:42 PM PDT 24
Finished Aug 06 04:46:58 PM PDT 24
Peak memory 250900 kb
Host smart-ba004e4f-24d3-49c4-b43a-4ec494b23732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975945138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.3975945138
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.1112746275
Short name T176
Test name
Test status
Simulation time 20215770309 ps
CPU time 41.82 seconds
Started Aug 06 04:45:47 PM PDT 24
Finished Aug 06 04:46:28 PM PDT 24
Peak memory 241684 kb
Host smart-75b282bb-8a8b-476d-b503-11b2408fbdc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112746275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.1112746275
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.3956236146
Short name T603
Test name
Test status
Simulation time 260204970 ps
CPU time 7.9 seconds
Started Aug 06 04:45:40 PM PDT 24
Finished Aug 06 04:45:48 PM PDT 24
Peak memory 225220 kb
Host smart-75941cc0-de8f-4665-a198-d072ed146f95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956236146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.3956236146
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_intercept.121001618
Short name T1011
Test name
Test status
Simulation time 5466417134 ps
CPU time 5.75 seconds
Started Aug 06 04:45:41 PM PDT 24
Finished Aug 06 04:45:47 PM PDT 24
Peak memory 225220 kb
Host smart-ba87e781-d297-45d4-b0bb-61816c0c3037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121001618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.121001618
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.1255730835
Short name T182
Test name
Test status
Simulation time 1788936944 ps
CPU time 25.29 seconds
Started Aug 06 04:45:41 PM PDT 24
Finished Aug 06 04:46:06 PM PDT 24
Peak memory 233428 kb
Host smart-f6d09fc3-1493-4319-975b-43ae5ae01fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255730835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.1255730835
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.22509762
Short name T522
Test name
Test status
Simulation time 25611970 ps
CPU time 1 seconds
Started Aug 06 04:45:45 PM PDT 24
Finished Aug 06 04:45:46 PM PDT 24
Peak memory 217064 kb
Host smart-811b870b-481b-4252-807a-18a93d87b14a
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22509762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TES
T_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.spi_device_mem_parity.22509762
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.440201015
Short name T276
Test name
Test status
Simulation time 2863615890 ps
CPU time 6.95 seconds
Started Aug 06 04:45:40 PM PDT 24
Finished Aug 06 04:45:47 PM PDT 24
Peak memory 233484 kb
Host smart-9b3bbece-e0f0-4bc5-9392-0499af9a7685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440201015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swap
.440201015
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.1697585183
Short name T686
Test name
Test status
Simulation time 20766385061 ps
CPU time 17.43 seconds
Started Aug 06 04:45:37 PM PDT 24
Finished Aug 06 04:45:55 PM PDT 24
Peak memory 233480 kb
Host smart-77048057-29ff-4d4b-95a8-84a181a5f728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697585183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.1697585183
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.707413343
Short name T791
Test name
Test status
Simulation time 1629222498 ps
CPU time 7.52 seconds
Started Aug 06 04:45:40 PM PDT 24
Finished Aug 06 04:45:47 PM PDT 24
Peak memory 219684 kb
Host smart-aee8e90d-8adc-4c98-950d-09c39ba57b55
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=707413343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dire
ct.707413343
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.2708460254
Short name T22
Test name
Test status
Simulation time 5256607873 ps
CPU time 22.19 seconds
Started Aug 06 04:45:42 PM PDT 24
Finished Aug 06 04:46:04 PM PDT 24
Peak memory 225288 kb
Host smart-45d78417-563f-4d43-866a-addb5d3a0e4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708460254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.2708460254
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.928095391
Short name T313
Test name
Test status
Simulation time 2854068820 ps
CPU time 14.05 seconds
Started Aug 06 04:45:39 PM PDT 24
Finished Aug 06 04:45:53 PM PDT 24
Peak memory 216904 kb
Host smart-8d20f328-ad44-4f5d-87e1-6f38483d16b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928095391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.928095391
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.465630423
Short name T781
Test name
Test status
Simulation time 1090800360 ps
CPU time 5.65 seconds
Started Aug 06 04:45:40 PM PDT 24
Finished Aug 06 04:45:46 PM PDT 24
Peak memory 216996 kb
Host smart-c88af577-0cf5-4d4b-921f-87ed92b36f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465630423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.465630423
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.965946962
Short name T482
Test name
Test status
Simulation time 13548720 ps
CPU time 0.71 seconds
Started Aug 06 04:45:41 PM PDT 24
Finished Aug 06 04:45:42 PM PDT 24
Peak memory 206036 kb
Host smart-bf4684b3-36d3-4da7-81ac-e0d924931189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965946962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.965946962
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.1713903538
Short name T867
Test name
Test status
Simulation time 18081150 ps
CPU time 0.77 seconds
Started Aug 06 04:45:39 PM PDT 24
Finished Aug 06 04:45:40 PM PDT 24
Peak memory 206768 kb
Host smart-1520df50-dee3-47d6-a791-9ec8c24fde4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713903538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.1713903538
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.999444893
Short name T685
Test name
Test status
Simulation time 5179409949 ps
CPU time 12.2 seconds
Started Aug 06 04:45:47 PM PDT 24
Finished Aug 06 04:45:59 PM PDT 24
Peak memory 241636 kb
Host smart-00a211ae-77b4-470c-8f87-826e461d78eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999444893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.999444893
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.17064849
Short name T549
Test name
Test status
Simulation time 12518443 ps
CPU time 0.71 seconds
Started Aug 06 04:45:49 PM PDT 24
Finished Aug 06 04:45:50 PM PDT 24
Peak memory 205252 kb
Host smart-bcc48ef0-9023-4376-995c-9d4cad5f07e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17064849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.17064849
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.1413905125
Short name T711
Test name
Test status
Simulation time 294812053 ps
CPU time 2.26 seconds
Started Aug 06 04:45:45 PM PDT 24
Finished Aug 06 04:45:48 PM PDT 24
Peak memory 225208 kb
Host smart-e3790546-ee5a-4dca-a552-7bc83bad0fbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413905125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.1413905125
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.1926437291
Short name T28
Test name
Test status
Simulation time 47899773 ps
CPU time 0.72 seconds
Started Aug 06 04:45:48 PM PDT 24
Finished Aug 06 04:45:49 PM PDT 24
Peak memory 206300 kb
Host smart-0711784a-3229-454d-985b-1bf28fdea7aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926437291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.1926437291
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.242792064
Short name T520
Test name
Test status
Simulation time 2047843902 ps
CPU time 21.85 seconds
Started Aug 06 04:45:49 PM PDT 24
Finished Aug 06 04:46:11 PM PDT 24
Peak memory 238548 kb
Host smart-89af3c0d-7b90-4d18-9aa8-f37f3d5a006a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242792064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.242792064
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.337524034
Short name T625
Test name
Test status
Simulation time 8520822522 ps
CPU time 23.71 seconds
Started Aug 06 04:45:49 PM PDT 24
Finished Aug 06 04:46:13 PM PDT 24
Peak memory 220252 kb
Host smart-ecf1e40f-db4c-4371-948f-904a71bdf5c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337524034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.337524034
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.1995783252
Short name T606
Test name
Test status
Simulation time 10126468846 ps
CPU time 52.47 seconds
Started Aug 06 04:45:50 PM PDT 24
Finished Aug 06 04:46:42 PM PDT 24
Peak memory 252612 kb
Host smart-a1b58738-c341-4aaf-957d-1b4e564ed1eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995783252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.1995783252
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.2606322890
Short name T741
Test name
Test status
Simulation time 354279698 ps
CPU time 5.59 seconds
Started Aug 06 04:45:38 PM PDT 24
Finished Aug 06 04:45:44 PM PDT 24
Peak memory 233308 kb
Host smart-a7e14682-c6c1-40b6-bf80-8dd39d1bfcad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606322890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.2606322890
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.3880049430
Short name T885
Test name
Test status
Simulation time 13863015361 ps
CPU time 87.86 seconds
Started Aug 06 04:45:48 PM PDT 24
Finished Aug 06 04:47:16 PM PDT 24
Peak memory 257196 kb
Host smart-87d1f9c8-7d52-480d-95c5-1fb72267bdda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880049430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmd
s.3880049430
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/19.spi_device_intercept.778174420
Short name T657
Test name
Test status
Simulation time 369917623 ps
CPU time 5.49 seconds
Started Aug 06 04:45:49 PM PDT 24
Finished Aug 06 04:45:55 PM PDT 24
Peak memory 229972 kb
Host smart-157a05ed-13b0-4de6-a4c5-d0122ca32d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778174420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.778174420
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.1315614942
Short name T219
Test name
Test status
Simulation time 292265800 ps
CPU time 7 seconds
Started Aug 06 04:45:46 PM PDT 24
Finished Aug 06 04:45:53 PM PDT 24
Peak memory 225260 kb
Host smart-4b6b013d-68b4-482d-8e60-b808abe4dddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315614942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.1315614942
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.1205931083
Short name T826
Test name
Test status
Simulation time 33047748 ps
CPU time 1.06 seconds
Started Aug 06 04:45:48 PM PDT 24
Finished Aug 06 04:45:49 PM PDT 24
Peak memory 217132 kb
Host smart-29c74b37-b28e-4151-b924-355e0682ded5
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205931083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.spi_device_mem_parity.1205931083
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.815218358
Short name T222
Test name
Test status
Simulation time 2289938853 ps
CPU time 11.96 seconds
Started Aug 06 04:45:46 PM PDT 24
Finished Aug 06 04:45:58 PM PDT 24
Peak memory 233452 kb
Host smart-725005af-eddf-400f-a304-0b516b6e7e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815218358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swap
.815218358
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.237176050
Short name T214
Test name
Test status
Simulation time 1844272853 ps
CPU time 4.08 seconds
Started Aug 06 04:45:49 PM PDT 24
Finished Aug 06 04:45:53 PM PDT 24
Peak memory 233416 kb
Host smart-b99ca975-c736-4829-a2be-fc643ce48b5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237176050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.237176050
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.3105041726
Short name T465
Test name
Test status
Simulation time 672325845 ps
CPU time 5.3 seconds
Started Aug 06 04:45:48 PM PDT 24
Finished Aug 06 04:45:53 PM PDT 24
Peak memory 220908 kb
Host smart-d86421f5-998a-43bc-877d-45363bab704b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3105041726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.3105041726
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.963752377
Short name T312
Test name
Test status
Simulation time 1707814881 ps
CPU time 13.87 seconds
Started Aug 06 04:45:42 PM PDT 24
Finished Aug 06 04:45:56 PM PDT 24
Peak memory 216880 kb
Host smart-6a5c421d-dfa0-4ce9-ba7c-36e0d8a20d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963752377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.963752377
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.3681847299
Short name T370
Test name
Test status
Simulation time 875911323 ps
CPU time 4.76 seconds
Started Aug 06 04:45:46 PM PDT 24
Finished Aug 06 04:45:51 PM PDT 24
Peak memory 216924 kb
Host smart-9025289f-71db-4b1e-acb6-01cb37fee13c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681847299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.3681847299
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.1951925491
Short name T889
Test name
Test status
Simulation time 368748860 ps
CPU time 1.84 seconds
Started Aug 06 04:45:47 PM PDT 24
Finished Aug 06 04:45:48 PM PDT 24
Peak memory 216956 kb
Host smart-b4e02f9b-a0fb-458b-9b22-e5efd3e47725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951925491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.1951925491
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.226579223
Short name T673
Test name
Test status
Simulation time 67591145 ps
CPU time 0.72 seconds
Started Aug 06 04:45:43 PM PDT 24
Finished Aug 06 04:45:44 PM PDT 24
Peak memory 206492 kb
Host smart-ec857829-d7ae-4282-808b-ebb6442dab66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226579223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.226579223
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.577620218
Short name T676
Test name
Test status
Simulation time 4617917643 ps
CPU time 19.16 seconds
Started Aug 06 04:45:47 PM PDT 24
Finished Aug 06 04:46:06 PM PDT 24
Peak memory 249728 kb
Host smart-18cb9bf6-6fa8-45c3-b18e-eaf5f65206f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577620218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.577620218
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.890112366
Short name T444
Test name
Test status
Simulation time 39563307 ps
CPU time 0.7 seconds
Started Aug 06 04:44:29 PM PDT 24
Finished Aug 06 04:44:30 PM PDT 24
Peak memory 206056 kb
Host smart-21a61521-0dc7-4891-8ce9-253aed6f552c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890112366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.890112366
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.3751734560
Short name T712
Test name
Test status
Simulation time 598342988 ps
CPU time 7.6 seconds
Started Aug 06 04:44:25 PM PDT 24
Finished Aug 06 04:44:33 PM PDT 24
Peak memory 233316 kb
Host smart-e182f1a6-89e5-4136-b583-707dc2b5a074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751734560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.3751734560
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.2972620465
Short name T572
Test name
Test status
Simulation time 17644202 ps
CPU time 0.79 seconds
Started Aug 06 04:44:29 PM PDT 24
Finished Aug 06 04:44:30 PM PDT 24
Peak memory 206920 kb
Host smart-91748f8b-9a9b-4c4f-aa9d-0db48991111d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972620465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.2972620465
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.3194005912
Short name T196
Test name
Test status
Simulation time 15605219543 ps
CPU time 152.86 seconds
Started Aug 06 04:44:29 PM PDT 24
Finished Aug 06 04:47:02 PM PDT 24
Peak memory 255624 kb
Host smart-55b5d843-f5b1-4fcd-8a21-fff6a9a42000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194005912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.3194005912
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.3352181454
Short name T401
Test name
Test status
Simulation time 5001716511 ps
CPU time 18.35 seconds
Started Aug 06 04:44:23 PM PDT 24
Finished Aug 06 04:44:42 PM PDT 24
Peak memory 218256 kb
Host smart-ceb637ae-a80c-4986-ad51-71f322015016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352181454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.3352181454
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.834231292
Short name T382
Test name
Test status
Simulation time 1002460850 ps
CPU time 10.11 seconds
Started Aug 06 04:44:32 PM PDT 24
Finished Aug 06 04:44:42 PM PDT 24
Peak memory 225112 kb
Host smart-5b73fffd-5287-40ff-8eb2-9f6ad87fad93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834231292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.834231292
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_intercept.1063536298
Short name T951
Test name
Test status
Simulation time 4519200384 ps
CPU time 44.13 seconds
Started Aug 06 04:44:26 PM PDT 24
Finished Aug 06 04:45:10 PM PDT 24
Peak memory 225152 kb
Host smart-8b8df708-3ee3-4818-94df-2e3a1317e9ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063536298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.1063536298
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.3771069843
Short name T273
Test name
Test status
Simulation time 1496512359 ps
CPU time 14.11 seconds
Started Aug 06 04:44:34 PM PDT 24
Finished Aug 06 04:44:48 PM PDT 24
Peak memory 233420 kb
Host smart-ebf86fe1-bb27-4724-9ee3-6509837599e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771069843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.3771069843
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.69006077
Short name T33
Test name
Test status
Simulation time 26195623 ps
CPU time 1.05 seconds
Started Aug 06 04:44:28 PM PDT 24
Finished Aug 06 04:44:30 PM PDT 24
Peak memory 217076 kb
Host smart-60555801-4372-47fa-af68-221f603175a5
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69006077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TES
T_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.spi_device_mem_parity.69006077
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.695087727
Short name T647
Test name
Test status
Simulation time 38002849530 ps
CPU time 25.24 seconds
Started Aug 06 04:44:26 PM PDT 24
Finished Aug 06 04:44:51 PM PDT 24
Peak memory 225100 kb
Host smart-ffe10670-44dc-4bec-8ccc-2a7f51fc4dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695087727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap.
695087727
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.534863588
Short name T577
Test name
Test status
Simulation time 17625005268 ps
CPU time 9.2 seconds
Started Aug 06 04:44:33 PM PDT 24
Finished Aug 06 04:44:42 PM PDT 24
Peak memory 233304 kb
Host smart-e99faee8-e2c1-4815-b55a-f8cb01fcb9d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534863588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.534863588
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.3093211272
Short name T769
Test name
Test status
Simulation time 469730338 ps
CPU time 5.48 seconds
Started Aug 06 04:44:28 PM PDT 24
Finished Aug 06 04:44:34 PM PDT 24
Peak memory 221404 kb
Host smart-5a9467bf-f09e-4445-9ead-cf8b033c614a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3093211272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.3093211272
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.4225438672
Short name T46
Test name
Test status
Simulation time 741275085 ps
CPU time 1.15 seconds
Started Aug 06 04:44:37 PM PDT 24
Finished Aug 06 04:44:38 PM PDT 24
Peak memory 236520 kb
Host smart-decb470b-1678-4a11-a3c4-146921ddbe1c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225438672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.4225438672
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.3298060313
Short name T557
Test name
Test status
Simulation time 255591653259 ps
CPU time 542.8 seconds
Started Aug 06 04:44:26 PM PDT 24
Finished Aug 06 04:53:29 PM PDT 24
Peak memory 268388 kb
Host smart-6f841350-ee52-4f17-830f-1241e234a34c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298060313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.3298060313
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.98533878
Short name T620
Test name
Test status
Simulation time 2803043264 ps
CPU time 2.51 seconds
Started Aug 06 04:44:37 PM PDT 24
Finished Aug 06 04:44:40 PM PDT 24
Peak memory 219500 kb
Host smart-c67aa24b-3316-4104-b544-b417ec78487e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98533878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.98533878
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.2718584994
Short name T360
Test name
Test status
Simulation time 3685878775 ps
CPU time 8.63 seconds
Started Aug 06 04:44:31 PM PDT 24
Finished Aug 06 04:44:40 PM PDT 24
Peak memory 217056 kb
Host smart-793e571b-a3ac-4a8d-96aa-fa97917bb763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718584994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.2718584994
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.774686253
Short name T825
Test name
Test status
Simulation time 88613237 ps
CPU time 1.8 seconds
Started Aug 06 04:44:29 PM PDT 24
Finished Aug 06 04:44:31 PM PDT 24
Peak memory 216784 kb
Host smart-4bb48841-a83f-4f2b-9ab0-7b6ee5dead77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774686253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.774686253
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.1114257574
Short name T468
Test name
Test status
Simulation time 179476935 ps
CPU time 0.83 seconds
Started Aug 06 04:44:27 PM PDT 24
Finished Aug 06 04:44:28 PM PDT 24
Peak memory 206352 kb
Host smart-b696f66f-2a7a-4fe2-a520-fa51cb9f844a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114257574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.1114257574
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.3849303887
Short name T339
Test name
Test status
Simulation time 3406364559 ps
CPU time 8.25 seconds
Started Aug 06 04:44:23 PM PDT 24
Finished Aug 06 04:44:31 PM PDT 24
Peak memory 233456 kb
Host smart-e58e3ae1-a689-4f08-945c-b82e7e69ebea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849303887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.3849303887
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.2477512887
Short name T543
Test name
Test status
Simulation time 43136930 ps
CPU time 0.74 seconds
Started Aug 06 04:45:47 PM PDT 24
Finished Aug 06 04:45:48 PM PDT 24
Peak memory 205268 kb
Host smart-c67ccb01-a90e-42ff-97a4-04e53dbc1db0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477512887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
2477512887
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.4091287532
Short name T72
Test name
Test status
Simulation time 1415380837 ps
CPU time 12.01 seconds
Started Aug 06 04:45:47 PM PDT 24
Finished Aug 06 04:45:59 PM PDT 24
Peak memory 224884 kb
Host smart-16655983-3ef9-493c-a65f-7c0d483901d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091287532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.4091287532
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.3084466163
Short name T498
Test name
Test status
Simulation time 16302116 ps
CPU time 0.78 seconds
Started Aug 06 04:45:49 PM PDT 24
Finished Aug 06 04:45:50 PM PDT 24
Peak memory 207036 kb
Host smart-31f3b865-314f-4672-9ec1-8078714d7d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084466163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.3084466163
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.1905790801
Short name T34
Test name
Test status
Simulation time 5064253896 ps
CPU time 66.64 seconds
Started Aug 06 04:45:46 PM PDT 24
Finished Aug 06 04:46:53 PM PDT 24
Peak memory 258076 kb
Host smart-e8c38440-a924-47b6-b63f-7118a13d8b9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905790801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.1905790801
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.3979899476
Short name T755
Test name
Test status
Simulation time 4009131440 ps
CPU time 46.04 seconds
Started Aug 06 04:45:52 PM PDT 24
Finished Aug 06 04:46:39 PM PDT 24
Peak memory 250324 kb
Host smart-5185db37-c6ba-4c86-869b-98a6f54e270a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979899476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.3979899476
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.1265679212
Short name T210
Test name
Test status
Simulation time 14580324304 ps
CPU time 95.43 seconds
Started Aug 06 04:45:46 PM PDT 24
Finished Aug 06 04:47:22 PM PDT 24
Peak memory 241660 kb
Host smart-2f365669-8007-4a9e-a176-d8b1be1ceeac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265679212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.1265679212
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.4174492766
Short name T653
Test name
Test status
Simulation time 3780809295 ps
CPU time 11.52 seconds
Started Aug 06 04:45:48 PM PDT 24
Finished Aug 06 04:46:00 PM PDT 24
Peak memory 225296 kb
Host smart-6a13ca39-8c04-435b-8a8e-18df6abe9026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174492766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmd
s.4174492766
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/20.spi_device_intercept.2822498849
Short name T342
Test name
Test status
Simulation time 1394385482 ps
CPU time 10.15 seconds
Started Aug 06 04:45:41 PM PDT 24
Finished Aug 06 04:45:51 PM PDT 24
Peak memory 225188 kb
Host smart-70072c57-6a5e-4b25-aa56-e2f306909973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822498849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.2822498849
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.1221732061
Short name T907
Test name
Test status
Simulation time 777496455 ps
CPU time 11.68 seconds
Started Aug 06 04:45:47 PM PDT 24
Finished Aug 06 04:45:59 PM PDT 24
Peak memory 241024 kb
Host smart-4ab89544-0ba8-46b2-ab15-191d4406de23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221732061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.1221732061
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.1197885043
Short name T365
Test name
Test status
Simulation time 73852487 ps
CPU time 2.25 seconds
Started Aug 06 04:45:39 PM PDT 24
Finished Aug 06 04:45:41 PM PDT 24
Peak memory 223480 kb
Host smart-df14f9d6-1c27-4fb9-a982-dd2c9c95e11c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197885043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.1197885043
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.3798451242
Short name T418
Test name
Test status
Simulation time 676643433 ps
CPU time 2.8 seconds
Started Aug 06 04:45:48 PM PDT 24
Finished Aug 06 04:45:51 PM PDT 24
Peak memory 225060 kb
Host smart-d0b92542-d7ee-4366-b922-367c6395d22c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798451242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.3798451242
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.599149575
Short name T530
Test name
Test status
Simulation time 86389649 ps
CPU time 3.61 seconds
Started Aug 06 04:45:53 PM PDT 24
Finished Aug 06 04:45:57 PM PDT 24
Peak memory 223512 kb
Host smart-2de5a8f9-1f31-40c6-8eb4-d6a461687b97
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=599149575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dire
ct.599149575
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.2889588809
Short name T21
Test name
Test status
Simulation time 10535346286 ps
CPU time 78.88 seconds
Started Aug 06 04:45:49 PM PDT 24
Finished Aug 06 04:47:08 PM PDT 24
Peak memory 240208 kb
Host smart-3dbbc3ce-fdaa-4f63-b268-b0b40b9e31af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889588809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.2889588809
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.135132510
Short name T971
Test name
Test status
Simulation time 1624026002 ps
CPU time 17.09 seconds
Started Aug 06 04:45:48 PM PDT 24
Finished Aug 06 04:46:05 PM PDT 24
Peak memory 217108 kb
Host smart-e596e0ee-26ba-4d51-8b88-a5cacbbf212d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135132510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.135132510
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.211336093
Short name T514
Test name
Test status
Simulation time 52103948 ps
CPU time 0.67 seconds
Started Aug 06 04:45:49 PM PDT 24
Finished Aug 06 04:45:50 PM PDT 24
Peak memory 206008 kb
Host smart-be5e0024-763e-49bd-905f-6831faf5033d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211336093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.211336093
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.1580078045
Short name T633
Test name
Test status
Simulation time 276139616 ps
CPU time 1.05 seconds
Started Aug 06 04:45:46 PM PDT 24
Finished Aug 06 04:45:48 PM PDT 24
Peak memory 207940 kb
Host smart-dd511a60-750e-4666-b42b-04e9c2018e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580078045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.1580078045
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.96753353
Short name T651
Test name
Test status
Simulation time 127556089 ps
CPU time 1.06 seconds
Started Aug 06 04:45:41 PM PDT 24
Finished Aug 06 04:45:42 PM PDT 24
Peak memory 206504 kb
Host smart-fd7fa2f9-0e7f-4e84-a12e-43c92803d9f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96753353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.96753353
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.822390642
Short name T908
Test name
Test status
Simulation time 11159423808 ps
CPU time 30.85 seconds
Started Aug 06 04:45:54 PM PDT 24
Finished Aug 06 04:46:24 PM PDT 24
Peak memory 233428 kb
Host smart-8868027e-9cae-4504-89b9-b2bd5f483b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822390642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.822390642
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.2803647165
Short name T917
Test name
Test status
Simulation time 44851520 ps
CPU time 0.72 seconds
Started Aug 06 04:45:46 PM PDT 24
Finished Aug 06 04:45:47 PM PDT 24
Peak memory 205252 kb
Host smart-fd9217e8-559e-4229-82a1-488526ceec4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803647165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
2803647165
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.737489296
Short name T406
Test name
Test status
Simulation time 162413111 ps
CPU time 2.54 seconds
Started Aug 06 04:45:48 PM PDT 24
Finished Aug 06 04:45:51 PM PDT 24
Peak memory 233396 kb
Host smart-2a2daaa8-88f9-4f9e-9465-04248dafbc3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737489296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.737489296
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.4240050355
Short name T321
Test name
Test status
Simulation time 81179350 ps
CPU time 0.76 seconds
Started Aug 06 04:45:44 PM PDT 24
Finished Aug 06 04:45:44 PM PDT 24
Peak memory 207240 kb
Host smart-e799ba3e-5b6c-44f2-b6c0-b3d73cea038c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240050355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.4240050355
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.215523565
Short name T937
Test name
Test status
Simulation time 113431963239 ps
CPU time 203.4 seconds
Started Aug 06 04:45:46 PM PDT 24
Finished Aug 06 04:49:10 PM PDT 24
Peak memory 252840 kb
Host smart-a7f8a0e8-0c9a-41aa-ae66-54623be72ced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215523565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.215523565
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.1121521386
Short name T207
Test name
Test status
Simulation time 12137144087 ps
CPU time 54.71 seconds
Started Aug 06 04:45:47 PM PDT 24
Finished Aug 06 04:46:42 PM PDT 24
Peak memory 252032 kb
Host smart-177bf774-bf4e-4d69-b3fc-a378577b8c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121521386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.1121521386
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.1603733482
Short name T778
Test name
Test status
Simulation time 4920324109 ps
CPU time 70.6 seconds
Started Aug 06 04:45:48 PM PDT 24
Finished Aug 06 04:46:59 PM PDT 24
Peak memory 249932 kb
Host smart-66503734-b6bc-4440-acb8-9c1a9b9cddbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603733482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.1603733482
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.255588027
Short name T794
Test name
Test status
Simulation time 2380748813 ps
CPU time 7.73 seconds
Started Aug 06 04:45:47 PM PDT 24
Finished Aug 06 04:45:55 PM PDT 24
Peak memory 233432 kb
Host smart-3692ae9a-7bd9-4244-99fc-ff21c8bb7a93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255588027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.255588027
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.636433973
Short name T275
Test name
Test status
Simulation time 27870177990 ps
CPU time 92.02 seconds
Started Aug 06 04:45:48 PM PDT 24
Finished Aug 06 04:47:20 PM PDT 24
Peak memory 249848 kb
Host smart-e274ed08-5004-46d6-b717-927598c828f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636433973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmds
.636433973
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_intercept.636132406
Short name T265
Test name
Test status
Simulation time 1278733124 ps
CPU time 13.65 seconds
Started Aug 06 04:45:45 PM PDT 24
Finished Aug 06 04:45:59 PM PDT 24
Peak memory 233312 kb
Host smart-3afdfd96-abf7-4f47-9dea-c48276d46c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636132406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.636132406
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.177511508
Short name T746
Test name
Test status
Simulation time 257572237 ps
CPU time 7.23 seconds
Started Aug 06 04:45:47 PM PDT 24
Finished Aug 06 04:45:54 PM PDT 24
Peak memory 233424 kb
Host smart-909bb314-0cdf-4a52-855e-56633cfe0c02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177511508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.177511508
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.2421381285
Short name T898
Test name
Test status
Simulation time 26606958568 ps
CPU time 10.36 seconds
Started Aug 06 04:45:49 PM PDT 24
Finished Aug 06 04:46:00 PM PDT 24
Peak memory 225128 kb
Host smart-d00ac40a-69ea-4715-b460-bcb67d6c4bb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421381285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.2421381285
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.3005343738
Short name T993
Test name
Test status
Simulation time 483423976 ps
CPU time 2.37 seconds
Started Aug 06 04:45:44 PM PDT 24
Finished Aug 06 04:45:46 PM PDT 24
Peak memory 223728 kb
Host smart-bf751c1e-f393-40cd-b81b-4720ce523a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005343738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.3005343738
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.3350461338
Short name T9
Test name
Test status
Simulation time 2816935863 ps
CPU time 9.77 seconds
Started Aug 06 04:45:46 PM PDT 24
Finished Aug 06 04:45:55 PM PDT 24
Peak memory 222992 kb
Host smart-b83cb47f-421a-4497-9426-eac762681cf7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3350461338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.3350461338
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.369247590
Short name T915
Test name
Test status
Simulation time 5048532990 ps
CPU time 17.03 seconds
Started Aug 06 04:45:43 PM PDT 24
Finished Aug 06 04:46:00 PM PDT 24
Peak memory 216940 kb
Host smart-57ec9e2a-49d7-4fe3-9608-69a62745d9c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369247590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.369247590
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.2580018112
Short name T833
Test name
Test status
Simulation time 450810506 ps
CPU time 2.59 seconds
Started Aug 06 04:45:46 PM PDT 24
Finished Aug 06 04:45:48 PM PDT 24
Peak memory 216928 kb
Host smart-7b8834b3-2318-45b4-9a08-14314a70bef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580018112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.2580018112
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.354923100
Short name T383
Test name
Test status
Simulation time 13879549 ps
CPU time 0.75 seconds
Started Aug 06 04:45:42 PM PDT 24
Finished Aug 06 04:45:43 PM PDT 24
Peak memory 206552 kb
Host smart-711be753-f190-4cb0-ba53-798433469349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354923100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.354923100
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.1888894472
Short name T473
Test name
Test status
Simulation time 308819897 ps
CPU time 0.89 seconds
Started Aug 06 04:45:49 PM PDT 24
Finished Aug 06 04:45:50 PM PDT 24
Peak memory 207452 kb
Host smart-c57354e1-66a0-41cc-a9e6-43e82f144a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888894472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.1888894472
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.1750096697
Short name T760
Test name
Test status
Simulation time 802057477 ps
CPU time 6.69 seconds
Started Aug 06 04:45:41 PM PDT 24
Finished Aug 06 04:45:48 PM PDT 24
Peak memory 225148 kb
Host smart-ebaa75af-78a2-4d3b-927f-c1d351f0de94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750096697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.1750096697
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.2835469112
Short name T379
Test name
Test status
Simulation time 19853553 ps
CPU time 0.71 seconds
Started Aug 06 04:45:53 PM PDT 24
Finished Aug 06 04:45:54 PM PDT 24
Peak memory 205800 kb
Host smart-6501c08d-4e91-4bcb-9b04-112a3b46e396
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835469112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
2835469112
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.3829007183
Short name T231
Test name
Test status
Simulation time 517273480 ps
CPU time 3.85 seconds
Started Aug 06 04:45:49 PM PDT 24
Finished Aug 06 04:45:53 PM PDT 24
Peak memory 233412 kb
Host smart-9b52fb57-c6e2-4867-b7fb-cc8408e4b04c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829007183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.3829007183
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.2344731875
Short name T816
Test name
Test status
Simulation time 17567068 ps
CPU time 0.77 seconds
Started Aug 06 04:45:49 PM PDT 24
Finished Aug 06 04:45:50 PM PDT 24
Peak memory 206952 kb
Host smart-e9f8c823-ab5a-4538-8904-bb25d7b23f6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344731875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.2344731875
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.3522511106
Short name T217
Test name
Test status
Simulation time 197098679407 ps
CPU time 300.94 seconds
Started Aug 06 04:45:48 PM PDT 24
Finished Aug 06 04:50:49 PM PDT 24
Peak memory 254408 kb
Host smart-eef35f50-cdf5-46b9-888f-1dd256b8f9e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522511106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.3522511106
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.3684997852
Short name T183
Test name
Test status
Simulation time 39399437913 ps
CPU time 127.47 seconds
Started Aug 06 04:45:47 PM PDT 24
Finished Aug 06 04:47:54 PM PDT 24
Peak memory 273172 kb
Host smart-a91ea8dd-d41f-49cc-a4e6-4b4abbc154e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684997852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.3684997852
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.2112357556
Short name T58
Test name
Test status
Simulation time 476867225 ps
CPU time 3.73 seconds
Started Aug 06 04:45:49 PM PDT 24
Finished Aug 06 04:45:53 PM PDT 24
Peak memory 240272 kb
Host smart-8a4640d2-1da4-41d4-8691-89efbe596d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112357556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.2112357556
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.1462720034
Short name T294
Test name
Test status
Simulation time 13839772926 ps
CPU time 77.94 seconds
Started Aug 06 04:45:47 PM PDT 24
Finished Aug 06 04:47:05 PM PDT 24
Peak memory 252020 kb
Host smart-ffec3d5f-ccf5-4226-9a8c-f554c46d26f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462720034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmd
s.1462720034
Directory /workspace/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/22.spi_device_intercept.4150159561
Short name T774
Test name
Test status
Simulation time 434633085 ps
CPU time 3.3 seconds
Started Aug 06 04:45:49 PM PDT 24
Finished Aug 06 04:45:52 PM PDT 24
Peak memory 233376 kb
Host smart-b1e11f4e-fa8e-48af-bad5-7ebc4ac63c34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150159561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.4150159561
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.4200890987
Short name T674
Test name
Test status
Simulation time 3731817410 ps
CPU time 37.57 seconds
Started Aug 06 04:45:49 PM PDT 24
Finished Aug 06 04:46:27 PM PDT 24
Peak memory 233288 kb
Host smart-50ccba66-1b65-481d-a6bc-bc1b0becb424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200890987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.4200890987
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.3333396471
Short name T999
Test name
Test status
Simulation time 33440868370 ps
CPU time 15.71 seconds
Started Aug 06 04:45:49 PM PDT 24
Finished Aug 06 04:46:05 PM PDT 24
Peak memory 233336 kb
Host smart-fbf629fd-45c0-4403-8c33-68d63d6df353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333396471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.3333396471
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.741895216
Short name T724
Test name
Test status
Simulation time 305282495 ps
CPU time 5.45 seconds
Started Aug 06 04:45:37 PM PDT 24
Finished Aug 06 04:45:42 PM PDT 24
Peak memory 225200 kb
Host smart-ed003438-2fac-41b8-aba7-3b8dfd97f374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741895216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.741895216
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.3305315822
Short name T330
Test name
Test status
Simulation time 3028643609 ps
CPU time 9.48 seconds
Started Aug 06 04:45:47 PM PDT 24
Finished Aug 06 04:45:56 PM PDT 24
Peak memory 220568 kb
Host smart-5c278b1a-0105-4caa-a98d-cb955325d0ce
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3305315822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.3305315822
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.1648808462
Short name T149
Test name
Test status
Simulation time 3186628570 ps
CPU time 35.86 seconds
Started Aug 06 04:45:46 PM PDT 24
Finished Aug 06 04:46:22 PM PDT 24
Peak memory 248908 kb
Host smart-dca21a0b-7e1d-4b45-9ecb-c0420864815a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648808462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.1648808462
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.3885209380
Short name T782
Test name
Test status
Simulation time 4271942230 ps
CPU time 21.65 seconds
Started Aug 06 04:45:49 PM PDT 24
Finished Aug 06 04:46:11 PM PDT 24
Peak memory 216940 kb
Host smart-486469c6-2e43-4e12-8caa-8d504c0c7f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885209380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.3885209380
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.106940939
Short name T721
Test name
Test status
Simulation time 3346985639 ps
CPU time 11.1 seconds
Started Aug 06 04:45:47 PM PDT 24
Finished Aug 06 04:45:58 PM PDT 24
Peak memory 216876 kb
Host smart-b3ece815-5c88-4f60-ab0b-8b949eb9f030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106940939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.106940939
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.2297459574
Short name T376
Test name
Test status
Simulation time 132213595 ps
CPU time 1.98 seconds
Started Aug 06 04:45:48 PM PDT 24
Finished Aug 06 04:45:50 PM PDT 24
Peak memory 216836 kb
Host smart-03b12158-ace5-4c2a-b030-a9f75ede93d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297459574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.2297459574
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.3093295379
Short name T841
Test name
Test status
Simulation time 45953858 ps
CPU time 0.87 seconds
Started Aug 06 04:45:49 PM PDT 24
Finished Aug 06 04:45:50 PM PDT 24
Peak memory 206468 kb
Host smart-e5e1363d-3486-4836-ab83-9974ba0aac93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093295379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.3093295379
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.1782611773
Short name T393
Test name
Test status
Simulation time 7837584111 ps
CPU time 8.31 seconds
Started Aug 06 04:45:49 PM PDT 24
Finished Aug 06 04:45:58 PM PDT 24
Peak memory 225296 kb
Host smart-caa2b5cd-4b6d-4644-8d84-73a3014b29a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782611773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.1782611773
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.3753222458
Short name T608
Test name
Test status
Simulation time 11029195 ps
CPU time 0.73 seconds
Started Aug 06 04:45:51 PM PDT 24
Finished Aug 06 04:45:52 PM PDT 24
Peak memory 205812 kb
Host smart-75311eb4-0120-4043-8f5c-1caa65696563
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753222458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
3753222458
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.1462018041
Short name T997
Test name
Test status
Simulation time 132511012 ps
CPU time 4.11 seconds
Started Aug 06 04:45:37 PM PDT 24
Finished Aug 06 04:45:42 PM PDT 24
Peak memory 233244 kb
Host smart-0a5f5f1e-6d80-4bba-b949-58d8b6a16c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462018041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.1462018041
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.4250197406
Short name T693
Test name
Test status
Simulation time 25234687 ps
CPU time 0.85 seconds
Started Aug 06 04:45:50 PM PDT 24
Finished Aug 06 04:45:51 PM PDT 24
Peak memory 206896 kb
Host smart-a70da8f5-a460-46da-a20b-cdbc42d7a1c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250197406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.4250197406
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.1412628239
Short name T839
Test name
Test status
Simulation time 28578902536 ps
CPU time 53.03 seconds
Started Aug 06 04:45:51 PM PDT 24
Finished Aug 06 04:46:44 PM PDT 24
Peak memory 240152 kb
Host smart-3d96764a-b773-46d5-b15d-c7c19edca62b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412628239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.1412628239
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.2378057641
Short name T31
Test name
Test status
Simulation time 86859948306 ps
CPU time 382.34 seconds
Started Aug 06 04:45:53 PM PDT 24
Finished Aug 06 04:52:16 PM PDT 24
Peak memory 253708 kb
Host smart-2f9bd6ce-5574-49e1-bb7a-4f7137453839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378057641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.2378057641
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.2945146041
Short name T948
Test name
Test status
Simulation time 2314551816 ps
CPU time 57.02 seconds
Started Aug 06 04:45:50 PM PDT 24
Finished Aug 06 04:46:47 PM PDT 24
Peak memory 251036 kb
Host smart-2ec4711a-e65c-4f02-9fb2-392da461d770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945146041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.2945146041
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.773251083
Short name T442
Test name
Test status
Simulation time 3873363282 ps
CPU time 51.5 seconds
Started Aug 06 04:45:47 PM PDT 24
Finished Aug 06 04:46:39 PM PDT 24
Peak memory 241620 kb
Host smart-010d3a34-faa8-454e-83aa-09ecb36217bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773251083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.773251083
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_intercept.1970764569
Short name T776
Test name
Test status
Simulation time 372143715 ps
CPU time 6.88 seconds
Started Aug 06 04:45:53 PM PDT 24
Finished Aug 06 04:46:00 PM PDT 24
Peak memory 233396 kb
Host smart-a15770fd-8207-4935-82f0-856b2f44d7f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970764569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.1970764569
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.921364015
Short name T197
Test name
Test status
Simulation time 1529199510 ps
CPU time 12.08 seconds
Started Aug 06 04:45:46 PM PDT 24
Finished Aug 06 04:45:58 PM PDT 24
Peak memory 233440 kb
Host smart-41c93f3c-ce35-4c77-9f87-b8b6c34ae426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921364015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.921364015
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.3529443706
Short name T449
Test name
Test status
Simulation time 2485871408 ps
CPU time 8.16 seconds
Started Aug 06 04:45:53 PM PDT 24
Finished Aug 06 04:46:02 PM PDT 24
Peak memory 225192 kb
Host smart-c467cba1-5cf2-4f63-a038-aa47197dac5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529443706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.3529443706
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.1217078640
Short name T537
Test name
Test status
Simulation time 526221422 ps
CPU time 4.47 seconds
Started Aug 06 04:45:47 PM PDT 24
Finished Aug 06 04:45:51 PM PDT 24
Peak memory 233424 kb
Host smart-4e3e9a2a-db31-421e-8bd4-4da28b455f14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217078640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.1217078640
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.3957603512
Short name T695
Test name
Test status
Simulation time 4682642778 ps
CPU time 10.86 seconds
Started Aug 06 04:46:00 PM PDT 24
Finished Aug 06 04:46:11 PM PDT 24
Peak memory 223608 kb
Host smart-085e4dd2-0f0e-4acf-a6e7-7cb1e8f74332
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3957603512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.3957603512
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.2705548683
Short name T994
Test name
Test status
Simulation time 2874396379 ps
CPU time 13.87 seconds
Started Aug 06 04:45:53 PM PDT 24
Finished Aug 06 04:46:07 PM PDT 24
Peak memory 217008 kb
Host smart-4fb9ad61-f4e7-44e7-a6a8-88da55c5e9f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705548683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.2705548683
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.3529599048
Short name T860
Test name
Test status
Simulation time 843463534 ps
CPU time 5.62 seconds
Started Aug 06 04:45:53 PM PDT 24
Finished Aug 06 04:45:58 PM PDT 24
Peak memory 216928 kb
Host smart-495234b2-cb9e-4d19-a673-4875d37a4628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529599048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.3529599048
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.30492058
Short name T436
Test name
Test status
Simulation time 336723293 ps
CPU time 10.28 seconds
Started Aug 06 04:45:52 PM PDT 24
Finished Aug 06 04:46:03 PM PDT 24
Peak memory 216896 kb
Host smart-66605853-d19d-44f4-a953-8bcd03626a13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30492058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.30492058
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.2644688873
Short name T738
Test name
Test status
Simulation time 80025132 ps
CPU time 0.89 seconds
Started Aug 06 04:45:39 PM PDT 24
Finished Aug 06 04:45:40 PM PDT 24
Peak memory 206468 kb
Host smart-b9e41cde-6a48-4b41-8534-15131a136a26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644688873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.2644688873
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.4235397553
Short name T229
Test name
Test status
Simulation time 3401175978 ps
CPU time 6.08 seconds
Started Aug 06 04:45:45 PM PDT 24
Finished Aug 06 04:45:52 PM PDT 24
Peak memory 233436 kb
Host smart-d04d7d8a-69b9-4735-bc66-8d787f15d84a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235397553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.4235397553
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.2766932012
Short name T43
Test name
Test status
Simulation time 14737576 ps
CPU time 0.74 seconds
Started Aug 06 04:45:54 PM PDT 24
Finished Aug 06 04:45:55 PM PDT 24
Peak memory 205760 kb
Host smart-51d52826-d39f-41f0-a0f9-54a4b8c0049d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766932012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
2766932012
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.2949185865
Short name T622
Test name
Test status
Simulation time 667108859 ps
CPU time 6.11 seconds
Started Aug 06 04:45:52 PM PDT 24
Finished Aug 06 04:45:58 PM PDT 24
Peak memory 233368 kb
Host smart-79101969-7e73-406a-be4a-8c6db429f8eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949185865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.2949185865
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.329804037
Short name T610
Test name
Test status
Simulation time 14951159 ps
CPU time 0.71 seconds
Started Aug 06 04:45:50 PM PDT 24
Finished Aug 06 04:45:51 PM PDT 24
Peak memory 206292 kb
Host smart-89dda2ca-27de-41c1-830c-f59d4d31137a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329804037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.329804037
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.1795897608
Short name T287
Test name
Test status
Simulation time 206791982838 ps
CPU time 359.61 seconds
Started Aug 06 04:45:55 PM PDT 24
Finished Aug 06 04:51:55 PM PDT 24
Peak memory 268156 kb
Host smart-2b794cd1-dfc0-41d9-880f-d172823bdf29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795897608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.1795897608
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.1694923157
Short name T720
Test name
Test status
Simulation time 27262536518 ps
CPU time 101.48 seconds
Started Aug 06 04:45:54 PM PDT 24
Finished Aug 06 04:47:35 PM PDT 24
Peak memory 258016 kb
Host smart-6a5a44ce-ba82-41e1-b47c-d09683a2a509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694923157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.1694923157
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.85026228
Short name T285
Test name
Test status
Simulation time 9518443147 ps
CPU time 82.62 seconds
Started Aug 06 04:46:01 PM PDT 24
Finished Aug 06 04:47:24 PM PDT 24
Peak memory 264476 kb
Host smart-9dadcfc1-dd40-4544-aa99-416bc84a5d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85026228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idle.85026228
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.436092711
Short name T888
Test name
Test status
Simulation time 114120138 ps
CPU time 3.18 seconds
Started Aug 06 04:45:56 PM PDT 24
Finished Aug 06 04:45:59 PM PDT 24
Peak memory 224876 kb
Host smart-633c0883-1522-441b-8e5a-9415c212fc19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436092711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.436092711
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.506008237
Short name T585
Test name
Test status
Simulation time 10329460012 ps
CPU time 20.48 seconds
Started Aug 06 04:45:54 PM PDT 24
Finished Aug 06 04:46:15 PM PDT 24
Peak memory 225172 kb
Host smart-11ee3fa6-a13a-4a58-af70-38839a102a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506008237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmds
.506008237
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/24.spi_device_intercept.3266572477
Short name T792
Test name
Test status
Simulation time 332740421 ps
CPU time 5.16 seconds
Started Aug 06 04:45:49 PM PDT 24
Finished Aug 06 04:45:55 PM PDT 24
Peak memory 233444 kb
Host smart-eb925e1c-b855-4c88-825b-dab0988d6e69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266572477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.3266572477
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.3665762446
Short name T583
Test name
Test status
Simulation time 71247305733 ps
CPU time 60.05 seconds
Started Aug 06 04:45:59 PM PDT 24
Finished Aug 06 04:47:00 PM PDT 24
Peak memory 241264 kb
Host smart-d694fed6-eaa2-44c4-939f-a57e0179213d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665762446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.3665762446
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.3024027692
Short name T263
Test name
Test status
Simulation time 1001812897 ps
CPU time 4.77 seconds
Started Aug 06 04:46:00 PM PDT 24
Finished Aug 06 04:46:05 PM PDT 24
Peak memory 233288 kb
Host smart-5945adf7-cfb5-4293-8678-eba2ae596b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024027692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.3024027692
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.1240991208
Short name T966
Test name
Test status
Simulation time 311405574 ps
CPU time 2.24 seconds
Started Aug 06 04:45:56 PM PDT 24
Finished Aug 06 04:45:58 PM PDT 24
Peak memory 223764 kb
Host smart-bddc1aff-bcec-40cf-b780-13aa4e643dc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240991208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.1240991208
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.4165560943
Short name T503
Test name
Test status
Simulation time 1013632336 ps
CPU time 11.36 seconds
Started Aug 06 04:45:48 PM PDT 24
Finished Aug 06 04:45:59 PM PDT 24
Peak memory 222820 kb
Host smart-748347de-d8be-4e45-87ea-58b011797c0a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4165560943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.4165560943
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.1604335922
Short name T963
Test name
Test status
Simulation time 11385689270 ps
CPU time 115.22 seconds
Started Aug 06 04:46:00 PM PDT 24
Finished Aug 06 04:47:56 PM PDT 24
Peak memory 250976 kb
Host smart-6031f1e3-40f7-44d9-93d4-29ec44bdd231
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604335922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.1604335922
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.667485127
Short name T987
Test name
Test status
Simulation time 85375276 ps
CPU time 0.69 seconds
Started Aug 06 04:45:54 PM PDT 24
Finished Aug 06 04:45:55 PM PDT 24
Peak memory 206164 kb
Host smart-5a460db5-d8d5-4f5a-a430-d5517c40ac46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667485127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.667485127
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.3947482092
Short name T527
Test name
Test status
Simulation time 394023599 ps
CPU time 2.14 seconds
Started Aug 06 04:45:51 PM PDT 24
Finished Aug 06 04:45:54 PM PDT 24
Peak memory 208512 kb
Host smart-329b6d0c-4162-4c10-9039-edd42b3c0928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947482092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.3947482092
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.3230683942
Short name T396
Test name
Test status
Simulation time 155070480 ps
CPU time 1.17 seconds
Started Aug 06 04:45:54 PM PDT 24
Finished Aug 06 04:45:56 PM PDT 24
Peak memory 207576 kb
Host smart-c183bc2c-0d0e-4014-82a9-defa505668df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230683942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.3230683942
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.1461342632
Short name T737
Test name
Test status
Simulation time 127053459 ps
CPU time 0.8 seconds
Started Aug 06 04:45:52 PM PDT 24
Finished Aug 06 04:45:53 PM PDT 24
Peak memory 206528 kb
Host smart-bce11b63-fca7-4e20-9bd0-31fd959d089b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461342632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.1461342632
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.4002534953
Short name T200
Test name
Test status
Simulation time 1153774369 ps
CPU time 7.08 seconds
Started Aug 06 04:45:54 PM PDT 24
Finished Aug 06 04:46:01 PM PDT 24
Peak memory 233396 kb
Host smart-392e2c59-fdaf-4143-93a5-663db2e3fd97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002534953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.4002534953
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.2910147288
Short name T637
Test name
Test status
Simulation time 28068667 ps
CPU time 0.72 seconds
Started Aug 06 04:45:54 PM PDT 24
Finished Aug 06 04:45:55 PM PDT 24
Peak memory 205768 kb
Host smart-cc7fe841-d2b8-491c-9632-d8f6cc02d398
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910147288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
2910147288
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.2774674711
Short name T843
Test name
Test status
Simulation time 538165605 ps
CPU time 4.77 seconds
Started Aug 06 04:45:54 PM PDT 24
Finished Aug 06 04:45:59 PM PDT 24
Peak memory 225216 kb
Host smart-ecf9e913-5d7d-41f9-8d57-7e738650c187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774674711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.2774674711
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.988223653
Short name T501
Test name
Test status
Simulation time 32701429 ps
CPU time 0.78 seconds
Started Aug 06 04:45:51 PM PDT 24
Finished Aug 06 04:45:52 PM PDT 24
Peak memory 207260 kb
Host smart-8f56f463-dd98-4b78-8b41-1b968a851c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988223653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.988223653
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.1198388946
Short name T986
Test name
Test status
Simulation time 10701458666 ps
CPU time 77.45 seconds
Started Aug 06 04:45:57 PM PDT 24
Finished Aug 06 04:47:15 PM PDT 24
Peak memory 249868 kb
Host smart-b371a387-31b1-43b7-8b2f-270998d65c3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198388946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.1198388946
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.1787186347
Short name T535
Test name
Test status
Simulation time 7254048082 ps
CPU time 11.34 seconds
Started Aug 06 04:45:56 PM PDT 24
Finished Aug 06 04:46:07 PM PDT 24
Peak memory 218444 kb
Host smart-a66bed3d-8776-4665-a457-ffa512dfbce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787186347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.1787186347
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.2517949929
Short name T1012
Test name
Test status
Simulation time 126637563 ps
CPU time 3.61 seconds
Started Aug 06 04:45:59 PM PDT 24
Finished Aug 06 04:46:03 PM PDT 24
Peak memory 225112 kb
Host smart-40b82c80-6b55-4db4-bb7d-37273549826e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517949929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.2517949929
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_intercept.194769385
Short name T56
Test name
Test status
Simulation time 7714984698 ps
CPU time 19.05 seconds
Started Aug 06 04:46:00 PM PDT 24
Finished Aug 06 04:46:19 PM PDT 24
Peak memory 225224 kb
Host smart-2f586471-9cea-4a31-863a-3b0e585d13bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194769385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.194769385
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.191242521
Short name T683
Test name
Test status
Simulation time 2384900104 ps
CPU time 30.71 seconds
Started Aug 06 04:45:53 PM PDT 24
Finished Aug 06 04:46:24 PM PDT 24
Peak memory 249796 kb
Host smart-4ea6786f-27cd-4a4d-b61a-d8580bef8c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191242521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.191242521
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.2206115357
Short name T838
Test name
Test status
Simulation time 339187872 ps
CPU time 2.41 seconds
Started Aug 06 04:46:09 PM PDT 24
Finished Aug 06 04:46:11 PM PDT 24
Peak memory 233232 kb
Host smart-6c7571b8-5fb2-43da-873b-16bfb25f1511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206115357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.2206115357
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.3294075930
Short name T869
Test name
Test status
Simulation time 36867959343 ps
CPU time 10.7 seconds
Started Aug 06 04:46:06 PM PDT 24
Finished Aug 06 04:46:17 PM PDT 24
Peak memory 233412 kb
Host smart-f80798c8-862e-41f4-a97c-05447221faef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294075930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.3294075930
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.2007713635
Short name T130
Test name
Test status
Simulation time 1604630137 ps
CPU time 7.72 seconds
Started Aug 06 04:45:55 PM PDT 24
Finished Aug 06 04:46:03 PM PDT 24
Peak memory 223468 kb
Host smart-3636a9c1-041a-4ffd-8e44-a0bc902bcc3b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2007713635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.2007713635
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.614933771
Short name T19
Test name
Test status
Simulation time 159978494832 ps
CPU time 394.82 seconds
Started Aug 06 04:45:54 PM PDT 24
Finished Aug 06 04:52:29 PM PDT 24
Peak memory 254112 kb
Host smart-8ca35478-30c9-455c-b34e-8e5c558e699c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614933771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stres
s_all.614933771
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.3003511196
Short name T718
Test name
Test status
Simulation time 19150048222 ps
CPU time 35.35 seconds
Started Aug 06 04:45:51 PM PDT 24
Finished Aug 06 04:46:26 PM PDT 24
Peak memory 216976 kb
Host smart-221c12b8-04fb-4547-8e84-865f3f217890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003511196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.3003511196
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.1039770822
Short name T995
Test name
Test status
Simulation time 803914530 ps
CPU time 4.36 seconds
Started Aug 06 04:45:57 PM PDT 24
Finished Aug 06 04:46:01 PM PDT 24
Peak memory 216876 kb
Host smart-9b2175f1-33c0-4286-abcd-e81b8361d39a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039770822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.1039770822
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.3671423069
Short name T506
Test name
Test status
Simulation time 93734797 ps
CPU time 1.03 seconds
Started Aug 06 04:46:06 PM PDT 24
Finished Aug 06 04:46:07 PM PDT 24
Peak memory 208436 kb
Host smart-fc03ce65-9e8b-4de1-bd65-fe5543df83ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671423069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.3671423069
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.4153236189
Short name T484
Test name
Test status
Simulation time 69250651 ps
CPU time 0.91 seconds
Started Aug 06 04:46:06 PM PDT 24
Finished Aug 06 04:46:07 PM PDT 24
Peak memory 206464 kb
Host smart-e468e921-1a8c-43a8-84b9-b506b6b1a2ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153236189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.4153236189
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.1918751995
Short name T1032
Test name
Test status
Simulation time 8753446686 ps
CPU time 7.13 seconds
Started Aug 06 04:46:00 PM PDT 24
Finished Aug 06 04:46:08 PM PDT 24
Peak memory 225140 kb
Host smart-47ab6ee9-e553-4492-9173-28d73c116ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918751995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.1918751995
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.4246104650
Short name T886
Test name
Test status
Simulation time 45008969 ps
CPU time 0.71 seconds
Started Aug 06 04:45:54 PM PDT 24
Finished Aug 06 04:45:55 PM PDT 24
Peak memory 205084 kb
Host smart-8588b6ea-febf-48cd-b38f-9849397b9e00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246104650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
4246104650
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.1421474804
Short name T766
Test name
Test status
Simulation time 311895064 ps
CPU time 6.15 seconds
Started Aug 06 04:46:09 PM PDT 24
Finished Aug 06 04:46:15 PM PDT 24
Peak memory 233204 kb
Host smart-c594188c-7da7-441a-9b59-29aa81f312f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421474804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.1421474804
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.4244777582
Short name T495
Test name
Test status
Simulation time 13044308 ps
CPU time 0.82 seconds
Started Aug 06 04:45:53 PM PDT 24
Finished Aug 06 04:45:54 PM PDT 24
Peak memory 206944 kb
Host smart-516146fb-ebc7-40cf-b9ef-1c90aef484a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244777582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.4244777582
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.2252354563
Short name T532
Test name
Test status
Simulation time 1887780313 ps
CPU time 20.73 seconds
Started Aug 06 04:45:55 PM PDT 24
Finished Aug 06 04:46:16 PM PDT 24
Peak memory 241520 kb
Host smart-017376e8-909d-49a8-945f-a04c55969581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252354563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.2252354563
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.1515582685
Short name T286
Test name
Test status
Simulation time 163866370566 ps
CPU time 618.32 seconds
Started Aug 06 04:45:54 PM PDT 24
Finished Aug 06 04:56:12 PM PDT 24
Peak memory 271508 kb
Host smart-656bb5ec-8226-47a8-b4e9-097c2d149224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515582685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.1515582685
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.226866459
Short name T1014
Test name
Test status
Simulation time 572797246 ps
CPU time 8.09 seconds
Started Aug 06 04:45:55 PM PDT 24
Finished Aug 06 04:46:03 PM PDT 24
Peak memory 225156 kb
Host smart-77934df6-3d37-4398-bbe4-ebc187604cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226866459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.226866459
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.1294611955
Short name T846
Test name
Test status
Simulation time 22305515376 ps
CPU time 149.04 seconds
Started Aug 06 04:46:00 PM PDT 24
Finished Aug 06 04:48:29 PM PDT 24
Peak memory 257012 kb
Host smart-8b4c8ad5-1450-46cc-994c-b9a30c3814f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294611955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmd
s.1294611955
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_intercept.2371684337
Short name T198
Test name
Test status
Simulation time 3151699847 ps
CPU time 20.32 seconds
Started Aug 06 04:46:09 PM PDT 24
Finished Aug 06 04:46:29 PM PDT 24
Peak memory 233288 kb
Host smart-1af78bb1-1028-4a8c-b83a-ba138359418e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371684337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.2371684337
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.917024028
Short name T228
Test name
Test status
Simulation time 26625169594 ps
CPU time 69.02 seconds
Started Aug 06 04:46:08 PM PDT 24
Finished Aug 06 04:47:17 PM PDT 24
Peak memory 249652 kb
Host smart-65148229-fd47-4c38-87b9-c3ca1c3511ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917024028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.917024028
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.477371309
Short name T150
Test name
Test status
Simulation time 766236939 ps
CPU time 4.44 seconds
Started Aug 06 04:46:08 PM PDT 24
Finished Aug 06 04:46:13 PM PDT 24
Peak memory 233144 kb
Host smart-eb0fb15d-b409-42d7-ac59-c8c5e3e9530a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477371309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swap
.477371309
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.1102839713
Short name T624
Test name
Test status
Simulation time 316976190 ps
CPU time 4.24 seconds
Started Aug 06 04:45:54 PM PDT 24
Finished Aug 06 04:45:58 PM PDT 24
Peak memory 233400 kb
Host smart-1e50170b-510b-4593-b7ac-e0239fd87749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102839713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.1102839713
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.3023900796
Short name T936
Test name
Test status
Simulation time 2133839577 ps
CPU time 4.36 seconds
Started Aug 06 04:45:57 PM PDT 24
Finished Aug 06 04:46:02 PM PDT 24
Peak memory 220900 kb
Host smart-55084221-4f33-4002-8ec2-43aa8be313bb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3023900796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.3023900796
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.2707088012
Short name T851
Test name
Test status
Simulation time 110034707502 ps
CPU time 110.8 seconds
Started Aug 06 04:45:57 PM PDT 24
Finished Aug 06 04:47:48 PM PDT 24
Peak memory 241152 kb
Host smart-ed317799-b266-4a22-b477-0ad3cf23ed4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707088012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.2707088012
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.907782084
Short name T807
Test name
Test status
Simulation time 1142626226 ps
CPU time 15.06 seconds
Started Aug 06 04:46:07 PM PDT 24
Finished Aug 06 04:46:23 PM PDT 24
Peak memory 216888 kb
Host smart-b96011e1-5a46-4517-8b21-2556fae01668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907782084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.907782084
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.3877242568
Short name T320
Test name
Test status
Simulation time 2522744388 ps
CPU time 8.86 seconds
Started Aug 06 04:46:08 PM PDT 24
Finished Aug 06 04:46:17 PM PDT 24
Peak memory 216816 kb
Host smart-2aa33f76-a67a-48cc-b476-1f55ddc742a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877242568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.3877242568
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.1855935189
Short name T1001
Test name
Test status
Simulation time 22098777 ps
CPU time 1.24 seconds
Started Aug 06 04:45:56 PM PDT 24
Finished Aug 06 04:45:58 PM PDT 24
Peak memory 216856 kb
Host smart-90068244-90b4-406a-bd2e-4b991016b291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855935189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.1855935189
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.1978580647
Short name T919
Test name
Test status
Simulation time 71010282 ps
CPU time 0.75 seconds
Started Aug 06 04:45:54 PM PDT 24
Finished Aug 06 04:45:55 PM PDT 24
Peak memory 206460 kb
Host smart-eb200f23-5c8a-46b0-94c3-6ac3d7046f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978580647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.1978580647
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.3656433581
Short name T245
Test name
Test status
Simulation time 10514186182 ps
CPU time 9.05 seconds
Started Aug 06 04:45:56 PM PDT 24
Finished Aug 06 04:46:05 PM PDT 24
Peak memory 233492 kb
Host smart-5758d6ed-f52d-426d-8d8b-3546eb942225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656433581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.3656433581
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.3846023149
Short name T708
Test name
Test status
Simulation time 13972248 ps
CPU time 0.71 seconds
Started Aug 06 04:46:06 PM PDT 24
Finished Aug 06 04:46:06 PM PDT 24
Peak memory 206096 kb
Host smart-9eae6d99-f215-42d6-b1fb-51b95342e998
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846023149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
3846023149
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.1069094171
Short name T578
Test name
Test status
Simulation time 654721770 ps
CPU time 3.56 seconds
Started Aug 06 04:45:58 PM PDT 24
Finished Aug 06 04:46:02 PM PDT 24
Peak memory 225240 kb
Host smart-30915108-0733-496b-b741-ffd9d199ee06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069094171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.1069094171
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.892959595
Short name T658
Test name
Test status
Simulation time 16111536 ps
CPU time 0.77 seconds
Started Aug 06 04:45:56 PM PDT 24
Finished Aug 06 04:45:57 PM PDT 24
Peak memory 207360 kb
Host smart-6d4a5105-c263-43cc-aa1f-995baffce9fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892959595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.892959595
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.595111506
Short name T4
Test name
Test status
Simulation time 66115856985 ps
CPU time 104.37 seconds
Started Aug 06 04:46:02 PM PDT 24
Finished Aug 06 04:47:47 PM PDT 24
Peak memory 252872 kb
Host smart-9e42de99-fcdb-4871-9b70-e1896d12a3e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595111506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.595111506
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.1044209855
Short name T391
Test name
Test status
Simulation time 13676289049 ps
CPU time 49.96 seconds
Started Aug 06 04:46:06 PM PDT 24
Finished Aug 06 04:46:56 PM PDT 24
Peak memory 225260 kb
Host smart-9fe8dd45-f6cc-495b-a5c6-d96a64942e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044209855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.1044209855
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.3088017510
Short name T629
Test name
Test status
Simulation time 942604721 ps
CPU time 5.41 seconds
Started Aug 06 04:45:58 PM PDT 24
Finished Aug 06 04:46:03 PM PDT 24
Peak memory 218220 kb
Host smart-072cbc7d-93c6-4dff-a004-4b8e04472942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088017510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.3088017510
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.3558534587
Short name T87
Test name
Test status
Simulation time 8397520237 ps
CPU time 14.97 seconds
Started Aug 06 04:46:04 PM PDT 24
Finished Aug 06 04:46:20 PM PDT 24
Peak memory 234268 kb
Host smart-75b92f84-3d56-4599-889f-f6c746e2a0f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558534587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.3558534587
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.3551095762
Short name T698
Test name
Test status
Simulation time 1106328550 ps
CPU time 8.63 seconds
Started Aug 06 04:45:59 PM PDT 24
Finished Aug 06 04:46:08 PM PDT 24
Peak memory 249772 kb
Host smart-c16b5477-4c49-4b20-bb26-9b9131615e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551095762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmd
s.3551095762
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/27.spi_device_intercept.1459013663
Short name T678
Test name
Test status
Simulation time 36491884 ps
CPU time 2.13 seconds
Started Aug 06 04:45:58 PM PDT 24
Finished Aug 06 04:46:00 PM PDT 24
Peak memory 233220 kb
Host smart-03416343-81c3-44d6-bbcf-cf045f0ecf8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459013663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.1459013663
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.1177660650
Short name T912
Test name
Test status
Simulation time 29170313993 ps
CPU time 65.84 seconds
Started Aug 06 04:45:58 PM PDT 24
Finished Aug 06 04:47:04 PM PDT 24
Peak memory 241324 kb
Host smart-1e345cab-b179-4f8d-a2b8-71abb0349234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177660650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.1177660650
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.2048301521
Short name T261
Test name
Test status
Simulation time 2403738517 ps
CPU time 10.34 seconds
Started Aug 06 04:45:58 PM PDT 24
Finished Aug 06 04:46:09 PM PDT 24
Peak memory 236980 kb
Host smart-fce95b76-72da-4a70-bcdd-45bf6447c8bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048301521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.2048301521
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.321762210
Short name T563
Test name
Test status
Simulation time 220818994 ps
CPU time 2.9 seconds
Started Aug 06 04:45:56 PM PDT 24
Finished Aug 06 04:45:59 PM PDT 24
Peak memory 225260 kb
Host smart-43f12b0e-75ab-4965-a312-e3c1ce111b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321762210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.321762210
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.899446507
Short name T483
Test name
Test status
Simulation time 539955184 ps
CPU time 4.28 seconds
Started Aug 06 04:45:58 PM PDT 24
Finished Aug 06 04:46:02 PM PDT 24
Peak memory 222860 kb
Host smart-0a9a05e4-e085-43ec-a38f-a2d2286e03a0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=899446507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dire
ct.899446507
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.3477083633
Short name T282
Test name
Test status
Simulation time 299287545610 ps
CPU time 1404.54 seconds
Started Aug 06 04:46:07 PM PDT 24
Finished Aug 06 05:09:32 PM PDT 24
Peak memory 303476 kb
Host smart-e89b5aea-5b6f-4f51-bcf5-dd362182e7e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477083633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.3477083633
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.358933965
Short name T51
Test name
Test status
Simulation time 8149972940 ps
CPU time 38.83 seconds
Started Aug 06 04:45:56 PM PDT 24
Finished Aug 06 04:46:35 PM PDT 24
Peak memory 217076 kb
Host smart-dbc96c4e-ff5b-472f-bf09-89cceae65595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358933965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.358933965
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.1258434815
Short name T363
Test name
Test status
Simulation time 8068312508 ps
CPU time 6.6 seconds
Started Aug 06 04:46:01 PM PDT 24
Finished Aug 06 04:46:07 PM PDT 24
Peak memory 217064 kb
Host smart-f44abfd3-2a6f-4be4-b24f-4e59881495d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258434815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.1258434815
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.1930449106
Short name T57
Test name
Test status
Simulation time 204032503 ps
CPU time 1.21 seconds
Started Aug 06 04:45:55 PM PDT 24
Finished Aug 06 04:45:56 PM PDT 24
Peak memory 216960 kb
Host smart-8f4e7725-66cd-4706-899e-30b3a1ae766e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930449106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.1930449106
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.1252097678
Short name T471
Test name
Test status
Simulation time 39309214 ps
CPU time 0.8 seconds
Started Aug 06 04:46:00 PM PDT 24
Finished Aug 06 04:46:01 PM PDT 24
Peak memory 206556 kb
Host smart-45cd7b46-e9f0-4218-8f83-e370804b8f4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252097678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.1252097678
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.3376509137
Short name T278
Test name
Test status
Simulation time 394041572 ps
CPU time 2.47 seconds
Started Aug 06 04:45:59 PM PDT 24
Finished Aug 06 04:46:01 PM PDT 24
Peak memory 225120 kb
Host smart-ec0741d1-9809-44b1-9216-0134c1349258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376509137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.3376509137
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.1788298768
Short name T336
Test name
Test status
Simulation time 46436045 ps
CPU time 0.69 seconds
Started Aug 06 04:46:19 PM PDT 24
Finished Aug 06 04:46:20 PM PDT 24
Peak memory 205540 kb
Host smart-949f7b5a-3f3d-4f86-89c9-0dd268958b08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788298768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
1788298768
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.703286820
Short name T516
Test name
Test status
Simulation time 2643322202 ps
CPU time 15.01 seconds
Started Aug 06 04:46:08 PM PDT 24
Finished Aug 06 04:46:23 PM PDT 24
Peak memory 233448 kb
Host smart-1574885f-f35c-4aa5-a5df-36acd32eb9b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703286820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.703286820
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.2129096751
Short name T422
Test name
Test status
Simulation time 23327839 ps
CPU time 0.79 seconds
Started Aug 06 04:46:06 PM PDT 24
Finished Aug 06 04:46:07 PM PDT 24
Peak memory 206940 kb
Host smart-fb969969-8043-4209-8494-f6593b2f4a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129096751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.2129096751
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.705512659
Short name T224
Test name
Test status
Simulation time 64219402347 ps
CPU time 212.87 seconds
Started Aug 06 04:46:06 PM PDT 24
Finished Aug 06 04:49:39 PM PDT 24
Peak memory 257088 kb
Host smart-594b3097-7d09-4a2e-82a6-66fef7014ab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705512659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.705512659
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.3433130966
Short name T507
Test name
Test status
Simulation time 2175033179 ps
CPU time 27.85 seconds
Started Aug 06 04:46:04 PM PDT 24
Finished Aug 06 04:46:32 PM PDT 24
Peak memory 218304 kb
Host smart-5b079725-b5d1-4773-875c-e55492891727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433130966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.3433130966
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.4233622790
Short name T37
Test name
Test status
Simulation time 15710916188 ps
CPU time 37.76 seconds
Started Aug 06 04:46:02 PM PDT 24
Finished Aug 06 04:46:40 PM PDT 24
Peak memory 237160 kb
Host smart-796bb669-2304-46f1-a5fb-79c3a50f437a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233622790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.4233622790
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.1351412298
Short name T301
Test name
Test status
Simulation time 3506294970 ps
CPU time 16.86 seconds
Started Aug 06 04:46:05 PM PDT 24
Finished Aug 06 04:46:22 PM PDT 24
Peak memory 249880 kb
Host smart-9f6a3f7d-4399-4b76-8275-b4b46242b7aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351412298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.1351412298
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.745330902
Short name T211
Test name
Test status
Simulation time 10370331794 ps
CPU time 134.64 seconds
Started Aug 06 04:46:07 PM PDT 24
Finished Aug 06 04:48:21 PM PDT 24
Peak memory 253480 kb
Host smart-2cf45703-7912-4b52-b40d-681c8077b03b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745330902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmds
.745330902
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/28.spi_device_intercept.1882744808
Short name T491
Test name
Test status
Simulation time 57402216000 ps
CPU time 31.09 seconds
Started Aug 06 04:46:06 PM PDT 24
Finished Aug 06 04:46:37 PM PDT 24
Peak memory 233468 kb
Host smart-2acb5efb-60ec-411c-9991-df75f954bd49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882744808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.1882744808
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.1836894276
Short name T671
Test name
Test status
Simulation time 17247644121 ps
CPU time 17.61 seconds
Started Aug 06 04:46:05 PM PDT 24
Finished Aug 06 04:46:23 PM PDT 24
Peak memory 249860 kb
Host smart-a8b3d065-7d02-4731-b910-30a9887e350f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836894276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.1836894276
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.2752871310
Short name T283
Test name
Test status
Simulation time 850337306 ps
CPU time 8.31 seconds
Started Aug 06 04:45:54 PM PDT 24
Finished Aug 06 04:46:02 PM PDT 24
Peak memory 233392 kb
Host smart-9914294d-3e66-41ae-bf5d-6c348b1092e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752871310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.2752871310
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.2660122812
Short name T533
Test name
Test status
Simulation time 103504870 ps
CPU time 2.41 seconds
Started Aug 06 04:46:08 PM PDT 24
Finished Aug 06 04:46:10 PM PDT 24
Peak memory 232808 kb
Host smart-9ed811ff-2f6c-420c-a67c-df16395b8eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660122812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.2660122812
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.1563549709
Short name T456
Test name
Test status
Simulation time 2747822407 ps
CPU time 10.67 seconds
Started Aug 06 04:46:07 PM PDT 24
Finished Aug 06 04:46:18 PM PDT 24
Peak memory 223240 kb
Host smart-13ff62f0-6a47-4806-b3b3-79194a473504
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1563549709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.1563549709
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.1282187731
Short name T757
Test name
Test status
Simulation time 13367352537 ps
CPU time 48.46 seconds
Started Aug 06 04:46:07 PM PDT 24
Finished Aug 06 04:46:56 PM PDT 24
Peak memory 255308 kb
Host smart-bab05ca0-d25e-4926-b316-42dcd0f8ca14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282187731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.1282187731
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.808500258
Short name T488
Test name
Test status
Simulation time 3224475980 ps
CPU time 15.01 seconds
Started Aug 06 04:45:56 PM PDT 24
Finished Aug 06 04:46:11 PM PDT 24
Peak memory 220160 kb
Host smart-c9c4b514-1dcc-469c-8cb4-cb141d3c4190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808500258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.808500258
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.1753019655
Short name T490
Test name
Test status
Simulation time 27495659814 ps
CPU time 18.23 seconds
Started Aug 06 04:46:06 PM PDT 24
Finished Aug 06 04:46:24 PM PDT 24
Peak memory 216908 kb
Host smart-02efed1a-a24f-47a9-865a-160a7b044983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753019655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.1753019655
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.2592496607
Short name T354
Test name
Test status
Simulation time 606494710 ps
CPU time 6.69 seconds
Started Aug 06 04:46:05 PM PDT 24
Finished Aug 06 04:46:11 PM PDT 24
Peak memory 216844 kb
Host smart-b913d5a5-c103-4ef0-bfa1-e9a8aac84325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592496607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.2592496607
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.394305164
Short name T754
Test name
Test status
Simulation time 79025801 ps
CPU time 0.96 seconds
Started Aug 06 04:45:55 PM PDT 24
Finished Aug 06 04:45:56 PM PDT 24
Peak memory 206788 kb
Host smart-8df6ace0-2bfa-40ba-9beb-192b88f4e8a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394305164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.394305164
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.3812540326
Short name T595
Test name
Test status
Simulation time 136383703 ps
CPU time 2.42 seconds
Started Aug 06 04:46:05 PM PDT 24
Finished Aug 06 04:46:07 PM PDT 24
Peak memory 233448 kb
Host smart-a1ad9473-4e03-4099-b737-a2ce07539248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812540326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.3812540326
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.3331781885
Short name T903
Test name
Test status
Simulation time 14861374 ps
CPU time 0.69 seconds
Started Aug 06 04:46:19 PM PDT 24
Finished Aug 06 04:46:20 PM PDT 24
Peak memory 204952 kb
Host smart-7ee35a09-02d4-40fd-8d1e-01fd70d7c6f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331781885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
3331781885
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.1665193143
Short name T824
Test name
Test status
Simulation time 66793940 ps
CPU time 3.4 seconds
Started Aug 06 04:46:19 PM PDT 24
Finished Aug 06 04:46:22 PM PDT 24
Peak memory 233152 kb
Host smart-dca9af5d-638b-4a87-8138-56d86c9390c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665193143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.1665193143
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.740341874
Short name T316
Test name
Test status
Simulation time 19176902 ps
CPU time 0.77 seconds
Started Aug 06 04:46:08 PM PDT 24
Finished Aug 06 04:46:09 PM PDT 24
Peak memory 206944 kb
Host smart-546cc457-aa5e-4541-ad8d-dd9502ffcbbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740341874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.740341874
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.1993032734
Short name T596
Test name
Test status
Simulation time 5668056180 ps
CPU time 56.52 seconds
Started Aug 06 04:46:19 PM PDT 24
Finished Aug 06 04:47:16 PM PDT 24
Peak memory 250120 kb
Host smart-5af01e84-2c1a-4a96-80dd-5d87d081782a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993032734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.1993032734
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.522953902
Short name T116
Test name
Test status
Simulation time 134549159307 ps
CPU time 318.93 seconds
Started Aug 06 04:46:16 PM PDT 24
Finished Aug 06 04:51:35 PM PDT 24
Peak memory 266172 kb
Host smart-893d8a42-d7ea-4de8-934c-a9d6114d39c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522953902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.522953902
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.3548521769
Short name T452
Test name
Test status
Simulation time 10019850552 ps
CPU time 51.56 seconds
Started Aug 06 04:46:08 PM PDT 24
Finished Aug 06 04:46:59 PM PDT 24
Peak memory 218344 kb
Host smart-98fb4441-451c-47e0-8b7c-caa963eed594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548521769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.3548521769
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.1705712694
Short name T592
Test name
Test status
Simulation time 2603785599 ps
CPU time 45.91 seconds
Started Aug 06 04:46:05 PM PDT 24
Finished Aug 06 04:46:51 PM PDT 24
Peak memory 225584 kb
Host smart-c4715ec4-02b4-4906-91e5-d9e0e4a225d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705712694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.1705712694
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.2404929539
Short name T253
Test name
Test status
Simulation time 27411061861 ps
CPU time 63.11 seconds
Started Aug 06 04:46:07 PM PDT 24
Finished Aug 06 04:47:10 PM PDT 24
Peak memory 253324 kb
Host smart-c2ed3321-3831-41d6-9015-428f2aafa1da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404929539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmd
s.2404929539
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/29.spi_device_intercept.1160695139
Short name T542
Test name
Test status
Simulation time 1621114465 ps
CPU time 3.38 seconds
Started Aug 06 04:46:06 PM PDT 24
Finished Aug 06 04:46:09 PM PDT 24
Peak memory 233368 kb
Host smart-741dfaca-3a27-4996-b12a-71bd58857204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160695139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.1160695139
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.3079613254
Short name T464
Test name
Test status
Simulation time 3972528658 ps
CPU time 27.22 seconds
Started Aug 06 04:46:08 PM PDT 24
Finished Aug 06 04:46:36 PM PDT 24
Peak memory 233468 kb
Host smart-83dc6887-8242-43a1-a030-7955b62e03b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079613254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.3079613254
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.3331930443
Short name T298
Test name
Test status
Simulation time 2309024620 ps
CPU time 8.67 seconds
Started Aug 06 04:46:08 PM PDT 24
Finished Aug 06 04:46:17 PM PDT 24
Peak memory 233492 kb
Host smart-4d40bc30-eb3b-4426-b15c-1817955a0b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331930443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.3331930443
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.1602273924
Short name T186
Test name
Test status
Simulation time 854012971 ps
CPU time 4.04 seconds
Started Aug 06 04:46:09 PM PDT 24
Finished Aug 06 04:46:13 PM PDT 24
Peak memory 225192 kb
Host smart-72211e72-c589-4b89-a390-fb88558ba355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602273924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.1602273924
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.4215245330
Short name T852
Test name
Test status
Simulation time 972530628 ps
CPU time 7.23 seconds
Started Aug 06 04:46:09 PM PDT 24
Finished Aug 06 04:46:16 PM PDT 24
Peak memory 222832 kb
Host smart-faaa7d74-064f-479c-876c-83b0be07ef8a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4215245330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.4215245330
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.1224212410
Short name T597
Test name
Test status
Simulation time 69148033 ps
CPU time 1.22 seconds
Started Aug 06 04:46:05 PM PDT 24
Finished Aug 06 04:46:06 PM PDT 24
Peak memory 207516 kb
Host smart-b2f1c470-0d58-4c80-9f5d-dc050ea2e354
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224212410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.1224212410
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.2949922512
Short name T874
Test name
Test status
Simulation time 6520693030 ps
CPU time 4.61 seconds
Started Aug 06 04:46:06 PM PDT 24
Finished Aug 06 04:46:11 PM PDT 24
Peak memory 217004 kb
Host smart-0a20b91d-b8f2-4f50-baec-3a9f97046f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949922512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.2949922512
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.319805264
Short name T587
Test name
Test status
Simulation time 403186169 ps
CPU time 1.57 seconds
Started Aug 06 04:46:09 PM PDT 24
Finished Aug 06 04:46:11 PM PDT 24
Peak memory 208488 kb
Host smart-8e39d4f1-5201-4aa1-9d7c-7710756cc8a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319805264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.319805264
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.2081581662
Short name T938
Test name
Test status
Simulation time 77616442 ps
CPU time 4.36 seconds
Started Aug 06 04:46:20 PM PDT 24
Finished Aug 06 04:46:24 PM PDT 24
Peak memory 216760 kb
Host smart-cdf541bc-b655-4bc9-85c1-c789e1595f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081581662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.2081581662
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.425238723
Short name T357
Test name
Test status
Simulation time 105434410 ps
CPU time 0.76 seconds
Started Aug 06 04:46:09 PM PDT 24
Finished Aug 06 04:46:10 PM PDT 24
Peak memory 206424 kb
Host smart-30c0b61a-3c17-4dc2-80bb-f57102d26178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425238723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.425238723
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.2649641147
Short name T1029
Test name
Test status
Simulation time 451821624 ps
CPU time 5.05 seconds
Started Aug 06 04:46:20 PM PDT 24
Finished Aug 06 04:46:25 PM PDT 24
Peak memory 233240 kb
Host smart-be0a4926-7d95-46bf-8513-4ec54717ec4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649641147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.2649641147
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.2193113029
Short name T567
Test name
Test status
Simulation time 38941062 ps
CPU time 0.76 seconds
Started Aug 06 04:44:32 PM PDT 24
Finished Aug 06 04:44:33 PM PDT 24
Peak memory 205808 kb
Host smart-bac1c9cf-97b2-4a7c-a44c-c7adba3d65ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193113029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.2
193113029
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.1525241188
Short name T409
Test name
Test status
Simulation time 1055966487 ps
CPU time 4.94 seconds
Started Aug 06 04:44:40 PM PDT 24
Finished Aug 06 04:44:45 PM PDT 24
Peak memory 233448 kb
Host smart-e3e903c6-7e07-4871-9f0d-d4262e0a2591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525241188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.1525241188
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.1791886494
Short name T973
Test name
Test status
Simulation time 59639203 ps
CPU time 0.78 seconds
Started Aug 06 04:44:27 PM PDT 24
Finished Aug 06 04:44:28 PM PDT 24
Peak memory 207256 kb
Host smart-950d201c-6119-4bad-9bb7-af141e1d467b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791886494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.1791886494
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.1416608476
Short name T260
Test name
Test status
Simulation time 22859761012 ps
CPU time 199.83 seconds
Started Aug 06 04:44:27 PM PDT 24
Finished Aug 06 04:47:47 PM PDT 24
Peak memory 257400 kb
Host smart-6270b75a-7f00-44a4-8087-d993dfc5d2ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416608476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.1416608476
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.266277560
Short name T428
Test name
Test status
Simulation time 3717769881 ps
CPU time 33.72 seconds
Started Aug 06 04:44:27 PM PDT 24
Finished Aug 06 04:45:01 PM PDT 24
Peak memory 237856 kb
Host smart-73305437-b093-48bb-bcd8-9e16cfbc4299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266277560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.266277560
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.1356489056
Short name T304
Test name
Test status
Simulation time 265794725 ps
CPU time 6 seconds
Started Aug 06 04:44:31 PM PDT 24
Finished Aug 06 04:44:37 PM PDT 24
Peak memory 233332 kb
Host smart-499cf6c8-64be-4b61-bede-c9e15d250129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356489056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.1356489056
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.4236832850
Short name T762
Test name
Test status
Simulation time 11197394696 ps
CPU time 39.47 seconds
Started Aug 06 04:44:31 PM PDT 24
Finished Aug 06 04:45:11 PM PDT 24
Peak memory 249356 kb
Host smart-492d9dcb-5926-4e8c-b5ca-96e7cb2cb990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236832850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds
.4236832850
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/3.spi_device_intercept.850890953
Short name T1031
Test name
Test status
Simulation time 1665493292 ps
CPU time 6.15 seconds
Started Aug 06 04:44:31 PM PDT 24
Finished Aug 06 04:44:37 PM PDT 24
Peak memory 225212 kb
Host smart-7b3b2037-a67e-4b45-b7fa-722f857b1881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850890953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.850890953
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.929113481
Short name T613
Test name
Test status
Simulation time 1196208896 ps
CPU time 4.46 seconds
Started Aug 06 04:44:26 PM PDT 24
Finished Aug 06 04:44:31 PM PDT 24
Peak memory 225064 kb
Host smart-999c7af1-00e0-4536-9d9e-fb299e3a82e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929113481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.929113481
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.3398759617
Short name T32
Test name
Test status
Simulation time 25136349 ps
CPU time 1.03 seconds
Started Aug 06 04:44:26 PM PDT 24
Finished Aug 06 04:44:27 PM PDT 24
Peak memory 217092 kb
Host smart-d5b153a3-e088-4f80-8229-afe6dcc759f7
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398759617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.spi_device_mem_parity.3398759617
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.491909534
Short name T600
Test name
Test status
Simulation time 57896812 ps
CPU time 2.31 seconds
Started Aug 06 04:44:27 PM PDT 24
Finished Aug 06 04:44:30 PM PDT 24
Peak memory 232996 kb
Host smart-56dfaa9e-6060-4a4c-b933-d2467b2dd108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491909534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap.
491909534
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.2809656067
Short name T887
Test name
Test status
Simulation time 531593193 ps
CPU time 5.91 seconds
Started Aug 06 04:44:24 PM PDT 24
Finished Aug 06 04:44:30 PM PDT 24
Peak memory 233284 kb
Host smart-350f7a4f-5ffc-4773-9972-e0b23aed8c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809656067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.2809656067
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.58758377
Short name T946
Test name
Test status
Simulation time 100778738 ps
CPU time 3.96 seconds
Started Aug 06 04:44:31 PM PDT 24
Finished Aug 06 04:44:35 PM PDT 24
Peak memory 222868 kb
Host smart-85f07628-9a85-448e-ba2a-8840af0e5e37
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=58758377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_direct
.58758377
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.1367113987
Short name T49
Test name
Test status
Simulation time 69013527 ps
CPU time 0.93 seconds
Started Aug 06 04:44:28 PM PDT 24
Finished Aug 06 04:44:29 PM PDT 24
Peak memory 235496 kb
Host smart-aa35beea-4082-4c78-a40d-bf9c8b8eefc0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367113987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.1367113987
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.3985206455
Short name T621
Test name
Test status
Simulation time 111915728785 ps
CPU time 273.83 seconds
Started Aug 06 04:44:25 PM PDT 24
Finished Aug 06 04:48:59 PM PDT 24
Peak memory 266312 kb
Host smart-dec3b824-9292-46fd-8bd3-254158e06568
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985206455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.3985206455
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.1881756055
Short name T955
Test name
Test status
Simulation time 1491183150 ps
CPU time 24.35 seconds
Started Aug 06 04:44:28 PM PDT 24
Finished Aug 06 04:44:52 PM PDT 24
Peak memory 216980 kb
Host smart-41f7a01a-e55e-4596-a602-05de5056efd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881756055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.1881756055
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.2404257982
Short name T561
Test name
Test status
Simulation time 6491231048 ps
CPU time 4.83 seconds
Started Aug 06 04:44:26 PM PDT 24
Finished Aug 06 04:44:31 PM PDT 24
Peak memory 216872 kb
Host smart-6703d165-8df0-4a6e-b7d2-b7667cb54677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404257982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.2404257982
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.227863938
Short name T153
Test name
Test status
Simulation time 20632181 ps
CPU time 0.93 seconds
Started Aug 06 04:44:43 PM PDT 24
Finished Aug 06 04:44:44 PM PDT 24
Peak memory 207616 kb
Host smart-e6c45af6-cd5e-497d-97de-3dbf79ca4b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227863938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.227863938
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.2993246605
Short name T552
Test name
Test status
Simulation time 47055257 ps
CPU time 0.75 seconds
Started Aug 06 04:44:24 PM PDT 24
Finished Aug 06 04:44:25 PM PDT 24
Peak memory 206404 kb
Host smart-c59c0042-f06c-4a28-b7d2-f8d66f93f12b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993246605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.2993246605
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.272935279
Short name T235
Test name
Test status
Simulation time 571044349 ps
CPU time 2.84 seconds
Started Aug 06 04:44:31 PM PDT 24
Finished Aug 06 04:44:34 PM PDT 24
Peak memory 225100 kb
Host smart-9ea20517-bc47-4ec6-a002-a83926d8ffcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272935279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.272935279
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.1375774849
Short name T742
Test name
Test status
Simulation time 17885750 ps
CPU time 0.71 seconds
Started Aug 06 04:46:06 PM PDT 24
Finished Aug 06 04:46:07 PM PDT 24
Peak memory 206088 kb
Host smart-3827948e-ac4b-483a-b0ff-0adf70946df3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375774849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
1375774849
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.712170213
Short name T395
Test name
Test status
Simulation time 176290381 ps
CPU time 3.36 seconds
Started Aug 06 04:46:22 PM PDT 24
Finished Aug 06 04:46:26 PM PDT 24
Peak memory 225060 kb
Host smart-fdc75386-b973-429b-8338-8b50a233b0b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712170213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.712170213
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.2801694847
Short name T690
Test name
Test status
Simulation time 15867719 ps
CPU time 0.79 seconds
Started Aug 06 04:46:06 PM PDT 24
Finished Aug 06 04:46:07 PM PDT 24
Peak memory 206936 kb
Host smart-5529f1d9-6840-4511-8e05-c3f0e3aa4093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801694847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.2801694847
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.4037739251
Short name T356
Test name
Test status
Simulation time 546016977 ps
CPU time 7.81 seconds
Started Aug 06 04:46:07 PM PDT 24
Finished Aug 06 04:46:15 PM PDT 24
Peak memory 225148 kb
Host smart-44bf6868-45eb-4722-a636-ede656a3ad69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037739251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.4037739251
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.1818692436
Short name T668
Test name
Test status
Simulation time 3901257244 ps
CPU time 72.69 seconds
Started Aug 06 04:46:09 PM PDT 24
Finished Aug 06 04:47:22 PM PDT 24
Peak memory 249944 kb
Host smart-26453e94-9cad-432b-8404-6133178ff522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818692436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.1818692436
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.155314284
Short name T822
Test name
Test status
Simulation time 15546848772 ps
CPU time 34.94 seconds
Started Aug 06 04:46:03 PM PDT 24
Finished Aug 06 04:46:38 PM PDT 24
Peak memory 249796 kb
Host smart-44025c5c-bb66-4c13-8830-fc3430b3927f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155314284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idle
.155314284
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.522576147
Short name T1002
Test name
Test status
Simulation time 4663382182 ps
CPU time 17.06 seconds
Started Aug 06 04:46:19 PM PDT 24
Finished Aug 06 04:46:36 PM PDT 24
Peak memory 225076 kb
Host smart-f18f65f8-89f6-4b0f-b953-de4e3ae651f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522576147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.522576147
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.1398950836
Short name T770
Test name
Test status
Simulation time 57145622 ps
CPU time 0.81 seconds
Started Aug 06 04:46:19 PM PDT 24
Finished Aug 06 04:46:20 PM PDT 24
Peak memory 216208 kb
Host smart-8c7f3933-30f9-4300-a6f5-849d4f561462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398950836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmd
s.1398950836
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/30.spi_device_intercept.131124017
Short name T890
Test name
Test status
Simulation time 4139872531 ps
CPU time 11.35 seconds
Started Aug 06 04:46:07 PM PDT 24
Finished Aug 06 04:46:18 PM PDT 24
Peak memory 233372 kb
Host smart-dd2d0a04-73b1-4e29-899b-f8b7b66d13f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131124017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.131124017
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.2020747016
Short name T739
Test name
Test status
Simulation time 38715098223 ps
CPU time 130.08 seconds
Started Aug 06 04:46:18 PM PDT 24
Finished Aug 06 04:48:29 PM PDT 24
Peak memory 238952 kb
Host smart-1e365d78-869a-4bf4-9c31-341661a56f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020747016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.2020747016
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.1996107160
Short name T38
Test name
Test status
Simulation time 955443406 ps
CPU time 4.4 seconds
Started Aug 06 04:46:06 PM PDT 24
Finished Aug 06 04:46:11 PM PDT 24
Peak memory 225188 kb
Host smart-bef4d697-d9b5-458e-8934-9eff6539e463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996107160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.1996107160
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.3774993089
Short name T243
Test name
Test status
Simulation time 4299386716 ps
CPU time 17.29 seconds
Started Aug 06 04:46:04 PM PDT 24
Finished Aug 06 04:46:21 PM PDT 24
Peak memory 241656 kb
Host smart-592a4888-f71d-4f98-a31f-79a545db7031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774993089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.3774993089
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.2563116449
Short name T458
Test name
Test status
Simulation time 11683368871 ps
CPU time 12.7 seconds
Started Aug 06 04:46:17 PM PDT 24
Finished Aug 06 04:46:30 PM PDT 24
Peak memory 223596 kb
Host smart-9c21259c-271f-4644-8cbc-fa736809e892
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2563116449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.2563116449
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.1446553603
Short name T910
Test name
Test status
Simulation time 103765440139 ps
CPU time 217.51 seconds
Started Aug 06 04:46:05 PM PDT 24
Finished Aug 06 04:49:42 PM PDT 24
Peak memory 267276 kb
Host smart-e3a9d796-a7b6-44d9-94c3-04cb63d7f7b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446553603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.1446553603
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.3924639300
Short name T849
Test name
Test status
Simulation time 4142138369 ps
CPU time 12.67 seconds
Started Aug 06 04:46:07 PM PDT 24
Finished Aug 06 04:46:20 PM PDT 24
Peak memory 216996 kb
Host smart-8bb508a7-a764-4d81-af5f-3d9dffccb40e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924639300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.3924639300
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.3942795333
Short name T968
Test name
Test status
Simulation time 1003714440 ps
CPU time 3.18 seconds
Started Aug 06 04:46:09 PM PDT 24
Finished Aug 06 04:46:12 PM PDT 24
Peak memory 216852 kb
Host smart-9168de19-764c-407a-a72a-7cf9a24af77b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942795333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.3942795333
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.3076468946
Short name T879
Test name
Test status
Simulation time 227688277 ps
CPU time 2.07 seconds
Started Aug 06 04:46:09 PM PDT 24
Finished Aug 06 04:46:11 PM PDT 24
Peak memory 216876 kb
Host smart-106a695b-9404-4ea9-8c7e-eddd4375f13d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076468946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.3076468946
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.725937643
Short name T675
Test name
Test status
Simulation time 180545865 ps
CPU time 0.94 seconds
Started Aug 06 04:46:08 PM PDT 24
Finished Aug 06 04:46:09 PM PDT 24
Peak memory 207632 kb
Host smart-2391b397-fa20-4b38-8f82-2224638ee2d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725937643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.725937643
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.517497392
Short name T517
Test name
Test status
Simulation time 2476248106 ps
CPU time 6.15 seconds
Started Aug 06 04:46:07 PM PDT 24
Finished Aug 06 04:46:13 PM PDT 24
Peak memory 233372 kb
Host smart-d5285ba1-00ca-4ea8-83aa-d5e74ee575a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517497392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.517497392
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.449232614
Short name T864
Test name
Test status
Simulation time 17000134 ps
CPU time 0.73 seconds
Started Aug 06 04:46:20 PM PDT 24
Finished Aug 06 04:46:21 PM PDT 24
Peak memory 205248 kb
Host smart-f0f8ab6e-dae2-414e-b8a4-566dcc759825
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449232614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.449232614
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.447995943
Short name T556
Test name
Test status
Simulation time 5308492053 ps
CPU time 4.32 seconds
Started Aug 06 04:46:24 PM PDT 24
Finished Aug 06 04:46:28 PM PDT 24
Peak memory 233368 kb
Host smart-567acc20-7482-4410-a701-258df67e2fce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447995943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.447995943
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.1181924067
Short name T410
Test name
Test status
Simulation time 15513648 ps
CPU time 0.8 seconds
Started Aug 06 04:46:22 PM PDT 24
Finished Aug 06 04:46:23 PM PDT 24
Peak memory 206924 kb
Host smart-554bf245-9d8f-4234-9ede-881d4e56db51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181924067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.1181924067
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.822704178
Short name T284
Test name
Test status
Simulation time 35899568170 ps
CPU time 250.07 seconds
Started Aug 06 04:46:25 PM PDT 24
Finished Aug 06 04:50:35 PM PDT 24
Peak memory 256416 kb
Host smart-8490ded6-4f17-42cd-a185-4d58cd292616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822704178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.822704178
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.2099204808
Short name T212
Test name
Test status
Simulation time 78367618290 ps
CPU time 180.74 seconds
Started Aug 06 04:46:22 PM PDT 24
Finished Aug 06 04:49:23 PM PDT 24
Peak memory 254936 kb
Host smart-b9f09666-cf85-43c9-b551-d288fd716415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099204808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.2099204808
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.3471672402
Short name T255
Test name
Test status
Simulation time 8139622208 ps
CPU time 20.44 seconds
Started Aug 06 04:46:25 PM PDT 24
Finished Aug 06 04:46:45 PM PDT 24
Peak memory 252108 kb
Host smart-d2c698c3-276f-4426-9fa6-8cc4ba3c4968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471672402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.3471672402
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.3155104889
Short name T659
Test name
Test status
Simulation time 2235358862 ps
CPU time 30.97 seconds
Started Aug 06 04:46:20 PM PDT 24
Finished Aug 06 04:46:51 PM PDT 24
Peak memory 249820 kb
Host smart-edbf6165-2d68-4511-80f9-2aa444b88c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155104889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.3155104889
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.197242286
Short name T173
Test name
Test status
Simulation time 50836433192 ps
CPU time 192.56 seconds
Started Aug 06 04:46:20 PM PDT 24
Finished Aug 06 04:49:33 PM PDT 24
Peak memory 250436 kb
Host smart-73486636-1e7f-4c8a-bdd6-3cc2b0474eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197242286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmds
.197242286
Directory /workspace/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/31.spi_device_intercept.2650942618
Short name T221
Test name
Test status
Simulation time 83303491 ps
CPU time 3.25 seconds
Started Aug 06 04:46:20 PM PDT 24
Finished Aug 06 04:46:23 PM PDT 24
Peak memory 233236 kb
Host smart-357e037d-d093-45f5-811b-57b18b0b53ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650942618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.2650942618
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.500355552
Short name T652
Test name
Test status
Simulation time 343968456 ps
CPU time 8.08 seconds
Started Aug 06 04:46:08 PM PDT 24
Finished Aug 06 04:46:16 PM PDT 24
Peak memory 225244 kb
Host smart-3eb277d8-6e8d-46ac-bdb2-8a2457bb7d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500355552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.500355552
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.2145340901
Short name T632
Test name
Test status
Simulation time 92288933 ps
CPU time 2.21 seconds
Started Aug 06 04:46:22 PM PDT 24
Finished Aug 06 04:46:24 PM PDT 24
Peak memory 225008 kb
Host smart-2f322aa7-3e71-4163-ae88-7a3fa7a56db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145340901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.2145340901
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.2758579920
Short name T438
Test name
Test status
Simulation time 135507280 ps
CPU time 2.25 seconds
Started Aug 06 04:46:26 PM PDT 24
Finished Aug 06 04:46:28 PM PDT 24
Peak memory 233216 kb
Host smart-c7f6ef65-41eb-42fd-ad19-85ea19405337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758579920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.2758579920
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.691124674
Short name T662
Test name
Test status
Simulation time 1792195446 ps
CPU time 6.92 seconds
Started Aug 06 04:46:21 PM PDT 24
Finished Aug 06 04:46:28 PM PDT 24
Peak memory 219584 kb
Host smart-c09ba83b-732a-432f-8661-87b1aa8627bd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=691124674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dire
ct.691124674
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.1243137922
Short name T854
Test name
Test status
Simulation time 49244700127 ps
CPU time 215.43 seconds
Started Aug 06 04:46:25 PM PDT 24
Finished Aug 06 04:50:00 PM PDT 24
Peak memory 255872 kb
Host smart-f362abbe-385a-4a24-940f-76794695189a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243137922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.1243137922
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.1987688377
Short name T731
Test name
Test status
Simulation time 6689170399 ps
CPU time 21.83 seconds
Started Aug 06 04:46:22 PM PDT 24
Finished Aug 06 04:46:44 PM PDT 24
Peak memory 216972 kb
Host smart-2a1a152d-26dc-4d93-a49d-3c97b22684d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987688377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.1987688377
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.78971831
Short name T328
Test name
Test status
Simulation time 754553480 ps
CPU time 1.7 seconds
Started Aug 06 04:46:07 PM PDT 24
Finished Aug 06 04:46:08 PM PDT 24
Peak memory 208384 kb
Host smart-3a9df15f-9304-41b2-bfb9-1dc9e9a711c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78971831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.78971831
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.1539091858
Short name T858
Test name
Test status
Simulation time 24022472 ps
CPU time 0.96 seconds
Started Aug 06 04:46:04 PM PDT 24
Finished Aug 06 04:46:05 PM PDT 24
Peak memory 207836 kb
Host smart-a3dc5fc5-23fc-4cdc-93d9-1e63c7432b3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539091858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.1539091858
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.3119893268
Short name T847
Test name
Test status
Simulation time 52170773 ps
CPU time 0.79 seconds
Started Aug 06 04:46:04 PM PDT 24
Finished Aug 06 04:46:05 PM PDT 24
Peak memory 206372 kb
Host smart-2c522f42-8811-483f-ac7c-21776806bbb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119893268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.3119893268
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.3961981107
Short name T747
Test name
Test status
Simulation time 182024997 ps
CPU time 2.14 seconds
Started Aug 06 04:46:17 PM PDT 24
Finished Aug 06 04:46:19 PM PDT 24
Peak memory 225104 kb
Host smart-f92d6075-6de9-4862-b8b5-b3bb6420ffac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961981107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.3961981107
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.57560999
Short name T474
Test name
Test status
Simulation time 50334093 ps
CPU time 0.72 seconds
Started Aug 06 04:46:21 PM PDT 24
Finished Aug 06 04:46:21 PM PDT 24
Peak memory 205268 kb
Host smart-fe6619b1-cc56-4640-8b2e-a58b6442c061
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57560999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.57560999
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.3819302549
Short name T1027
Test name
Test status
Simulation time 1399539502 ps
CPU time 13.22 seconds
Started Aug 06 04:46:21 PM PDT 24
Finished Aug 06 04:46:34 PM PDT 24
Peak memory 233380 kb
Host smart-ffc88a95-d3f7-4897-8f4e-88a0e9cf6c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819302549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.3819302549
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.3234757016
Short name T638
Test name
Test status
Simulation time 82961531 ps
CPU time 0.76 seconds
Started Aug 06 04:46:19 PM PDT 24
Finished Aug 06 04:46:20 PM PDT 24
Peak memory 207032 kb
Host smart-e9f00545-c72a-45e8-9817-1a6c9f5109c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234757016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.3234757016
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.675213041
Short name T352
Test name
Test status
Simulation time 2300528784 ps
CPU time 19.97 seconds
Started Aug 06 04:46:21 PM PDT 24
Finished Aug 06 04:46:41 PM PDT 24
Peak memory 241584 kb
Host smart-5d7be4e8-eab1-4bc0-a0f5-60483994bb7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675213041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.675213041
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.3365840778
Short name T661
Test name
Test status
Simulation time 4262948776 ps
CPU time 14.78 seconds
Started Aug 06 04:46:21 PM PDT 24
Finished Aug 06 04:46:36 PM PDT 24
Peak memory 224484 kb
Host smart-21838156-6b3d-4962-a3fb-78191e4f2fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365840778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.3365840778
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.3089269059
Short name T956
Test name
Test status
Simulation time 7704741620 ps
CPU time 30.74 seconds
Started Aug 06 04:46:20 PM PDT 24
Finished Aug 06 04:46:51 PM PDT 24
Peak memory 224292 kb
Host smart-dad9649c-089b-4534-9fb6-393680288c4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089269059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.3089269059
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.4117573531
Short name T305
Test name
Test status
Simulation time 468573911 ps
CPU time 7.43 seconds
Started Aug 06 04:46:21 PM PDT 24
Finished Aug 06 04:46:28 PM PDT 24
Peak memory 225208 kb
Host smart-1dcb169e-1eff-4d35-98ea-ac4c21eeacf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117573531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.4117573531
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.3412422139
Short name T670
Test name
Test status
Simulation time 2186698634 ps
CPU time 43.01 seconds
Started Aug 06 04:46:25 PM PDT 24
Finished Aug 06 04:47:08 PM PDT 24
Peak memory 250428 kb
Host smart-736e20c7-61ac-4eb7-824f-35c11bf24947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412422139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmd
s.3412422139
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/32.spi_device_intercept.1775400189
Short name T669
Test name
Test status
Simulation time 1937697344 ps
CPU time 22.35 seconds
Started Aug 06 04:46:23 PM PDT 24
Finished Aug 06 04:46:46 PM PDT 24
Peak memory 233460 kb
Host smart-ccfad33a-02ef-483e-ab5e-79683e3cd5d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775400189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.1775400189
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.3561933715
Short name T272
Test name
Test status
Simulation time 9117817257 ps
CPU time 29.32 seconds
Started Aug 06 04:46:21 PM PDT 24
Finished Aug 06 04:46:50 PM PDT 24
Peak memory 239812 kb
Host smart-4689baf4-5132-482f-8785-25abe58ac082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561933715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.3561933715
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.2138767568
Short name T545
Test name
Test status
Simulation time 2471666411 ps
CPU time 11.07 seconds
Started Aug 06 04:46:19 PM PDT 24
Finished Aug 06 04:46:30 PM PDT 24
Peak memory 233448 kb
Host smart-936fb136-37a5-4c7d-91b5-5d1fd4572085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138767568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.2138767568
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.1468379575
Short name T813
Test name
Test status
Simulation time 1167984045 ps
CPU time 8.75 seconds
Started Aug 06 04:46:25 PM PDT 24
Finished Aug 06 04:46:34 PM PDT 24
Peak memory 233352 kb
Host smart-1f5ffdf9-abc5-4e0e-bdf4-f94f7fbae73f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468379575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.1468379575
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.503116196
Short name T349
Test name
Test status
Simulation time 4889739341 ps
CPU time 14.53 seconds
Started Aug 06 04:46:18 PM PDT 24
Finished Aug 06 04:46:33 PM PDT 24
Peak memory 223640 kb
Host smart-83f199ea-073d-4ee1-a0b3-9ba2b7357361
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=503116196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dire
ct.503116196
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.2980658811
Short name T144
Test name
Test status
Simulation time 151956747935 ps
CPU time 385.98 seconds
Started Aug 06 04:46:24 PM PDT 24
Finished Aug 06 04:52:50 PM PDT 24
Peak memory 270336 kb
Host smart-f2ec3a8c-d5ad-41f7-99c5-6bdf902b7ab7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980658811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.2980658811
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.3116356135
Short name T703
Test name
Test status
Simulation time 353592110 ps
CPU time 6.83 seconds
Started Aug 06 04:46:23 PM PDT 24
Finished Aug 06 04:46:30 PM PDT 24
Peak memory 216844 kb
Host smart-cdce1370-0e68-442c-bcdf-4f3881337e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116356135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.3116356135
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.3767545542
Short name T12
Test name
Test status
Simulation time 6030721904 ps
CPU time 12.31 seconds
Started Aug 06 04:46:25 PM PDT 24
Finished Aug 06 04:46:37 PM PDT 24
Peak memory 216952 kb
Host smart-3f48e257-481b-4a1a-a129-c3d4a5de603e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767545542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.3767545542
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.3720060586
Short name T425
Test name
Test status
Simulation time 342779431 ps
CPU time 8.31 seconds
Started Aug 06 04:46:25 PM PDT 24
Finished Aug 06 04:46:33 PM PDT 24
Peak memory 216932 kb
Host smart-e434a148-88f4-44ac-8ba0-2ed4319c3a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720060586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.3720060586
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.3620254505
Short name T460
Test name
Test status
Simulation time 31035384 ps
CPU time 0.75 seconds
Started Aug 06 04:46:22 PM PDT 24
Finished Aug 06 04:46:22 PM PDT 24
Peak memory 206556 kb
Host smart-35ac939b-0408-46a1-8b25-90f4cd9155e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620254505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.3620254505
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.3577526638
Short name T713
Test name
Test status
Simulation time 3503388699 ps
CPU time 5.5 seconds
Started Aug 06 04:46:23 PM PDT 24
Finished Aug 06 04:46:29 PM PDT 24
Peak memory 233368 kb
Host smart-8e671f0e-fbc6-4d72-a878-885a1ec0c3b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577526638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.3577526638
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.1300808513
Short name T41
Test name
Test status
Simulation time 39861870 ps
CPU time 0.72 seconds
Started Aug 06 04:46:22 PM PDT 24
Finished Aug 06 04:46:22 PM PDT 24
Peak memory 205648 kb
Host smart-037d6cd1-976b-4dd6-ad7a-624fd0a42b95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300808513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
1300808513
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.38965999
Short name T706
Test name
Test status
Simulation time 710542834 ps
CPU time 9.88 seconds
Started Aug 06 04:46:23 PM PDT 24
Finished Aug 06 04:46:33 PM PDT 24
Peak memory 225144 kb
Host smart-626abcf3-2f52-4720-a512-c9f8672eb032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38965999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.38965999
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.2678397293
Short name T453
Test name
Test status
Simulation time 206876899 ps
CPU time 0.77 seconds
Started Aug 06 04:46:25 PM PDT 24
Finished Aug 06 04:46:26 PM PDT 24
Peak memory 206232 kb
Host smart-5124694d-e125-4825-a187-bb2f387aa431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678397293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.2678397293
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.2595877905
Short name T850
Test name
Test status
Simulation time 28217329961 ps
CPU time 18.94 seconds
Started Aug 06 04:46:23 PM PDT 24
Finished Aug 06 04:46:42 PM PDT 24
Peak memory 249028 kb
Host smart-318b95eb-2818-406a-b604-080df08eccbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595877905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.2595877905
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.1143583439
Short name T249
Test name
Test status
Simulation time 12136909741 ps
CPU time 73.89 seconds
Started Aug 06 04:46:24 PM PDT 24
Finished Aug 06 04:47:38 PM PDT 24
Peak memory 254144 kb
Host smart-3627e8cf-114f-4736-9d45-5af2ef5c3f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143583439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.1143583439
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.2767189273
Short name T467
Test name
Test status
Simulation time 17171383687 ps
CPU time 89.42 seconds
Started Aug 06 04:46:24 PM PDT 24
Finished Aug 06 04:47:54 PM PDT 24
Peak memory 250908 kb
Host smart-ffd1ecc0-34d8-4166-863f-fc489bd181fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767189273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.2767189273
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.4085638302
Short name T923
Test name
Test status
Simulation time 1115776276 ps
CPU time 20.26 seconds
Started Aug 06 04:46:23 PM PDT 24
Finished Aug 06 04:46:43 PM PDT 24
Peak memory 225204 kb
Host smart-c5f691d6-b6e5-4a00-990b-678ac88f22a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085638302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.4085638302
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.191820727
Short name T933
Test name
Test status
Simulation time 70730178563 ps
CPU time 135.31 seconds
Started Aug 06 04:46:26 PM PDT 24
Finished Aug 06 04:48:41 PM PDT 24
Peak memory 249708 kb
Host smart-d223771d-62a8-4c62-bd27-874f2b9ac5e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191820727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmds
.191820727
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/33.spi_device_intercept.4065408909
Short name T884
Test name
Test status
Simulation time 1522317241 ps
CPU time 5.23 seconds
Started Aug 06 04:46:24 PM PDT 24
Finished Aug 06 04:46:29 PM PDT 24
Peak memory 233412 kb
Host smart-00fe607a-2b48-4a29-989a-ccf7d7e894e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065408909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.4065408909
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.4291278872
Short name T906
Test name
Test status
Simulation time 3951138699 ps
CPU time 30.19 seconds
Started Aug 06 04:46:21 PM PDT 24
Finished Aug 06 04:46:52 PM PDT 24
Peak memory 233480 kb
Host smart-4fabaeae-c628-4fbe-8a86-23e73182f818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291278872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.4291278872
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.3696095478
Short name T511
Test name
Test status
Simulation time 279748697 ps
CPU time 5.75 seconds
Started Aug 06 04:46:25 PM PDT 24
Finished Aug 06 04:46:31 PM PDT 24
Peak memory 233276 kb
Host smart-2d56cb92-e19e-4ad1-9e04-f258780697e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696095478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.3696095478
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.643738573
Short name T223
Test name
Test status
Simulation time 5114239348 ps
CPU time 8.09 seconds
Started Aug 06 04:46:20 PM PDT 24
Finished Aug 06 04:46:28 PM PDT 24
Peak memory 233428 kb
Host smart-451f400b-0317-485b-9f52-079ecafcf68e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643738573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.643738573
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.3298199375
Short name T649
Test name
Test status
Simulation time 1370997732 ps
CPU time 7.79 seconds
Started Aug 06 04:46:21 PM PDT 24
Finished Aug 06 04:46:29 PM PDT 24
Peak memory 220244 kb
Host smart-3e40dc73-7500-48f4-9856-a07b44fc47d6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3298199375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.3298199375
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.3170160453
Short name T580
Test name
Test status
Simulation time 3669809758 ps
CPU time 29.67 seconds
Started Aug 06 04:46:24 PM PDT 24
Finished Aug 06 04:46:54 PM PDT 24
Peak memory 224216 kb
Host smart-ed88c00c-a81d-44dd-9470-657d92bfeff1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170160453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.3170160453
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.3937311425
Short name T962
Test name
Test status
Simulation time 1807642357 ps
CPU time 26 seconds
Started Aug 06 04:46:24 PM PDT 24
Finished Aug 06 04:46:50 PM PDT 24
Peak memory 220136 kb
Host smart-d266cbd7-1de7-4df6-a31a-e6e81a74ece5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937311425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.3937311425
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.1947078432
Short name T477
Test name
Test status
Simulation time 9412755633 ps
CPU time 7.93 seconds
Started Aug 06 04:46:21 PM PDT 24
Finished Aug 06 04:46:29 PM PDT 24
Peak memory 216892 kb
Host smart-66eebfad-e126-4df9-98f7-eb9ec38e9861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947078432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.1947078432
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.2431008897
Short name T540
Test name
Test status
Simulation time 96850498 ps
CPU time 1.34 seconds
Started Aug 06 04:46:26 PM PDT 24
Finished Aug 06 04:46:27 PM PDT 24
Peak memory 216848 kb
Host smart-1e5a7200-e9b1-40ce-8236-51c46443e5d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431008897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.2431008897
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.350362989
Short name T830
Test name
Test status
Simulation time 19042812 ps
CPU time 0.73 seconds
Started Aug 06 04:46:21 PM PDT 24
Finished Aug 06 04:46:22 PM PDT 24
Peak memory 206576 kb
Host smart-6b091ea0-a1fc-4c56-bd19-5b38cf357a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350362989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.350362989
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.3416566277
Short name T271
Test name
Test status
Simulation time 4322239724 ps
CPU time 15.77 seconds
Started Aug 06 04:46:24 PM PDT 24
Finished Aug 06 04:46:40 PM PDT 24
Peak memory 233344 kb
Host smart-e1288d7d-8871-495f-ac34-0aeba68c35cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416566277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.3416566277
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.1044832707
Short name T329
Test name
Test status
Simulation time 13763029 ps
CPU time 0.71 seconds
Started Aug 06 04:46:41 PM PDT 24
Finished Aug 06 04:46:41 PM PDT 24
Peak memory 205772 kb
Host smart-fdee6289-db1c-44ef-b44a-dacee505c96b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044832707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
1044832707
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.2852173323
Short name T639
Test name
Test status
Simulation time 465912417 ps
CPU time 3.07 seconds
Started Aug 06 04:46:37 PM PDT 24
Finished Aug 06 04:46:40 PM PDT 24
Peak memory 233416 kb
Host smart-6b4cfd2a-d702-4e3c-928f-547a3795e8ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852173323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.2852173323
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.1489428076
Short name T486
Test name
Test status
Simulation time 18330448 ps
CPU time 0.81 seconds
Started Aug 06 04:46:24 PM PDT 24
Finished Aug 06 04:46:25 PM PDT 24
Peak memory 205020 kb
Host smart-fe6b12b1-a4ac-4829-9d1d-3e3e82549929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489428076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.1489428076
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.2221782982
Short name T192
Test name
Test status
Simulation time 147123601242 ps
CPU time 673.67 seconds
Started Aug 06 04:46:40 PM PDT 24
Finished Aug 06 04:57:54 PM PDT 24
Peak memory 263992 kb
Host smart-6f0863fa-91b4-4693-93ad-0c3264212e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221782982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.2221782982
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.2237355547
Short name T306
Test name
Test status
Simulation time 3136137225 ps
CPU time 14.88 seconds
Started Aug 06 04:46:37 PM PDT 24
Finished Aug 06 04:46:52 PM PDT 24
Peak memory 234584 kb
Host smart-194ea27c-7445-4eca-89ba-fe642f7c4f11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237355547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.2237355547
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.348323310
Short name T895
Test name
Test status
Simulation time 6739836487 ps
CPU time 36.16 seconds
Started Aug 06 04:46:38 PM PDT 24
Finished Aug 06 04:47:15 PM PDT 24
Peak memory 250160 kb
Host smart-69aae46e-9315-49ff-8142-e74f0fd8ae7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348323310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmds
.348323310
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/34.spi_device_intercept.3770565661
Short name T573
Test name
Test status
Simulation time 8512613426 ps
CPU time 15.13 seconds
Started Aug 06 04:46:37 PM PDT 24
Finished Aug 06 04:46:52 PM PDT 24
Peak memory 225276 kb
Host smart-78a25760-c9a0-4a16-b780-8f6034a79dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770565661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.3770565661
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.7358590
Short name T369
Test name
Test status
Simulation time 3111367825 ps
CPU time 11.32 seconds
Started Aug 06 04:46:37 PM PDT 24
Finished Aug 06 04:46:48 PM PDT 24
Peak memory 241268 kb
Host smart-a43aee32-bd28-483b-ac11-199a412f128e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7358590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.7358590
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.1944080877
Short name T266
Test name
Test status
Simulation time 5114140015 ps
CPU time 16.24 seconds
Started Aug 06 04:46:42 PM PDT 24
Finished Aug 06 04:46:58 PM PDT 24
Peak memory 225136 kb
Host smart-6a4740be-798b-42a9-b0bb-a1cb6c400ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944080877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.1944080877
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.3387511207
Short name T641
Test name
Test status
Simulation time 18073243502 ps
CPU time 13.78 seconds
Started Aug 06 04:46:42 PM PDT 24
Finished Aug 06 04:46:56 PM PDT 24
Peak memory 233468 kb
Host smart-d1d390a5-d096-462a-a95f-621ee01f0e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387511207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.3387511207
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.3117897010
Short name T439
Test name
Test status
Simulation time 1471033188 ps
CPU time 13.87 seconds
Started Aug 06 04:46:38 PM PDT 24
Finished Aug 06 04:46:52 PM PDT 24
Peak memory 222656 kb
Host smart-4f42dbcc-5066-47bf-9507-aa401c9a6c6f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3117897010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.3117897010
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.1196465129
Short name T539
Test name
Test status
Simulation time 18720668208 ps
CPU time 184.34 seconds
Started Aug 06 04:46:34 PM PDT 24
Finished Aug 06 04:49:39 PM PDT 24
Peak memory 264212 kb
Host smart-8dfa80a0-3b9d-4e46-b18a-6658167762f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196465129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.1196465129
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.4057260553
Short name T654
Test name
Test status
Simulation time 13215638 ps
CPU time 0.71 seconds
Started Aug 06 04:46:25 PM PDT 24
Finished Aug 06 04:46:26 PM PDT 24
Peak memory 206204 kb
Host smart-a569e2c9-ded0-412b-bc8f-ee8e3d1db57d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057260553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.4057260553
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.59067888
Short name T967
Test name
Test status
Simulation time 969215683 ps
CPU time 4.8 seconds
Started Aug 06 04:46:24 PM PDT 24
Finished Aug 06 04:46:29 PM PDT 24
Peak memory 216820 kb
Host smart-0b73c231-9e95-410e-a58a-f4137175550d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59067888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.59067888
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.744300028
Short name T768
Test name
Test status
Simulation time 384257740 ps
CPU time 3.37 seconds
Started Aug 06 04:46:37 PM PDT 24
Finished Aug 06 04:46:41 PM PDT 24
Peak memory 216748 kb
Host smart-302e2a0b-42c2-4f81-84d7-9d43b15f91ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744300028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.744300028
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.233163724
Short name T576
Test name
Test status
Simulation time 48323132 ps
CPU time 0.76 seconds
Started Aug 06 04:46:23 PM PDT 24
Finished Aug 06 04:46:24 PM PDT 24
Peak memory 206508 kb
Host smart-b7a9abee-c360-49c0-942f-a2e67f12642b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233163724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.233163724
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.3976995679
Short name T440
Test name
Test status
Simulation time 3573275791 ps
CPU time 6.03 seconds
Started Aug 06 04:46:37 PM PDT 24
Finished Aug 06 04:46:43 PM PDT 24
Peak memory 233428 kb
Host smart-9a752727-15e5-488a-9aea-30c5dd7e0c7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976995679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.3976995679
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.1542720477
Short name T42
Test name
Test status
Simulation time 17406219 ps
CPU time 0.72 seconds
Started Aug 06 04:46:39 PM PDT 24
Finished Aug 06 04:46:40 PM PDT 24
Peak memory 205784 kb
Host smart-4f597b6c-ff9e-407e-902e-21da6174da2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542720477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
1542720477
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.2892099439
Short name T771
Test name
Test status
Simulation time 1904602716 ps
CPU time 18.07 seconds
Started Aug 06 04:46:42 PM PDT 24
Finished Aug 06 04:47:01 PM PDT 24
Peak memory 233396 kb
Host smart-1177a762-ae22-4331-80ff-2e9c41f876cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892099439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.2892099439
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.658620423
Short name T318
Test name
Test status
Simulation time 32008824 ps
CPU time 0.78 seconds
Started Aug 06 04:46:39 PM PDT 24
Finished Aug 06 04:46:40 PM PDT 24
Peak memory 207028 kb
Host smart-0387bef9-4026-4f4d-9886-97860ca48fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658620423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.658620423
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.3597174665
Short name T998
Test name
Test status
Simulation time 5462361766 ps
CPU time 54.23 seconds
Started Aug 06 04:46:41 PM PDT 24
Finished Aug 06 04:47:35 PM PDT 24
Peak memory 257760 kb
Host smart-1076bf8d-7b42-4304-a1c6-1835fb813fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597174665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.3597174665
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.2798489143
Short name T574
Test name
Test status
Simulation time 7168305408 ps
CPU time 91.42 seconds
Started Aug 06 04:46:41 PM PDT 24
Finished Aug 06 04:48:12 PM PDT 24
Peak memory 252552 kb
Host smart-62965e3b-0bd1-40d4-a8d0-b7a524f943b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798489143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.2798489143
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.1966809981
Short name T872
Test name
Test status
Simulation time 250199286964 ps
CPU time 586.35 seconds
Started Aug 06 04:46:39 PM PDT 24
Finished Aug 06 04:56:25 PM PDT 24
Peak memory 266240 kb
Host smart-a02850d1-c0f1-4e53-984d-8644bb11a013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966809981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.1966809981
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.3836953177
Short name T303
Test name
Test status
Simulation time 384755845 ps
CPU time 7.84 seconds
Started Aug 06 04:46:36 PM PDT 24
Finished Aug 06 04:46:44 PM PDT 24
Peak memory 236140 kb
Host smart-af979ac7-1de1-42b6-b788-cb5849e0216c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836953177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.3836953177
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.3835934283
Short name T220
Test name
Test status
Simulation time 13963162238 ps
CPU time 136.77 seconds
Started Aug 06 04:46:35 PM PDT 24
Finished Aug 06 04:48:52 PM PDT 24
Peak memory 262976 kb
Host smart-853f761e-f607-4383-931c-1fcbeaad0d15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835934283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmd
s.3835934283
Directory /workspace/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/35.spi_device_intercept.1710816511
Short name T789
Test name
Test status
Simulation time 298151754 ps
CPU time 3.48 seconds
Started Aug 06 04:46:39 PM PDT 24
Finished Aug 06 04:46:43 PM PDT 24
Peak memory 225208 kb
Host smart-6a735627-e521-492e-8a13-cec44e786aa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710816511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.1710816511
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.471788281
Short name T244
Test name
Test status
Simulation time 566114029 ps
CPU time 9.38 seconds
Started Aug 06 04:46:36 PM PDT 24
Finished Aug 06 04:46:45 PM PDT 24
Peak memory 249512 kb
Host smart-edc1598e-d98c-4276-a849-4bfe5b3bb654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471788281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.471788281
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.1031412359
Short name T446
Test name
Test status
Simulation time 2225753961 ps
CPU time 9.82 seconds
Started Aug 06 04:46:38 PM PDT 24
Finished Aug 06 04:46:48 PM PDT 24
Peak memory 249528 kb
Host smart-3fd6a545-e997-4bc1-93d3-10e0a1e3483e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031412359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.1031412359
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.920654281
Short name T691
Test name
Test status
Simulation time 933242991 ps
CPU time 7.89 seconds
Started Aug 06 04:46:39 PM PDT 24
Finished Aug 06 04:46:47 PM PDT 24
Peak memory 233244 kb
Host smart-8568b4c5-9d00-42da-9f8a-d232f8dc4377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920654281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.920654281
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.1636041800
Short name T575
Test name
Test status
Simulation time 644707389 ps
CPU time 8.74 seconds
Started Aug 06 04:46:42 PM PDT 24
Finished Aug 06 04:46:51 PM PDT 24
Peak memory 222696 kb
Host smart-da4139b7-89fd-4555-981e-c315e0e8be0b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1636041800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.1636041800
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.3188229652
Short name T588
Test name
Test status
Simulation time 169939343 ps
CPU time 0.91 seconds
Started Aug 06 04:46:40 PM PDT 24
Finished Aug 06 04:46:42 PM PDT 24
Peak memory 207224 kb
Host smart-00e4b263-6468-4b05-94c9-eb6b30393a6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188229652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.3188229652
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.486047308
Short name T893
Test name
Test status
Simulation time 2023899919 ps
CPU time 13.13 seconds
Started Aug 06 04:46:38 PM PDT 24
Finished Aug 06 04:46:52 PM PDT 24
Peak memory 216916 kb
Host smart-816576bc-ef87-4a18-b5b3-6ad25b84e73b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486047308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.486047308
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.1893353939
Short name T820
Test name
Test status
Simulation time 6115960734 ps
CPU time 11.68 seconds
Started Aug 06 04:46:39 PM PDT 24
Finished Aug 06 04:46:50 PM PDT 24
Peak memory 217036 kb
Host smart-620426b7-246b-4613-9974-06084fbdfce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893353939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.1893353939
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.2027162601
Short name T707
Test name
Test status
Simulation time 29787553 ps
CPU time 0.83 seconds
Started Aug 06 04:46:39 PM PDT 24
Finished Aug 06 04:46:40 PM PDT 24
Peak memory 207316 kb
Host smart-1ed621a2-39d7-4994-9136-2233bc1a41d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027162601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.2027162601
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.208200057
Short name T609
Test name
Test status
Simulation time 55648258 ps
CPU time 0.87 seconds
Started Aug 06 04:46:40 PM PDT 24
Finished Aug 06 04:46:41 PM PDT 24
Peak memory 206400 kb
Host smart-c18ccdb0-5086-4505-939e-50074b7a27e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208200057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.208200057
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.2816983960
Short name T451
Test name
Test status
Simulation time 3722465877 ps
CPU time 10.27 seconds
Started Aug 06 04:46:35 PM PDT 24
Finished Aug 06 04:46:46 PM PDT 24
Peak memory 225300 kb
Host smart-eb67cd7d-35e3-4f2d-9e3d-332e721f9a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816983960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.2816983960
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.466971708
Short name T969
Test name
Test status
Simulation time 56574940 ps
CPU time 0.7 seconds
Started Aug 06 04:46:45 PM PDT 24
Finished Aug 06 04:46:45 PM PDT 24
Peak memory 206172 kb
Host smart-c43d5fe6-43c2-4f34-8655-64dcb8c238ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466971708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.466971708
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.2573837586
Short name T930
Test name
Test status
Simulation time 3262416737 ps
CPU time 25.27 seconds
Started Aug 06 04:46:40 PM PDT 24
Finished Aug 06 04:47:05 PM PDT 24
Peak memory 225128 kb
Host smart-80b64287-bc4c-4df1-854c-ec8f804be4c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573837586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.2573837586
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.2583186270
Short name T402
Test name
Test status
Simulation time 17953794 ps
CPU time 0.85 seconds
Started Aug 06 04:46:38 PM PDT 24
Finished Aug 06 04:46:39 PM PDT 24
Peak memory 207040 kb
Host smart-29beb0db-4a7a-498a-93ab-5725403cbe50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583186270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.2583186270
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.2612943999
Short name T978
Test name
Test status
Simulation time 114945924382 ps
CPU time 378.07 seconds
Started Aug 06 04:46:40 PM PDT 24
Finished Aug 06 04:52:58 PM PDT 24
Peak memory 254920 kb
Host smart-ff3bbf7b-40e8-4417-a1cd-c46621ced5da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612943999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.2612943999
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.1923369661
Short name T519
Test name
Test status
Simulation time 16062333520 ps
CPU time 82.95 seconds
Started Aug 06 04:46:41 PM PDT 24
Finished Aug 06 04:48:04 PM PDT 24
Peak memory 250284 kb
Host smart-f369fcd1-0bbb-4699-a310-cd845c995fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923369661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.1923369661
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.2462994978
Short name T373
Test name
Test status
Simulation time 607695064853 ps
CPU time 315.61 seconds
Started Aug 06 04:46:40 PM PDT 24
Finished Aug 06 04:51:56 PM PDT 24
Peak memory 252872 kb
Host smart-ce6801dd-0cc4-4c56-a320-6bc7d272ce81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462994978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.2462994978
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.3815727924
Short name T840
Test name
Test status
Simulation time 81901899 ps
CPU time 4.14 seconds
Started Aug 06 04:46:40 PM PDT 24
Finished Aug 06 04:46:44 PM PDT 24
Peak memory 235792 kb
Host smart-0c3b8df2-bd1e-4417-a5b2-6157b0e3c9c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815727924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.3815727924
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.4141236530
Short name T892
Test name
Test status
Simulation time 81773515843 ps
CPU time 285.34 seconds
Started Aug 06 04:46:37 PM PDT 24
Finished Aug 06 04:51:23 PM PDT 24
Peak memory 249720 kb
Host smart-d16e5d3c-aae2-4ab3-b72d-3937e2539696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141236530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmd
s.4141236530
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_intercept.606206851
Short name T457
Test name
Test status
Simulation time 68826611 ps
CPU time 2.18 seconds
Started Aug 06 04:46:40 PM PDT 24
Finished Aug 06 04:46:43 PM PDT 24
Peak memory 225080 kb
Host smart-3c9c1556-f389-4a33-883a-5e27845d7df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606206851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.606206851
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.542748125
Short name T990
Test name
Test status
Simulation time 36656469395 ps
CPU time 108.19 seconds
Started Aug 06 04:46:39 PM PDT 24
Finished Aug 06 04:48:27 PM PDT 24
Peak memory 241528 kb
Host smart-bbec9089-c680-4932-8489-217c78e1967e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542748125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.542748125
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.2663159500
Short name T866
Test name
Test status
Simulation time 3961243727 ps
CPU time 11.37 seconds
Started Aug 06 04:46:38 PM PDT 24
Finished Aug 06 04:46:49 PM PDT 24
Peak memory 233380 kb
Host smart-4bbb2f72-61f6-489c-9dce-05d8cbcc9faa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663159500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.2663159500
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.3525871896
Short name T570
Test name
Test status
Simulation time 3237631247 ps
CPU time 11.58 seconds
Started Aug 06 04:46:42 PM PDT 24
Finished Aug 06 04:46:54 PM PDT 24
Peak memory 233348 kb
Host smart-97677fd6-2fff-40f1-8741-0dfe6289098e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525871896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.3525871896
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.1846286050
Short name T531
Test name
Test status
Simulation time 2134453163 ps
CPU time 4.26 seconds
Started Aug 06 04:46:42 PM PDT 24
Finished Aug 06 04:46:46 PM PDT 24
Peak memory 223076 kb
Host smart-5790d071-b393-4a91-af10-8ed5b117ddd3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1846286050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.1846286050
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.594276644
Short name T17
Test name
Test status
Simulation time 145315937 ps
CPU time 0.98 seconds
Started Aug 06 04:46:40 PM PDT 24
Finished Aug 06 04:46:41 PM PDT 24
Peak memory 207100 kb
Host smart-57b91bce-32d3-4404-9ee7-32c32e55edc3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594276644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stres
s_all.594276644
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.1810713869
Short name T745
Test name
Test status
Simulation time 1678170301 ps
CPU time 14.08 seconds
Started Aug 06 04:46:37 PM PDT 24
Finished Aug 06 04:46:51 PM PDT 24
Peak memory 217004 kb
Host smart-efbafc27-034e-49fb-b23b-9b2bd91cf071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810713869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.1810713869
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.1895791179
Short name T988
Test name
Test status
Simulation time 3142709149 ps
CPU time 8.34 seconds
Started Aug 06 04:46:39 PM PDT 24
Finished Aug 06 04:46:47 PM PDT 24
Peak memory 216928 kb
Host smart-c23989a6-a6f1-4fea-86b4-2f8de0fe4044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895791179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.1895791179
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.1480186742
Short name T343
Test name
Test status
Simulation time 50822298 ps
CPU time 2.42 seconds
Started Aug 06 04:46:38 PM PDT 24
Finished Aug 06 04:46:41 PM PDT 24
Peak memory 216892 kb
Host smart-f3281365-84a4-47c8-9f5b-0b40259c1952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480186742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.1480186742
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.174295158
Short name T958
Test name
Test status
Simulation time 127779484 ps
CPU time 0.88 seconds
Started Aug 06 04:46:37 PM PDT 24
Finished Aug 06 04:46:38 PM PDT 24
Peak memory 206760 kb
Host smart-ab24e970-8274-4c3b-9a15-80a518498f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174295158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.174295158
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.1880983540
Short name T788
Test name
Test status
Simulation time 653699038 ps
CPU time 3.23 seconds
Started Aug 06 04:46:40 PM PDT 24
Finished Aug 06 04:46:43 PM PDT 24
Peak memory 233228 kb
Host smart-2494feb7-9b28-4312-bb84-628582468783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880983540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.1880983540
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.2126454617
Short name T798
Test name
Test status
Simulation time 47457079 ps
CPU time 0.72 seconds
Started Aug 06 04:46:37 PM PDT 24
Finished Aug 06 04:46:37 PM PDT 24
Peak memory 205236 kb
Host smart-09f38e0d-c99e-482d-8957-e2ebd1114c51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126454617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
2126454617
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.934264625
Short name T829
Test name
Test status
Simulation time 227754046 ps
CPU time 2.7 seconds
Started Aug 06 04:46:43 PM PDT 24
Finished Aug 06 04:46:46 PM PDT 24
Peak memory 225244 kb
Host smart-2846aa23-2d77-4354-ae5a-5c464b8c6882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934264625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.934264625
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.2913369158
Short name T1021
Test name
Test status
Simulation time 13158865 ps
CPU time 0.74 seconds
Started Aug 06 04:46:41 PM PDT 24
Finished Aug 06 04:46:42 PM PDT 24
Peak memory 206984 kb
Host smart-860acd93-b5bd-4241-9036-521ba6cf2a2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913369158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.2913369158
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.1638879065
Short name T722
Test name
Test status
Simulation time 93707824793 ps
CPU time 196.06 seconds
Started Aug 06 04:46:44 PM PDT 24
Finished Aug 06 04:50:00 PM PDT 24
Peak memory 249828 kb
Host smart-36d8c9a6-f53b-43ee-84de-dfa46efb1fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638879065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.1638879065
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.2387358168
Short name T160
Test name
Test status
Simulation time 22785714747 ps
CPU time 125.12 seconds
Started Aug 06 04:46:43 PM PDT 24
Finished Aug 06 04:48:49 PM PDT 24
Peak memory 254064 kb
Host smart-a8d83457-4e6d-46d2-b53c-1a66c5898f4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387358168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.2387358168
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.465662500
Short name T190
Test name
Test status
Simulation time 16034337697 ps
CPU time 39 seconds
Started Aug 06 04:46:44 PM PDT 24
Finished Aug 06 04:47:23 PM PDT 24
Peak memory 239288 kb
Host smart-a87ff0a2-5bfb-4bad-8e98-3eaba6f8855f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465662500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idle
.465662500
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.2344482642
Short name T307
Test name
Test status
Simulation time 118821982 ps
CPU time 7.94 seconds
Started Aug 06 04:46:44 PM PDT 24
Finished Aug 06 04:46:52 PM PDT 24
Peak memory 233420 kb
Host smart-1ee49661-dd75-4e99-b00d-0796f7dca59a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344482642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.2344482642
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.67913378
Short name T77
Test name
Test status
Simulation time 19825660592 ps
CPU time 83.26 seconds
Started Aug 06 04:46:44 PM PDT 24
Finished Aug 06 04:48:07 PM PDT 24
Peak memory 253240 kb
Host smart-ea79cf6b-1584-4953-9edf-65761538c0e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67913378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmds.67913378
Directory /workspace/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/37.spi_device_intercept.3438485514
Short name T634
Test name
Test status
Simulation time 844183877 ps
CPU time 11.92 seconds
Started Aug 06 04:46:44 PM PDT 24
Finished Aug 06 04:46:56 PM PDT 24
Peak memory 225164 kb
Host smart-3410cd08-8d8c-457f-9517-cf126f58f93e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438485514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.3438485514
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.2126942631
Short name T378
Test name
Test status
Simulation time 24044370778 ps
CPU time 51.43 seconds
Started Aug 06 04:46:44 PM PDT 24
Finished Aug 06 04:47:36 PM PDT 24
Peak memory 225328 kb
Host smart-9d1dddb3-2303-4cfb-8266-eb5c97a1d47f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126942631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.2126942631
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.1931326013
Short name T389
Test name
Test status
Simulation time 639112550 ps
CPU time 2.39 seconds
Started Aug 06 04:46:43 PM PDT 24
Finished Aug 06 04:46:46 PM PDT 24
Peak memory 225140 kb
Host smart-f2fc0747-5590-4686-b731-873b9caed73c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931326013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.1931326013
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.934595064
Short name T700
Test name
Test status
Simulation time 971689506 ps
CPU time 5.79 seconds
Started Aug 06 04:46:42 PM PDT 24
Finished Aug 06 04:46:47 PM PDT 24
Peak memory 233388 kb
Host smart-8640fee3-1485-48ea-aaed-69fdd0aef8f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934595064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.934595064
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.861704820
Short name T29
Test name
Test status
Simulation time 484173397 ps
CPU time 3.82 seconds
Started Aug 06 04:46:44 PM PDT 24
Finished Aug 06 04:46:48 PM PDT 24
Peak memory 221232 kb
Host smart-1b05ac95-11a1-45fc-bb67-22d3521717fd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=861704820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dire
ct.861704820
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.2582312665
Short name T433
Test name
Test status
Simulation time 74411062720 ps
CPU time 62.88 seconds
Started Aug 06 04:46:41 PM PDT 24
Finished Aug 06 04:47:44 PM PDT 24
Peak memory 216972 kb
Host smart-a1f8c5ce-0198-4667-9122-e7c2e1a495d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582312665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.2582312665
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.1920405912
Short name T772
Test name
Test status
Simulation time 1933962399 ps
CPU time 6.98 seconds
Started Aug 06 04:46:41 PM PDT 24
Finished Aug 06 04:46:48 PM PDT 24
Peak memory 216872 kb
Host smart-3a3376db-6c57-49ea-b7e5-48cf1e48acd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920405912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.1920405912
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.3185547294
Short name T119
Test name
Test status
Simulation time 119924435 ps
CPU time 1.19 seconds
Started Aug 06 04:46:40 PM PDT 24
Finished Aug 06 04:46:42 PM PDT 24
Peak memory 216936 kb
Host smart-e93aa9f5-6a66-41e0-9de1-00a80d7ac407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185547294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.3185547294
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.2424084221
Short name T414
Test name
Test status
Simulation time 100738763 ps
CPU time 1.01 seconds
Started Aug 06 04:46:39 PM PDT 24
Finished Aug 06 04:46:40 PM PDT 24
Peak memory 206532 kb
Host smart-528767c3-1b56-4c35-9eaf-c99ab3ffebe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424084221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.2424084221
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.1750104993
Short name T274
Test name
Test status
Simulation time 2326478015 ps
CPU time 7.53 seconds
Started Aug 06 04:46:43 PM PDT 24
Finished Aug 06 04:46:51 PM PDT 24
Peak memory 225268 kb
Host smart-2ee0b827-60b4-47bf-86c1-b0960254cd70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750104993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.1750104993
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.1631218460
Short name T518
Test name
Test status
Simulation time 11710592 ps
CPU time 0.75 seconds
Started Aug 06 04:46:44 PM PDT 24
Finished Aug 06 04:46:45 PM PDT 24
Peak memory 205272 kb
Host smart-27c86782-d2cd-464e-b1dd-e714252ff7d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631218460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
1631218460
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.3958256804
Short name T728
Test name
Test status
Simulation time 1693813950 ps
CPU time 15.33 seconds
Started Aug 06 04:46:42 PM PDT 24
Finished Aug 06 04:46:58 PM PDT 24
Peak memory 225240 kb
Host smart-9452a30d-7746-4f9d-a01c-2564e62ecc1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958256804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.3958256804
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.3682413878
Short name T1023
Test name
Test status
Simulation time 68925803 ps
CPU time 0.79 seconds
Started Aug 06 04:46:42 PM PDT 24
Finished Aug 06 04:46:43 PM PDT 24
Peak memory 206876 kb
Host smart-675c2463-b28f-4bfb-8879-4a3424643054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682413878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.3682413878
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.330566169
Short name T202
Test name
Test status
Simulation time 28537482403 ps
CPU time 72.75 seconds
Started Aug 06 04:46:45 PM PDT 24
Finished Aug 06 04:47:58 PM PDT 24
Peak memory 249904 kb
Host smart-fd76d72e-0f24-4377-8449-1825d4909da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330566169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.330566169
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.3750108045
Short name T952
Test name
Test status
Simulation time 32452572045 ps
CPU time 278.08 seconds
Started Aug 06 04:46:41 PM PDT 24
Finished Aug 06 04:51:20 PM PDT 24
Peak memory 256252 kb
Host smart-d1c6b61a-5d1c-4ae1-aadc-39d85e73c910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750108045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.3750108045
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.3381760645
Short name T68
Test name
Test status
Simulation time 5979966455 ps
CPU time 10.75 seconds
Started Aug 06 04:46:42 PM PDT 24
Finished Aug 06 04:46:53 PM PDT 24
Peak memory 218332 kb
Host smart-2867658c-087b-4509-a36f-0beadc0d2a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381760645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.3381760645
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.3614785986
Short name T299
Test name
Test status
Simulation time 7484348811 ps
CPU time 21.66 seconds
Started Aug 06 04:46:42 PM PDT 24
Finished Aug 06 04:47:04 PM PDT 24
Peak memory 233484 kb
Host smart-6cb123df-1225-4604-9852-0e443806bde4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614785986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.3614785986
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.3324319855
Short name T174
Test name
Test status
Simulation time 9871623651 ps
CPU time 67.04 seconds
Started Aug 06 04:46:42 PM PDT 24
Finished Aug 06 04:47:49 PM PDT 24
Peak memory 258028 kb
Host smart-b5056f41-f709-4e8a-aeef-9fbd082c30b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324319855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmd
s.3324319855
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/38.spi_device_intercept.1940143020
Short name T384
Test name
Test status
Simulation time 8087813529 ps
CPU time 18.19 seconds
Started Aug 06 04:46:42 PM PDT 24
Finished Aug 06 04:47:01 PM PDT 24
Peak memory 225256 kb
Host smart-33946b7a-9b4b-438c-8908-889c6239ef15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940143020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.1940143020
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.1248059233
Short name T922
Test name
Test status
Simulation time 11189519514 ps
CPU time 94.41 seconds
Started Aug 06 04:46:43 PM PDT 24
Finished Aug 06 04:48:17 PM PDT 24
Peak memory 224124 kb
Host smart-783de885-d95e-4641-94da-5e2181830de3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248059233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.1248059233
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.2907967210
Short name T687
Test name
Test status
Simulation time 156234222185 ps
CPU time 25.93 seconds
Started Aug 06 04:46:41 PM PDT 24
Finished Aug 06 04:47:07 PM PDT 24
Peak memory 225276 kb
Host smart-adba584e-67ab-4398-8a1b-3516219190af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907967210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.2907967210
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.1257108678
Short name T448
Test name
Test status
Simulation time 2995194118 ps
CPU time 7.2 seconds
Started Aug 06 04:46:47 PM PDT 24
Finished Aug 06 04:46:55 PM PDT 24
Peak memory 233420 kb
Host smart-b6b12bdb-56ef-4f12-b146-68359494c17c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257108678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.1257108678
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.886416784
Short name T796
Test name
Test status
Simulation time 1978028046 ps
CPU time 6.22 seconds
Started Aug 06 04:46:42 PM PDT 24
Finished Aug 06 04:46:49 PM PDT 24
Peak memory 222872 kb
Host smart-1a954831-922c-45c8-9170-3404540f81a0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=886416784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dire
ct.886416784
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.2560390958
Short name T148
Test name
Test status
Simulation time 40080632466 ps
CPU time 307.4 seconds
Started Aug 06 04:46:45 PM PDT 24
Finished Aug 06 04:51:52 PM PDT 24
Peak memory 268732 kb
Host smart-b353ab15-3f5b-495f-ac8e-72ffe21d9806
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560390958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.2560390958
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.186548445
Short name T499
Test name
Test status
Simulation time 29433318947 ps
CPU time 40.29 seconds
Started Aug 06 04:46:47 PM PDT 24
Finished Aug 06 04:47:28 PM PDT 24
Peak memory 217052 kb
Host smart-078e64ac-3cca-4c1b-816a-b985687e1649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186548445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.186548445
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.2924468980
Short name T505
Test name
Test status
Simulation time 2013174846 ps
CPU time 6.19 seconds
Started Aug 06 04:46:41 PM PDT 24
Finished Aug 06 04:46:47 PM PDT 24
Peak memory 216872 kb
Host smart-28013a7d-708a-4769-b419-158a091690f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924468980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.2924468980
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.2059574007
Short name T783
Test name
Test status
Simulation time 139663542 ps
CPU time 2.34 seconds
Started Aug 06 04:46:47 PM PDT 24
Finished Aug 06 04:46:50 PM PDT 24
Peak memory 216832 kb
Host smart-850654f6-703a-4037-85aa-7fd51d3b7845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059574007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.2059574007
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.3236370533
Short name T480
Test name
Test status
Simulation time 20604402 ps
CPU time 0.86 seconds
Started Aug 06 04:46:47 PM PDT 24
Finished Aug 06 04:46:48 PM PDT 24
Peak memory 206468 kb
Host smart-731b67e0-d3b0-43d6-8c90-c7fd077f08da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236370533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.3236370533
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.588678626
Short name T856
Test name
Test status
Simulation time 41699494 ps
CPU time 2.47 seconds
Started Aug 06 04:46:40 PM PDT 24
Finished Aug 06 04:46:43 PM PDT 24
Peak memory 224780 kb
Host smart-6304c0e2-ba5a-4b09-8079-25cb95c877a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588678626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.588678626
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.4198328447
Short name T871
Test name
Test status
Simulation time 40145774 ps
CPU time 0.71 seconds
Started Aug 06 04:46:56 PM PDT 24
Finished Aug 06 04:46:57 PM PDT 24
Peak memory 205820 kb
Host smart-26bea4a4-c1e3-4fd8-a1b9-8251c99eb90e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198328447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
4198328447
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.456979875
Short name T740
Test name
Test status
Simulation time 3188319906 ps
CPU time 10.36 seconds
Started Aug 06 04:46:56 PM PDT 24
Finished Aug 06 04:47:07 PM PDT 24
Peak memory 233516 kb
Host smart-1399919e-7710-495d-92a8-ad1dccbe066d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456979875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.456979875
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.1995078494
Short name T381
Test name
Test status
Simulation time 73937828 ps
CPU time 0.74 seconds
Started Aug 06 04:46:38 PM PDT 24
Finished Aug 06 04:46:39 PM PDT 24
Peak memory 207020 kb
Host smart-24faff23-53bc-495d-a7e2-c1ecec382612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995078494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.1995078494
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.2262224592
Short name T521
Test name
Test status
Simulation time 5011378982 ps
CPU time 25.52 seconds
Started Aug 06 04:46:55 PM PDT 24
Finished Aug 06 04:47:21 PM PDT 24
Peak memory 249156 kb
Host smart-c678ace2-89c4-4584-b245-776926eefee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262224592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.2262224592
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.1195588566
Short name T195
Test name
Test status
Simulation time 10864832796 ps
CPU time 91.03 seconds
Started Aug 06 04:47:00 PM PDT 24
Finished Aug 06 04:48:31 PM PDT 24
Peak memory 254568 kb
Host smart-ad943cac-0619-4233-85d5-72ff09370ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195588566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.1195588566
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.2931088802
Short name T392
Test name
Test status
Simulation time 3567650530 ps
CPU time 29.31 seconds
Started Aug 06 04:46:57 PM PDT 24
Finished Aug 06 04:47:27 PM PDT 24
Peak memory 249828 kb
Host smart-f94c026c-4b1f-4abf-8253-2a49a760dcd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931088802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.2931088802
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.422622839
Short name T664
Test name
Test status
Simulation time 428418240 ps
CPU time 9.68 seconds
Started Aug 06 04:46:56 PM PDT 24
Finished Aug 06 04:47:06 PM PDT 24
Peak memory 233396 kb
Host smart-5833ee97-5903-4efb-ba80-48903922fadb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422622839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.422622839
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.715384849
Short name T1017
Test name
Test status
Simulation time 44825333485 ps
CPU time 166.42 seconds
Started Aug 06 04:47:00 PM PDT 24
Finished Aug 06 04:49:46 PM PDT 24
Peak memory 253744 kb
Host smart-86542ac1-6474-40ad-84fa-1675f143bbe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715384849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmds
.715384849
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/39.spi_device_intercept.1650377881
Short name T226
Test name
Test status
Simulation time 57625742 ps
CPU time 3 seconds
Started Aug 06 04:46:57 PM PDT 24
Finished Aug 06 04:47:00 PM PDT 24
Peak memory 233312 kb
Host smart-887e091b-f8fe-4d8b-b1e0-9855b76ea3b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650377881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.1650377881
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.3827954962
Short name T264
Test name
Test status
Simulation time 2677419583 ps
CPU time 12.94 seconds
Started Aug 06 04:46:55 PM PDT 24
Finished Aug 06 04:47:08 PM PDT 24
Peak memory 240004 kb
Host smart-b807b138-0824-4635-b340-957c33fa2334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827954962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.3827954962
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.3706485700
Short name T957
Test name
Test status
Simulation time 98649258 ps
CPU time 2.35 seconds
Started Aug 06 04:46:55 PM PDT 24
Finished Aug 06 04:46:57 PM PDT 24
Peak memory 232900 kb
Host smart-883bf5bc-6d1e-441a-8ed7-e17b1edeea3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706485700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.3706485700
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.205648579
Short name T940
Test name
Test status
Simulation time 3185295540 ps
CPU time 6.85 seconds
Started Aug 06 04:46:56 PM PDT 24
Finished Aug 06 04:47:03 PM PDT 24
Peak memory 233368 kb
Host smart-ffd8d9b9-fb15-4310-b88c-dd21a2530a75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205648579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.205648579
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.1554514738
Short name T362
Test name
Test status
Simulation time 1319047980 ps
CPU time 6.42 seconds
Started Aug 06 04:46:55 PM PDT 24
Finished Aug 06 04:47:02 PM PDT 24
Peak memory 222496 kb
Host smart-1ebb6e09-f6ab-448f-80a5-d8a70a320536
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1554514738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.1554514738
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.3722787988
Short name T257
Test name
Test status
Simulation time 44951383424 ps
CPU time 270.84 seconds
Started Aug 06 04:46:59 PM PDT 24
Finished Aug 06 04:51:30 PM PDT 24
Peak memory 254312 kb
Host smart-f40982c7-bf59-4114-8b51-9bd73ad590d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722787988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.3722787988
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.2350829280
Short name T310
Test name
Test status
Simulation time 28628229306 ps
CPU time 39.46 seconds
Started Aug 06 04:46:41 PM PDT 24
Finished Aug 06 04:47:20 PM PDT 24
Peak memory 216940 kb
Host smart-e70d51d0-89b7-4ed5-9176-1c498648af64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350829280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.2350829280
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.1353161446
Short name T331
Test name
Test status
Simulation time 2679196129 ps
CPU time 4.6 seconds
Started Aug 06 04:46:42 PM PDT 24
Finished Aug 06 04:46:47 PM PDT 24
Peak memory 217040 kb
Host smart-7ba2b31c-1070-4b7b-8b30-7f827a0c3774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353161446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.1353161446
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.2176813754
Short name T417
Test name
Test status
Simulation time 1279622481 ps
CPU time 2.31 seconds
Started Aug 06 04:46:57 PM PDT 24
Finished Aug 06 04:47:00 PM PDT 24
Peak memory 216944 kb
Host smart-4a1462dc-66f7-4dfd-a4e7-5238737cf272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176813754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.2176813754
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.497226300
Short name T541
Test name
Test status
Simulation time 102710294 ps
CPU time 0.83 seconds
Started Aug 06 04:46:42 PM PDT 24
Finished Aug 06 04:46:43 PM PDT 24
Peak memory 206540 kb
Host smart-7f2384b7-c3a3-45e6-8c58-1ecccabd4fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497226300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.497226300
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.1941095570
Short name T904
Test name
Test status
Simulation time 488240187 ps
CPU time 2.79 seconds
Started Aug 06 04:46:58 PM PDT 24
Finished Aug 06 04:47:01 PM PDT 24
Peak memory 233308 kb
Host smart-344aa03d-05c8-4123-a600-9f1600c08876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941095570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.1941095570
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.1918721282
Short name T568
Test name
Test status
Simulation time 36711452 ps
CPU time 0.7 seconds
Started Aug 06 04:44:33 PM PDT 24
Finished Aug 06 04:44:34 PM PDT 24
Peak memory 205104 kb
Host smart-288c6e66-45b6-4173-80fb-0c43452a862a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918721282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.1
918721282
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.2374986033
Short name T814
Test name
Test status
Simulation time 96095475 ps
CPU time 3.01 seconds
Started Aug 06 04:44:34 PM PDT 24
Finished Aug 06 04:44:38 PM PDT 24
Peak memory 225228 kb
Host smart-d1e32abb-a847-4342-a72c-dc78fa3c97c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374986033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.2374986033
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.994127323
Short name T443
Test name
Test status
Simulation time 95190985 ps
CPU time 0.78 seconds
Started Aug 06 04:44:31 PM PDT 24
Finished Aug 06 04:44:31 PM PDT 24
Peak memory 206916 kb
Host smart-0507f6cc-bf14-4003-8370-016672d50722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994127323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.994127323
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.3084590442
Short name T753
Test name
Test status
Simulation time 217301541582 ps
CPU time 282.03 seconds
Started Aug 06 04:44:47 PM PDT 24
Finished Aug 06 04:49:29 PM PDT 24
Peak memory 256668 kb
Host smart-6587b9f4-9398-4c56-bf52-f299a4636b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084590442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.3084590442
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.4168036226
Short name T842
Test name
Test status
Simulation time 13737633319 ps
CPU time 98.09 seconds
Started Aug 06 04:44:31 PM PDT 24
Finished Aug 06 04:46:09 PM PDT 24
Peak memory 257368 kb
Host smart-5977057e-7aa7-40b0-9ac8-4c4093eb69a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168036226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.4168036226
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.2536275363
Short name T848
Test name
Test status
Simulation time 14935795062 ps
CPU time 166.18 seconds
Started Aug 06 04:44:32 PM PDT 24
Finished Aug 06 04:47:18 PM PDT 24
Peak memory 249848 kb
Host smart-ac54f22f-d1ca-4ecd-9242-02a5c3da92f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536275363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.2536275363
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.557667559
Short name T836
Test name
Test status
Simulation time 5866523926 ps
CPU time 41.42 seconds
Started Aug 06 04:44:34 PM PDT 24
Finished Aug 06 04:45:16 PM PDT 24
Peak memory 249848 kb
Host smart-46bfc83a-8373-48cc-9928-8b75e8453f8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557667559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds.
557667559
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/4.spi_device_intercept.1265074195
Short name T701
Test name
Test status
Simulation time 192533958 ps
CPU time 4.66 seconds
Started Aug 06 04:44:30 PM PDT 24
Finished Aug 06 04:44:35 PM PDT 24
Peak memory 233416 kb
Host smart-6726189d-3d48-42d3-b6a1-c8dd9f278e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265074195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.1265074195
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.23923930
Short name T800
Test name
Test status
Simulation time 687042035 ps
CPU time 6.69 seconds
Started Aug 06 04:44:36 PM PDT 24
Finished Aug 06 04:44:43 PM PDT 24
Peak memory 225136 kb
Host smart-7ce1e9d6-86ba-4f4d-8323-f0a70c029bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23923930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.23923930
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.458818938
Short name T611
Test name
Test status
Simulation time 308186053 ps
CPU time 1.02 seconds
Started Aug 06 04:44:28 PM PDT 24
Finished Aug 06 04:44:29 PM PDT 24
Peak memory 217140 kb
Host smart-b843b1b6-c7d0-4693-8164-88c6ae39fc06
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458818938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.spi_device_mem_parity.458818938
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.2490465358
Short name T528
Test name
Test status
Simulation time 2266090597 ps
CPU time 12 seconds
Started Aug 06 04:44:36 PM PDT 24
Finished Aug 06 04:44:48 PM PDT 24
Peak memory 233476 kb
Host smart-6fcd00dc-d29f-4f62-af8f-11b97708222e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490465358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.2490465358
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.3842578689
Short name T797
Test name
Test status
Simulation time 1231023743 ps
CPU time 4.72 seconds
Started Aug 06 04:44:29 PM PDT 24
Finished Aug 06 04:44:34 PM PDT 24
Peak memory 238560 kb
Host smart-067fd1ce-d211-465d-b18d-24fcaf9453a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842578689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.3842578689
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.3980993805
Short name T749
Test name
Test status
Simulation time 3154691354 ps
CPU time 7.79 seconds
Started Aug 06 04:44:26 PM PDT 24
Finished Aug 06 04:44:34 PM PDT 24
Peak memory 223628 kb
Host smart-0f3a4b68-c1e6-47ef-894d-e7ed8e4d4667
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3980993805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.3980993805
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.2631017438
Short name T50
Test name
Test status
Simulation time 63517089 ps
CPU time 0.97 seconds
Started Aug 06 04:44:32 PM PDT 24
Finished Aug 06 04:44:33 PM PDT 24
Peak memory 235136 kb
Host smart-3ba69405-fb58-466b-8101-e52227e7be5f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631017438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.2631017438
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.3473426189
Short name T589
Test name
Test status
Simulation time 38529605 ps
CPU time 0.98 seconds
Started Aug 06 04:44:32 PM PDT 24
Finished Aug 06 04:44:33 PM PDT 24
Peak memory 207220 kb
Host smart-c468c03e-3445-4c73-b6dd-ac7c9b3c68b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473426189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.3473426189
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.354507572
Short name T677
Test name
Test status
Simulation time 377997113 ps
CPU time 4.8 seconds
Started Aug 06 04:44:38 PM PDT 24
Finished Aug 06 04:44:42 PM PDT 24
Peak memory 216984 kb
Host smart-53c8168e-7c51-484d-84c7-c2c30dea7465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354507572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.354507572
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.2161301961
Short name T536
Test name
Test status
Simulation time 6397407054 ps
CPU time 9.56 seconds
Started Aug 06 04:44:27 PM PDT 24
Finished Aug 06 04:44:37 PM PDT 24
Peak memory 216924 kb
Host smart-d7669f36-a287-4c7f-84e3-7371bd7a9186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161301961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.2161301961
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.270415485
Short name T808
Test name
Test status
Simulation time 78044005 ps
CPU time 1.03 seconds
Started Aug 06 04:44:24 PM PDT 24
Finished Aug 06 04:44:25 PM PDT 24
Peak memory 207528 kb
Host smart-0387608d-989e-4f09-8084-faa12866a4ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270415485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.270415485
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.184388307
Short name T894
Test name
Test status
Simulation time 113086354 ps
CPU time 1.08 seconds
Started Aug 06 04:44:34 PM PDT 24
Finished Aug 06 04:44:36 PM PDT 24
Peak memory 207468 kb
Host smart-2bbd0e46-c553-42d2-9794-91937ffd39db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184388307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.184388307
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.3044682759
Short name T510
Test name
Test status
Simulation time 7604359642 ps
CPU time 9.53 seconds
Started Aug 06 04:44:31 PM PDT 24
Finished Aug 06 04:44:41 PM PDT 24
Peak memory 232904 kb
Host smart-6fe45989-4b1c-493e-90b2-4d6c1d34c12a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044682759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.3044682759
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.2467561361
Short name T54
Test name
Test status
Simulation time 10868011 ps
CPU time 0.7 seconds
Started Aug 06 04:47:02 PM PDT 24
Finished Aug 06 04:47:03 PM PDT 24
Peak memory 205632 kb
Host smart-41731a25-4507-40a2-ade4-083c665cd58d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467561361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
2467561361
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.2398541930
Short name T238
Test name
Test status
Simulation time 154658853 ps
CPU time 5.04 seconds
Started Aug 06 04:47:03 PM PDT 24
Finished Aug 06 04:47:09 PM PDT 24
Peak memory 233292 kb
Host smart-5d945d1c-340b-4496-8eef-e272335b3e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398541930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.2398541930
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.1258910963
Short name T322
Test name
Test status
Simulation time 40383167 ps
CPU time 0.76 seconds
Started Aug 06 04:46:59 PM PDT 24
Finished Aug 06 04:47:00 PM PDT 24
Peak memory 207316 kb
Host smart-10a8dc1f-44f5-47a1-abf7-f4356d437ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258910963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.1258910963
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.4056123830
Short name T470
Test name
Test status
Simulation time 25460838775 ps
CPU time 46.14 seconds
Started Aug 06 04:47:02 PM PDT 24
Finished Aug 06 04:47:48 PM PDT 24
Peak memory 237480 kb
Host smart-eba02dc7-66f8-4b48-9dbc-3c79e0c0b53a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056123830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.4056123830
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.4013344624
Short name T121
Test name
Test status
Simulation time 2205529985 ps
CPU time 51.67 seconds
Started Aug 06 04:47:04 PM PDT 24
Finished Aug 06 04:47:56 PM PDT 24
Peak memory 256816 kb
Host smart-772b24da-ad8b-4f88-931e-1bbe5716c986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013344624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.4013344624
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.2789802321
Short name T960
Test name
Test status
Simulation time 2699252654 ps
CPU time 18.28 seconds
Started Aug 06 04:47:06 PM PDT 24
Finished Aug 06 04:47:25 PM PDT 24
Peak memory 225096 kb
Host smart-d05dc096-dc76-47df-be2a-29f60380ae09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789802321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.2789802321
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.1676527323
Short name T873
Test name
Test status
Simulation time 699584769 ps
CPU time 4.18 seconds
Started Aug 06 04:47:03 PM PDT 24
Finished Aug 06 04:47:08 PM PDT 24
Peak memory 233352 kb
Host smart-f75f9b70-3086-4f88-8542-4f9de9384eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676527323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.1676527323
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.1177334442
Short name T1
Test name
Test status
Simulation time 23924867710 ps
CPU time 169.39 seconds
Started Aug 06 04:47:01 PM PDT 24
Finished Aug 06 04:49:51 PM PDT 24
Peak memory 253328 kb
Host smart-d55bef88-a941-4f8c-8a27-c18517d9c5b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177334442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmd
s.1177334442
Directory /workspace/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/40.spi_device_intercept.1507863498
Short name T472
Test name
Test status
Simulation time 643557354 ps
CPU time 4.79 seconds
Started Aug 06 04:47:01 PM PDT 24
Finished Aug 06 04:47:06 PM PDT 24
Peak memory 233452 kb
Host smart-fb8b4fe9-746e-49d4-9b43-82a412136428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507863498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.1507863498
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.4247669953
Short name T35
Test name
Test status
Simulation time 3884948639 ps
CPU time 44.28 seconds
Started Aug 06 04:47:01 PM PDT 24
Finished Aug 06 04:47:46 PM PDT 24
Peak memory 236868 kb
Host smart-3c51abe8-8932-4639-9545-7416a8a7c6e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247669953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.4247669953
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.4182597283
Short name T215
Test name
Test status
Simulation time 289297473 ps
CPU time 7.87 seconds
Started Aug 06 04:46:59 PM PDT 24
Finished Aug 06 04:47:07 PM PDT 24
Peak memory 236584 kb
Host smart-9dba6b87-b1f6-46e7-a80a-2ba57195f933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182597283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.4182597283
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.1663733392
Short name T870
Test name
Test status
Simulation time 44799888 ps
CPU time 2.51 seconds
Started Aug 06 04:46:59 PM PDT 24
Finished Aug 06 04:47:01 PM PDT 24
Peak memory 233416 kb
Host smart-29a61671-9b77-41fb-9d0a-e8a62a61ffe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663733392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.1663733392
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.3564572888
Short name T131
Test name
Test status
Simulation time 2402796377 ps
CPU time 7.63 seconds
Started Aug 06 04:47:01 PM PDT 24
Finished Aug 06 04:47:09 PM PDT 24
Peak memory 221428 kb
Host smart-0bf00a94-c5b8-4f76-909d-0d1f67fc8adb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3564572888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.3564572888
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.1081533791
Short name T941
Test name
Test status
Simulation time 2204463963 ps
CPU time 24.85 seconds
Started Aug 06 04:46:56 PM PDT 24
Finished Aug 06 04:47:21 PM PDT 24
Peak memory 217080 kb
Host smart-59e673e0-932c-4f08-bb07-8af678f99fb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081533791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.1081533791
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.3411209690
Short name T380
Test name
Test status
Simulation time 2380529424 ps
CPU time 4.53 seconds
Started Aug 06 04:47:00 PM PDT 24
Finished Aug 06 04:47:04 PM PDT 24
Peak memory 216944 kb
Host smart-ee61ab0a-d098-42eb-bd7c-3130a73518b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411209690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.3411209690
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.1268212292
Short name T667
Test name
Test status
Simulation time 42533715 ps
CPU time 1.46 seconds
Started Aug 06 04:47:01 PM PDT 24
Finished Aug 06 04:47:02 PM PDT 24
Peak memory 216988 kb
Host smart-29be738f-5f3d-4cd0-a028-e0c3c9caeb0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268212292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.1268212292
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.21028315
Short name T793
Test name
Test status
Simulation time 57473966 ps
CPU time 0.84 seconds
Started Aug 06 04:46:56 PM PDT 24
Finished Aug 06 04:46:57 PM PDT 24
Peak memory 206452 kb
Host smart-5f30551b-b532-4d4c-b829-7da86e26bfd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21028315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.21028315
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.2538960186
Short name T734
Test name
Test status
Simulation time 2702502607 ps
CPU time 6.48 seconds
Started Aug 06 04:47:03 PM PDT 24
Finished Aug 06 04:47:10 PM PDT 24
Peak memory 225128 kb
Host smart-fb9a38c2-7d76-4d78-acbf-de8c1a93ef01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538960186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.2538960186
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.1025039042
Short name T157
Test name
Test status
Simulation time 46005218 ps
CPU time 0.71 seconds
Started Aug 06 04:46:57 PM PDT 24
Finished Aug 06 04:46:58 PM PDT 24
Peak memory 205184 kb
Host smart-7ce6a8ee-a81c-489f-b0dc-5360dcc9a709
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025039042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
1025039042
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.3430938097
Short name T441
Test name
Test status
Simulation time 1305395109 ps
CPU time 2.47 seconds
Started Aug 06 04:47:05 PM PDT 24
Finished Aug 06 04:47:08 PM PDT 24
Peak memory 225116 kb
Host smart-80fb9e88-d4fa-44c2-b756-aee1c16d90ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430938097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.3430938097
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.3319483007
Short name T924
Test name
Test status
Simulation time 16303489 ps
CPU time 0.76 seconds
Started Aug 06 04:47:03 PM PDT 24
Finished Aug 06 04:47:04 PM PDT 24
Peak memory 205924 kb
Host smart-bc14b7b3-1cf4-4aeb-865d-58a4779e25f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319483007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.3319483007
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.3597153851
Short name T161
Test name
Test status
Simulation time 6120163869 ps
CPU time 79.66 seconds
Started Aug 06 04:47:03 PM PDT 24
Finished Aug 06 04:48:23 PM PDT 24
Peak memory 258064 kb
Host smart-c74afaaf-807f-4550-8b4c-b895157ccd44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597153851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.3597153851
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.3855607153
Short name T199
Test name
Test status
Simulation time 6324544306 ps
CPU time 77.61 seconds
Started Aug 06 04:47:02 PM PDT 24
Finished Aug 06 04:48:20 PM PDT 24
Peak memory 254032 kb
Host smart-21b8f977-9448-4ef2-9871-e3cf70ce2e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855607153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.3855607153
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.1080185084
Short name T88
Test name
Test status
Simulation time 18315276909 ps
CPU time 163.57 seconds
Started Aug 06 04:46:55 PM PDT 24
Finished Aug 06 04:49:39 PM PDT 24
Peak memory 249800 kb
Host smart-d7658cd1-52a6-42c4-bc66-e8dd4b31cefa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080185084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.1080185084
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.419162373
Short name T509
Test name
Test status
Simulation time 3643971913 ps
CPU time 8.77 seconds
Started Aug 06 04:47:06 PM PDT 24
Finished Aug 06 04:47:15 PM PDT 24
Peak memory 233364 kb
Host smart-afbfdd17-04ea-46dd-8943-e92dad6fb356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419162373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.419162373
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.4008448850
Short name T218
Test name
Test status
Simulation time 44494221283 ps
CPU time 214.98 seconds
Started Aug 06 04:47:02 PM PDT 24
Finished Aug 06 04:50:38 PM PDT 24
Peak memory 267844 kb
Host smart-7860b397-7bed-4870-8093-b98e7472d38f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008448850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmd
s.4008448850
Directory /workspace/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/41.spi_device_intercept.2749407632
Short name T1024
Test name
Test status
Simulation time 280418871 ps
CPU time 1.98 seconds
Started Aug 06 04:47:05 PM PDT 24
Finished Aug 06 04:47:08 PM PDT 24
Peak memory 223548 kb
Host smart-6c2b863d-e487-418a-bc3b-1fcd34e1f48a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749407632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.2749407632
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.580078180
Short name T646
Test name
Test status
Simulation time 509096040 ps
CPU time 13.21 seconds
Started Aug 06 04:47:01 PM PDT 24
Finished Aug 06 04:47:14 PM PDT 24
Peak memory 241300 kb
Host smart-41fc56fe-6cc1-45ea-ad40-7c24d0415d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580078180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.580078180
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.1643071664
Short name T717
Test name
Test status
Simulation time 39498376 ps
CPU time 2.79 seconds
Started Aug 06 04:47:04 PM PDT 24
Finished Aug 06 04:47:07 PM PDT 24
Peak memory 233408 kb
Host smart-006c74d1-068e-4bb8-a141-3a83e7d6886b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643071664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.1643071664
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.3377922294
Short name T118
Test name
Test status
Simulation time 510429395 ps
CPU time 8.36 seconds
Started Aug 06 04:47:01 PM PDT 24
Finished Aug 06 04:47:09 PM PDT 24
Peak memory 233448 kb
Host smart-d5c52c11-8f24-4056-ab8c-f037364b34e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377922294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.3377922294
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.409376640
Short name T877
Test name
Test status
Simulation time 167188600 ps
CPU time 4.95 seconds
Started Aug 06 04:46:58 PM PDT 24
Finished Aug 06 04:47:03 PM PDT 24
Peak memory 223192 kb
Host smart-14facd58-62f7-45bb-b80c-cd2d2f1e22ae
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=409376640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dire
ct.409376640
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.806322933
Short name T123
Test name
Test status
Simulation time 16861102502 ps
CPU time 125.78 seconds
Started Aug 06 04:46:59 PM PDT 24
Finished Aug 06 04:49:05 PM PDT 24
Peak memory 266112 kb
Host smart-51e44fea-d13f-40b8-a469-3ff31bd43e37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806322933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stres
s_all.806322933
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.3667532703
Short name T359
Test name
Test status
Simulation time 4692989411 ps
CPU time 23.79 seconds
Started Aug 06 04:47:05 PM PDT 24
Finished Aug 06 04:47:29 PM PDT 24
Peak memory 216996 kb
Host smart-afef10e4-91c6-4bed-9ea3-1958e7ac3a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667532703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.3667532703
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.3242823123
Short name T326
Test name
Test status
Simulation time 1984255253 ps
CPU time 10.52 seconds
Started Aug 06 04:47:02 PM PDT 24
Finished Aug 06 04:47:13 PM PDT 24
Peak memory 216704 kb
Host smart-ac1744b4-aef3-4621-8112-d927180a2ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242823123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.3242823123
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.2496877227
Short name T857
Test name
Test status
Simulation time 195906235 ps
CPU time 1.55 seconds
Started Aug 06 04:47:03 PM PDT 24
Finished Aug 06 04:47:04 PM PDT 24
Peak memory 208724 kb
Host smart-acfd1ed2-29a6-4a87-a4df-7e5873410139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496877227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.2496877227
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.1187160737
Short name T699
Test name
Test status
Simulation time 389215310 ps
CPU time 0.91 seconds
Started Aug 06 04:47:04 PM PDT 24
Finished Aug 06 04:47:05 PM PDT 24
Peak memory 206316 kb
Host smart-f3ec3d1c-acbc-43cc-b25c-51d51ac09612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187160737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.1187160737
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.3215597266
Short name T55
Test name
Test status
Simulation time 6344720454 ps
CPU time 10 seconds
Started Aug 06 04:47:06 PM PDT 24
Finished Aug 06 04:47:16 PM PDT 24
Peak memory 225048 kb
Host smart-5a46a5b6-dbe4-4d52-b839-b9a8b098ae45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215597266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.3215597266
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.1523303566
Short name T837
Test name
Test status
Simulation time 10947146 ps
CPU time 0.72 seconds
Started Aug 06 04:47:02 PM PDT 24
Finished Aug 06 04:47:03 PM PDT 24
Peak memory 206068 kb
Host smart-f83cb8bf-686f-4c1b-8177-512573ffa568
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523303566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
1523303566
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.2714384187
Short name T801
Test name
Test status
Simulation time 89687849 ps
CPU time 2.47 seconds
Started Aug 06 04:47:01 PM PDT 24
Finished Aug 06 04:47:03 PM PDT 24
Peak memory 225244 kb
Host smart-7c6a29af-ee06-49a3-b8d8-576ed15359b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714384187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.2714384187
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.1238283466
Short name T429
Test name
Test status
Simulation time 24855161 ps
CPU time 0.73 seconds
Started Aug 06 04:46:57 PM PDT 24
Finished Aug 06 04:46:58 PM PDT 24
Peak memory 205948 kb
Host smart-ce8461db-1448-406e-a868-f84a11dd35f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238283466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.1238283466
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.1371546312
Short name T427
Test name
Test status
Simulation time 93042335753 ps
CPU time 55.04 seconds
Started Aug 06 04:46:59 PM PDT 24
Finished Aug 06 04:47:54 PM PDT 24
Peak memory 236980 kb
Host smart-1cd15d14-d104-44e6-8bc6-38a410306e2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371546312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.1371546312
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.2770416728
Short name T861
Test name
Test status
Simulation time 1630778809 ps
CPU time 8.64 seconds
Started Aug 06 04:46:57 PM PDT 24
Finished Aug 06 04:47:05 PM PDT 24
Peak memory 241528 kb
Host smart-13938324-7ad1-43d0-879f-49bd40c0a3eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770416728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.2770416728
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.3194475999
Short name T434
Test name
Test status
Simulation time 20351959925 ps
CPU time 88.98 seconds
Started Aug 06 04:46:56 PM PDT 24
Finished Aug 06 04:48:25 PM PDT 24
Peak memory 251640 kb
Host smart-337ff0ba-6822-45ab-ac53-7cd22a2fa6ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194475999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmd
s.3194475999
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/42.spi_device_intercept.4252511215
Short name T558
Test name
Test status
Simulation time 9731263437 ps
CPU time 22.92 seconds
Started Aug 06 04:46:58 PM PDT 24
Finished Aug 06 04:47:21 PM PDT 24
Peak memory 233388 kb
Host smart-af7e20ae-0ba3-48e8-b246-2744731e3f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252511215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.4252511215
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.3831870165
Short name T500
Test name
Test status
Simulation time 2239166381 ps
CPU time 13.81 seconds
Started Aug 06 04:46:57 PM PDT 24
Finished Aug 06 04:47:11 PM PDT 24
Peak memory 250940 kb
Host smart-96ea3fea-e875-4c26-b7f8-6604b849dc9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831870165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.3831870165
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.2368829110
Short name T258
Test name
Test status
Simulation time 786843075 ps
CPU time 4.7 seconds
Started Aug 06 04:46:54 PM PDT 24
Finished Aug 06 04:46:59 PM PDT 24
Peak memory 233376 kb
Host smart-0787788d-f5ef-463d-b6ef-225a5737e3d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368829110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.2368829110
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.3398328012
Short name T216
Test name
Test status
Simulation time 2328742154 ps
CPU time 8.77 seconds
Started Aug 06 04:46:54 PM PDT 24
Finished Aug 06 04:47:03 PM PDT 24
Peak memory 233332 kb
Host smart-a753b516-a75b-47ef-ab49-f6b8aabef440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398328012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.3398328012
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.3442066127
Short name T534
Test name
Test status
Simulation time 141247423 ps
CPU time 4.66 seconds
Started Aug 06 04:47:02 PM PDT 24
Finished Aug 06 04:47:07 PM PDT 24
Peak memory 220512 kb
Host smart-244403a5-548e-46c1-b9c5-3c2d1d87cf36
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3442066127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.3442066127
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.3754963345
Short name T400
Test name
Test status
Simulation time 82096674041 ps
CPU time 146.78 seconds
Started Aug 06 04:47:01 PM PDT 24
Finished Aug 06 04:49:28 PM PDT 24
Peak memory 258136 kb
Host smart-d0b502d9-5b63-492d-b62e-b8cfccac9413
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754963345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.3754963345
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.676028431
Short name T970
Test name
Test status
Simulation time 5308006162 ps
CPU time 32.78 seconds
Started Aug 06 04:46:59 PM PDT 24
Finished Aug 06 04:47:32 PM PDT 24
Peak memory 220736 kb
Host smart-342b6b6b-35e4-4c9e-ba81-463dfc0ec980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676028431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.676028431
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.4167354861
Short name T416
Test name
Test status
Simulation time 741445440 ps
CPU time 2.97 seconds
Started Aug 06 04:46:56 PM PDT 24
Finished Aug 06 04:46:59 PM PDT 24
Peak memory 208456 kb
Host smart-c14b092b-b9f9-4442-8a4f-a50217a09267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167354861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.4167354861
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.266692350
Short name T897
Test name
Test status
Simulation time 73967645 ps
CPU time 1.21 seconds
Started Aug 06 04:46:59 PM PDT 24
Finished Aug 06 04:47:00 PM PDT 24
Peak memory 208552 kb
Host smart-43ce3e21-3032-42e9-ba0a-13a52a6166e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266692350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.266692350
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.2868039563
Short name T374
Test name
Test status
Simulation time 61532597 ps
CPU time 0.78 seconds
Started Aug 06 04:46:56 PM PDT 24
Finished Aug 06 04:46:57 PM PDT 24
Peak memory 206436 kb
Host smart-378e38ba-b2ed-4f6f-8c0e-422a91f9d21b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868039563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.2868039563
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.3595855913
Short name T926
Test name
Test status
Simulation time 65175504 ps
CPU time 2.12 seconds
Started Aug 06 04:46:56 PM PDT 24
Finished Aug 06 04:46:58 PM PDT 24
Peak memory 224600 kb
Host smart-b1b1a062-1945-4f6d-86cf-2880e4eddc4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595855913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.3595855913
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.1614803411
Short name T1009
Test name
Test status
Simulation time 89982029 ps
CPU time 0.75 seconds
Started Aug 06 04:47:04 PM PDT 24
Finished Aug 06 04:47:05 PM PDT 24
Peak memory 205836 kb
Host smart-8eace8b4-17ec-4d85-b56d-c5c9938d3b1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614803411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
1614803411
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.3354381466
Short name T236
Test name
Test status
Simulation time 482068430 ps
CPU time 4.56 seconds
Started Aug 06 04:47:00 PM PDT 24
Finished Aug 06 04:47:05 PM PDT 24
Peak memory 233304 kb
Host smart-738da7eb-0422-4bda-8330-3489d4afdd7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354381466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.3354381466
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.2083874534
Short name T419
Test name
Test status
Simulation time 41367116 ps
CPU time 0.75 seconds
Started Aug 06 04:47:02 PM PDT 24
Finished Aug 06 04:47:03 PM PDT 24
Peak memory 206016 kb
Host smart-8bb933a2-3775-4454-910d-60d3a994b188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083874534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.2083874534
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.4248334987
Short name T1025
Test name
Test status
Simulation time 17176405568 ps
CPU time 30.15 seconds
Started Aug 06 04:47:04 PM PDT 24
Finished Aug 06 04:47:34 PM PDT 24
Peak memory 218272 kb
Host smart-60544095-67bf-4196-adaa-5e64e49fd9a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248334987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.4248334987
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.1011378327
Short name T672
Test name
Test status
Simulation time 18049602513 ps
CPU time 193.3 seconds
Started Aug 06 04:47:03 PM PDT 24
Finished Aug 06 04:50:17 PM PDT 24
Peak memory 257788 kb
Host smart-761b8a9c-8d42-46e4-9628-87c78326682d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011378327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.1011378327
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.2437145558
Short name T943
Test name
Test status
Simulation time 3219167294 ps
CPU time 13.71 seconds
Started Aug 06 04:47:04 PM PDT 24
Finished Aug 06 04:47:17 PM PDT 24
Peak memory 233396 kb
Host smart-f3848c27-92b2-4a1f-aff4-6e9865b6f3d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437145558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.2437145558
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.730785697
Short name T213
Test name
Test status
Simulation time 31164309834 ps
CPU time 201.44 seconds
Started Aug 06 04:47:04 PM PDT 24
Finished Aug 06 04:50:26 PM PDT 24
Peak memory 249680 kb
Host smart-fd30214d-be6e-4e20-9a91-f19fd06b34e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730785697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmds
.730785697
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/43.spi_device_intercept.2505666897
Short name T615
Test name
Test status
Simulation time 277223686 ps
CPU time 2.7 seconds
Started Aug 06 04:47:02 PM PDT 24
Finished Aug 06 04:47:05 PM PDT 24
Peak memory 233296 kb
Host smart-85084976-091e-4fc8-8271-910d05ad3096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505666897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.2505666897
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.1084441398
Short name T459
Test name
Test status
Simulation time 86905026300 ps
CPU time 72 seconds
Started Aug 06 04:47:02 PM PDT 24
Finished Aug 06 04:48:14 PM PDT 24
Peak memory 234348 kb
Host smart-5de2ee74-a209-4848-8920-39d0fe6593d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084441398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.1084441398
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.3841793520
Short name T939
Test name
Test status
Simulation time 468297504 ps
CPU time 3.87 seconds
Started Aug 06 04:47:01 PM PDT 24
Finished Aug 06 04:47:05 PM PDT 24
Peak memory 233288 kb
Host smart-759f6a24-0419-4884-8df6-694c67a4f250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841793520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.3841793520
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.3389848389
Short name T702
Test name
Test status
Simulation time 8685697558 ps
CPU time 10.91 seconds
Started Aug 06 04:47:06 PM PDT 24
Finished Aug 06 04:47:17 PM PDT 24
Peak memory 233276 kb
Host smart-936d4f7a-3fd6-41cb-942f-c64f87d97e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389848389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.3389848389
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.1638134248
Short name T323
Test name
Test status
Simulation time 434991186 ps
CPU time 3.57 seconds
Started Aug 06 04:47:03 PM PDT 24
Finished Aug 06 04:47:06 PM PDT 24
Peak memory 223624 kb
Host smart-60972edc-ba71-42a2-b0a2-6b696446d173
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1638134248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.1638134248
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.3210230557
Short name T679
Test name
Test status
Simulation time 6387361707 ps
CPU time 35.76 seconds
Started Aug 06 04:46:59 PM PDT 24
Finished Aug 06 04:47:35 PM PDT 24
Peak memory 239356 kb
Host smart-68b15f99-2108-44c5-b1b4-c44bd2187591
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210230557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.3210230557
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.1694404791
Short name T975
Test name
Test status
Simulation time 19431966970 ps
CPU time 24.32 seconds
Started Aug 06 04:47:00 PM PDT 24
Finished Aug 06 04:47:24 PM PDT 24
Peak memory 217080 kb
Host smart-fbec5b69-3e66-4f81-b983-f6c5762f8922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694404791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.1694404791
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.2212478346
Short name T564
Test name
Test status
Simulation time 1142505378 ps
CPU time 5.74 seconds
Started Aug 06 04:47:03 PM PDT 24
Finished Aug 06 04:47:09 PM PDT 24
Peak memory 216824 kb
Host smart-875900f2-c75c-490d-bf68-aaac1152cee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212478346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.2212478346
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.3612947618
Short name T709
Test name
Test status
Simulation time 1096307040 ps
CPU time 10.65 seconds
Started Aug 06 04:47:02 PM PDT 24
Finished Aug 06 04:47:13 PM PDT 24
Peak memory 216856 kb
Host smart-75657fc0-480d-4dc3-a97e-4ae405eaf8b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612947618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.3612947618
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.3570911175
Short name T714
Test name
Test status
Simulation time 80595836 ps
CPU time 0.98 seconds
Started Aug 06 04:46:57 PM PDT 24
Finished Aug 06 04:46:58 PM PDT 24
Peak memory 206544 kb
Host smart-c78b66f2-2395-4597-960c-04067ee51b13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570911175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.3570911175
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.3246931160
Short name T694
Test name
Test status
Simulation time 1263440095 ps
CPU time 4.97 seconds
Started Aug 06 04:46:57 PM PDT 24
Finished Aug 06 04:47:02 PM PDT 24
Peak memory 233392 kb
Host smart-1e57efba-45ba-43ca-a17c-4ad3955c5bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246931160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.3246931160
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.1932192571
Short name T455
Test name
Test status
Simulation time 41560950 ps
CPU time 0.7 seconds
Started Aug 06 04:47:13 PM PDT 24
Finished Aug 06 04:47:14 PM PDT 24
Peak memory 205808 kb
Host smart-92336c61-03a5-4d07-a031-8328427e9ab5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932192571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
1932192571
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.2648182601
Short name T692
Test name
Test status
Simulation time 7772199302 ps
CPU time 15.06 seconds
Started Aug 06 04:47:10 PM PDT 24
Finished Aug 06 04:47:25 PM PDT 24
Peak memory 225204 kb
Host smart-fe07d313-8960-4dce-8afb-b39cd02297b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648182601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.2648182601
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.2223571596
Short name T1008
Test name
Test status
Simulation time 19012890 ps
CPU time 0.78 seconds
Started Aug 06 04:47:06 PM PDT 24
Finished Aug 06 04:47:06 PM PDT 24
Peak memory 206936 kb
Host smart-b837d23c-66d0-485b-b95c-df7143e34159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223571596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.2223571596
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.3340027632
Short name T705
Test name
Test status
Simulation time 12076073940 ps
CPU time 59.83 seconds
Started Aug 06 04:47:08 PM PDT 24
Finished Aug 06 04:48:08 PM PDT 24
Peak memory 249956 kb
Host smart-b7ad0d42-fafe-4b1b-ad6d-9ceb17d6dd49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340027632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.3340027632
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.2672981881
Short name T288
Test name
Test status
Simulation time 19495730657 ps
CPU time 218.63 seconds
Started Aug 06 04:47:11 PM PDT 24
Finished Aug 06 04:50:50 PM PDT 24
Peak memory 265992 kb
Host smart-369294c5-3047-4dff-bf91-3026cc5345e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672981881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.2672981881
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.777075621
Short name T300
Test name
Test status
Simulation time 4969909623 ps
CPU time 19.56 seconds
Started Aug 06 04:47:11 PM PDT 24
Finished Aug 06 04:47:31 PM PDT 24
Peak memory 241672 kb
Host smart-8869d9f6-6c8d-4914-a2c3-cdccfc2b74b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777075621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.777075621
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.3520275597
Short name T280
Test name
Test status
Simulation time 110676729719 ps
CPU time 182.8 seconds
Started Aug 06 04:47:15 PM PDT 24
Finished Aug 06 04:50:18 PM PDT 24
Peak memory 250132 kb
Host smart-c4b1c207-acff-494d-a9c6-263adb79ec79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520275597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmd
s.3520275597
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/44.spi_device_intercept.81177256
Short name T630
Test name
Test status
Simulation time 254741029 ps
CPU time 4.15 seconds
Started Aug 06 04:47:01 PM PDT 24
Finished Aug 06 04:47:05 PM PDT 24
Peak memory 229132 kb
Host smart-2a2b37a6-c92b-45ad-abe8-7f94e66c9129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81177256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.81177256
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.2599104362
Short name T319
Test name
Test status
Simulation time 319797492 ps
CPU time 5.51 seconds
Started Aug 06 04:47:03 PM PDT 24
Finished Aug 06 04:47:08 PM PDT 24
Peak memory 241160 kb
Host smart-ca643381-b9f8-4fac-9923-5cd9a8c61b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599104362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.2599104362
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.3305973342
Short name T337
Test name
Test status
Simulation time 624165365 ps
CPU time 4.22 seconds
Started Aug 06 04:46:57 PM PDT 24
Finished Aug 06 04:47:02 PM PDT 24
Peak memory 233420 kb
Host smart-fcc6fd1e-35d9-41be-a327-db79faba6dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305973342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.3305973342
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.1522183347
Short name T268
Test name
Test status
Simulation time 419692050 ps
CPU time 3.38 seconds
Started Aug 06 04:47:03 PM PDT 24
Finished Aug 06 04:47:06 PM PDT 24
Peak memory 225196 kb
Host smart-0359c156-cc3c-4d6d-ac32-2ef91d843d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522183347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.1522183347
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.4072262584
Short name T476
Test name
Test status
Simulation time 350205843 ps
CPU time 5.42 seconds
Started Aug 06 04:47:12 PM PDT 24
Finished Aug 06 04:47:18 PM PDT 24
Peak memory 222768 kb
Host smart-0ffabcfb-701d-432f-8178-3947faaf1a78
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4072262584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.4072262584
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.1642024683
Short name T3
Test name
Test status
Simulation time 9492830186 ps
CPU time 93.44 seconds
Started Aug 06 04:47:13 PM PDT 24
Finished Aug 06 04:48:47 PM PDT 24
Peak memory 249860 kb
Host smart-894d7944-315d-450c-a727-530ad60a635e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642024683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.1642024683
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.1840869932
Short name T823
Test name
Test status
Simulation time 44468194767 ps
CPU time 34.05 seconds
Started Aug 06 04:47:05 PM PDT 24
Finished Aug 06 04:47:39 PM PDT 24
Peak memory 216884 kb
Host smart-198ee7ae-969d-44d5-ae1b-74724344ad30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840869932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.1840869932
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.3396557568
Short name T787
Test name
Test status
Simulation time 2445427581 ps
CPU time 9.86 seconds
Started Aug 06 04:47:06 PM PDT 24
Finished Aug 06 04:47:16 PM PDT 24
Peak memory 216840 kb
Host smart-fe3845b2-9d79-4b3d-8aa9-bc6f5cc1b4ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396557568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.3396557568
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.3515042243
Short name T845
Test name
Test status
Simulation time 39866318 ps
CPU time 0.8 seconds
Started Aug 06 04:47:06 PM PDT 24
Finished Aug 06 04:47:07 PM PDT 24
Peak memory 206912 kb
Host smart-43dc687b-7ec7-4598-810f-2b2bd35d0b7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515042243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.3515042243
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.3805593390
Short name T853
Test name
Test status
Simulation time 162027209 ps
CPU time 0.89 seconds
Started Aug 06 04:47:02 PM PDT 24
Finished Aug 06 04:47:04 PM PDT 24
Peak memory 206540 kb
Host smart-202d8828-1f4e-475d-b2c1-26032d22cb42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805593390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.3805593390
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.1738461499
Short name T605
Test name
Test status
Simulation time 1310262632 ps
CPU time 8.21 seconds
Started Aug 06 04:46:55 PM PDT 24
Finished Aug 06 04:47:03 PM PDT 24
Peak memory 225120 kb
Host smart-f6882bd9-75e9-4af2-9c2a-d9c79633fae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738461499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.1738461499
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.2789921165
Short name T704
Test name
Test status
Simulation time 85931689 ps
CPU time 0.7 seconds
Started Aug 06 04:47:17 PM PDT 24
Finished Aug 06 04:47:18 PM PDT 24
Peak memory 205744 kb
Host smart-62769989-e99a-4863-b363-7a3021d568d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789921165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
2789921165
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.3324785752
Short name T74
Test name
Test status
Simulation time 625723460 ps
CPU time 4.24 seconds
Started Aug 06 04:47:15 PM PDT 24
Finished Aug 06 04:47:19 PM PDT 24
Peak memory 233420 kb
Host smart-6ca32284-caa7-4b5b-99fa-6cb4b8362e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324785752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.3324785752
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.3978609364
Short name T682
Test name
Test status
Simulation time 14676287 ps
CPU time 0.8 seconds
Started Aug 06 04:47:13 PM PDT 24
Finished Aug 06 04:47:14 PM PDT 24
Peak memory 207032 kb
Host smart-20489300-5072-4ddd-8981-86c79eceb5a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978609364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.3978609364
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.2040917173
Short name T297
Test name
Test status
Simulation time 8639816863 ps
CPU time 123.14 seconds
Started Aug 06 04:47:15 PM PDT 24
Finished Aug 06 04:49:19 PM PDT 24
Peak memory 265124 kb
Host smart-b5bc3fcd-e3a4-41c9-aa69-15b790dae904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040917173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.2040917173
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.3555180475
Short name T565
Test name
Test status
Simulation time 4492551885 ps
CPU time 71.96 seconds
Started Aug 06 04:47:17 PM PDT 24
Finished Aug 06 04:48:29 PM PDT 24
Peak memory 241652 kb
Host smart-7585c641-6851-4b2f-ad8c-971b8c5fec52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555180475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.3555180475
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.658366170
Short name T607
Test name
Test status
Simulation time 13689076138 ps
CPU time 48.88 seconds
Started Aug 06 04:47:16 PM PDT 24
Finished Aug 06 04:48:05 PM PDT 24
Peak memory 249888 kb
Host smart-87ebab01-3748-43b1-b256-5f7758fca4a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658366170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.658366170
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.192688858
Short name T377
Test name
Test status
Simulation time 3435046076 ps
CPU time 23.27 seconds
Started Aug 06 04:47:15 PM PDT 24
Finished Aug 06 04:47:38 PM PDT 24
Peak memory 236424 kb
Host smart-3096c817-0632-40a7-9b4c-18b1a131c6d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192688858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmds
.192688858
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_intercept.3176348183
Short name T156
Test name
Test status
Simulation time 9105090778 ps
CPU time 18.15 seconds
Started Aug 06 04:47:16 PM PDT 24
Finished Aug 06 04:47:34 PM PDT 24
Peak memory 225212 kb
Host smart-a91c3b75-227f-4f4b-aa2d-05df7a896340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176348183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.3176348183
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.3303157240
Short name T899
Test name
Test status
Simulation time 35918824122 ps
CPU time 71.13 seconds
Started Aug 06 04:47:11 PM PDT 24
Finished Aug 06 04:48:23 PM PDT 24
Peak memory 234868 kb
Host smart-e86a5d97-2021-4794-be5e-e89d466e2bdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303157240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.3303157240
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.2979757363
Short name T697
Test name
Test status
Simulation time 540232373 ps
CPU time 3.72 seconds
Started Aug 06 04:47:16 PM PDT 24
Finished Aug 06 04:47:20 PM PDT 24
Peak memory 225148 kb
Host smart-39c1a59c-e6fe-4823-a463-ef46e553b8cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979757363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.2979757363
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.916592307
Short name T594
Test name
Test status
Simulation time 180088089 ps
CPU time 4.8 seconds
Started Aug 06 04:47:15 PM PDT 24
Finished Aug 06 04:47:20 PM PDT 24
Peak memory 241408 kb
Host smart-0b6a55cb-d54c-4e94-ba6c-33f23224c4a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916592307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.916592307
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.4023077508
Short name T405
Test name
Test status
Simulation time 1720724265 ps
CPU time 6.49 seconds
Started Aug 06 04:47:26 PM PDT 24
Finished Aug 06 04:47:32 PM PDT 24
Peak memory 219748 kb
Host smart-ce57accb-c24e-49a3-9391-349e8db6c6a3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4023077508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.4023077508
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.3754852352
Short name T146
Test name
Test status
Simulation time 33362089113 ps
CPU time 267.06 seconds
Started Aug 06 04:47:26 PM PDT 24
Finished Aug 06 04:51:53 PM PDT 24
Peak memory 249748 kb
Host smart-b4fb3402-2cc8-4bd2-91e4-437b3570f22d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754852352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.3754852352
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.540114648
Short name T616
Test name
Test status
Simulation time 2211219509 ps
CPU time 6.11 seconds
Started Aug 06 04:47:10 PM PDT 24
Finished Aug 06 04:47:16 PM PDT 24
Peak memory 217284 kb
Host smart-488d9ed4-6c4d-467e-a49b-ac0a045f257b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540114648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.540114648
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.3866729774
Short name T831
Test name
Test status
Simulation time 30453626007 ps
CPU time 19.54 seconds
Started Aug 06 04:47:12 PM PDT 24
Finished Aug 06 04:47:32 PM PDT 24
Peak memory 216948 kb
Host smart-d6d1f478-52a3-4b33-b7a3-295f846b7979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866729774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.3866729774
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.1466961376
Short name T355
Test name
Test status
Simulation time 56569514 ps
CPU time 1.29 seconds
Started Aug 06 04:47:15 PM PDT 24
Finished Aug 06 04:47:16 PM PDT 24
Peak memory 216684 kb
Host smart-2cc70129-114b-4be1-8c94-32806fbff109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466961376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.1466961376
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.2969297
Short name T964
Test name
Test status
Simulation time 43770834 ps
CPU time 0.82 seconds
Started Aug 06 04:47:14 PM PDT 24
Finished Aug 06 04:47:15 PM PDT 24
Peak memory 206544 kb
Host smart-8bb0c48b-8295-4f2d-85e7-0e796e5e8547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.2969297
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.3132403714
Short name T944
Test name
Test status
Simulation time 3656979005 ps
CPU time 8.59 seconds
Started Aug 06 04:47:15 PM PDT 24
Finished Aug 06 04:47:24 PM PDT 24
Peak memory 225284 kb
Host smart-9bf22f41-2a03-481c-9210-2c1639da2672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132403714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.3132403714
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.1092871512
Short name T478
Test name
Test status
Simulation time 23912020 ps
CPU time 0.78 seconds
Started Aug 06 04:47:18 PM PDT 24
Finished Aug 06 04:47:19 PM PDT 24
Peak memory 205820 kb
Host smart-e832926c-a282-4a05-a5f2-b86852d22528
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092871512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
1092871512
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.989586960
Short name T790
Test name
Test status
Simulation time 92316926 ps
CPU time 2.46 seconds
Started Aug 06 04:47:23 PM PDT 24
Finished Aug 06 04:47:26 PM PDT 24
Peak memory 225184 kb
Host smart-4ab69e97-2fc6-4e4c-b089-274df305f2a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989586960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.989586960
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.1872601057
Short name T546
Test name
Test status
Simulation time 15295483 ps
CPU time 0.77 seconds
Started Aug 06 04:47:18 PM PDT 24
Finished Aug 06 04:47:19 PM PDT 24
Peak memory 206992 kb
Host smart-8527f0cf-4faf-4d24-a666-5764da6fc32e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872601057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.1872601057
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.1664977004
Short name T366
Test name
Test status
Simulation time 24876418 ps
CPU time 0.74 seconds
Started Aug 06 04:47:18 PM PDT 24
Finished Aug 06 04:47:19 PM PDT 24
Peak memory 216432 kb
Host smart-6dd3ada4-5611-4eb0-872a-f435493adf4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664977004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.1664977004
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.1099608962
Short name T346
Test name
Test status
Simulation time 4216982813 ps
CPU time 42.24 seconds
Started Aug 06 04:47:15 PM PDT 24
Finished Aug 06 04:47:57 PM PDT 24
Peak memory 249880 kb
Host smart-03056fd1-7d82-49e8-b54b-cf3c56583cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099608962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.1099608962
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.3121232451
Short name T732
Test name
Test status
Simulation time 2083952481 ps
CPU time 17.63 seconds
Started Aug 06 04:47:17 PM PDT 24
Finished Aug 06 04:47:35 PM PDT 24
Peak memory 225180 kb
Host smart-1339412b-7a75-461e-99ad-6ae7ebd133fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121232451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.3121232451
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.4154796051
Short name T680
Test name
Test status
Simulation time 57968858 ps
CPU time 0.74 seconds
Started Aug 06 04:47:16 PM PDT 24
Finished Aug 06 04:47:16 PM PDT 24
Peak memory 216392 kb
Host smart-43c24c25-ca6b-432b-8963-10db1501b075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154796051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmd
s.4154796051
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_intercept.1798665174
Short name T586
Test name
Test status
Simulation time 10109016081 ps
CPU time 19.27 seconds
Started Aug 06 04:47:23 PM PDT 24
Finished Aug 06 04:47:42 PM PDT 24
Peak memory 225224 kb
Host smart-12a4adb0-b2fc-49f5-a86c-3868763a3d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798665174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.1798665174
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.427415162
Short name T784
Test name
Test status
Simulation time 614007769 ps
CPU time 8.69 seconds
Started Aug 06 04:47:23 PM PDT 24
Finished Aug 06 04:47:32 PM PDT 24
Peak memory 233368 kb
Host smart-89ef09bb-0d54-4a77-90d5-cb2542647468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427415162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.427415162
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.2201968548
Short name T39
Test name
Test status
Simulation time 7589865966 ps
CPU time 19.44 seconds
Started Aug 06 04:47:18 PM PDT 24
Finished Aug 06 04:47:37 PM PDT 24
Peak memory 225092 kb
Host smart-afd4345a-9bfd-45bb-b131-88208bcccf92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201968548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.2201968548
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.4150275489
Short name T421
Test name
Test status
Simulation time 2563201573 ps
CPU time 7.89 seconds
Started Aug 06 04:47:18 PM PDT 24
Finished Aug 06 04:47:26 PM PDT 24
Peak memory 225176 kb
Host smart-f0882ff9-1048-4545-a595-61688076d0af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150275489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.4150275489
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.1860901480
Short name T424
Test name
Test status
Simulation time 696418938 ps
CPU time 3.8 seconds
Started Aug 06 04:47:23 PM PDT 24
Finished Aug 06 04:47:27 PM PDT 24
Peak memory 219384 kb
Host smart-04c890c8-ae63-4bbe-b0e6-c127a6f80bd9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1860901480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.1860901480
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.4057079507
Short name T1010
Test name
Test status
Simulation time 76344307569 ps
CPU time 710.02 seconds
Started Aug 06 04:47:16 PM PDT 24
Finished Aug 06 04:59:06 PM PDT 24
Peak memory 266564 kb
Host smart-271b7725-3fee-4435-ac3e-c65ff8fc6eab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057079507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.4057079507
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.3409565067
Short name T795
Test name
Test status
Simulation time 11023551970 ps
CPU time 16.67 seconds
Started Aug 06 04:47:23 PM PDT 24
Finished Aug 06 04:47:40 PM PDT 24
Peak memory 220660 kb
Host smart-b5ab4bcd-c85b-4e2e-89b4-acc244178f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409565067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.3409565067
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.1723246115
Short name T24
Test name
Test status
Simulation time 1924709517 ps
CPU time 6.45 seconds
Started Aug 06 04:47:18 PM PDT 24
Finished Aug 06 04:47:25 PM PDT 24
Peak memory 216852 kb
Host smart-d2e871ae-bff8-4a49-92cf-439da26f242f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723246115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.1723246115
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.4080353789
Short name T756
Test name
Test status
Simulation time 362462114 ps
CPU time 2.09 seconds
Started Aug 06 04:47:18 PM PDT 24
Finished Aug 06 04:47:20 PM PDT 24
Peak memory 216900 kb
Host smart-7b4a2f5e-88f4-4d57-9ed5-4c8c0edd9a79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080353789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.4080353789
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.684231263
Short name T560
Test name
Test status
Simulation time 43703785 ps
CPU time 0.69 seconds
Started Aug 06 04:47:23 PM PDT 24
Finished Aug 06 04:47:24 PM PDT 24
Peak memory 206528 kb
Host smart-8e43e704-53fa-4307-9389-a1d7847fe49b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684231263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.684231263
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.1915735070
Short name T158
Test name
Test status
Simulation time 42647169166 ps
CPU time 17.28 seconds
Started Aug 06 04:47:20 PM PDT 24
Finished Aug 06 04:47:38 PM PDT 24
Peak memory 225220 kb
Host smart-d8a4f35f-47de-4890-b432-3797f9a9a0f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915735070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.1915735070
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.2333634716
Short name T368
Test name
Test status
Simulation time 17040414 ps
CPU time 0.73 seconds
Started Aug 06 04:47:14 PM PDT 24
Finished Aug 06 04:47:15 PM PDT 24
Peak memory 205152 kb
Host smart-0623f725-f937-4d45-8bdf-0d67399aba71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333634716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
2333634716
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.239910617
Short name T277
Test name
Test status
Simulation time 3536040943 ps
CPU time 9.38 seconds
Started Aug 06 04:47:14 PM PDT 24
Finished Aug 06 04:47:24 PM PDT 24
Peak memory 225252 kb
Host smart-4f66d87d-3c78-4646-8133-903a1bd74e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239910617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.239910617
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.1719343593
Short name T719
Test name
Test status
Simulation time 44761291 ps
CPU time 0.76 seconds
Started Aug 06 04:47:19 PM PDT 24
Finished Aug 06 04:47:19 PM PDT 24
Peak memory 206228 kb
Host smart-72cdbd9d-d5f5-4738-99f2-1ecdb3fd1f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719343593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.1719343593
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.3748329883
Short name T475
Test name
Test status
Simulation time 12287734655 ps
CPU time 87.54 seconds
Started Aug 06 04:47:12 PM PDT 24
Finished Aug 06 04:48:39 PM PDT 24
Peak memory 252628 kb
Host smart-3807c2e0-0bd0-45ce-bc15-31eb596e8f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748329883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.3748329883
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.1885481030
Short name T643
Test name
Test status
Simulation time 20966004464 ps
CPU time 115.55 seconds
Started Aug 06 04:47:16 PM PDT 24
Finished Aug 06 04:49:11 PM PDT 24
Peak memory 246624 kb
Host smart-4fab78a7-447b-4d6a-9dbb-cf9c2c38ba74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885481030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.1885481030
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.121335256
Short name T947
Test name
Test status
Simulation time 8812518847 ps
CPU time 52.57 seconds
Started Aug 06 04:47:11 PM PDT 24
Finished Aug 06 04:48:04 PM PDT 24
Peak memory 241640 kb
Host smart-9d1ccf07-f91a-435a-8180-fa572c7d6cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121335256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.121335256
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.170215344
Short name T175
Test name
Test status
Simulation time 128733961508 ps
CPU time 282.53 seconds
Started Aug 06 04:47:13 PM PDT 24
Finished Aug 06 04:51:56 PM PDT 24
Peak memory 249828 kb
Host smart-d6ab9765-ef59-47b5-ad4f-91364f15585d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170215344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmds
.170215344
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/47.spi_device_intercept.1360017239
Short name T233
Test name
Test status
Simulation time 428868581 ps
CPU time 5.98 seconds
Started Aug 06 04:47:11 PM PDT 24
Finished Aug 06 04:47:17 PM PDT 24
Peak memory 233424 kb
Host smart-c2557cc4-0edd-4256-90a3-92c00a5da46c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360017239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.1360017239
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.4093766873
Short name T334
Test name
Test status
Simulation time 159193914 ps
CPU time 2.47 seconds
Started Aug 06 04:47:14 PM PDT 24
Finished Aug 06 04:47:16 PM PDT 24
Peak memory 232992 kb
Host smart-1af1bd36-d2b2-4eca-94c2-7a1c5ef024e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093766873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.4093766873
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.3002754616
Short name T961
Test name
Test status
Simulation time 138937960 ps
CPU time 2.15 seconds
Started Aug 06 04:47:11 PM PDT 24
Finished Aug 06 04:47:13 PM PDT 24
Peak memory 224268 kb
Host smart-0cd6a30d-2588-4032-aba2-fca27fa0c428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002754616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.3002754616
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.4007381894
Short name T554
Test name
Test status
Simulation time 1287257129 ps
CPU time 8.68 seconds
Started Aug 06 04:47:12 PM PDT 24
Finished Aug 06 04:47:21 PM PDT 24
Peak memory 233308 kb
Host smart-d78822c9-0dab-46b2-9086-2ff54264a06c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007381894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.4007381894
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.2110750336
Short name T332
Test name
Test status
Simulation time 2024301441 ps
CPU time 6.55 seconds
Started Aug 06 04:47:16 PM PDT 24
Finished Aug 06 04:47:23 PM PDT 24
Peak memory 219948 kb
Host smart-baf202c7-9f85-42f1-8b39-8bd65368211d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2110750336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.2110750336
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.3690181754
Short name T954
Test name
Test status
Simulation time 7061571320 ps
CPU time 86.32 seconds
Started Aug 06 04:47:16 PM PDT 24
Finished Aug 06 04:48:43 PM PDT 24
Peak memory 272916 kb
Host smart-f9b281f7-2f29-40b2-910f-e7571c4d661a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690181754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.3690181754
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.1299759655
Short name T779
Test name
Test status
Simulation time 5950006666 ps
CPU time 17.57 seconds
Started Aug 06 04:47:18 PM PDT 24
Finished Aug 06 04:47:36 PM PDT 24
Peak memory 220776 kb
Host smart-ef2cde50-f3a3-4201-8c36-4eee2de7b9be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299759655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.1299759655
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.2428055645
Short name T636
Test name
Test status
Simulation time 2641744394 ps
CPU time 3.48 seconds
Started Aug 06 04:47:11 PM PDT 24
Finished Aug 06 04:47:15 PM PDT 24
Peak memory 217024 kb
Host smart-3caaa704-b96f-4dbf-acc5-831cf85d9a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428055645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.2428055645
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.736001310
Short name T953
Test name
Test status
Simulation time 426973920 ps
CPU time 4.06 seconds
Started Aug 06 04:47:14 PM PDT 24
Finished Aug 06 04:47:18 PM PDT 24
Peak memory 216956 kb
Host smart-aa496249-0daa-4c7d-b25f-c5b3689134f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736001310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.736001310
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.3936563923
Short name T805
Test name
Test status
Simulation time 26964769 ps
CPU time 0.77 seconds
Started Aug 06 04:47:18 PM PDT 24
Finished Aug 06 04:47:19 PM PDT 24
Peak memory 206536 kb
Host smart-91ebd790-2668-4cff-8ce1-0a8a245af30d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936563923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.3936563923
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.1826703129
Short name T120
Test name
Test status
Simulation time 4435334725 ps
CPU time 5.24 seconds
Started Aug 06 04:47:10 PM PDT 24
Finished Aug 06 04:47:16 PM PDT 24
Peak memory 225152 kb
Host smart-8d102796-664b-405b-8175-8e104e289b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826703129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.1826703129
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.1036252349
Short name T935
Test name
Test status
Simulation time 19165748 ps
CPU time 0.72 seconds
Started Aug 06 04:47:29 PM PDT 24
Finished Aug 06 04:47:29 PM PDT 24
Peak memory 205272 kb
Host smart-3b3229c4-9e58-4501-8350-27fb4baad4aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036252349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
1036252349
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.228081201
Short name T538
Test name
Test status
Simulation time 777176905 ps
CPU time 7.66 seconds
Started Aug 06 04:47:26 PM PDT 24
Finished Aug 06 04:47:34 PM PDT 24
Peak memory 233240 kb
Host smart-eec29ccb-aaee-4461-948a-c4b8a1dbd534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228081201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.228081201
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.1878085385
Short name T340
Test name
Test status
Simulation time 46928604 ps
CPU time 0.74 seconds
Started Aug 06 04:47:14 PM PDT 24
Finished Aug 06 04:47:14 PM PDT 24
Peak memory 206928 kb
Host smart-34f9ddab-f264-4314-9fa3-97ab39c48829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878085385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.1878085385
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.4011198505
Short name T205
Test name
Test status
Simulation time 6622662332 ps
CPU time 34.84 seconds
Started Aug 06 04:47:22 PM PDT 24
Finished Aug 06 04:47:57 PM PDT 24
Peak memory 241616 kb
Host smart-31ae3a1c-7b98-4e87-a090-76b516e29926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011198505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.4011198505
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.578393125
Short name T240
Test name
Test status
Simulation time 5008727252 ps
CPU time 50.13 seconds
Started Aug 06 04:47:18 PM PDT 24
Finished Aug 06 04:48:08 PM PDT 24
Peak memory 241632 kb
Host smart-3a8a92de-88dd-4671-a74d-6ae725a148b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578393125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.578393125
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.3067917085
Short name T399
Test name
Test status
Simulation time 3970476336 ps
CPU time 66.19 seconds
Started Aug 06 04:47:17 PM PDT 24
Finished Aug 06 04:48:24 PM PDT 24
Peak memory 256064 kb
Host smart-63657425-ecd2-4a9e-8735-fed45d5422b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067917085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.3067917085
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.3455518186
Short name T308
Test name
Test status
Simulation time 2424458724 ps
CPU time 26.08 seconds
Started Aug 06 04:47:26 PM PDT 24
Finished Aug 06 04:47:52 PM PDT 24
Peak memory 233284 kb
Host smart-eac757f4-2e22-4cff-b00c-94794d42c6e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455518186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.3455518186
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.1159722066
Short name T407
Test name
Test status
Simulation time 9348580549 ps
CPU time 63.63 seconds
Started Aug 06 04:47:15 PM PDT 24
Finished Aug 06 04:48:19 PM PDT 24
Peak memory 241560 kb
Host smart-7da3e503-19e7-4fd9-a65c-b838268f3f21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159722066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmd
s.1159722066
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/48.spi_device_intercept.4207808662
Short name T865
Test name
Test status
Simulation time 29330432 ps
CPU time 2.46 seconds
Started Aug 06 04:47:16 PM PDT 24
Finished Aug 06 04:47:19 PM PDT 24
Peak memory 232948 kb
Host smart-162d4d69-27bc-4491-b7a3-f7a5f5b27698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207808662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.4207808662
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.591195367
Short name T725
Test name
Test status
Simulation time 352524935 ps
CPU time 11.48 seconds
Started Aug 06 04:47:15 PM PDT 24
Finished Aug 06 04:47:26 PM PDT 24
Peak memory 234400 kb
Host smart-1ea36579-6fba-478c-8cb3-eaa9ea33edfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591195367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.591195367
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.1782633938
Short name T324
Test name
Test status
Simulation time 370587724 ps
CPU time 2.27 seconds
Started Aug 06 04:47:26 PM PDT 24
Finished Aug 06 04:47:28 PM PDT 24
Peak memory 224260 kb
Host smart-e2479a31-524f-4ed0-b59b-ed6c0d751c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782633938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.1782633938
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.568904423
Short name T759
Test name
Test status
Simulation time 24608591789 ps
CPU time 16.1 seconds
Started Aug 06 04:47:14 PM PDT 24
Finished Aug 06 04:47:30 PM PDT 24
Peak memory 236476 kb
Host smart-326e6110-d8d3-4af1-a2fa-aa2c468232b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568904423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.568904423
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.1540098078
Short name T730
Test name
Test status
Simulation time 1296607296 ps
CPU time 8.05 seconds
Started Aug 06 04:47:14 PM PDT 24
Finished Aug 06 04:47:22 PM PDT 24
Peak memory 223176 kb
Host smart-9aacc932-9057-43e8-8d75-96445f43004c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1540098078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.1540098078
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.3534969586
Short name T145
Test name
Test status
Simulation time 69086146179 ps
CPU time 165.53 seconds
Started Aug 06 04:47:18 PM PDT 24
Finished Aug 06 04:50:04 PM PDT 24
Peak memory 249980 kb
Host smart-a52b202e-f803-46f4-9bcf-3153aec7892b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534969586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.3534969586
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.3633762196
Short name T555
Test name
Test status
Simulation time 12804894737 ps
CPU time 20.67 seconds
Started Aug 06 04:47:15 PM PDT 24
Finished Aug 06 04:47:35 PM PDT 24
Peak memory 217148 kb
Host smart-c2794da1-f56b-4991-911c-2847dc28bcb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633762196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.3633762196
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.3091894344
Short name T397
Test name
Test status
Simulation time 1200489915 ps
CPU time 2.68 seconds
Started Aug 06 04:47:14 PM PDT 24
Finished Aug 06 04:47:17 PM PDT 24
Peak memory 216796 kb
Host smart-3f98cbff-dde8-46db-bb7e-756ae78106f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091894344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.3091894344
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.3123101547
Short name T913
Test name
Test status
Simulation time 801423839 ps
CPU time 1.91 seconds
Started Aug 06 04:47:26 PM PDT 24
Finished Aug 06 04:47:28 PM PDT 24
Peak memory 216816 kb
Host smart-1bb5c81b-58a4-40c7-a843-89c3c0914a5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123101547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.3123101547
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.589331215
Short name T1033
Test name
Test status
Simulation time 41541213 ps
CPU time 0.78 seconds
Started Aug 06 04:47:16 PM PDT 24
Finished Aug 06 04:47:17 PM PDT 24
Peak memory 206552 kb
Host smart-2632332c-5b31-4d77-b3a3-b9a7ddbc16ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589331215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.589331215
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.344483588
Short name T590
Test name
Test status
Simulation time 1098167151 ps
CPU time 9.14 seconds
Started Aug 06 04:47:18 PM PDT 24
Finished Aug 06 04:47:27 PM PDT 24
Peak memory 238108 kb
Host smart-0394d7cf-5c61-48af-b648-bb6a787199f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344483588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.344483588
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.2004425327
Short name T878
Test name
Test status
Simulation time 29174035 ps
CPU time 0.71 seconds
Started Aug 06 04:47:28 PM PDT 24
Finished Aug 06 04:47:29 PM PDT 24
Peak memory 205256 kb
Host smart-4a7c68b2-4581-42fe-8236-73639e7a0a4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004425327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
2004425327
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.643183325
Short name T764
Test name
Test status
Simulation time 72763423 ps
CPU time 2.41 seconds
Started Aug 06 04:47:29 PM PDT 24
Finished Aug 06 04:47:31 PM PDT 24
Peak memory 225192 kb
Host smart-e5e193f6-460c-4d84-b9c8-1a96d0ca1016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643183325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.643183325
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.600379653
Short name T431
Test name
Test status
Simulation time 47348938 ps
CPU time 0.73 seconds
Started Aug 06 04:47:27 PM PDT 24
Finished Aug 06 04:47:27 PM PDT 24
Peak memory 205948 kb
Host smart-0c69d0e6-e4e5-4fd7-8ee1-05029e706cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600379653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.600379653
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.3566953943
Short name T775
Test name
Test status
Simulation time 12086394 ps
CPU time 0.75 seconds
Started Aug 06 04:47:28 PM PDT 24
Finished Aug 06 04:47:28 PM PDT 24
Peak memory 216404 kb
Host smart-c869626d-21ce-4302-bed1-f3f7b7b536b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566953943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.3566953943
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.3662244822
Short name T394
Test name
Test status
Simulation time 40453017164 ps
CPU time 86.72 seconds
Started Aug 06 04:47:26 PM PDT 24
Finished Aug 06 04:48:52 PM PDT 24
Peak memory 256820 kb
Host smart-5c8dd76b-f698-4d81-a5ee-302fb4da7e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662244822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.3662244822
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.3200889653
Short name T859
Test name
Test status
Simulation time 545578802 ps
CPU time 3.72 seconds
Started Aug 06 04:47:27 PM PDT 24
Finished Aug 06 04:47:31 PM PDT 24
Peak memory 231768 kb
Host smart-072d9de2-d5d9-4aca-b088-e51cb51682ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200889653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.3200889653
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.2705629528
Short name T40
Test name
Test status
Simulation time 252763918693 ps
CPU time 435.8 seconds
Started Aug 06 04:47:29 PM PDT 24
Finished Aug 06 04:54:45 PM PDT 24
Peak memory 251696 kb
Host smart-c230eb3d-ef62-4b82-a0ad-aaa90d51a6e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705629528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmd
s.2705629528
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/49.spi_device_intercept.3844890160
Short name T344
Test name
Test status
Simulation time 4068745880 ps
CPU time 16.04 seconds
Started Aug 06 04:47:31 PM PDT 24
Finished Aug 06 04:47:47 PM PDT 24
Peak memory 220484 kb
Host smart-fa174928-b4ab-4941-b637-04f807b39e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844890160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.3844890160
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.94201739
Short name T631
Test name
Test status
Simulation time 7226618514 ps
CPU time 43.76 seconds
Started Aug 06 04:47:29 PM PDT 24
Finished Aug 06 04:48:13 PM PDT 24
Peak memory 249772 kb
Host smart-fafb9393-08c5-45bf-bfb2-875bb5ae776b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94201739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.94201739
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.2484793460
Short name T254
Test name
Test status
Simulation time 12098562439 ps
CPU time 16.58 seconds
Started Aug 06 04:47:27 PM PDT 24
Finished Aug 06 04:47:44 PM PDT 24
Peak memory 233452 kb
Host smart-3d205a44-1bda-427f-8d49-28b472b33f4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484793460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.2484793460
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.3788434914
Short name T815
Test name
Test status
Simulation time 57988885 ps
CPU time 2.11 seconds
Started Aug 06 04:47:28 PM PDT 24
Finished Aug 06 04:47:30 PM PDT 24
Peak memory 224656 kb
Host smart-3263fea3-ff6b-4bc5-8638-95dcd9e6676f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788434914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.3788434914
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.2519554803
Short name T408
Test name
Test status
Simulation time 676303082 ps
CPU time 5.91 seconds
Started Aug 06 04:47:28 PM PDT 24
Finished Aug 06 04:47:34 PM PDT 24
Peak memory 223068 kb
Host smart-54ffe624-2d0b-4a6c-84ba-80dba95498f6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2519554803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.2519554803
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.1281786070
Short name T601
Test name
Test status
Simulation time 55472009 ps
CPU time 0.73 seconds
Started Aug 06 04:47:27 PM PDT 24
Finished Aug 06 04:47:28 PM PDT 24
Peak memory 206160 kb
Host smart-65fe9680-0f84-4768-9037-fcbd9cb45946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281786070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.1281786070
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.3543333064
Short name T67
Test name
Test status
Simulation time 12849247359 ps
CPU time 17.38 seconds
Started Aug 06 04:47:28 PM PDT 24
Finished Aug 06 04:47:45 PM PDT 24
Peak memory 217028 kb
Host smart-d0471bd5-69ba-4810-ae54-b66154b77af7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543333064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.3543333064
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.2407911501
Short name T828
Test name
Test status
Simulation time 37370155 ps
CPU time 2.05 seconds
Started Aug 06 04:47:30 PM PDT 24
Finished Aug 06 04:47:32 PM PDT 24
Peak memory 216968 kb
Host smart-1cf25d01-ebdd-47e5-8f01-e6ef4908c65b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407911501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.2407911501
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.1204519879
Short name T571
Test name
Test status
Simulation time 69705865 ps
CPU time 0.78 seconds
Started Aug 06 04:47:29 PM PDT 24
Finished Aug 06 04:47:30 PM PDT 24
Peak memory 206476 kb
Host smart-327396c7-b65b-4193-b759-71d3144c69ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204519879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.1204519879
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.4070637960
Short name T640
Test name
Test status
Simulation time 5270651174 ps
CPU time 8.77 seconds
Started Aug 06 04:47:34 PM PDT 24
Finished Aug 06 04:47:43 PM PDT 24
Peak memory 236852 kb
Host smart-7caebc84-c8c7-442c-8fc0-b916af752b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070637960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.4070637960
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.2700413972
Short name T614
Test name
Test status
Simulation time 45906233 ps
CPU time 0.71 seconds
Started Aug 06 04:44:53 PM PDT 24
Finished Aug 06 04:44:54 PM PDT 24
Peak memory 205256 kb
Host smart-edeea91e-68d1-4016-89b8-86185715a943
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700413972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.2
700413972
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.3039831702
Short name T581
Test name
Test status
Simulation time 117127827 ps
CPU time 2.48 seconds
Started Aug 06 04:44:42 PM PDT 24
Finished Aug 06 04:44:44 PM PDT 24
Peak memory 233012 kb
Host smart-03f10601-fd38-46f9-83e9-5878fc67fa8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039831702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.3039831702
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.791675724
Short name T981
Test name
Test status
Simulation time 21853932 ps
CPU time 0.74 seconds
Started Aug 06 04:44:41 PM PDT 24
Finished Aug 06 04:44:41 PM PDT 24
Peak memory 205912 kb
Host smart-659ed125-ce6c-48cc-859f-3c7f4c660ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791675724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.791675724
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.256896120
Short name T295
Test name
Test status
Simulation time 25794906119 ps
CPU time 185.06 seconds
Started Aug 06 04:44:32 PM PDT 24
Finished Aug 06 04:47:38 PM PDT 24
Peak memory 252328 kb
Host smart-58fc8ef4-85d6-43e9-a3a1-0dd96d85f170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256896120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.256896120
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.1497589413
Short name T36
Test name
Test status
Simulation time 48317669778 ps
CPU time 196.93 seconds
Started Aug 06 04:44:29 PM PDT 24
Finished Aug 06 04:47:46 PM PDT 24
Peak memory 249840 kb
Host smart-2d5a1c59-b602-497e-9ff7-610d05e851cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497589413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.1497589413
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.3073061453
Short name T1003
Test name
Test status
Simulation time 27474400633 ps
CPU time 81.05 seconds
Started Aug 06 04:44:55 PM PDT 24
Finished Aug 06 04:46:17 PM PDT 24
Peak memory 249984 kb
Host smart-1b004283-8a35-43f4-91bc-f3b1b38f140d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073061453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.3073061453
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.1621011921
Short name T735
Test name
Test status
Simulation time 344125924 ps
CPU time 6.95 seconds
Started Aug 06 04:44:39 PM PDT 24
Finished Aug 06 04:44:46 PM PDT 24
Peak memory 233468 kb
Host smart-83a16fd5-e077-47ba-b1d5-75f03cfdf184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621011921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.1621011921
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.2703985942
Short name T976
Test name
Test status
Simulation time 13337574877 ps
CPU time 112.13 seconds
Started Aug 06 04:44:27 PM PDT 24
Finished Aug 06 04:46:19 PM PDT 24
Peak memory 241268 kb
Host smart-eb0c4dae-a5fd-433d-a7cc-843d86265655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703985942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds
.2703985942
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/5.spi_device_intercept.4037715436
Short name T1007
Test name
Test status
Simulation time 7431987440 ps
CPU time 21.37 seconds
Started Aug 06 04:44:29 PM PDT 24
Finished Aug 06 04:44:51 PM PDT 24
Peak memory 225276 kb
Host smart-9d44a4c0-7fe4-4314-a684-a3216c6dcc03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037715436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.4037715436
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.1220180428
Short name T1016
Test name
Test status
Simulation time 5777886723 ps
CPU time 59.81 seconds
Started Aug 06 04:44:31 PM PDT 24
Finished Aug 06 04:45:31 PM PDT 24
Peak memory 249748 kb
Host smart-7548a8b0-7c93-4cb8-8f6f-cae095c6e125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220180428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.1220180428
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.1415596384
Short name T502
Test name
Test status
Simulation time 30760769 ps
CPU time 1.03 seconds
Started Aug 06 04:44:38 PM PDT 24
Finished Aug 06 04:44:39 PM PDT 24
Peak memory 217072 kb
Host smart-eb214ec5-18cc-4668-898c-189c54de3f17
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415596384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.spi_device_mem_parity.1415596384
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.2366818359
Short name T270
Test name
Test status
Simulation time 5654245182 ps
CPU time 9.32 seconds
Started Aug 06 04:44:41 PM PDT 24
Finished Aug 06 04:44:50 PM PDT 24
Peak memory 241572 kb
Host smart-88460e2d-aaf3-4433-bc7c-6367cde877e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366818359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.2366818359
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.3159439976
Short name T239
Test name
Test status
Simulation time 4285470869 ps
CPU time 15.21 seconds
Started Aug 06 04:44:36 PM PDT 24
Finished Aug 06 04:44:52 PM PDT 24
Peak memory 233384 kb
Host smart-e2542ae3-54da-4874-bd07-1f8d35d62cf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159439976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.3159439976
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.3996784973
Short name T566
Test name
Test status
Simulation time 413499958 ps
CPU time 3.51 seconds
Started Aug 06 04:44:31 PM PDT 24
Finished Aug 06 04:44:35 PM PDT 24
Peak memory 223800 kb
Host smart-c80aeafe-fb22-4a93-a660-e4f318f15208
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3996784973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.3996784973
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.253537216
Short name T147
Test name
Test status
Simulation time 168692109205 ps
CPU time 612.84 seconds
Started Aug 06 04:44:50 PM PDT 24
Finished Aug 06 04:55:03 PM PDT 24
Peak memory 274528 kb
Host smart-12793be4-7649-4682-ad0a-3c7605c063d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253537216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stress
_all.253537216
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.2573272797
Short name T309
Test name
Test status
Simulation time 14590149535 ps
CPU time 36.72 seconds
Started Aug 06 04:44:32 PM PDT 24
Finished Aug 06 04:45:08 PM PDT 24
Peak memory 216876 kb
Host smart-40cb1442-486f-4c61-a929-b58eed2f53ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573272797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.2573272797
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.724818441
Short name T656
Test name
Test status
Simulation time 6977964153 ps
CPU time 17.4 seconds
Started Aug 06 04:44:31 PM PDT 24
Finished Aug 06 04:44:49 PM PDT 24
Peak memory 216912 kb
Host smart-0aa3fc7f-32f4-46d4-97c0-cd223d466298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724818441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.724818441
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.2674427070
Short name T733
Test name
Test status
Simulation time 79041664 ps
CPU time 0.98 seconds
Started Aug 06 04:44:30 PM PDT 24
Finished Aug 06 04:44:31 PM PDT 24
Peak memory 207484 kb
Host smart-af61cf3f-d2e4-4edc-b911-050b9fd7c57b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674427070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.2674427070
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.2962322945
Short name T1030
Test name
Test status
Simulation time 93568469 ps
CPU time 0.77 seconds
Started Aug 06 04:44:32 PM PDT 24
Finished Aug 06 04:44:33 PM PDT 24
Peak memory 206376 kb
Host smart-3f0e51d8-ede8-41cb-bf4b-05810582b91a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962322945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.2962322945
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.2180978356
Short name T23
Test name
Test status
Simulation time 114186263 ps
CPU time 2.34 seconds
Started Aug 06 04:44:44 PM PDT 24
Finished Aug 06 04:44:47 PM PDT 24
Peak memory 223600 kb
Host smart-f1dc77c3-d5ef-4ae7-800c-b00d056acf49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180978356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.2180978356
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.1057504041
Short name T385
Test name
Test status
Simulation time 45245066 ps
CPU time 0.74 seconds
Started Aug 06 04:44:50 PM PDT 24
Finished Aug 06 04:44:50 PM PDT 24
Peak memory 205676 kb
Host smart-4f747dcf-6bce-4f2a-a8fc-7136079edc01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057504041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.1
057504041
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.581860843
Short name T247
Test name
Test status
Simulation time 359629361 ps
CPU time 6.25 seconds
Started Aug 06 04:44:50 PM PDT 24
Finished Aug 06 04:44:56 PM PDT 24
Peak memory 233348 kb
Host smart-0d41f9e9-d57a-46a7-84bd-0dbb9960a67a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581860843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.581860843
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.3087192536
Short name T317
Test name
Test status
Simulation time 35399236 ps
CPU time 0.74 seconds
Started Aug 06 04:44:50 PM PDT 24
Finished Aug 06 04:44:51 PM PDT 24
Peak memory 205980 kb
Host smart-8679ebf0-f35c-494e-a95c-0e3d8822054b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087192536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.3087192536
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.2032129540
Short name T181
Test name
Test status
Simulation time 36349829423 ps
CPU time 189.64 seconds
Started Aug 06 04:44:48 PM PDT 24
Finished Aug 06 04:47:58 PM PDT 24
Peak memory 266232 kb
Host smart-f1d1d178-632c-47f4-8594-ce1ff56023a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032129540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.2032129540
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.3493868524
Short name T203
Test name
Test status
Simulation time 3776826814 ps
CPU time 31.93 seconds
Started Aug 06 04:44:47 PM PDT 24
Finished Aug 06 04:45:19 PM PDT 24
Peak memory 225320 kb
Host smart-16670107-2c75-4319-89c2-3b6abcc9825e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493868524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.3493868524
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.594122493
Short name T124
Test name
Test status
Simulation time 92812337253 ps
CPU time 225.76 seconds
Started Aug 06 04:44:49 PM PDT 24
Finished Aug 06 04:48:35 PM PDT 24
Peak memory 250552 kb
Host smart-55af1fb3-6716-42b9-bfa4-c0d8004dc51b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594122493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle.
594122493
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.1523158224
Short name T584
Test name
Test status
Simulation time 1188081270 ps
CPU time 14.64 seconds
Started Aug 06 04:44:48 PM PDT 24
Finished Aug 06 04:45:03 PM PDT 24
Peak memory 233288 kb
Host smart-c5cf83ab-0f62-4546-a8b3-23ef65ffb452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523158224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.1523158224
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_intercept.3818204845
Short name T185
Test name
Test status
Simulation time 4496047709 ps
CPU time 8.22 seconds
Started Aug 06 04:44:53 PM PDT 24
Finished Aug 06 04:45:01 PM PDT 24
Peak memory 233448 kb
Host smart-2a5d1109-11f5-4c13-9b76-9639c57c7ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818204845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.3818204845
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.2362276538
Short name T882
Test name
Test status
Simulation time 5815161428 ps
CPU time 78.92 seconds
Started Aug 06 04:44:49 PM PDT 24
Finished Aug 06 04:46:08 PM PDT 24
Peak memory 234088 kb
Host smart-baa93099-db40-4251-8c90-276717d60b38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362276538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.2362276538
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.1940905067
Short name T835
Test name
Test status
Simulation time 96761853 ps
CPU time 1.1 seconds
Started Aug 06 04:45:05 PM PDT 24
Finished Aug 06 04:45:06 PM PDT 24
Peak memory 217188 kb
Host smart-326e4cfb-76ab-49a6-9d26-99e80f53012c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940905067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.spi_device_mem_parity.1940905067
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.2993175439
Short name T604
Test name
Test status
Simulation time 301296396 ps
CPU time 2.43 seconds
Started Aug 06 04:44:54 PM PDT 24
Finished Aug 06 04:44:57 PM PDT 24
Peak memory 225128 kb
Host smart-242f5105-2363-4a65-8f49-f23d8a3c277e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993175439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.2993175439
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.1132753579
Short name T248
Test name
Test status
Simulation time 416555092 ps
CPU time 3.79 seconds
Started Aug 06 04:44:50 PM PDT 24
Finished Aug 06 04:44:54 PM PDT 24
Peak memory 225160 kb
Host smart-20cbd1d8-927f-4a64-b569-d94ae5def7da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132753579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.1132753579
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.524575401
Short name T7
Test name
Test status
Simulation time 688982942 ps
CPU time 7.95 seconds
Started Aug 06 04:44:55 PM PDT 24
Finished Aug 06 04:45:03 PM PDT 24
Peak memory 223480 kb
Host smart-7a5c752d-516f-46e2-ae11-f110dbbcf9f2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=524575401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_direc
t.524575401
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.388054294
Short name T143
Test name
Test status
Simulation time 425650840170 ps
CPU time 468.53 seconds
Started Aug 06 04:44:57 PM PDT 24
Finished Aug 06 04:52:45 PM PDT 24
Peak memory 268680 kb
Host smart-4bdc5187-7a11-4b43-ba1a-d4bc0a8af024
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388054294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stress
_all.388054294
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.2532395555
Short name T612
Test name
Test status
Simulation time 3294868873 ps
CPU time 22.63 seconds
Started Aug 06 04:44:50 PM PDT 24
Finished Aug 06 04:45:12 PM PDT 24
Peak memory 220556 kb
Host smart-9a3d3060-ea0f-4356-bdf1-ba3a197a07dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532395555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.2532395555
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.1095625520
Short name T927
Test name
Test status
Simulation time 4198318652 ps
CPU time 14.64 seconds
Started Aug 06 04:44:50 PM PDT 24
Finished Aug 06 04:45:05 PM PDT 24
Peak memory 217036 kb
Host smart-0c868459-dc9d-4295-bd50-90ee8b455765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095625520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.1095625520
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.679361521
Short name T390
Test name
Test status
Simulation time 14822218 ps
CPU time 0.96 seconds
Started Aug 06 04:44:48 PM PDT 24
Finished Aug 06 04:44:50 PM PDT 24
Peak memory 208452 kb
Host smart-979f43fd-616e-4215-9abb-6e236d0628b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679361521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.679361521
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.2107428610
Short name T1026
Test name
Test status
Simulation time 26221012 ps
CPU time 0.71 seconds
Started Aug 06 04:44:52 PM PDT 24
Finished Aug 06 04:44:53 PM PDT 24
Peak memory 206528 kb
Host smart-b2ee251f-135c-4845-bb5c-9e06267ada58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107428610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.2107428610
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.2969774737
Short name T508
Test name
Test status
Simulation time 12749133299 ps
CPU time 25.58 seconds
Started Aug 06 04:44:49 PM PDT 24
Finished Aug 06 04:45:14 PM PDT 24
Peak memory 249612 kb
Host smart-642f5da6-78db-4204-990a-e4f543f6485b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969774737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.2969774737
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.3363370508
Short name T479
Test name
Test status
Simulation time 20269441 ps
CPU time 0.73 seconds
Started Aug 06 04:44:59 PM PDT 24
Finished Aug 06 04:44:59 PM PDT 24
Peak memory 205648 kb
Host smart-8b585c43-a087-4320-86c1-fdbc4ee068dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363370508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.3
363370508
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.510591765
Short name T492
Test name
Test status
Simulation time 11600173657 ps
CPU time 28.14 seconds
Started Aug 06 04:44:51 PM PDT 24
Finished Aug 06 04:45:19 PM PDT 24
Peak memory 241364 kb
Host smart-33b5fee7-2380-4977-b59b-cbbb87b4af87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510591765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.510591765
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.2597098094
Short name T949
Test name
Test status
Simulation time 16186642 ps
CPU time 0.8 seconds
Started Aug 06 04:44:52 PM PDT 24
Finished Aug 06 04:44:52 PM PDT 24
Peak memory 207032 kb
Host smart-1a216f56-b289-4804-ae07-1ca19f982c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597098094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.2597098094
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.1603120876
Short name T985
Test name
Test status
Simulation time 288256342006 ps
CPU time 485.75 seconds
Started Aug 06 04:44:53 PM PDT 24
Finished Aug 06 04:52:58 PM PDT 24
Peak memory 263424 kb
Host smart-34d0ea61-287e-4725-afb0-c979da47e142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603120876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.1603120876
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.2244083824
Short name T984
Test name
Test status
Simulation time 2400082438 ps
CPU time 24.6 seconds
Started Aug 06 04:45:03 PM PDT 24
Finished Aug 06 04:45:28 PM PDT 24
Peak memory 218304 kb
Host smart-27e225f7-2b98-4cf8-abf9-2259cde90936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244083824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.2244083824
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.1199825518
Short name T931
Test name
Test status
Simulation time 3428548349 ps
CPU time 31.93 seconds
Started Aug 06 04:44:59 PM PDT 24
Finished Aug 06 04:45:31 PM PDT 24
Peak memory 235196 kb
Host smart-be5a41c0-0f55-48fd-ae06-fc5bc0496283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199825518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.1199825518
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.1485730233
Short name T302
Test name
Test status
Simulation time 4662610574 ps
CPU time 18.35 seconds
Started Aug 06 04:44:50 PM PDT 24
Finished Aug 06 04:45:09 PM PDT 24
Peak memory 233372 kb
Host smart-6f517afd-f440-4ff7-9743-34adcedf0274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485730233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.1485730233
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.618173280
Short name T650
Test name
Test status
Simulation time 165422116999 ps
CPU time 249.57 seconds
Started Aug 06 04:44:54 PM PDT 24
Finished Aug 06 04:49:04 PM PDT 24
Peak memory 252404 kb
Host smart-1d28998d-b559-4a04-a8b7-4b4d3dbf9351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618173280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds.
618173280
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_intercept.2238910787
Short name T430
Test name
Test status
Simulation time 146048816 ps
CPU time 3.79 seconds
Started Aug 06 04:44:50 PM PDT 24
Finished Aug 06 04:44:54 PM PDT 24
Peak memory 233284 kb
Host smart-c70e89bd-29fd-49eb-8e09-0a8fef7b42c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238910787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.2238910787
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.1279648477
Short name T398
Test name
Test status
Simulation time 515007117 ps
CPU time 3.17 seconds
Started Aug 06 04:44:53 PM PDT 24
Finished Aug 06 04:44:56 PM PDT 24
Peak memory 228764 kb
Host smart-0f2020ea-fd69-4c46-ba5b-5794d7e162c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279648477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.1279648477
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.341250708
Short name T426
Test name
Test status
Simulation time 86602560 ps
CPU time 1.13 seconds
Started Aug 06 04:44:51 PM PDT 24
Finished Aug 06 04:44:53 PM PDT 24
Peak memory 217160 kb
Host smart-cd466acf-0f9c-40c0-a82b-4680d3d97223
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341250708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.spi_device_mem_parity.341250708
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.4190609535
Short name T279
Test name
Test status
Simulation time 4780148064 ps
CPU time 18.23 seconds
Started Aug 06 04:44:52 PM PDT 24
Finished Aug 06 04:45:11 PM PDT 24
Peak memory 225300 kb
Host smart-2161f04b-e4bc-480e-b8fe-141818efc77a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190609535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.4190609535
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.569453981
Short name T593
Test name
Test status
Simulation time 1859216419 ps
CPU time 8 seconds
Started Aug 06 04:44:54 PM PDT 24
Finished Aug 06 04:45:02 PM PDT 24
Peak memory 233368 kb
Host smart-269c46f3-14fc-42d2-a24e-9d22c7e00be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569453981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.569453981
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.4282903722
Short name T151
Test name
Test status
Simulation time 17480552895 ps
CPU time 13.37 seconds
Started Aug 06 04:44:57 PM PDT 24
Finished Aug 06 04:45:10 PM PDT 24
Peak memory 219652 kb
Host smart-d683ccb7-e064-49ae-8d27-5bbe0f170326
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4282903722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.4282903722
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.3331761323
Short name T413
Test name
Test status
Simulation time 74023879 ps
CPU time 1.02 seconds
Started Aug 06 04:44:57 PM PDT 24
Finished Aug 06 04:44:58 PM PDT 24
Peak memory 207200 kb
Host smart-a81e5a61-193d-4615-82a2-f321e0f56796
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331761323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.3331761323
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.821552172
Short name T526
Test name
Test status
Simulation time 1407046893 ps
CPU time 17.49 seconds
Started Aug 06 04:44:53 PM PDT 24
Finished Aug 06 04:45:11 PM PDT 24
Peak memory 216884 kb
Host smart-26fb86c3-ba97-4b29-a165-42bfa7c93959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821552172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.821552172
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.2085854163
Short name T412
Test name
Test status
Simulation time 2082940306 ps
CPU time 6.4 seconds
Started Aug 06 04:44:51 PM PDT 24
Finished Aug 06 04:44:58 PM PDT 24
Peak memory 216996 kb
Host smart-3d73c1f3-686b-4c2e-bab1-19edfd3521ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085854163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.2085854163
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.375149252
Short name T364
Test name
Test status
Simulation time 615530992 ps
CPU time 3.38 seconds
Started Aug 06 04:44:53 PM PDT 24
Finished Aug 06 04:44:56 PM PDT 24
Peak memory 216948 kb
Host smart-1ca8d559-113b-4c57-b0fd-599fd83e153a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375149252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.375149252
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.4194206424
Short name T982
Test name
Test status
Simulation time 98445242 ps
CPU time 0.68 seconds
Started Aug 06 04:44:57 PM PDT 24
Finished Aug 06 04:44:58 PM PDT 24
Peak memory 205988 kb
Host smart-0d19fcdf-bf59-4b64-9e79-ebfb017bdaf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194206424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.4194206424
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.3302252511
Short name T817
Test name
Test status
Simulation time 7240103643 ps
CPU time 6.93 seconds
Started Aug 06 04:44:53 PM PDT 24
Finished Aug 06 04:45:00 PM PDT 24
Peak memory 225108 kb
Host smart-23363168-5739-485f-b13d-50538f752a61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302252511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.3302252511
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.34283762
Short name T743
Test name
Test status
Simulation time 15030198 ps
CPU time 0.7 seconds
Started Aug 06 04:44:53 PM PDT 24
Finished Aug 06 04:44:53 PM PDT 24
Peak memory 205868 kb
Host smart-ef7ec9e2-b15f-43f2-84ee-04bbf9d2ce63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34283762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.34283762
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.3514646219
Short name T959
Test name
Test status
Simulation time 1008523927 ps
CPU time 4.16 seconds
Started Aug 06 04:44:55 PM PDT 24
Finished Aug 06 04:44:59 PM PDT 24
Peak memory 225140 kb
Host smart-78d9d9b1-6172-4ccb-97ee-919fdddbc30e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514646219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.3514646219
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.1359388524
Short name T909
Test name
Test status
Simulation time 37888187 ps
CPU time 0.76 seconds
Started Aug 06 04:44:57 PM PDT 24
Finished Aug 06 04:44:58 PM PDT 24
Peak memory 206912 kb
Host smart-d897bc0d-707f-479e-9507-7673cd2738b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359388524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.1359388524
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.2790508299
Short name T645
Test name
Test status
Simulation time 133233696145 ps
CPU time 223.26 seconds
Started Aug 06 04:44:52 PM PDT 24
Finished Aug 06 04:48:35 PM PDT 24
Peak memory 264620 kb
Host smart-c08a3754-bfe2-4011-8dad-05200afb9a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790508299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.2790508299
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.2677679795
Short name T371
Test name
Test status
Simulation time 32742874706 ps
CPU time 119.18 seconds
Started Aug 06 04:44:57 PM PDT 24
Finished Aug 06 04:46:56 PM PDT 24
Peak memory 258152 kb
Host smart-78ffc17f-2b10-4fc0-9dd1-24552438b662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677679795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.2677679795
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.4120458926
Short name T921
Test name
Test status
Simulation time 44450518673 ps
CPU time 391.47 seconds
Started Aug 06 04:44:59 PM PDT 24
Finished Aug 06 04:51:31 PM PDT 24
Peak memory 250056 kb
Host smart-4f36a5fd-22c4-4191-a335-c8c70f9b6a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120458926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.4120458926
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.1532907599
Short name T748
Test name
Test status
Simulation time 2796889916 ps
CPU time 11.28 seconds
Started Aug 06 04:44:59 PM PDT 24
Finished Aug 06 04:45:10 PM PDT 24
Peak memory 225300 kb
Host smart-4c1d6160-b5fd-4460-9091-2032d67bf7a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532907599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.1532907599
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_intercept.3687460044
Short name T716
Test name
Test status
Simulation time 828369866 ps
CPU time 8.77 seconds
Started Aug 06 04:45:01 PM PDT 24
Finished Aug 06 04:45:10 PM PDT 24
Peak memory 225100 kb
Host smart-8d2ffbf6-6f2e-470f-9d86-785c009f454b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687460044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.3687460044
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.1919835047
Short name T70
Test name
Test status
Simulation time 7058885400 ps
CPU time 27.1 seconds
Started Aug 06 04:44:56 PM PDT 24
Finished Aug 06 04:45:23 PM PDT 24
Peak memory 225160 kb
Host smart-cc0500ff-af46-4a6a-8549-2f243a7f4864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919835047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.1919835047
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.211838985
Short name T744
Test name
Test status
Simulation time 43629471 ps
CPU time 1.07 seconds
Started Aug 06 04:44:56 PM PDT 24
Finished Aug 06 04:44:57 PM PDT 24
Peak memory 217180 kb
Host smart-60267511-6911-4314-8a4e-c32a16959c00
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211838985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.spi_device_mem_parity.211838985
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.2174623670
Short name T681
Test name
Test status
Simulation time 4422985602 ps
CPU time 6.61 seconds
Started Aug 06 04:45:01 PM PDT 24
Finished Aug 06 04:45:07 PM PDT 24
Peak memory 233384 kb
Host smart-30da2e36-82b8-4fb0-bd89-ad691119a84c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174623670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.2174623670
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.2377272152
Short name T350
Test name
Test status
Simulation time 125541661 ps
CPU time 2.6 seconds
Started Aug 06 04:44:56 PM PDT 24
Finished Aug 06 04:44:59 PM PDT 24
Peak memory 225260 kb
Host smart-436e8d0b-08ef-4444-8ba9-31cc7d6eb8c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377272152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.2377272152
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.1301844076
Short name T918
Test name
Test status
Simulation time 3385626079 ps
CPU time 8.51 seconds
Started Aug 06 04:44:50 PM PDT 24
Finished Aug 06 04:44:59 PM PDT 24
Peak memory 219604 kb
Host smart-7a2639f0-3422-45d3-9c1d-608dfd42adf3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1301844076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.1301844076
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.847555871
Short name T689
Test name
Test status
Simulation time 139035048 ps
CPU time 0.89 seconds
Started Aug 06 04:44:53 PM PDT 24
Finished Aug 06 04:44:54 PM PDT 24
Peak memory 206196 kb
Host smart-cba8414e-d0cc-4b6e-b2b4-507e6fc5c2bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847555871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stress
_all.847555871
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.1565580644
Short name T494
Test name
Test status
Simulation time 900962913 ps
CPU time 8.33 seconds
Started Aug 06 04:44:57 PM PDT 24
Finished Aug 06 04:45:05 PM PDT 24
Peak memory 216884 kb
Host smart-65724ed6-957d-42ce-b6f8-3dd1fddc535b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565580644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.1565580644
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.3366933987
Short name T876
Test name
Test status
Simulation time 3336066459 ps
CPU time 9.85 seconds
Started Aug 06 04:44:57 PM PDT 24
Finished Aug 06 04:45:06 PM PDT 24
Peak memory 217072 kb
Host smart-80d7be01-76ce-49ed-9da1-b2746b7d8d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366933987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.3366933987
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.870646248
Short name T929
Test name
Test status
Simulation time 249704534 ps
CPU time 0.91 seconds
Started Aug 06 04:44:56 PM PDT 24
Finished Aug 06 04:44:57 PM PDT 24
Peak memory 207600 kb
Host smart-b0969221-ced8-4d63-ab95-a3b44e7016b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870646248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.870646248
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.433318515
Short name T420
Test name
Test status
Simulation time 64104775 ps
CPU time 0.74 seconds
Started Aug 06 04:44:56 PM PDT 24
Finished Aug 06 04:44:57 PM PDT 24
Peak memory 206532 kb
Host smart-ae4f0b09-9e8e-4ed9-83d5-6a6d7a06137f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433318515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.433318515
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.3875759509
Short name T225
Test name
Test status
Simulation time 809045037 ps
CPU time 4.32 seconds
Started Aug 06 04:45:01 PM PDT 24
Finished Aug 06 04:45:05 PM PDT 24
Peak memory 225076 kb
Host smart-45e1db2a-6ee1-42d4-9367-3f82415bc03b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875759509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.3875759509
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.1828293980
Short name T710
Test name
Test status
Simulation time 51903386 ps
CPU time 0.71 seconds
Started Aug 06 04:44:50 PM PDT 24
Finished Aug 06 04:44:51 PM PDT 24
Peak memory 205144 kb
Host smart-90ff03d0-b859-4c4c-a2ba-2d25efcd7cd9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828293980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.1
828293980
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.2117805270
Short name T767
Test name
Test status
Simulation time 2192762610 ps
CPU time 11.65 seconds
Started Aug 06 04:44:52 PM PDT 24
Finished Aug 06 04:45:04 PM PDT 24
Peak memory 233500 kb
Host smart-ed84de2f-f0fc-42cf-ae04-0955801cfb33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117805270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.2117805270
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.3925773499
Short name T466
Test name
Test status
Simulation time 20087565 ps
CPU time 0.75 seconds
Started Aug 06 04:44:52 PM PDT 24
Finished Aug 06 04:44:53 PM PDT 24
Peak memory 206968 kb
Host smart-3419bfba-b15b-4ed2-afb5-2f032234aaa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925773499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.3925773499
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.2407060877
Short name T761
Test name
Test status
Simulation time 5212364535 ps
CPU time 64.66 seconds
Started Aug 06 04:44:50 PM PDT 24
Finished Aug 06 04:45:55 PM PDT 24
Peak memory 254592 kb
Host smart-4b99cb68-777d-4198-927b-506afd94d49a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407060877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.2407060877
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.812727112
Short name T1015
Test name
Test status
Simulation time 15660046534 ps
CPU time 57.82 seconds
Started Aug 06 04:44:51 PM PDT 24
Finished Aug 06 04:45:49 PM PDT 24
Peak memory 249384 kb
Host smart-833691ea-1ea0-459a-854d-c69d48c1991d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812727112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.812727112
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.1842071794
Short name T623
Test name
Test status
Simulation time 11157730621 ps
CPU time 76.95 seconds
Started Aug 06 04:44:53 PM PDT 24
Finished Aug 06 04:46:10 PM PDT 24
Peak memory 253856 kb
Host smart-c1938887-0d5e-4726-863a-e0ac69ee37dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842071794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.1842071794
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.1728094141
Short name T129
Test name
Test status
Simulation time 7304782447 ps
CPU time 9.85 seconds
Started Aug 06 04:44:51 PM PDT 24
Finished Aug 06 04:45:01 PM PDT 24
Peak memory 236256 kb
Host smart-d6ddab63-b76c-4a37-bcf4-0130b6badbd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728094141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.1728094141
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.1498204274
Short name T1022
Test name
Test status
Simulation time 13782271 ps
CPU time 0.76 seconds
Started Aug 06 04:44:53 PM PDT 24
Finished Aug 06 04:44:54 PM PDT 24
Peak memory 216424 kb
Host smart-ceef6fad-2374-4986-8853-bf0d45f14145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498204274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds
.1498204274
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/9.spi_device_intercept.3806342073
Short name T591
Test name
Test status
Simulation time 7161017177 ps
CPU time 14.07 seconds
Started Aug 06 04:44:48 PM PDT 24
Finished Aug 06 04:45:03 PM PDT 24
Peak memory 225124 kb
Host smart-f291a9b0-a6b0-4db1-93ab-e21d4317e916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806342073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.3806342073
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.1188902941
Short name T932
Test name
Test status
Simulation time 11332330086 ps
CPU time 94.68 seconds
Started Aug 06 04:44:50 PM PDT 24
Finished Aug 06 04:46:25 PM PDT 24
Peak memory 233412 kb
Host smart-bfe2734f-57f9-46d5-8713-b228b15067c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188902941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.1188902941
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.574672018
Short name T902
Test name
Test status
Simulation time 105423849 ps
CPU time 1.31 seconds
Started Aug 06 04:44:50 PM PDT 24
Finished Aug 06 04:44:51 PM PDT 24
Peak memory 217184 kb
Host smart-4fb76ef3-a6bc-447f-88d3-305869c04f4b
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574672018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.spi_device_mem_parity.574672018
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.1640074458
Short name T209
Test name
Test status
Simulation time 5230087466 ps
CPU time 9.2 seconds
Started Aug 06 04:44:53 PM PDT 24
Finished Aug 06 04:45:02 PM PDT 24
Peak memory 233472 kb
Host smart-ca2f3aee-fcde-475f-bfcd-263a52d2e4a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640074458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.1640074458
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.1829211268
Short name T896
Test name
Test status
Simulation time 3766169450 ps
CPU time 11.51 seconds
Started Aug 06 04:44:50 PM PDT 24
Finished Aug 06 04:45:02 PM PDT 24
Peak memory 233416 kb
Host smart-96ff64cf-3447-41fd-9b70-5fd342648eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829211268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.1829211268
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.115736916
Short name T353
Test name
Test status
Simulation time 481798415 ps
CPU time 6.18 seconds
Started Aug 06 04:44:49 PM PDT 24
Finished Aug 06 04:44:55 PM PDT 24
Peak memory 219656 kb
Host smart-b63105ac-9bc4-47c3-9bb5-5fc2ca58b8e6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=115736916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_direc
t.115736916
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.633433901
Short name T315
Test name
Test status
Simulation time 3729860322 ps
CPU time 14.62 seconds
Started Aug 06 04:44:49 PM PDT 24
Finished Aug 06 04:45:03 PM PDT 24
Peak memory 217308 kb
Host smart-145c129e-50a3-45e2-a18f-7d71a1712e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633433901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.633433901
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.3082353416
Short name T445
Test name
Test status
Simulation time 13361481219 ps
CPU time 9.53 seconds
Started Aug 06 04:44:51 PM PDT 24
Finished Aug 06 04:45:00 PM PDT 24
Peak memory 216948 kb
Host smart-86a98fe7-39f1-46af-b2f1-6aaa1177b930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082353416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.3082353416
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.1226188293
Short name T52
Test name
Test status
Simulation time 1085990607 ps
CPU time 4.05 seconds
Started Aug 06 04:44:54 PM PDT 24
Finished Aug 06 04:44:58 PM PDT 24
Peak memory 216980 kb
Host smart-ac96651a-7cf1-4be0-b59c-68a934389537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226188293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.1226188293
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.3147024879
Short name T1020
Test name
Test status
Simulation time 15501881 ps
CPU time 0.76 seconds
Started Aug 06 04:45:01 PM PDT 24
Finished Aug 06 04:45:01 PM PDT 24
Peak memory 206468 kb
Host smart-5166a871-afa1-426d-a83f-c1c4a4b8f367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147024879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.3147024879
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.3525467164
Short name T241
Test name
Test status
Simulation time 1602639939 ps
CPU time 7.54 seconds
Started Aug 06 04:44:48 PM PDT 24
Finished Aug 06 04:44:56 PM PDT 24
Peak memory 225068 kb
Host smart-742da74a-e927-458f-bd65-e0585ac335d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525467164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.3525467164
Directory /workspace/9.spi_device_upload/latest
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