Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2698025	1			T2	1		T3	1		T4	26
all_values[1]	2698025	1			T2	1		T3	1		T4	26
all_values[2]	2698025	1			T2	1		T3	1		T4	26
all_values[3]	2698025	1			T2	1		T3	1		T4	26
all_values[4]	2698025	1			T2	1		T3	1		T4	26
all_values[5]	2698025	1			T2	1		T3	1		T4	26
all_values[6]	2698025	1			T2	1		T3	1		T4	26
all_values[7]	2698025	1			T2	1		T3	1		T4	26

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20794127

1

T2

8

T3

8

T4

100

auto[1]

790073

1

T4

108

T29

82343

T16

30

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21559282

1

T2

8

T3

8

T4

133

auto[1]

24918

1

T4

75

T5

31

T7

20

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2587858	1			T2	1		T3	1		T4	9
all_values[0]	auto[0]	auto[1]	10919	1			T4	8		T5	31		T7	12
all_values[0]	auto[1]	auto[0]	98404	1			T4	5		T29	11575		T17	1
all_values[0]	auto[1]	auto[1]	844	1			T4	4		T29	188		T16	1
all_values[1]	auto[0]	auto[0]	2557928	1			T2	1		T3	1		T4	5
all_values[1]	auto[0]	auto[1]	7494	1			T4	5		T7	8		T26	189
all_values[1]	auto[1]	auto[0]	131860	1			T4	9		T29	11640		T16	4
all_values[1]	auto[1]	auto[1]	743	1			T4	7		T29	120		T17	3
all_values[2]	auto[0]	auto[0]	2576347	1			T2	1		T3	1		T4	8
all_values[2]	auto[0]	auto[1]	2493	1			T4	3		T26	53		T29	28
all_values[2]	auto[1]	auto[0]	118821	1			T4	7		T29	11720		T16	5
all_values[2]	auto[1]	auto[1]	364	1			T4	8		T29	41		T17	3
all_values[3]	auto[0]	auto[0]	2625400	1			T2	1		T3	1		T4	9
all_values[3]	auto[0]	auto[1]	209	1			T4	7		T29	6		T17	4
all_values[3]	auto[1]	auto[0]	72202	1			T4	7		T29	11759		T16	3
all_values[3]	auto[1]	auto[1]	214	1			T4	3		T29	2		T16	3
all_values[4]	auto[0]	auto[0]	2600793	1			T2	1		T3	1		T4	10
all_values[4]	auto[0]	auto[1]	193	1			T4	1		T29	2		T17	4
all_values[4]	auto[1]	auto[0]	96834	1			T4	11		T29	11761		T16	2
all_values[4]	auto[1]	auto[1]	205	1			T4	4		T29	3		T16	3
all_values[5]	auto[0]	auto[0]	2628477	1			T2	1		T3	1		T4	4
all_values[5]	auto[0]	auto[1]	195	1			T4	6		T29	2		T16	2
all_values[5]	auto[1]	auto[0]	69167	1			T4	12		T29	11761		T17	6
all_values[5]	auto[1]	auto[1]	186	1			T4	4		T29	5		T17	2
all_values[6]	auto[0]	auto[0]	2643109	1			T2	1		T3	1		T4	10
all_values[6]	auto[0]	auto[1]	229	1			T4	3		T29	4		T17	1
all_values[6]	auto[1]	auto[0]	54482	1			T4	9		T29	6		T16	4
all_values[6]	auto[1]	auto[1]	205	1			T4	4		T29	2		T17	4
all_values[7]	auto[0]	auto[0]	2552243	1			T2	1		T3	1		T4	7
all_values[7]	auto[0]	auto[1]	240	1			T4	5		T29	3		T17	1
all_values[7]	auto[1]	auto[0]	145357	1			T4	11		T29	11760		T16	3
all_values[7]	auto[1]	auto[1]	185	1			T4	3		T16	2		T17	2