Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	34875	1			T3	6		T5	12		T6	18
auto[SpiFlashAddrCfg]	7532	1			T3	6		T5	2		T7	56
auto[SpiFlashAddr3b]	8893	1			T2	2		T3	4		T5	5
auto[SpiFlashAddr4b]	7666	1			T3	2		T5	2		T7	51

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

35001

1

T2

2

T3

18

T5

17

auto[1]

23965

1

T5

4

T7

139

T12

100

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30766

1

T2

2

T3

6

T5

6

auto[1]

28200

1

T3

12

T5

15

T6

8

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	39461	1			T3	2		T5	13		T6	22
values[1]	1102	1			T5	1		T7	11		T12	2
values[2]	1458	1			T7	10		T8	6		T12	12
values[3]	1403	1			T3	8		T5	3		T7	11
values[4]	1476	1			T5	2		T7	6		T12	7
values[5]	1444	1			T7	17		T12	11		T26	16
values[6]	1468	1			T7	10		T12	6		T26	12
values[7]	1430	1			T5	1		T7	10		T12	7
values[8]	9724	1			T2	2		T3	8		T5	1

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30023

1

T2

2

T3

18

T6

22

auto[1]

28943

1

T5

21

T15

4

T39

8

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

55769

1

T2

2

T3

16

T5

21

write

3197

1

T3

2

T7

16

T12

22

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

18659

1

T2

2

T3

8

T5

10

valids[0x1]

40307

1

T3

10

T5

11

T6

22

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1548	1			T5	1		T6	4		T7	8
internal_process_ops[0x5a]	1593	1			T5	1		T6	4		T7	9
internal_process_ops[0x05]	21332	1			T5	3		T6	8		T7	70
internal_process_ops[0x35]	1552	1			T5	1		T6	4		T7	6
internal_process_ops[0x15]	1561	1			T5	1		T6	2		T7	10
internal_process_ops[0x03]	1038	1			T7	7		T12	4		T39	5
internal_process_ops[0x0b]	1035	1			T7	11		T12	13		T39	1
internal_process_ops[0x3b]	1022	1			T3	2		T7	10		T12	11
internal_process_ops[0x6b]	1010	1			T2	2		T7	9		T8	4
internal_process_ops[0xbb]	1011	1			T7	8		T8	2		T12	10
internal_process_ops[0xeb]	1060	1			T3	2		T5	1		T7	11

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

57364

1

T2

2

T3

18

T5

21

auto[1]

1602

1

T7

12

T12

14

T26

12

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

56685

1

T2

2

T3

18

T5

20

auto[1]

2281

1

T5

1

T7

8

T12

18

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10856

1

T3

4

T6

18

T7

77

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

5554

1

T7

65

T12

18

T37

177

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1968

1

T3

6

T7

24

T8

4

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1770

1

T7

27

T12

20

T37

24

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2421

1

T2

2

T3

4

T6

4

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2048

1

T7

19

T12

25

T37

32

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2158

1

T3

2

T7

27

T12

20

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1754

1

T7

22

T12

26

T37

11

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

95

1

T3

2

T37

1

T29

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

93

1

T7

3

T12

1

T41

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

86

1

T12

1

T37

2

T41

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

94

1

T7

3

T37

1

T41

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

132

1

T7

3

T12

2

T29

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

85

1

T7

2

T12

2

T37

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

75

1

T12

2

T37

2

T29

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

106

1

T12

1

T37

1

T29

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

81

1

T12

1

T46

2

T42

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

88

1

T7

1

T12

3

T42

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

83

1

T7

1

T152

4

T43

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

112

1

T7

1

T12

5

T37

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

120

1

T12

2

T37

2

T29

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

63

1

T7

1

T29

2

T41

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

86

1

T37

3

T29

6

T41

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

95

1

T7

1

T12

2

T37

1

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

11138

1

T5

10

T15

3

T26

106

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6528

1

T5

2

T26

61

T29

44

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1558

1

T5

2

T39

1

T26

25

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1424

1

T26

29

T29

11

T38

17

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1822

1

T5

5

T39

1

T26

25

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1794

1

T26

39

T29

17

T38

17

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1508

1

T15

1

T39

6

T26

19

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1468

1

T5

2

T26

20

T29

17

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

97

1

T29

1

T153

3

T154

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

109

1

T26

2

T29

1

T30

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

119

1

T26

4

T38

3

T30

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

106

1

T29

1

T38

1

T74

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

101

1

T26

2

T29

2

T83

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

96

1

T29

2

T30

1

T47

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

117

1

T26

4

T30

2

T74

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

100

1

T30

3

T83

1

T147

9

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

89

1

T26

2

T29

1

T38

3

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

117

1

T26

1

T29

1

T38

3

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

96

1

T29

1

T30

1

T47

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

142

1

T26

5

T29

3

T38

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

112

1

T26

3

T29

2

T30

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

94

1

T26

3

T83

3

T153

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

106

1

T26

3

T38

2

T47

5

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

102

1

T26

1

T38

1

T30

3

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3606	1			T7	34		T12	46		T37	50
auto[0]	values[0]	valids[0x1]	15471	1			T3	2		T6	22		T7	125
auto[0]	values[1]	valids[0x1]	580	1			T7	11		T12	2		T37	7
auto[0]	values[2]	valids[0x0]	564	1			T7	5		T8	6		T12	11
auto[0]	values[2]	valids[0x1]	271	1			T7	5		T12	1		T37	1
auto[0]	values[3]	valids[0x0]	511	1			T3	2		T7	8		T12	5
auto[0]	values[3]	valids[0x1]	276	1			T3	6		T7	3		T12	4
auto[0]	values[4]	valids[0x0]	498	1			T7	4		T12	6		T37	2
auto[0]	values[4]	valids[0x1]	332	1			T7	2		T12	1		T37	3
auto[0]	values[5]	valids[0x0]	556	1			T7	15		T12	4		T37	6
auto[0]	values[5]	valids[0x1]	272	1			T7	2		T12	7		T37	4
auto[0]	values[6]	valids[0x0]	502	1			T7	9		T12	5		T37	7
auto[0]	values[6]	valids[0x1]	298	1			T7	1		T12	1		T37	3
auto[0]	values[7]	valids[0x0]	510	1			T7	6		T12	4		T37	7
auto[0]	values[7]	valids[0x1]	319	1			T7	4		T12	3		T37	3
auto[0]	values[8]	valids[0x0]	3394	1			T2	2		T3	6		T7	58
auto[0]	values[8]	valids[0x1]	2063	1			T3	2		T7	29		T12	20
auto[1]	values[0]	valids[0x0]	3772	1			T5	6		T15	3		T26	44
auto[1]	values[0]	valids[0x1]	16612	1			T5	7		T39	6		T26	163
auto[1]	values[1]	valids[0x1]	522	1			T5	1		T26	5		T29	7
auto[1]	values[2]	valids[0x0]	365	1			T26	8		T29	3		T38	1
auto[1]	values[2]	valids[0x1]	258	1			T26	5		T29	2		T38	3
auto[1]	values[3]	valids[0x0]	364	1			T5	1		T15	1		T39	1
auto[1]	values[3]	valids[0x1]	252	1			T5	2		T26	4		T29	1
auto[1]	values[4]	valids[0x0]	391	1			T5	2		T26	5		T29	5
auto[1]	values[4]	valids[0x1]	255	1			T38	2		T30	2		T83	2
auto[1]	values[5]	valids[0x0]	358	1			T26	8		T29	2		T38	5
auto[1]	values[5]	valids[0x1]	258	1			T26	8		T40	1		T38	1
auto[1]	values[6]	valids[0x0]	410	1			T26	10		T29	5		T38	7
auto[1]	values[6]	valids[0x1]	258	1			T26	2		T29	4		T38	4
auto[1]	values[7]	valids[0x0]	338	1			T5	1		T26	7		T29	2
auto[1]	values[7]	valids[0x1]	263	1			T26	1		T38	8		T30	4
auto[1]	values[8]	valids[0x0]	2520	1			T39	1		T26	50		T29	16
auto[1]	values[8]	valids[0x1]	1747	1			T5	1		T26	31		T29	18