Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3225199

1

T2

840

T3

1

T5

912

auto[1]

31118

1

T5

1

T7

61

T12

444

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

913557

1

T2

840

T3

1

T5

11

auto[1]

2342760

1

T5

902

T6

5388

T7

13865

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	587133	1			T2	359		T3	1		T5	2
auto[524288:1048575]	390715	1			T6	259		T7	5021		T8	15117
auto[1048576:1572863]	419197	1			T2	409		T5	4		T6	255
auto[1572864:2097151]	373673	1			T2	1		T6	844		T7	260
auto[2097152:2621439]	380444	1			T6	12396		T7	7		T8	2
auto[2621440:3145727]	382959	1			T6	1437		T7	2623		T12	481
auto[3145728:3670015]	375778	1			T2	71		T6	379		T7	1084
auto[3670016:4194303]	346418	1			T5	907		T6	2084		T7	1052

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2374679

1

T2

9

T3

1

T5

913

auto[1]

881638

1

T2

831

T6

14929

T7

3

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2797800

1

T2

840

T3

1

T5

913

auto[1]

458517

1

T7

564

T12

4082

T26

358

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	159450	1			T2	359		T3	1		T5	2
auto[0]	auto[0]	auto[0:524287]	auto[1]	361821	1			T6	2680		T7	1054		T12	256
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	123531	1			T6	2		T7	6		T8	15117
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	203644	1			T6	257		T7	4999		T12	3
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	121180	1			T2	409		T5	4		T6	1
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	231110	1			T6	254		T7	2779		T12	2660
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	74745	1			T2	1		T6	707		T7	4
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	236548	1			T6	137		T7	256		T12	2855
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	101140	1			T6	10713		T7	3		T8	2
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	206632	1			T6	1683		T7	1		T12	513
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	116371	1			T6	1429		T7	5		T12	3
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	219133	1			T6	8		T7	2608		T12	41
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	104888	1			T2	71		T6	379		T7	5
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	205681	1			T7	1079		T12	1		T37	4973
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	97328	1			T5	4		T6	1715		T7	7
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	207909	1			T5	902		T6	369		T7	520
auto[0]	auto[1]	auto[0:524287]	auto[0]	3216	1			T7	2		T26	1		T37	3
auto[0]	auto[1]	auto[0:524287]	auto[1]	58237	1			T7	1		T37	280		T29	4840
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	530	1			T12	3		T29	3		T38	15
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	57954	1			T12	897		T29	132		T38	5
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	1794	1			T7	4		T26	1		T29	9
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	62159	1			T7	1		T26	119		T29	513
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	760	1			T12	1		T26	1		T38	16
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	57537	1			T12	512		T26	1		T29	5
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	651	1			T12	4		T26	2		T48	13
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	67667	1			T12	258		T29	1		T38	256
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	484	1			T7	2		T12	2		T26	2
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	43607	1			T7	1		T12	433		T26	227
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	2974	1			T12	3		T26	2		T29	3
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	59343	1			T12	1911		T29	1		T47	256
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	868	1			T7	11		T29	4		T30	1
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	36307	1			T7	513		T29	768		T30	1
auto[1]	auto[0]	auto[0:524287]	auto[0]	438	1			T26	2		T37	1		T29	1
auto[1]	auto[0]	auto[0:524287]	auto[1]	3248	1			T26	2		T37	4		T29	2
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	410	1			T7	1		T12	2		T26	4
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	4221	1			T7	15		T12	31		T26	11
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	332	1			T7	1		T12	2		T26	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	2170	1			T7	7		T12	73		T37	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	392	1			T12	2		T26	6		T37	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	3053	1			T12	29		T26	9		T37	31
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	359	1			T7	1		T12	1		T26	3
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	3458	1			T7	2		T12	42		T26	33
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	396	1			T7	1		T12	1		T26	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	2455	1			T7	4		T12	1		T37	156
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	339	1			T12	1		T37	1		T29	4
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	1995	1			T12	56		T37	18		T29	13
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	364	1			T5	1		T12	5		T37	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	3059	1			T12	140		T41	29		T18	117
auto[1]	auto[1]	auto[0:524287]	auto[0]	91	1			T7	1		T274	1		T178	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	632	1			T7	10		T274	3		T178	1
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	76	1			T12	1		T38	2		T30	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	349	1			T12	34		T30	3		T19	4
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	53	1			T7	1		T29	1		T30	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	399	1			T7	14		T29	3		T30	15
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	91	1			T26	1		T38	5		T47	4
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	547	1			T26	1		T74	1		T153	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	70	1			T12	2		T29	1		T30	3
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	467	1			T12	19		T29	3		T30	31
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	98	1			T7	1		T41	1		T43	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	415	1			T7	1		T41	6		T43	13
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	81	1			T12	1		T29	1		T38	3
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	477	1			T12	1		T29	4		T18	3
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	57	1			T7	1		T30	1		T19	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	526	1			T30	38		T19	1		T22	1

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1897351	1			T2	9		T3	1		T5	912
auto[0]	auto[0]	auto[1]	873760	1			T2	831		T6	14929		T7	1
auto[0]	auto[1]	auto[0]	446820	1			T7	535		T12	4022		T26	356
auto[0]	auto[1]	auto[1]	7268	1			T12	2		T49	6		T30	5
auto[1]	auto[0]	auto[0]	26191	1			T5	1		T7	30		T12	386
auto[1]	auto[0]	auto[1]	498	1			T7	2		T37	3		T38	7
auto[1]	auto[1]	auto[0]	4317	1			T7	29		T12	58		T26	2
auto[1]	auto[1]	auto[1]	112	1			T38	2		T30	2		T47	1