Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2698025	1			T2	1		T3	1		T4	26
all_pins[1]	2698025	1			T2	1		T3	1		T4	26
all_pins[2]	2698025	1			T2	1		T3	1		T4	26
all_pins[3]	2698025	1			T2	1		T3	1		T4	26
all_pins[4]	2698025	1			T2	1		T3	1		T4	26
all_pins[5]	2698025	1			T2	1		T3	1		T4	26
all_pins[6]	2698025	1			T2	1		T3	1		T4	26
all_pins[7]	2698025	1			T2	1		T3	1		T4	26

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	21526938	1			T2	8		T3	8		T4	171
values[0x1]	57262	1			T4	37		T29	894		T16	9
transitions[0x0=>0x1]	55783	1			T4	29		T29	714		T16	6
transitions[0x1=>0x0]	55790	1			T4	29		T29	714		T16	6

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2697097	1			T2	1		T3	1		T4	22
all_pins[0]	values[0x1]	928	1			T4	4		T29	202		T16	1
all_pins[0]	transitions[0x0=>0x1]	439	1			T4	4		T29	72		T16	1
all_pins[0]	transitions[0x1=>0x0]	299	1			T4	7		T17	2		T18	4
all_pins[1]	values[0x0]	2697237	1			T2	1		T3	1		T4	19
all_pins[1]	values[0x1]	788	1			T4	7		T29	130		T17	3
all_pins[1]	transitions[0x0=>0x1]	567	1			T4	4		T29	87		T17	3
all_pins[1]	transitions[0x1=>0x0]	156	1			T4	5		T29	2		T17	3
all_pins[2]	values[0x0]	2697648	1			T2	1		T3	1		T4	18
all_pins[2]	values[0x1]	377	1			T4	8		T29	45		T17	3
all_pins[2]	transitions[0x0=>0x1]	303	1			T4	6		T29	43		T17	3
all_pins[2]	transitions[0x1=>0x0]	140	1			T4	1		T16	3		T18	1
all_pins[3]	values[0x0]	2697811	1			T2	1		T3	1		T4	23
all_pins[3]	values[0x1]	214	1			T4	3		T29	2		T16	3
all_pins[3]	transitions[0x0=>0x1]	163	1			T4	3		T18	2		T19	2
all_pins[3]	transitions[0x1=>0x0]	154	1			T4	4		T29	1		T17	1
all_pins[4]	values[0x0]	2697820	1			T2	1		T3	1		T4	22
all_pins[4]	values[0x1]	205	1			T4	4		T29	3		T16	3
all_pins[4]	transitions[0x0=>0x1]	163	1			T4	3		T29	1		T16	3
all_pins[4]	transitions[0x1=>0x0]	1913	1			T4	3		T29	508		T17	2
all_pins[5]	values[0x0]	2696070	1			T2	1		T3	1		T4	22
all_pins[5]	values[0x1]	1955	1			T4	4		T29	510		T17	2
all_pins[5]	transitions[0x0=>0x1]	1432	1			T4	3		T29	509		T17	1
all_pins[5]	transitions[0x1=>0x0]	52087	1			T4	3		T29	1		T17	3
all_pins[6]	values[0x0]	2645415	1			T2	1		T3	1		T4	22
all_pins[6]	values[0x1]	52610	1			T4	4		T29	2		T17	4
all_pins[6]	transitions[0x0=>0x1]	52570	1			T4	4		T29	2		T17	2
all_pins[6]	transitions[0x1=>0x0]	145	1			T4	3		T16	2		T18	4
all_pins[7]	values[0x0]	2697840	1			T2	1		T3	1		T4	23
all_pins[7]	values[0x1]	185	1			T4	3		T16	2		T17	2
all_pins[7]	transitions[0x0=>0x1]	146	1			T4	2		T16	2		T17	1
all_pins[7]	transitions[0x1=>0x0]	896	1			T4	3		T29	202		T16	1