Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18160

1

T2

2

T3

18

T6

22

auto[1]

11863

1

T7

139

T12

100

T37

255

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4255	1			T7	20		T12	20		T37	147
values[1]	3859	1			T2	2		T7	60		T12	141
values[2]	3014	1			T7	36		T37	200		T18	225
values[3]	3418	1			T3	18		T7	20		T8	6
values[4]	4192	1			T7	28		T12	166		T37	40
values[5]	3699	1			T7	82		T12	131		T37	40
values[6]	3834	1			T7	20		T12	124		T85	8
values[7]	3752	1			T6	22		T7	55		T12	46

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3696	1			T3	18		T6	22		T7	82
values[1]	3729	1			T29	26		T160	12		T41	94
values[2]	4588	1			T7	35		T12	141		T29	98
values[3]	3833	1			T7	20		T12	155		T37	93
values[4]	3101	1			T7	20		T8	6		T12	66
values[5]	3736	1			T2	2		T7	20		T144	10
values[6]	3615	1			T7	116		T12	146		T29	24
values[7]	3725	1			T7	28		T12	156		T37	180

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	450	1			T12	15		T37	86		T44	14
auto[0]	values[0]	values[1]	370	1			T41	23		T42	12		T279	6
auto[0]	values[0]	values[2]	343	1			T29	11		T41	13		T187	9
auto[0]	values[0]	values[3]	295	1			T37	48		T43	5		T22	13
auto[0]	values[0]	values[4]	292	1			T152	11		T23	35		T185	8
auto[0]	values[0]	values[5]	397	1			T41	14		T43	8		T44	12
auto[0]	values[0]	values[6]	342	1			T7	11		T29	16		T43	14
auto[0]	values[0]	values[7]	222	1			T22	15		T187	9		T280	18
auto[0]	values[1]	values[0]	159	1			T7	16		T29	11		T183	11
auto[0]	values[1]	values[1]	396	1			T174	10		T172	13		T207	11
auto[0]	values[1]	values[2]	325	1			T12	112		T22	10		T169	30
auto[0]	values[1]	values[3]	452	1			T7	9		T29	13		T22	13
auto[0]	values[1]	values[4]	224	1			T12	10		T281	8		T175	12
auto[0]	values[1]	values[5]	360	1			T2	2		T7	9		T144	10
auto[0]	values[1]	values[6]	221	1			T42	13		T22	11		T23	15
auto[0]	values[1]	values[7]	294	1			T29	15		T43	65		T22	8
auto[0]	values[2]	values[0]	195	1			T37	14		T44	6		T157	16
auto[0]	values[2]	values[1]	157	1			T18	11		T167	2		T182	14
auto[0]	values[2]	values[2]	277	1			T275	12		T282	6		T283	2
auto[0]	values[2]	values[3]	253	1			T168	10		T191	12		T207	15
auto[0]	values[2]	values[4]	69	1			T18	9		T204	10		T284	10
auto[0]	values[2]	values[5]	232	1			T43	25		T186	4		T157	6
auto[0]	values[2]	values[6]	180	1			T7	11		T18	6		T200	2
auto[0]	values[2]	values[7]	156	1			T37	12		T178	23		T182	12
auto[0]	values[3]	values[0]	321	1			T3	18		T37	5		T159	8
auto[0]	values[3]	values[1]	266	1			T157	10		T23	13		T168	13
auto[0]	values[3]	values[2]	294	1			T44	11		T157	14		T174	10
auto[0]	values[3]	values[3]	241	1			T178	13		T195	8		T82	14
auto[0]	values[3]	values[4]	137	1			T8	6		T18	10		T221	8
auto[0]	values[3]	values[5]	165	1			T22	7		T158	13		T174	17
auto[0]	values[3]	values[6]	312	1			T7	15		T49	10		T43	72
auto[0]	values[3]	values[7]	452	1			T12	47		T176	6		T23	93
auto[0]	values[4]	values[0]	176	1			T22	8		T157	13		T285	2
auto[0]	values[4]	values[1]	174	1			T41	10		T44	17		T165	8
auto[0]	values[4]	values[2]	377	1			T29	38		T156	6		T182	7
auto[0]	values[4]	values[3]	162	1			T37	12		T152	5		T44	8
auto[0]	values[4]	values[4]	573	1			T12	43		T168	22		T171	13
auto[0]	values[4]	values[5]	462	1			T37	11		T29	13		T42	8
auto[0]	values[4]	values[6]	387	1			T12	107		T41	12		T18	6
auto[0]	values[4]	values[7]	169	1			T7	12		T23	19		T286	10
auto[0]	values[5]	values[0]	366	1			T7	51		T42	9		T161	38
auto[0]	values[5]	values[1]	165	1			T29	16		T160	12		T18	9
auto[0]	values[5]	values[2]	447	1			T86	24		T152	94		T87	2
auto[0]	values[5]	values[3]	304	1			T12	22		T37	11		T157	19
auto[0]	values[5]	values[4]	120	1			T174	16		T184	15		T191	20
auto[0]	values[5]	values[5]	248	1			T37	15		T48	18		T287	2
auto[0]	values[5]	values[6]	278	1			T7	17		T180	16		T178	15
auto[0]	values[5]	values[7]	328	1			T12	93		T41	25		T44	15
auto[0]	values[6]	values[0]	287	1			T43	20		T265	19		T288	20
auto[0]	values[6]	values[1]	334	1			T157	15		T23	56		T268	14
auto[0]	values[6]	values[2]	267	1			T46	72		T289	18		T207	14
auto[0]	values[6]	values[3]	429	1			T12	106		T29	28		T18	78
auto[0]	values[6]	values[4]	152	1			T41	10		T171	8		T165	7
auto[0]	values[6]	values[5]	339	1			T85	8		T37	16		T18	82
auto[0]	values[6]	values[6]	460	1			T7	14		T41	125		T197	10
auto[0]	values[6]	values[7]	226	1			T29	6		T18	31		T174	10
auto[0]	values[7]	values[0]	303	1			T6	22		T37	36		T41	10
auto[0]	values[7]	values[1]	272	1			T80	10		T23	25		T187	7
auto[0]	values[7]	values[2]	264	1			T7	9		T12	9		T201	6
auto[0]	values[7]	values[3]	363	1			T44	14		T158	21		T187	36
auto[0]	values[7]	values[4]	263	1			T7	8		T165	27		T207	23
auto[0]	values[7]	values[5]	167	1			T37	12		T18	9		T290	4
auto[0]	values[7]	values[6]	104	1			T12	20		T178	11		T168	13
auto[0]	values[7]	values[7]	345	1			T155	6		T174	12		T261	14
auto[1]	values[0]	values[0]	217	1			T12	5		T37	8		T44	6
auto[1]	values[0]	values[1]	196	1			T41	51		T42	8		T170	12
auto[1]	values[0]	values[2]	293	1			T29	9		T41	22		T187	11
auto[1]	values[0]	values[3]	147	1			T37	5		T43	15		T22	7
auto[1]	values[0]	values[4]	166	1			T152	9		T23	7		T183	8
auto[1]	values[0]	values[5]	189	1			T41	6		T43	12		T44	9
auto[1]	values[0]	values[6]	203	1			T7	9		T29	8		T43	6
auto[1]	values[0]	values[7]	133	1			T22	5		T187	27		T178	9
auto[1]	values[1]	values[0]	138	1			T7	4		T29	9		T183	9
auto[1]	values[1]	values[1]	218	1			T174	10		T224	18		T172	10
auto[1]	values[1]	values[2]	95	1			T12	9		T22	11		T169	19
auto[1]	values[1]	values[3]	198	1			T7	11		T29	11		T22	9
auto[1]	values[1]	values[4]	146	1			T12	10		T175	8		T235	10
auto[1]	values[1]	values[5]	201	1			T7	11		T22	11		T61	8
auto[1]	values[1]	values[6]	177	1			T42	7		T22	16		T23	68
auto[1]	values[1]	values[7]	255	1			T29	9		T43	8		T22	12
auto[1]	values[2]	values[0]	137	1			T37	6		T44	19		T157	9
auto[1]	values[2]	values[1]	264	1			T18	116		T182	6		T183	16
auto[1]	values[2]	values[2]	182	1			T275	8		T182	15		T184	8
auto[1]	values[2]	values[3]	117	1			T168	10		T191	9		T207	5
auto[1]	values[2]	values[4]	98	1			T18	11		T204	10		T284	15
auto[1]	values[2]	values[5]	195	1			T43	5		T157	15		T158	35
auto[1]	values[2]	values[6]	223	1			T7	25		T18	72		T193	22
auto[1]	values[2]	values[7]	279	1			T37	168		T178	19		T182	8
auto[1]	values[3]	values[0]	266	1			T37	15		T168	7		T220	21
auto[1]	values[3]	values[1]	176	1			T157	10		T23	7		T168	11
auto[1]	values[3]	values[2]	238	1			T44	9		T157	9		T174	79
auto[1]	values[3]	values[3]	99	1			T178	7		T175	9		T225	16
auto[1]	values[3]	values[4]	109	1			T18	10		T221	12		T172	14
auto[1]	values[3]	values[5]	91	1			T22	17		T158	10		T174	14
auto[1]	values[3]	values[6]	126	1			T7	5		T43	13		T22	4
auto[1]	values[3]	values[7]	125	1			T12	9		T23	6		T174	8
auto[1]	values[4]	values[0]	163	1			T22	14		T157	7		T165	9
auto[1]	values[4]	values[1]	217	1			T41	10		T44	3		T165	12
auto[1]	values[4]	values[2]	304	1			T29	40		T182	13		T175	11
auto[1]	values[4]	values[3]	197	1			T37	8		T53	10		T152	45
auto[1]	values[4]	values[4]	147	1			T12	3		T168	7		T171	7
auto[1]	values[4]	values[5]	232	1			T37	9		T29	10		T42	12
auto[1]	values[4]	values[6]	312	1			T12	13		T41	8		T18	76
auto[1]	values[4]	values[7]	140	1			T7	16		T23	26		T286	35
auto[1]	values[5]	values[0]	147	1			T7	11		T42	11		T158	25
auto[1]	values[5]	values[1]	144	1			T29	10		T18	11		T203	83
auto[1]	values[5]	values[2]	285	1			T152	23		T44	10		T157	8
auto[1]	values[5]	values[3]	184	1			T12	9		T37	9		T157	6
auto[1]	values[5]	values[4]	214	1			T174	26		T177	10		T184	20
auto[1]	values[5]	values[5]	185	1			T37	5		T178	15		T179	24
auto[1]	values[5]	values[6]	92	1			T7	3		T178	5		T150	10
auto[1]	values[5]	values[7]	192	1			T12	7		T41	37		T44	20
auto[1]	values[6]	values[0]	184	1			T43	12		T291	2		T292	6
auto[1]	values[6]	values[1]	146	1			T157	5		T23	7		T150	16
auto[1]	values[6]	values[2]	218	1			T293	4		T192	8		T207	6
auto[1]	values[6]	values[3]	164	1			T12	18		T29	10		T18	9
auto[1]	values[6]	values[4]	153	1			T41	33		T171	12		T165	13
auto[1]	values[6]	values[5]	160	1			T37	11		T18	23		T23	21
auto[1]	values[6]	values[6]	124	1			T7	6		T41	3		T168	7
auto[1]	values[6]	values[7]	191	1			T29	18		T18	9		T174	52
auto[1]	values[7]	values[0]	187	1			T37	3		T41	17		T18	53
auto[1]	values[7]	values[1]	234	1			T23	15		T187	46		T178	5
auto[1]	values[7]	values[2]	379	1			T7	26		T12	11		T199	10
auto[1]	values[7]	values[3]	228	1			T44	6		T158	7		T187	7
auto[1]	values[7]	values[4]	238	1			T7	12		T165	13		T207	17
auto[1]	values[7]	values[5]	113	1			T37	8		T166	6		T18	26
auto[1]	values[7]	values[6]	74	1			T12	6		T178	9		T168	7
auto[1]	values[7]	values[7]	218	1			T174	44		T171	4		T165	52