Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	456	1			T7	5		T8	4		T12	6
auto[ReadAddrCrossIntoMailbox]	316	1			T7	4		T8	2		T12	5
auto[ReadAddrCrossOutOfMailbox]	320	1			T7	8		T12	9		T37	4
auto[ReadAddrCrossAllMailbox]	212	1			T7	2		T12	2		T37	6
auto[ReadAddrOutsideMailbox]	3313	1			T2	2		T3	4		T7	37

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2237

1

T2

1

T3

2

T7

20

auto[1]

2380

1

T2

1

T3

2

T7

36

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	748	1			T7	7		T12	4		T144	2
read_ops[0x0b]	767	1			T7	11		T12	13		T85	2
read_ops[0x3b]	766	1			T3	2		T7	10		T12	11
read_ops[0x6b]	773	1			T2	2		T7	9		T8	4
read_ops[0xbb]	771	1			T7	8		T8	2		T12	10
read_ops[0xeb]	792	1			T3	2		T7	11		T12	12

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	24	1			T144	1		T37	1		T152	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	40	1			T144	1		T269	2		T178	2
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	15	1			T18	1		T22	1		T150	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	26	1			T168	1		T171	1		T183	2
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	21	1			T37	1		T18	1		T44	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	20	1			T7	1		T12	1		T29	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T37	1		T182	1		T169	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	19	1			T152	1		T182	1		T175	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	272	1			T7	4		T12	2		T37	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	295	1			T7	2		T12	1		T37	4
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	35	1			T7	1		T12	2		T37	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	42	1			T7	1		T37	1		T41	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	27	1			T43	1		T157	1		T23	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	22	1			T41	3		T174	1		T150	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	31	1			T43	1		T44	1		T157	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	19	1			T7	1		T12	1		T43	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T7	1		T44	2		T23	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	30	1			T12	2		T18	1		T23	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	260	1			T7	2		T12	3		T85	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	286	1			T7	5		T12	5		T85	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	31	1			T144	4		T41	1		T18	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	41	1			T144	4		T42	1		T18	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	30	1			T37	1		T41	1		T42	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	23	1			T7	2		T29	1		T42	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	31	1			T12	1		T18	2		T43	2
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	24	1			T7	1		T12	1		T18	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	22	1			T180	1		T187	1		T174	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	15	1			T37	1		T43	1		T180	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	270	1			T3	1		T7	2		T12	4
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	279	1			T3	1		T7	5		T12	5
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	36	1			T8	2		T152	1		T18	2
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	54	1			T8	2		T37	1		T29	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	15	1			T12	2		T18	2		T169	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	36	1			T7	2		T43	1		T150	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	28	1			T12	1		T29	1		T42	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	30	1			T7	1		T12	1		T44	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	9	1			T225	1		T238	1		T217	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	19	1			T7	1		T43	1		T165	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	279	1			T2	1		T7	1		T12	3
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	267	1			T2	1		T7	4		T12	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	40	1			T7	1		T37	1		T18	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	30	1			T7	1		T29	1		T152	3
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	26	1			T8	1		T12	1		T37	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	36	1			T8	1		T12	1		T37	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	31	1			T12	1		T18	1		T280	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	30	1			T12	1		T29	1		T152	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T150	1		T294	1		T61	2
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	18	1			T37	3		T43	1		T44	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	285	1			T7	1		T12	3		T29	3
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	259	1			T7	5		T12	3		T37	2
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	39	1			T7	1		T12	2		T37	4
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	44	1			T12	2		T42	1		T18	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	33	1			T12	1		T37	2		T18	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	27	1			T152	1		T165	2		T61	2
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	29	1			T7	2		T37	3		T18	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	26	1			T7	2		T12	1		T152	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	10	1			T37	1		T152	1		T180	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	23	1			T180	1		T22	1		T157	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	261	1			T3	1		T7	4		T12	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	300	1			T3	1		T7	2		T12	5