Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.32	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	1	127	99.22

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	1	127	99.22	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3627	1			T2	2		T7	20		T12	72
values[1]	3659	1			T3	18		T7	66		T37	73
values[2]	3717	1			T12	156		T37	20		T29	62
values[3]	4177	1			T7	56		T8	6		T12	244
values[4]	3790	1			T6	22		T7	20		T12	20
values[5]	4633	1			T7	51		T12	141		T144	10
values[6]	3330	1			T7	20		T12	51		T85	8
values[7]	3090	1			T7	88		T37	20		T41	109

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3681	1			T12	46		T37	93		T29	24
values[1]	3750	1			T7	40		T12	20		T37	40
values[2]	3868	1			T3	18		T7	111		T12	135
values[3]	3620	1			T6	22		T7	51		T8	6
values[4]	3509	1			T2	2		T7	51		T12	146
values[5]	3727	1			T7	40		T12	76		T37	200
values[6]	3623	1			T29	70		T155	6		T41	121
values[7]	4245	1			T7	28		T12	141		T37	27

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29287

1

T2

2

T3

18

T6

22

auto[1]

736

1

T7

12

T12

14

T37

6

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	1	127	99.22	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[6]]	[values[6]]	0	1	1

Covered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	426	1			T12	44		T156	6		T44	19
auto[0]	values[0]	values[1]	338	1			T157	18		T158	20		T159	8
auto[0]	values[0]	values[2]	390	1			T7	20		T53	10		T160	12
auto[0]	values[0]	values[3]	416	1			T37	20		T18	20		T87	2
auto[0]	values[0]	values[4]	333	1			T2	2		T12	23		T161	38
auto[0]	values[0]	values[5]	293	1			T162	14		T163	28		T164	22
auto[0]	values[0]	values[6]	668	1			T29	18		T18	205		T23	20
auto[0]	values[0]	values[7]	678	1			T37	27		T41	39		T22	40
auto[0]	values[1]	values[0]	831	1			T37	72		T41	126		T152	31
auto[0]	values[1]	values[1]	358	1			T29	23		T157	22		T165	20
auto[0]	values[1]	values[2]	365	1			T3	18		T7	33		T44	25
auto[0]	values[1]	values[3]	520	1			T29	20		T152	86		T157	43
auto[0]	values[1]	values[4]	385	1			T7	28		T48	18		T166	6
auto[0]	values[1]	values[5]	501	1			T86	24		T22	44		T82	14
auto[0]	values[1]	values[6]	263	1			T167	2		T168	20		T169	30
auto[0]	values[1]	values[7]	353	1			T29	23		T150	37		T170	20
auto[0]	values[2]	values[0]	227	1			T171	19		T172	25		T173	17
auto[0]	values[2]	values[1]	470	1			T174	127		T171	20		T175	30
auto[0]	values[2]	values[2]	595	1			T29	24		T43	32		T44	42
auto[0]	values[2]	values[3]	427	1			T176	6		T23	20		T174	20
auto[0]	values[2]	values[4]	473	1			T12	100		T18	63		T177	10
auto[0]	values[2]	values[5]	444	1			T12	55		T37	19		T29	38
auto[0]	values[2]	values[6]	277	1			T43	28		T178	27		T179	22
auto[0]	values[2]	values[7]	692	1			T41	20		T42	19		T23	40
auto[0]	values[3]	values[0]	340	1			T180	16		T178	20		T181	12
auto[0]	values[3]	values[1]	335	1			T12	20		T182	19		T183	20
auto[0]	values[3]	values[2]	627	1			T7	36		T12	103		T18	34
auto[0]	values[3]	values[3]	785	1			T8	6		T12	118		T46	72
auto[0]	values[3]	values[4]	565	1			T37	94		T18	39		T184	19
auto[0]	values[3]	values[5]	396	1			T7	20		T41	42		T158	21
auto[0]	values[3]	values[6]	620	1			T41	19		T43	20		T23	103
auto[0]	values[3]	values[7]	406	1			T23	78		T178	20		T175	20
auto[0]	values[4]	values[0]	350	1			T37	20		T29	24		T157	20
auto[0]	values[4]	values[1]	583	1			T152	20		T22	20		T80	10
auto[0]	values[4]	values[2]	341	1			T7	18		T182	20		T175	20
auto[0]	values[4]	values[3]	300	1			T6	22		T185	8		T178	20
auto[0]	values[4]	values[4]	579	1			T29	24		T22	20		T157	18
auto[0]	values[4]	values[5]	584	1			T37	178		T29	22		T186	4
auto[0]	values[4]	values[6]	444	1			T22	21		T23	19		T172	20
auto[0]	values[4]	values[7]	525	1			T12	20		T44	20		T187	95
auto[0]	values[5]	values[0]	746	1			T44	35		T174	54		T165	20
auto[0]	values[5]	values[1]	708	1			T37	19		T18	20		T22	48
auto[0]	values[5]	values[2]	458	1			T144	10		T188	8		T189	14
auto[0]	values[5]	values[3]	354	1			T7	28		T190	4		T191	18
auto[0]	values[5]	values[4]	557	1			T18	82		T192	6		T171	20
auto[0]	values[5]	values[5]	383	1			T7	20		T12	20		T22	20
auto[0]	values[5]	values[6]	627	1			T29	26		T41	46		T193	35
auto[0]	values[5]	values[7]	695	1			T12	120		T29	27		T158	21
auto[0]	values[6]	values[0]	323	1			T42	19		T194	10		T195	8
auto[0]	values[6]	values[1]	493	1			T7	20		T37	20		T42	20
auto[0]	values[6]	values[2]	421	1			T12	31		T37	38		T168	20
auto[0]	values[6]	values[3]	413	1			T85	8		T49	10		T175	20
auto[0]	values[6]	values[4]	255	1			T12	16		T150	25		T196	24
auto[0]	values[6]	values[5]	682	1			T152	49		T18	86		T43	79
auto[0]	values[6]	values[6]	225	1			T29	24		T155	6		T197	10
auto[0]	values[6]	values[7]	438	1			T42	19		T43	18		T44	20
auto[0]	values[7]	values[0]	343	1			T18	18		T175	19		T198	44
auto[0]	values[7]	values[1]	364	1			T7	19		T44	18		T22	21
auto[0]	values[7]	values[2]	593	1			T37	20		T157	23		T199	10
auto[0]	values[7]	values[3]	307	1			T7	20		T200	2		T178	19
auto[0]	values[7]	values[4]	272	1			T7	20		T201	6		T44	20
auto[0]	values[7]	values[5]	358	1			T43	20		T169	16		T202	18
auto[0]	values[7]	values[6]	417	1			T41	54		T174	148		T203	51
auto[0]	values[7]	values[7]	352	1			T7	27		T41	55		T44	21
auto[1]	values[0]	values[0]	10	1			T12	2		T44	1		T23	2
auto[1]	values[0]	values[1]	10	1			T157	2		T204	1		T173	5
auto[1]	values[0]	values[2]	4	1			T191	1		T205	2		T206	1
auto[1]	values[0]	values[3]	13	1			T22	2		T207	1		T127	1
auto[1]	values[0]	values[4]	15	1			T12	3		T23	1		T150	1
auto[1]	values[0]	values[5]	1	1			T164	1		-	-		-	-
auto[1]	values[0]	values[6]	15	1			T29	2		T158	1		T150	2
auto[1]	values[0]	values[7]	17	1			T41	1		T22	2		T158	3
auto[1]	values[1]	values[0]	11	1			T37	1		T41	2		T178	3
auto[1]	values[1]	values[1]	13	1			T29	1		T157	3		T208	2
auto[1]	values[1]	values[2]	10	1			T7	2		T182	2		T183	1
auto[1]	values[1]	values[3]	7	1			T157	2		T174	2		T127	3
auto[1]	values[1]	values[4]	11	1			T7	3		T168	2		T209	2
auto[1]	values[1]	values[5]	20	1			T22	3		T175	1		T170	1
auto[1]	values[1]	values[6]	4	1			T169	1		T172	1		T210	2
auto[1]	values[1]	values[7]	7	1			T29	2		T208	4		T203	1
auto[1]	values[2]	values[0]	21	1			T171	1		T172	3		T173	3
auto[1]	values[2]	values[1]	11	1			T174	3		T184	1		T198	1
auto[1]	values[2]	values[2]	17	1			T174	3		T169	1		T211	1
auto[1]	values[2]	values[3]	11	1			T212	2		T213	3		T214	4
auto[1]	values[2]	values[4]	8	1			T18	2		T172	2		T215	2
auto[1]	values[2]	values[5]	11	1			T12	1		T37	1		T157	1
auto[1]	values[2]	values[6]	19	1			T43	2		T178	3		T179	2
auto[1]	values[2]	values[7]	14	1			T42	1		T23	2		T191	3
auto[1]	values[3]	values[0]	12	1			T216	1		T217	4		T218	1
auto[1]	values[3]	values[1]	10	1			T182	1		T183	1		T169	2
auto[1]	values[3]	values[2]	9	1			T12	1		T18	1		T43	2
auto[1]	values[3]	values[3]	17	1			T12	2		T23	1		T150	2
auto[1]	values[3]	values[4]	20	1			T18	1		T184	2		T164	7
auto[1]	values[3]	values[5]	8	1			T41	1		T158	1		T219	2
auto[1]	values[3]	values[6]	13	1			T41	1		T178	1		T220	1
auto[1]	values[3]	values[7]	14	1			T23	5		T221	1		T211	4
auto[1]	values[4]	values[0]	11	1			T204	1		T210	1		T222	1
auto[1]	values[4]	values[1]	15	1			T182	3		T170	1		T198	2
auto[1]	values[4]	values[2]	7	1			T7	2		T198	3		T223	1
auto[1]	values[4]	values[3]	13	1			T224	2		T164	1		T225	1
auto[1]	values[4]	values[4]	8	1			T157	2		T182	1		T210	1
auto[1]	values[4]	values[5]	11	1			T37	2		T29	1		T209	2
auto[1]	values[4]	values[6]	7	1			T23	1		T164	1		T226	3
auto[1]	values[4]	values[7]	12	1			T187	1		T184	1		T227	4
auto[1]	values[5]	values[0]	12	1			T174	2		T165	1		T191	1
auto[1]	values[5]	values[1]	21	1			T37	1		T150	1		T184	3
auto[1]	values[5]	values[2]	7	1			T173	1		T228	3		T212	2
auto[1]	values[5]	values[3]	13	1			T7	3		T191	2		T229	1
auto[1]	values[5]	values[4]	12	1			T192	2		T165	1		T169	2
auto[1]	values[5]	values[5]	3	1			T219	1		T230	1		T231	1
auto[1]	values[5]	values[6]	19	1			T41	1		T208	1		T217	2
auto[1]	values[5]	values[7]	18	1			T12	1		T29	2		T158	2
auto[1]	values[6]	values[0]	8	1			T42	1		T232	2		T198	2
auto[1]	values[6]	values[1]	5	1			T171	1		T233	1		T234	1
auto[1]	values[6]	values[2]	14	1			T37	1		T175	2		T235	2
auto[1]	values[6]	values[3]	9	1			T164	2		T123	1		T222	1
auto[1]	values[6]	values[4]	9	1			T12	4		T216	2		T236	1
auto[1]	values[6]	values[5]	25	1			T152	1		T18	1		T43	6
auto[1]	values[6]	values[7]	10	1			T42	1		T43	2		T187	3
auto[1]	values[7]	values[0]	10	1			T18	2		T175	1		T237	4
auto[1]	values[7]	values[1]	16	1			T7	1		T44	2		T22	1
auto[1]	values[7]	values[2]	10	1			T157	1		T184	2		T169	1
auto[1]	values[7]	values[3]	15	1			T178	1		T175	3		T184	4
auto[1]	values[7]	values[4]	7	1			T207	2		T61	1		T219	2
auto[1]	values[7]	values[5]	7	1			T169	4		T238	1		T239	2
auto[1]	values[7]	values[6]	5	1			T203	1		T240	1		T230	1
auto[1]	values[7]	values[7]	14	1			T7	1		T158	2		T165	1