Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	892	1			T4	21		T29	11		T16	4
all_values[1]	892	1			T4	21		T29	11		T16	4
all_values[2]	892	1			T4	21		T29	11		T16	4
all_values[3]	892	1			T4	21		T29	11		T16	4
all_values[4]	892	1			T4	21		T29	11		T16	4
all_values[5]	892	1			T4	21		T29	11		T16	4
all_values[6]	892	1			T4	21		T29	11		T16	4
all_values[7]	892	1			T4	21		T29	11		T16	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3793

1

T4

89

T29

36

T16

16

auto[1]

3343

1

T4

79

T29

52

T16

16

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2908

1

T4

71

T29

31

T16

18

auto[1]

4228

1

T4

97

T29

57

T16

14

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4101

1

T4

100

T29

48

T16

22

auto[1]

3035

1

T4

68

T29

40

T16

10

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	192	1			T4	3		T29	1		T16	2
all_values[0]	auto[0]	auto[0]	auto[1]	71	1			T4	3		T29	2		T17	2
all_values[0]	auto[0]	auto[1]	auto[0]	165	1			T4	5		T29	1		T18	2
all_values[0]	auto[0]	auto[1]	auto[1]	86	1			T4	3		T29	1		T17	2
all_values[0]	auto[1]	auto[0]	auto[1]	200	1			T4	4		T29	1		T16	1
all_values[0]	auto[1]	auto[1]	auto[1]	178	1			T4	3		T29	5		T16	1
all_values[1]	auto[0]	auto[0]	auto[0]	181	1			T4	2		T29	3		T16	1
all_values[1]	auto[0]	auto[0]	auto[1]	69	1			T4	3		T29	1		T17	2
all_values[1]	auto[0]	auto[1]	auto[0]	150	1			T4	2		T29	2		T16	2
all_values[1]	auto[0]	auto[1]	auto[1]	102	1			T4	2		T29	1		T17	1
all_values[1]	auto[1]	auto[0]	auto[1]	195	1			T4	5		T29	2		T16	1
all_values[1]	auto[1]	auto[1]	auto[1]	195	1			T4	7		T29	2		T17	2
all_values[2]	auto[0]	auto[0]	auto[0]	179	1			T4	3		T29	3		T16	1
all_values[2]	auto[0]	auto[0]	auto[1]	90	1			T4	3		T29	1		T18	2
all_values[2]	auto[0]	auto[1]	auto[0]	154	1			T4	3		T29	1		T16	3
all_values[2]	auto[0]	auto[1]	auto[1]	90	1			T4	3		T29	2		T17	1
all_values[2]	auto[1]	auto[0]	auto[1]	199	1			T4	6		T29	1		T17	1
all_values[2]	auto[1]	auto[1]	auto[1]	180	1			T4	3		T29	3		T17	3
all_values[3]	auto[0]	auto[0]	auto[0]	181	1			T4	6		T16	1		T17	3
all_values[3]	auto[0]	auto[0]	auto[1]	75	1			T4	4		T29	1		T17	1
all_values[3]	auto[0]	auto[1]	auto[0]	150	1			T4	2		T29	1		T17	2
all_values[3]	auto[0]	auto[1]	auto[1]	87	1			T4	1		T29	1		T16	1
all_values[3]	auto[1]	auto[0]	auto[1]	213	1			T4	6		T29	4		T17	3
all_values[3]	auto[1]	auto[1]	auto[1]	186	1			T4	2		T29	4		T16	2
all_values[4]	auto[0]	auto[0]	auto[0]	193	1			T4	5		T29	2		T16	1
all_values[4]	auto[0]	auto[0]	auto[1]	76	1			T4	1		T17	3		T20	3
all_values[4]	auto[0]	auto[1]	auto[0]	170	1			T4	8		T29	2		T17	2
all_values[4]	auto[0]	auto[1]	auto[1]	100	1			T29	2		T16	2		T18	2
all_values[4]	auto[1]	auto[0]	auto[1]	208	1			T4	4		T29	2		T16	1
all_values[4]	auto[1]	auto[1]	auto[1]	145	1			T4	3		T29	3		T17	1
all_values[5]	auto[0]	auto[0]	auto[0]	257	1			T4	5		T29	1		T16	2
all_values[5]	auto[0]	auto[1]	auto[0]	254	1			T4	6		T29	3		T17	3
all_values[5]	auto[1]	auto[0]	auto[1]	216	1			T4	6		T29	1		T16	2
all_values[5]	auto[1]	auto[1]	auto[1]	165	1			T4	4		T29	6		T17	2
all_values[6]	auto[0]	auto[0]	auto[0]	181	1			T4	5		T16	2		T17	3
all_values[6]	auto[0]	auto[0]	auto[1]	92	1			T29	3		T18	2		T19	2
all_values[6]	auto[0]	auto[1]	auto[0]	155	1			T4	6		T29	3		T16	2
all_values[6]	auto[0]	auto[1]	auto[1]	72	1			T4	2		T29	1		T17	2
all_values[6]	auto[1]	auto[0]	auto[1]	236	1			T4	6		T29	2		T17	1
all_values[6]	auto[1]	auto[1]	auto[1]	156	1			T4	2		T29	2		T17	3
all_values[7]	auto[0]	auto[0]	auto[0]	184	1			T4	4		T29	2		T17	3
all_values[7]	auto[0]	auto[0]	auto[1]	91	1			T29	1		T17	1		T18	3
all_values[7]	auto[0]	auto[1]	auto[0]	162	1			T4	6		T29	6		T16	1
all_values[7]	auto[0]	auto[1]	auto[1]	92	1			T4	4		T16	1		T17	1
all_values[7]	auto[1]	auto[0]	auto[1]	214	1			T4	5		T29	2		T16	1
all_values[7]	auto[1]	auto[1]	auto[1]	149	1			T4	2		T16	1		T17	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal