Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1863

1

T5

8

T7

1

T10

5

auto[1]

1883

1

T5

7

T10

7

T25

12

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1811

1

T5

11

T7

1

T26

11

auto[1]

1935

1

T5

4

T10

12

T25

26

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3059

1

T5

10

T10

12

T25

26

auto[1]

687

1

T5

5

T7

1

T26

5

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	732	1			T5	3		T10	1		T25	4
valid[1]	798	1			T5	4		T10	3		T25	5
valid[2]	737	1			T5	1		T10	1		T25	9
valid[3]	734	1			T5	2		T10	5		T25	5
valid[4]	745	1			T5	5		T7	1		T10	2

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	101	1			T5	1		T26	1		T19	1
auto[0]	auto[0]	valid[0]	auto[1]	204	1			T10	1		T25	2		T19	2
auto[0]	auto[0]	valid[1]	auto[0]	125	1			T5	1		T29	1		T74	2
auto[0]	auto[0]	valid[1]	auto[1]	203	1			T10	1		T25	4		T27	1
auto[0]	auto[0]	valid[2]	auto[0]	115	1			T26	3		T29	1		T30	2
auto[0]	auto[0]	valid[2]	auto[1]	183	1			T25	3		T27	2		T29	3
auto[0]	auto[0]	valid[3]	auto[0]	110	1			T26	1		T29	3		T19	1
auto[0]	auto[0]	valid[3]	auto[1]	181	1			T5	1		T10	1		T25	3
auto[0]	auto[0]	valid[4]	auto[0]	110	1			T5	2		T26	1		T20	2
auto[0]	auto[0]	valid[4]	auto[1]	206	1			T5	1		T10	2		T25	2
auto[0]	auto[1]	valid[0]	auto[0]	104	1			T29	1		T30	1		T41	1
auto[0]	auto[1]	valid[0]	auto[1]	177	1			T5	1		T25	2		T77	1
auto[0]	auto[1]	valid[1]	auto[0]	119	1			T5	1		T29	1		T74	4
auto[0]	auto[1]	valid[1]	auto[1]	212	1			T10	2		T25	1		T29	2
auto[0]	auto[1]	valid[2]	auto[0]	103	1			T29	2		T74	2		T44	1
auto[0]	auto[1]	valid[2]	auto[1]	201	1			T10	1		T25	6		T27	2
auto[0]	auto[1]	valid[3]	auto[0]	121	1			T19	1		T44	3		T153	1
auto[0]	auto[1]	valid[3]	auto[1]	187	1			T5	1		T10	4		T25	2
auto[0]	auto[1]	valid[4]	auto[0]	116	1			T5	1		T29	1		T74	1
auto[0]	auto[1]	valid[4]	auto[1]	181	1			T25	1		T77	2		T78	3
auto[1]	auto[0]	valid[0]	auto[0]	71	1			T26	2		T41	1		T153	1
auto[1]	auto[0]	valid[1]	auto[0]	58	1			T29	1		T308	1		T147	1
auto[1]	auto[0]	valid[2]	auto[0]	69	1			T5	1		T29	2		T74	2
auto[1]	auto[0]	valid[3]	auto[0]	62	1			T44	1		T153	1		T157	2
auto[1]	auto[0]	valid[4]	auto[0]	65	1			T5	1		T7	1		T74	1
auto[1]	auto[1]	valid[0]	auto[0]	75	1			T5	1		T26	1		T29	1
auto[1]	auto[1]	valid[1]	auto[0]	81	1			T5	2		T26	1		T29	3
auto[1]	auto[1]	valid[2]	auto[0]	66	1			T26	1		T19	1		T74	2
auto[1]	auto[1]	valid[3]	auto[0]	73	1			T29	2		T306	1		T157	2
auto[1]	auto[1]	valid[4]	auto[0]	67	1			T19	1		T74	1		T157	3

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal