Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

45677

1

T5

246

T7

64

T11

7

auto[1]

20266

1

T5

23

T10

98

T25

424

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

49079

1

T5

175

T7

44

T10

98

auto[1]

16864

1

T5

94

T7

20

T11

6

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	33871	1			T5	129		T7	38		T10	51
others[1]	5759	1			T5	29		T7	4		T10	5
others[2]	5495	1			T5	24		T7	5		T10	9
others[3]	6279	1			T5	31		T7	8		T10	12
interest[1]	3611	1			T5	15		T7	2		T10	4
interest[4]	22246	1			T5	88		T7	22		T10	36
interest[64]	10928	1			T5	41		T7	7		T10	17

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	14775	1			T5	75		T7	21		T26	117
auto[0]	auto[0]	others[1]	2544	1			T5	18		T7	4		T26	19
auto[0]	auto[0]	others[2]	2353	1			T5	13		T7	4		T26	18
auto[0]	auto[0]	others[3]	2757	1			T5	15		T7	7		T26	16
auto[0]	auto[0]	interest[1]	1564	1			T5	9		T7	2		T26	15
auto[0]	auto[0]	interest[4]	9656	1			T5	51		T7	13		T26	79
auto[0]	auto[0]	interest[64]	4820	1			T5	22		T7	6		T11	1
auto[0]	auto[1]	others[0]	10551	1			T5	11		T10	51		T25	224
auto[0]	auto[1]	others[1]	1740	1			T5	1		T10	5		T25	37
auto[0]	auto[1]	others[2]	1742	1			T5	1		T10	9		T25	40
auto[0]	auto[1]	others[3]	1841	1			T5	3		T10	12		T25	44
auto[0]	auto[1]	interest[1]	1103	1			T5	2		T10	4		T25	23
auto[0]	auto[1]	interest[4]	7042	1			T5	6		T10	36		T25	145
auto[0]	auto[1]	interest[64]	3289	1			T5	5		T10	17		T25	56
auto[1]	auto[0]	others[0]	8545	1			T5	43		T7	17		T11	4
auto[1]	auto[0]	others[1]	1475	1			T5	10		T11	1		T26	9
auto[1]	auto[0]	others[2]	1400	1			T5	10		T7	1		T26	7
auto[1]	auto[0]	others[3]	1681	1			T5	13		T7	1		T26	6
auto[1]	auto[0]	interest[1]	944	1			T5	4		T26	5		T28	1
auto[1]	auto[0]	interest[4]	5548	1			T5	31		T7	9		T11	3
auto[1]	auto[0]	interest[64]	2819	1			T5	14		T7	1		T11	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal