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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.06 98.45 94.08 98.62 89.36 97.29 95.43 99.21


Total test records in report: 1150
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T92 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.3414821072 Aug 07 04:57:47 PM PDT 24 Aug 07 04:57:55 PM PDT 24 1249201805 ps
T94 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.3980120145 Aug 07 04:57:59 PM PDT 24 Aug 07 04:58:05 PM PDT 24 97769530 ps
T93 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.4159023821 Aug 07 04:57:44 PM PDT 24 Aug 07 04:58:04 PM PDT 24 312543482 ps
T95 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.3064477594 Aug 07 04:57:45 PM PDT 24 Aug 07 04:57:50 PM PDT 24 282709550 ps
T137 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1735503921 Aug 07 04:57:50 PM PDT 24 Aug 07 04:57:55 PM PDT 24 1014846465 ps
T1044 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.1402739730 Aug 07 04:57:49 PM PDT 24 Aug 07 04:57:49 PM PDT 24 14712292 ps
T1045 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.313415272 Aug 07 04:57:35 PM PDT 24 Aug 07 04:57:36 PM PDT 24 19108753 ps
T1046 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1674333330 Aug 07 04:57:58 PM PDT 24 Aug 07 04:57:59 PM PDT 24 12135540 ps
T101 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.1716946818 Aug 07 04:57:40 PM PDT 24 Aug 07 04:57:41 PM PDT 24 107721435 ps
T243 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.2756305117 Aug 07 04:57:34 PM PDT 24 Aug 07 04:57:55 PM PDT 24 1204554355 ps
T138 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.1484242409 Aug 07 04:57:47 PM PDT 24 Aug 07 04:57:50 PM PDT 24 625291160 ps
T103 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1328325269 Aug 07 04:57:34 PM PDT 24 Aug 07 04:57:37 PM PDT 24 84526018 ps
T146 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.3158827931 Aug 07 04:57:57 PM PDT 24 Aug 07 04:58:00 PM PDT 24 775608585 ps
T1047 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.3497263586 Aug 07 04:57:48 PM PDT 24 Aug 07 04:57:49 PM PDT 24 54994312 ps
T112 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.4279322654 Aug 07 04:57:42 PM PDT 24 Aug 07 04:57:44 PM PDT 24 91111756 ps
T71 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.1999329070 Aug 07 04:57:38 PM PDT 24 Aug 07 04:57:40 PM PDT 24 30586921 ps
T1048 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3781725343 Aug 07 04:58:03 PM PDT 24 Aug 07 04:58:06 PM PDT 24 327097989 ps
T1049 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.900071717 Aug 07 04:57:42 PM PDT 24 Aug 07 04:57:45 PM PDT 24 75918774 ps
T113 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.3092913549 Aug 07 04:57:53 PM PDT 24 Aug 07 04:57:55 PM PDT 24 38490968 ps
T96 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.4147216497 Aug 07 04:57:37 PM PDT 24 Aug 07 04:57:41 PM PDT 24 55972720 ps
T114 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.1585415056 Aug 07 04:57:35 PM PDT 24 Aug 07 04:57:39 PM PDT 24 273259019 ps
T1050 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.2588076721 Aug 07 04:57:59 PM PDT 24 Aug 07 04:58:00 PM PDT 24 17114493 ps
T1051 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.3823545883 Aug 07 04:57:57 PM PDT 24 Aug 07 04:57:58 PM PDT 24 15863618 ps
T1052 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.2990427759 Aug 07 04:57:55 PM PDT 24 Aug 07 04:57:56 PM PDT 24 43367413 ps
T1053 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.3839129576 Aug 07 04:57:31 PM PDT 24 Aug 07 04:57:31 PM PDT 24 25232971 ps
T72 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2657672449 Aug 07 04:57:38 PM PDT 24 Aug 07 04:57:39 PM PDT 24 35431557 ps
T1054 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.941923935 Aug 07 04:57:46 PM PDT 24 Aug 07 04:57:49 PM PDT 24 141248754 ps
T73 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.734420226 Aug 07 04:57:36 PM PDT 24 Aug 07 04:57:37 PM PDT 24 80691717 ps
T97 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.3107405486 Aug 07 04:57:30 PM PDT 24 Aug 07 04:57:33 PM PDT 24 1619962607 ps
T1055 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.3891521129 Aug 07 04:57:37 PM PDT 24 Aug 07 04:57:38 PM PDT 24 28937791 ps
T115 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.3193598541 Aug 07 04:57:38 PM PDT 24 Aug 07 04:57:40 PM PDT 24 725218305 ps
T1056 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.754748158 Aug 07 04:57:57 PM PDT 24 Aug 07 04:57:58 PM PDT 24 94504490 ps
T100 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.780480798 Aug 07 04:57:42 PM PDT 24 Aug 07 04:57:45 PM PDT 24 110137402 ps
T253 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.2454431403 Aug 07 04:57:44 PM PDT 24 Aug 07 04:57:58 PM PDT 24 1322558494 ps
T1057 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.2147353625 Aug 07 04:57:35 PM PDT 24 Aug 07 04:57:37 PM PDT 24 113122426 ps
T1058 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.2134909636 Aug 07 04:57:47 PM PDT 24 Aug 07 04:57:48 PM PDT 24 13542509 ps
T1059 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.1272762337 Aug 07 04:57:58 PM PDT 24 Aug 07 04:57:59 PM PDT 24 34732873 ps
T1060 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3074181318 Aug 07 04:57:37 PM PDT 24 Aug 07 04:57:40 PM PDT 24 80825973 ps
T1061 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.721005759 Aug 07 04:58:10 PM PDT 24 Aug 07 04:58:13 PM PDT 24 427366904 ps
T116 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.2139645503 Aug 07 04:57:39 PM PDT 24 Aug 07 04:57:40 PM PDT 24 189113146 ps
T246 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.2429789135 Aug 07 04:57:52 PM PDT 24 Aug 07 04:57:59 PM PDT 24 228037023 ps
T118 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.1189962060 Aug 07 04:57:39 PM PDT 24 Aug 07 04:57:41 PM PDT 24 44670422 ps
T1062 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.3391867094 Aug 07 04:57:58 PM PDT 24 Aug 07 04:57:59 PM PDT 24 12356490 ps
T1063 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.2165327592 Aug 07 04:58:03 PM PDT 24 Aug 07 04:58:04 PM PDT 24 32871414 ps
T1064 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.2624334679 Aug 07 04:57:34 PM PDT 24 Aug 07 04:57:35 PM PDT 24 47833166 ps
T117 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3559033448 Aug 07 04:57:38 PM PDT 24 Aug 07 04:57:39 PM PDT 24 73098211 ps
T98 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.2836096799 Aug 07 04:57:37 PM PDT 24 Aug 07 04:57:42 PM PDT 24 612781701 ps
T1065 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.596816361 Aug 07 04:57:33 PM PDT 24 Aug 07 04:57:47 PM PDT 24 2263443845 ps
T1066 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.1739919448 Aug 07 04:58:04 PM PDT 24 Aug 07 04:58:05 PM PDT 24 56889836 ps
T119 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.2478954054 Aug 07 04:57:44 PM PDT 24 Aug 07 04:57:47 PM PDT 24 163778060 ps
T1067 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.1006385565 Aug 07 04:57:33 PM PDT 24 Aug 07 04:57:34 PM PDT 24 31105387 ps
T1068 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.1139017003 Aug 07 04:57:45 PM PDT 24 Aug 07 04:57:47 PM PDT 24 255697077 ps
T1069 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.3784371182 Aug 07 04:57:53 PM PDT 24 Aug 07 04:58:06 PM PDT 24 785559985 ps
T120 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.3745214625 Aug 07 04:57:59 PM PDT 24 Aug 07 04:58:01 PM PDT 24 86862482 ps
T1070 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.3815970415 Aug 07 04:57:49 PM PDT 24 Aug 07 04:57:51 PM PDT 24 458307711 ps
T1071 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3228417391 Aug 07 04:57:40 PM PDT 24 Aug 07 04:57:43 PM PDT 24 46205764 ps
T102 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.2620839756 Aug 07 04:57:42 PM PDT 24 Aug 07 04:57:45 PM PDT 24 165157996 ps
T1072 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2368403649 Aug 07 04:57:50 PM PDT 24 Aug 07 04:57:51 PM PDT 24 14265044 ps
T1073 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.1451158773 Aug 07 04:57:44 PM PDT 24 Aug 07 04:57:46 PM PDT 24 387440693 ps
T247 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.1387873919 Aug 07 04:57:41 PM PDT 24 Aug 07 04:57:59 PM PDT 24 2977775264 ps
T1074 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.278678073 Aug 07 04:57:50 PM PDT 24 Aug 07 04:57:54 PM PDT 24 199176677 ps
T99 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.3832503716 Aug 07 04:57:38 PM PDT 24 Aug 07 04:57:41 PM PDT 24 191161154 ps
T1075 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.3667872068 Aug 07 04:57:49 PM PDT 24 Aug 07 04:58:04 PM PDT 24 622493286 ps
T121 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.3781920145 Aug 07 04:57:59 PM PDT 24 Aug 07 04:58:01 PM PDT 24 47969854 ps
T1076 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.404302125 Aug 07 04:57:33 PM PDT 24 Aug 07 04:57:34 PM PDT 24 12640414 ps
T1077 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.4012838390 Aug 07 04:57:44 PM PDT 24 Aug 07 04:57:48 PM PDT 24 793452475 ps
T1078 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.3657949233 Aug 07 04:57:57 PM PDT 24 Aug 07 04:57:58 PM PDT 24 42518299 ps
T122 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.1425029669 Aug 07 04:57:40 PM PDT 24 Aug 07 04:57:42 PM PDT 24 67954365 ps
T1079 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3655933225 Aug 07 04:57:41 PM PDT 24 Aug 07 04:57:43 PM PDT 24 112516923 ps
T1080 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.1704643114 Aug 07 04:57:43 PM PDT 24 Aug 07 04:57:46 PM PDT 24 613417674 ps
T1081 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.129664498 Aug 07 04:57:50 PM PDT 24 Aug 07 04:57:52 PM PDT 24 43687907 ps
T1082 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.1388001894 Aug 07 04:57:35 PM PDT 24 Aug 07 04:57:38 PM PDT 24 1185631494 ps
T1083 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.3514083457 Aug 07 04:58:43 PM PDT 24 Aug 07 04:58:44 PM PDT 24 19107297 ps
T1084 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.2357153281 Aug 07 04:57:50 PM PDT 24 Aug 07 04:57:50 PM PDT 24 16671774 ps
T1085 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.438397353 Aug 07 04:58:02 PM PDT 24 Aug 07 04:58:04 PM PDT 24 74413119 ps
T1086 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.4115233757 Aug 07 04:57:33 PM PDT 24 Aug 07 04:57:34 PM PDT 24 101740401 ps
T1087 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.3427070234 Aug 07 04:57:50 PM PDT 24 Aug 07 04:57:51 PM PDT 24 57401024 ps
T252 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.2581071416 Aug 07 04:57:34 PM PDT 24 Aug 07 04:57:50 PM PDT 24 722486207 ps
T1088 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2399806962 Aug 07 04:57:41 PM PDT 24 Aug 07 04:57:43 PM PDT 24 21375924 ps
T1089 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.1061219908 Aug 07 04:57:42 PM PDT 24 Aug 07 04:57:47 PM PDT 24 203596196 ps
T1090 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.2917380761 Aug 07 04:57:39 PM PDT 24 Aug 07 04:57:48 PM PDT 24 314882135 ps
T1091 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.3781045125 Aug 07 04:57:34 PM PDT 24 Aug 07 04:57:35 PM PDT 24 15445131 ps
T1092 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.1174991811 Aug 07 04:57:52 PM PDT 24 Aug 07 04:57:55 PM PDT 24 149268786 ps
T249 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.394305557 Aug 07 04:58:10 PM PDT 24 Aug 07 04:58:22 PM PDT 24 791426219 ps
T1093 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.3781310620 Aug 07 04:57:47 PM PDT 24 Aug 07 04:57:47 PM PDT 24 49342160 ps
T1094 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.657972991 Aug 07 04:57:48 PM PDT 24 Aug 07 04:57:49 PM PDT 24 45324701 ps
T1095 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.2337342661 Aug 07 04:57:33 PM PDT 24 Aug 07 04:57:42 PM PDT 24 1478223591 ps
T1096 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.2751266159 Aug 07 04:57:48 PM PDT 24 Aug 07 04:57:49 PM PDT 24 40443706 ps
T104 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2916004310 Aug 07 04:57:40 PM PDT 24 Aug 07 04:57:42 PM PDT 24 187719639 ps
T250 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.654196617 Aug 07 04:57:39 PM PDT 24 Aug 07 04:58:00 PM PDT 24 843158017 ps
T1097 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.1253653660 Aug 07 04:57:48 PM PDT 24 Aug 07 04:57:49 PM PDT 24 17605611 ps
T1098 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.3153876595 Aug 07 04:57:53 PM PDT 24 Aug 07 04:57:55 PM PDT 24 70400631 ps
T1099 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.3803472270 Aug 07 04:57:35 PM PDT 24 Aug 07 04:57:43 PM PDT 24 436553679 ps
T1100 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.1577261621 Aug 07 04:57:57 PM PDT 24 Aug 07 04:57:57 PM PDT 24 18235345 ps
T1101 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.1088739647 Aug 07 04:57:50 PM PDT 24 Aug 07 04:57:52 PM PDT 24 10897360 ps
T1102 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.2028184047 Aug 07 04:57:51 PM PDT 24 Aug 07 04:57:54 PM PDT 24 74186095 ps
T1103 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3883319624 Aug 07 04:57:40 PM PDT 24 Aug 07 04:57:41 PM PDT 24 42758586 ps
T1104 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.4077165701 Aug 07 04:57:42 PM PDT 24 Aug 07 04:58:16 PM PDT 24 1839232147 ps
T1105 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3725434310 Aug 07 04:57:36 PM PDT 24 Aug 07 04:57:38 PM PDT 24 241547306 ps
T1106 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.2193756392 Aug 07 04:58:02 PM PDT 24 Aug 07 04:58:03 PM PDT 24 132644407 ps
T1107 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1397428885 Aug 07 04:57:43 PM PDT 24 Aug 07 04:57:46 PM PDT 24 40630841 ps
T1108 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2470861741 Aug 07 04:57:42 PM PDT 24 Aug 07 04:57:46 PM PDT 24 120522202 ps
T1109 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.3838337915 Aug 07 04:57:42 PM PDT 24 Aug 07 04:57:44 PM PDT 24 131508638 ps
T1110 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.3126021275 Aug 07 04:57:47 PM PDT 24 Aug 07 04:57:48 PM PDT 24 136595844 ps
T1111 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.3290373368 Aug 07 04:57:28 PM PDT 24 Aug 07 04:57:29 PM PDT 24 11538365 ps
T1112 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.889453877 Aug 07 04:57:42 PM PDT 24 Aug 07 04:57:46 PM PDT 24 583052297 ps
T1113 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.301614762 Aug 07 04:57:38 PM PDT 24 Aug 07 04:57:40 PM PDT 24 83007990 ps
T1114 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.600095388 Aug 07 04:57:45 PM PDT 24 Aug 07 04:57:46 PM PDT 24 59476544 ps
T1115 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.203923109 Aug 07 04:57:49 PM PDT 24 Aug 07 04:57:51 PM PDT 24 883080139 ps
T1116 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.2764849960 Aug 07 04:57:33 PM PDT 24 Aug 07 04:57:54 PM PDT 24 302568031 ps
T1117 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.3885427755 Aug 07 04:57:40 PM PDT 24 Aug 07 04:57:40 PM PDT 24 20145978 ps
T1118 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3451941987 Aug 07 04:57:42 PM PDT 24 Aug 07 04:57:53 PM PDT 24 306902037 ps
T1119 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.1984873211 Aug 07 04:58:38 PM PDT 24 Aug 07 04:58:39 PM PDT 24 17855211 ps
T1120 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.2542883443 Aug 07 04:57:48 PM PDT 24 Aug 07 04:57:51 PM PDT 24 160736615 ps
T1121 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.53104731 Aug 07 04:57:45 PM PDT 24 Aug 07 04:57:49 PM PDT 24 102498968 ps
T1122 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.3615205954 Aug 07 04:57:42 PM PDT 24 Aug 07 04:57:43 PM PDT 24 230978182 ps
T251 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.631648147 Aug 07 04:57:37 PM PDT 24 Aug 07 04:58:04 PM PDT 24 816396797 ps
T1123 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.993389602 Aug 07 04:58:08 PM PDT 24 Aug 07 04:58:09 PM PDT 24 32216407 ps
T1124 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1909761895 Aug 07 04:57:44 PM PDT 24 Aug 07 04:58:20 PM PDT 24 3069586218 ps
T1125 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.2334911222 Aug 07 04:58:08 PM PDT 24 Aug 07 04:58:15 PM PDT 24 206087267 ps
T1126 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.2257076519 Aug 07 04:57:33 PM PDT 24 Aug 07 04:57:36 PM PDT 24 145404114 ps
T1127 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.2706896530 Aug 07 04:57:55 PM PDT 24 Aug 07 04:57:56 PM PDT 24 27439028 ps
T248 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.3907422909 Aug 07 04:57:49 PM PDT 24 Aug 07 04:58:04 PM PDT 24 2636904681 ps
T1128 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.3126348763 Aug 07 04:57:38 PM PDT 24 Aug 07 04:57:39 PM PDT 24 22591651 ps
T1129 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2441126155 Aug 07 04:57:39 PM PDT 24 Aug 07 04:57:43 PM PDT 24 1082754562 ps
T1130 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.922395150 Aug 07 04:57:49 PM PDT 24 Aug 07 04:57:52 PM PDT 24 339634303 ps
T1131 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3036787581 Aug 07 04:57:48 PM PDT 24 Aug 07 04:57:50 PM PDT 24 170123992 ps
T244 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.491927991 Aug 07 04:57:35 PM PDT 24 Aug 07 04:57:49 PM PDT 24 633938157 ps
T1132 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.397515897 Aug 07 04:57:29 PM PDT 24 Aug 07 04:57:31 PM PDT 24 124889827 ps
T1133 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.488041328 Aug 07 04:57:49 PM PDT 24 Aug 07 04:57:49 PM PDT 24 16406604 ps
T1134 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.467016901 Aug 07 04:57:46 PM PDT 24 Aug 07 04:57:48 PM PDT 24 156410407 ps
T1135 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.1990573549 Aug 07 04:57:40 PM PDT 24 Aug 07 04:57:42 PM PDT 24 402572360 ps
T1136 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.4151146057 Aug 07 04:57:41 PM PDT 24 Aug 07 04:57:43 PM PDT 24 98260210 ps
T1137 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1034261547 Aug 07 04:57:42 PM PDT 24 Aug 07 04:57:54 PM PDT 24 828566603 ps
T1138 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2006060544 Aug 07 04:57:45 PM PDT 24 Aug 07 04:57:49 PM PDT 24 123316452 ps
T241 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.3046448194 Aug 07 04:57:42 PM PDT 24 Aug 07 04:57:47 PM PDT 24 81361292 ps
T1139 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2222567458 Aug 07 04:57:50 PM PDT 24 Aug 07 04:57:52 PM PDT 24 14163826 ps
T1140 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3563665862 Aug 07 04:57:49 PM PDT 24 Aug 07 04:57:53 PM PDT 24 208488672 ps
T1141 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.1866741297 Aug 07 04:57:44 PM PDT 24 Aug 07 04:57:46 PM PDT 24 192511690 ps
T245 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.3494650323 Aug 07 04:57:37 PM PDT 24 Aug 07 04:57:59 PM PDT 24 3832119905 ps
T1142 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.713600029 Aug 07 04:57:34 PM PDT 24 Aug 07 04:58:00 PM PDT 24 1253980613 ps
T242 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.870715203 Aug 07 04:57:43 PM PDT 24 Aug 07 04:57:48 PM PDT 24 500242081 ps
T1143 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.3666328775 Aug 07 04:57:36 PM PDT 24 Aug 07 04:57:42 PM PDT 24 317642244 ps
T1144 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3024776335 Aug 07 04:57:32 PM PDT 24 Aug 07 04:58:07 PM PDT 24 10021933492 ps
T1145 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.4231403652 Aug 07 04:57:35 PM PDT 24 Aug 07 04:57:52 PM PDT 24 3056792761 ps
T1146 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3524119286 Aug 07 04:57:45 PM PDT 24 Aug 07 04:57:48 PM PDT 24 123159126 ps
T1147 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.2296449049 Aug 07 04:57:42 PM PDT 24 Aug 07 04:57:43 PM PDT 24 42721587 ps
T1148 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.447634759 Aug 07 04:57:32 PM PDT 24 Aug 07 04:57:35 PM PDT 24 202762716 ps
T1149 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.101161279 Aug 07 04:57:45 PM PDT 24 Aug 07 04:57:47 PM PDT 24 91156104 ps
T1150 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.3719094572 Aug 07 04:57:38 PM PDT 24 Aug 07 04:57:41 PM PDT 24 88550007 ps

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.1392873022
Short name T7
Test name
Test status
Simulation time 48128814995 ps
CPU time 390.28 seconds
Started Aug 07 06:21:54 PM PDT 24
Finished Aug 07 06:28:24 PM PDT 24
Peak memory 264620 kb
Host smart-77af8a59-1b3b-4691-b368-1d1daade3e60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392873022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.1392873022
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.1732104714
Short name T29
Test name
Test status
Simulation time 32407856996 ps
CPU time 275.21 seconds
Started Aug 07 06:20:55 PM PDT 24
Finished Aug 07 06:25:31 PM PDT 24
Peak memory 274532 kb
Host smart-bc7d22a0-addf-45ff-9c56-4352be68efac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732104714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.1732104714
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.2891525018
Short name T22
Test name
Test status
Simulation time 392590516683 ps
CPU time 643.68 seconds
Started Aug 07 06:20:54 PM PDT 24
Finished Aug 07 06:31:38 PM PDT 24
Peak memory 270584 kb
Host smart-d8afe2c5-f6b0-4001-b21a-2f1b8911a9bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891525018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.2891525018
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.3414821072
Short name T92
Test name
Test status
Simulation time 1249201805 ps
CPU time 8 seconds
Started Aug 07 04:57:47 PM PDT 24
Finished Aug 07 04:57:55 PM PDT 24
Peak memory 215776 kb
Host smart-9ffcebbd-c3dc-40e6-9ef4-4eaab6e7c18d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414821072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.3414821072
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.2978644750
Short name T178
Test name
Test status
Simulation time 17023061866 ps
CPU time 244.13 seconds
Started Aug 07 06:21:25 PM PDT 24
Finished Aug 07 06:25:29 PM PDT 24
Peak memory 268992 kb
Host smart-307a61d5-03aa-4237-aa41-a4d08d91a9f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978644750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.2978644750
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.542190084
Short name T54
Test name
Test status
Simulation time 16193826 ps
CPU time 0.78 seconds
Started Aug 07 06:19:47 PM PDT 24
Finished Aug 07 06:19:48 PM PDT 24
Peak memory 216700 kb
Host smart-35508c46-99dc-4070-bded-a0d2ab16dd32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542190084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.542190084
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.3064477594
Short name T95
Test name
Test status
Simulation time 282709550 ps
CPU time 3.99 seconds
Started Aug 07 04:57:45 PM PDT 24
Finished Aug 07 04:57:50 PM PDT 24
Peak memory 215980 kb
Host smart-7ae52038-bd1c-495a-9c20-9fb66512556b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064477594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
3064477594
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.2861569000
Short name T12
Test name
Test status
Simulation time 4744756305 ps
CPU time 85.04 seconds
Started Aug 07 06:21:52 PM PDT 24
Finished Aug 07 06:23:17 PM PDT 24
Peak memory 253832 kb
Host smart-f354ef2e-c5d8-453f-834e-2d15a8d795d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861569000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.2861569000
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.2786835754
Short name T184
Test name
Test status
Simulation time 191187645873 ps
CPU time 278.33 seconds
Started Aug 07 06:21:19 PM PDT 24
Finished Aug 07 06:25:58 PM PDT 24
Peak memory 266280 kb
Host smart-9d5245f5-43e4-41f4-86db-df932b7d04af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786835754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.2786835754
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.2634490574
Short name T198
Test name
Test status
Simulation time 63622491405 ps
CPU time 499.97 seconds
Started Aug 07 06:21:55 PM PDT 24
Finished Aug 07 06:30:15 PM PDT 24
Peak memory 271208 kb
Host smart-3d9e772b-0484-42fe-9d20-322ad2c46e95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634490574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.2634490574
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.3363923882
Short name T81
Test name
Test status
Simulation time 406174825 ps
CPU time 11.48 seconds
Started Aug 07 06:20:20 PM PDT 24
Finished Aug 07 06:20:32 PM PDT 24
Peak memory 225292 kb
Host smart-d5dbe974-5fe0-4a7e-8e3e-df5b7995e6a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363923882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.3363923882
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.3358659896
Short name T23
Test name
Test status
Simulation time 5755832463 ps
CPU time 127.95 seconds
Started Aug 07 06:21:38 PM PDT 24
Finished Aug 07 06:23:46 PM PDT 24
Peak memory 267268 kb
Host smart-1c9f7260-5d49-4ddf-91f8-bd108748fbdb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358659896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.3358659896
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.4002995705
Short name T343
Test name
Test status
Simulation time 12283559 ps
CPU time 0.75 seconds
Started Aug 07 06:19:51 PM PDT 24
Finished Aug 07 06:19:52 PM PDT 24
Peak memory 205896 kb
Host smart-660ad6c9-c2d8-4476-87fe-d73107d3e21c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002995705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.4
002995705
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.4125841766
Short name T147
Test name
Test status
Simulation time 166100163771 ps
CPU time 405.28 seconds
Started Aug 07 06:20:15 PM PDT 24
Finished Aug 07 06:27:01 PM PDT 24
Peak memory 266388 kb
Host smart-d36686e0-e4e5-4ac5-9a5f-cd8a2e015abc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125841766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.4125841766
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1503440885
Short name T109
Test name
Test status
Simulation time 149920978 ps
CPU time 1.9 seconds
Started Aug 07 04:57:43 PM PDT 24
Finished Aug 07 04:57:45 PM PDT 24
Peak memory 215680 kb
Host smart-f59fd438-0bb7-4e11-a9fc-c12972beaec5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503440885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
1503440885
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.2632812920
Short name T175
Test name
Test status
Simulation time 49453501817 ps
CPU time 211.8 seconds
Started Aug 07 06:20:56 PM PDT 24
Finished Aug 07 06:24:28 PM PDT 24
Peak memory 266012 kb
Host smart-343535e8-9627-4405-b46e-c27fef7f9b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632812920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.2632812920
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.10678083
Short name T169
Test name
Test status
Simulation time 91733041954 ps
CPU time 630.64 seconds
Started Aug 07 06:21:41 PM PDT 24
Finished Aug 07 06:32:12 PM PDT 24
Peak memory 269968 kb
Host smart-9a3d40eb-04eb-4bfb-ab03-68d5ede0134a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10678083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stress
_all.10678083
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.3936122504
Short name T173
Test name
Test status
Simulation time 15051981679 ps
CPU time 112.19 seconds
Started Aug 07 06:22:05 PM PDT 24
Finished Aug 07 06:23:58 PM PDT 24
Peak memory 266160 kb
Host smart-6d8a7e92-16b6-4c8b-915e-d3e5e68e5e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936122504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.3936122504
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.1381816662
Short name T571
Test name
Test status
Simulation time 62023516 ps
CPU time 1.2 seconds
Started Aug 07 06:19:49 PM PDT 24
Finished Aug 07 06:19:51 PM PDT 24
Peak memory 217256 kb
Host smart-d926e5c2-be22-4987-94ac-a2c33d23cab2
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381816662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.spi_device_mem_parity.1381816662
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.2703113449
Short name T18
Test name
Test status
Simulation time 6868759835 ps
CPU time 78.86 seconds
Started Aug 07 06:19:51 PM PDT 24
Finished Aug 07 06:21:10 PM PDT 24
Peak memory 253908 kb
Host smart-ce88d9aa-f186-4a84-8589-814dad47c2d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703113449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.2703113449
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.2818168735
Short name T57
Test name
Test status
Simulation time 122522554 ps
CPU time 1.19 seconds
Started Aug 07 06:19:49 PM PDT 24
Finished Aug 07 06:19:50 PM PDT 24
Peak memory 235984 kb
Host smart-80a58f6f-574c-4823-b8db-dc7fbcc801c6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818168735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.2818168735
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.1763572817
Short name T182
Test name
Test status
Simulation time 9364736847 ps
CPU time 115.55 seconds
Started Aug 07 06:21:41 PM PDT 24
Finished Aug 07 06:23:36 PM PDT 24
Peak memory 241272 kb
Host smart-11fc420c-a7a2-493b-9105-d9f41d8d8b64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763572817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmd
s.1763572817
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.1332493900
Short name T164
Test name
Test status
Simulation time 216722662576 ps
CPU time 548.45 seconds
Started Aug 07 06:20:24 PM PDT 24
Finished Aug 07 06:29:33 PM PDT 24
Peak memory 260732 kb
Host smart-15b20d76-dca8-45c4-bde0-a60ff6796c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332493900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.1332493900
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.2487285552
Short name T26
Test name
Test status
Simulation time 43100734780 ps
CPU time 152.39 seconds
Started Aug 07 06:22:16 PM PDT 24
Finished Aug 07 06:24:48 PM PDT 24
Peak memory 268624 kb
Host smart-b3704042-f0d5-45b9-8e41-d8be730c8b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487285552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.2487285552
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.1387873919
Short name T247
Test name
Test status
Simulation time 2977775264 ps
CPU time 17.95 seconds
Started Aug 07 04:57:41 PM PDT 24
Finished Aug 07 04:57:59 PM PDT 24
Peak memory 215780 kb
Host smart-4d2f4a05-65cf-4d5c-b335-40490d68252c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387873919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.1387873919
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.1319476123
Short name T219
Test name
Test status
Simulation time 26996161835 ps
CPU time 346.21 seconds
Started Aug 07 06:20:44 PM PDT 24
Finished Aug 07 06:26:30 PM PDT 24
Peak memory 282892 kb
Host smart-24f66eca-2f2d-414e-bc4d-499d289d2baa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319476123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.1319476123
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.3046448194
Short name T241
Test name
Test status
Simulation time 81361292 ps
CPU time 4.85 seconds
Started Aug 07 04:57:42 PM PDT 24
Finished Aug 07 04:57:47 PM PDT 24
Peak memory 216160 kb
Host smart-7694535f-0444-422d-bac4-fc11e3e5c89f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046448194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
3046448194
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.1393494530
Short name T44
Test name
Test status
Simulation time 17577831410 ps
CPU time 231.24 seconds
Started Aug 07 06:21:24 PM PDT 24
Finished Aug 07 06:25:15 PM PDT 24
Peak memory 249952 kb
Host smart-40758c01-3132-4f44-8e81-ea778c693117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393494530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.1393494530
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.217972111
Short name T78
Test name
Test status
Simulation time 23659377062 ps
CPU time 13.9 seconds
Started Aug 07 06:20:31 PM PDT 24
Finished Aug 07 06:20:45 PM PDT 24
Peak memory 217064 kb
Host smart-6a05905b-9b05-4afb-8f70-2cfb96160b4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217972111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.217972111
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.2810522925
Short name T214
Test name
Test status
Simulation time 470251582078 ps
CPU time 536.14 seconds
Started Aug 07 06:21:28 PM PDT 24
Finished Aug 07 06:30:24 PM PDT 24
Peak memory 272268 kb
Host smart-dc121018-0d97-447f-8888-a9d37d7e6a17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810522925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.2810522925
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.2139707859
Short name T157
Test name
Test status
Simulation time 180720513374 ps
CPU time 473.37 seconds
Started Aug 07 06:21:57 PM PDT 24
Finished Aug 07 06:29:51 PM PDT 24
Peak memory 257984 kb
Host smart-12fd9733-e6a4-4885-964b-d8d60309b4a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139707859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.2139707859
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.3066423393
Short name T514
Test name
Test status
Simulation time 8067267882 ps
CPU time 39.78 seconds
Started Aug 07 06:20:37 PM PDT 24
Finished Aug 07 06:21:17 PM PDT 24
Peak memory 236872 kb
Host smart-96c354df-be13-4a40-b840-692e6d2fe0b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066423393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.3066423393
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.806395067
Short name T222
Test name
Test status
Simulation time 4035085335 ps
CPU time 95.15 seconds
Started Aug 07 06:19:55 PM PDT 24
Finished Aug 07 06:21:30 PM PDT 24
Peak memory 265792 kb
Host smart-bc1a9bd1-ecb8-4ce3-80f5-8b5f8aa48d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806395067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.806395067
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.2145142839
Short name T41
Test name
Test status
Simulation time 217148873568 ps
CPU time 459.62 seconds
Started Aug 07 06:22:01 PM PDT 24
Finished Aug 07 06:29:41 PM PDT 24
Peak memory 265320 kb
Host smart-5486dfeb-b1fd-40b5-932a-277cd16bd9eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145142839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.2145142839
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.394305557
Short name T249
Test name
Test status
Simulation time 791426219 ps
CPU time 12.58 seconds
Started Aug 07 04:58:10 PM PDT 24
Finished Aug 07 04:58:22 PM PDT 24
Peak memory 215836 kb
Host smart-6daec0bf-39aa-4c0b-a8ca-f9c18bf5c0da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394305557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device
_tl_intg_err.394305557
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.2427234534
Short name T171
Test name
Test status
Simulation time 56774780053 ps
CPU time 393.57 seconds
Started Aug 07 06:20:52 PM PDT 24
Finished Aug 07 06:27:26 PM PDT 24
Peak memory 249908 kb
Host smart-396ee67b-d822-4522-bcab-8c651375f44b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427234534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmd
s.2427234534
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.851898785
Short name T139
Test name
Test status
Simulation time 1890229501 ps
CPU time 38.02 seconds
Started Aug 07 06:21:56 PM PDT 24
Finished Aug 07 06:22:34 PM PDT 24
Peak memory 252368 kb
Host smart-858c98bf-cc0b-4b04-83fa-0bdec9b74b16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851898785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.851898785
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.3678273331
Short name T298
Test name
Test status
Simulation time 719427477 ps
CPU time 7.54 seconds
Started Aug 07 06:22:21 PM PDT 24
Finished Aug 07 06:22:29 PM PDT 24
Peak memory 241728 kb
Host smart-1426aa01-c5c9-4f19-bfe3-f69b3634f046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678273331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.3678273331
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.3832503716
Short name T99
Test name
Test status
Simulation time 191161154 ps
CPU time 3.23 seconds
Started Aug 07 04:57:38 PM PDT 24
Finished Aug 07 04:57:41 PM PDT 24
Peak memory 216028 kb
Host smart-7d5813bd-1480-460c-82c3-e04a36ca9dda
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832503716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.3
832503716
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.491927991
Short name T244
Test name
Test status
Simulation time 633938157 ps
CPU time 14.43 seconds
Started Aug 07 04:57:35 PM PDT 24
Finished Aug 07 04:57:49 PM PDT 24
Peak memory 216228 kb
Host smart-99920b18-4113-444a-aa79-eb019b247151
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491927991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device
_tl_intg_err.491927991
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.1479289504
Short name T74
Test name
Test status
Simulation time 9406369326 ps
CPU time 92.92 seconds
Started Aug 07 06:19:50 PM PDT 24
Finished Aug 07 06:21:23 PM PDT 24
Peak memory 248036 kb
Host smart-4f86db88-a86f-4d0a-a1f7-0255822a7b46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479289504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.1479289504
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.3813114269
Short name T216
Test name
Test status
Simulation time 33100701677 ps
CPU time 75.03 seconds
Started Aug 07 06:20:24 PM PDT 24
Finished Aug 07 06:21:39 PM PDT 24
Peak memory 254400 kb
Host smart-b5c6f94a-963a-4307-83f8-a6fe09ed469e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813114269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.3813114269
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.1361915136
Short name T191
Test name
Test status
Simulation time 47189624118 ps
CPU time 371.97 seconds
Started Aug 07 06:20:24 PM PDT 24
Finished Aug 07 06:26:37 PM PDT 24
Peak memory 273576 kb
Host smart-b7846ca7-7506-4011-85e5-5ceec6371ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361915136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.1361915136
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.2574865332
Short name T220
Test name
Test status
Simulation time 2251291561 ps
CPU time 16.23 seconds
Started Aug 07 06:20:43 PM PDT 24
Finished Aug 07 06:21:00 PM PDT 24
Peak memory 239356 kb
Host smart-7ea49bd5-d887-4740-9c76-331635a241fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574865332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.2574865332
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.710635677
Short name T266
Test name
Test status
Simulation time 21564106910 ps
CPU time 110.18 seconds
Started Aug 07 06:21:22 PM PDT 24
Finished Aug 07 06:23:12 PM PDT 24
Peak memory 249908 kb
Host smart-c9075252-4956-4372-b068-54b5b847e3ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710635677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.710635677
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.563117702
Short name T203
Test name
Test status
Simulation time 134422219296 ps
CPU time 278.22 seconds
Started Aug 07 06:21:23 PM PDT 24
Finished Aug 07 06:26:01 PM PDT 24
Peak memory 258036 kb
Host smart-a87048c3-c20f-4797-ade3-32d17a3112fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563117702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stres
s_all.563117702
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_intercept.897547187
Short name T85
Test name
Test status
Simulation time 648015227 ps
CPU time 4.59 seconds
Started Aug 07 06:21:08 PM PDT 24
Finished Aug 07 06:21:12 PM PDT 24
Peak memory 233420 kb
Host smart-9d6cbba9-14b7-4238-9cd7-dce70a8d98af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897547187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.897547187
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.163271972
Short name T76
Test name
Test status
Simulation time 33060810380 ps
CPU time 49.9 seconds
Started Aug 07 06:20:48 PM PDT 24
Finished Aug 07 06:21:38 PM PDT 24
Peak memory 249896 kb
Host smart-2cb2efc8-9d8c-4d75-95dc-e6f601f41dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163271972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmds
.163271972
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.734420226
Short name T73
Test name
Test status
Simulation time 80691717 ps
CPU time 1.24 seconds
Started Aug 07 04:57:36 PM PDT 24
Finished Aug 07 04:57:37 PM PDT 24
Peak memory 216840 kb
Host smart-a1ac9023-c9b0-4b61-920e-e66d818c14a9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734420226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_hw_reset.734420226
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.4231403652
Short name T1145
Test name
Test status
Simulation time 3056792761 ps
CPU time 16.21 seconds
Started Aug 07 04:57:35 PM PDT 24
Finished Aug 07 04:57:52 PM PDT 24
Peak memory 215892 kb
Host smart-5c00f05b-6540-4553-9c81-01622f3aa5e1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231403652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.4231403652
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3024776335
Short name T1144
Test name
Test status
Simulation time 10021933492 ps
CPU time 34.47 seconds
Started Aug 07 04:57:32 PM PDT 24
Finished Aug 07 04:58:07 PM PDT 24
Peak memory 207488 kb
Host smart-7e7b2173-ae83-4983-bf55-18731e3b67e2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024776335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.3024776335
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2340847973
Short name T106
Test name
Test status
Simulation time 64358601 ps
CPU time 1.81 seconds
Started Aug 07 04:57:38 PM PDT 24
Finished Aug 07 04:57:40 PM PDT 24
Peak memory 215728 kb
Host smart-d0420a73-8cbc-44e5-83bc-60c5fbfc6b29
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340847973 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.2340847973
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.3193598541
Short name T115
Test name
Test status
Simulation time 725218305 ps
CPU time 2.06 seconds
Started Aug 07 04:57:38 PM PDT 24
Finished Aug 07 04:57:40 PM PDT 24
Peak memory 215696 kb
Host smart-25fdc029-371e-4990-ae37-1f88f1f02576
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193598541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.3
193598541
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.3834296316
Short name T1040
Test name
Test status
Simulation time 48276120 ps
CPU time 0.7 seconds
Started Aug 07 04:57:32 PM PDT 24
Finished Aug 07 04:57:33 PM PDT 24
Peak memory 204196 kb
Host smart-d6d779a4-7e04-47b4-8236-c29b8768e2ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834296316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.3
834296316
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.1189962060
Short name T118
Test name
Test status
Simulation time 44670422 ps
CPU time 1.74 seconds
Started Aug 07 04:57:39 PM PDT 24
Finished Aug 07 04:57:41 PM PDT 24
Peak memory 215796 kb
Host smart-0579e8ce-8f1b-45d7-b526-24c4535d510e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189962060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.1189962060
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.3839129576
Short name T1053
Test name
Test status
Simulation time 25232971 ps
CPU time 0.66 seconds
Started Aug 07 04:57:31 PM PDT 24
Finished Aug 07 04:57:31 PM PDT 24
Peak memory 204496 kb
Host smart-f6134ca7-4fe3-4f10-a2ce-eab5a1f88867
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839129576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.3839129576
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3228417391
Short name T1071
Test name
Test status
Simulation time 46205764 ps
CPU time 2.83 seconds
Started Aug 07 04:57:40 PM PDT 24
Finished Aug 07 04:57:43 PM PDT 24
Peak memory 215640 kb
Host smart-c4f55d0e-d1e1-4fa0-a432-7508f0453a03
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228417391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.3228417391
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.2581071416
Short name T252
Test name
Test status
Simulation time 722486207 ps
CPU time 16.08 seconds
Started Aug 07 04:57:34 PM PDT 24
Finished Aug 07 04:57:50 PM PDT 24
Peak memory 215848 kb
Host smart-cf291329-ca93-4940-961d-7b89d04a0e95
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581071416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.2581071416
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1732971670
Short name T145
Test name
Test status
Simulation time 839314897 ps
CPU time 8.73 seconds
Started Aug 07 04:57:37 PM PDT 24
Finished Aug 07 04:57:46 PM PDT 24
Peak memory 207632 kb
Host smart-a4fd4577-16b2-4646-910a-fe60b2b0f694
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732971670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.1732971670
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.4077165701
Short name T1104
Test name
Test status
Simulation time 1839232147 ps
CPU time 33.97 seconds
Started Aug 07 04:57:42 PM PDT 24
Finished Aug 07 04:58:16 PM PDT 24
Peak memory 215704 kb
Host smart-5472872a-2b06-4192-bb1b-74c5e913a41d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077165701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.4077165701
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3883319624
Short name T1103
Test name
Test status
Simulation time 42758586 ps
CPU time 0.95 seconds
Started Aug 07 04:57:40 PM PDT 24
Finished Aug 07 04:57:41 PM PDT 24
Peak memory 207172 kb
Host smart-988858b2-88be-4a14-8dd0-86be0b52c2e3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883319624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.3883319624
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.1716946818
Short name T101
Test name
Test status
Simulation time 107721435 ps
CPU time 1.75 seconds
Started Aug 07 04:57:40 PM PDT 24
Finished Aug 07 04:57:41 PM PDT 24
Peak memory 215680 kb
Host smart-40722c2d-0f13-468a-b951-9d0fe25ec2c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716946818 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.1716946818
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3559033448
Short name T117
Test name
Test status
Simulation time 73098211 ps
CPU time 1.34 seconds
Started Aug 07 04:57:38 PM PDT 24
Finished Aug 07 04:57:39 PM PDT 24
Peak memory 207652 kb
Host smart-0d679225-9843-419f-a3ce-f13e4e945ccd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559033448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.3
559033448
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.3290373368
Short name T1111
Test name
Test status
Simulation time 11538365 ps
CPU time 0.7 seconds
Started Aug 07 04:57:28 PM PDT 24
Finished Aug 07 04:57:29 PM PDT 24
Peak memory 204312 kb
Host smart-8669b2a8-8a38-4cdb-ba88-c0d2791125ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290373368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.3
290373368
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.301614762
Short name T1113
Test name
Test status
Simulation time 83007990 ps
CPU time 1.69 seconds
Started Aug 07 04:57:38 PM PDT 24
Finished Aug 07 04:57:40 PM PDT 24
Peak memory 215696 kb
Host smart-c85fdd43-9a2c-415d-8d23-42eae635d122
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301614762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_
device_mem_partial_access.301614762
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.687285769
Short name T1037
Test name
Test status
Simulation time 10287018 ps
CPU time 0.66 seconds
Started Aug 07 04:57:38 PM PDT 24
Finished Aug 07 04:57:38 PM PDT 24
Peak memory 204004 kb
Host smart-a5cf9a71-aa33-4445-91bd-ece294af2fb5
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687285769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_mem
_walk.687285769
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2441126155
Short name T1129
Test name
Test status
Simulation time 1082754562 ps
CPU time 4.32 seconds
Started Aug 07 04:57:39 PM PDT 24
Finished Aug 07 04:57:43 PM PDT 24
Peak memory 215692 kb
Host smart-dd36f374-e6d5-40bc-9092-b4f5e72dacd6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441126155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.2441126155
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.3719094572
Short name T1150
Test name
Test status
Simulation time 88550007 ps
CPU time 2.43 seconds
Started Aug 07 04:57:38 PM PDT 24
Finished Aug 07 04:57:41 PM PDT 24
Peak memory 216060 kb
Host smart-c0d47e65-7e3e-410c-8f62-7afbf4a67729
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719094572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.3
719094572
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.596816361
Short name T1065
Test name
Test status
Simulation time 2263443845 ps
CPU time 13.27 seconds
Started Aug 07 04:57:33 PM PDT 24
Finished Aug 07 04:57:47 PM PDT 24
Peak memory 215892 kb
Host smart-bfb1453c-e27f-426a-b513-7d15ab9d2a27
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596816361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_
tl_intg_err.596816361
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2470861741
Short name T1108
Test name
Test status
Simulation time 120522202 ps
CPU time 3.59 seconds
Started Aug 07 04:57:42 PM PDT 24
Finished Aug 07 04:57:46 PM PDT 24
Peak memory 218052 kb
Host smart-f642d125-8d2a-48a5-8306-70582b3239e9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470861741 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.2470861741
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.203923109
Short name T1115
Test name
Test status
Simulation time 883080139 ps
CPU time 2.45 seconds
Started Aug 07 04:57:49 PM PDT 24
Finished Aug 07 04:57:51 PM PDT 24
Peak memory 215628 kb
Host smart-f804586e-10bb-46bf-8e80-e600a5120144
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203923109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.203923109
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.2751266159
Short name T1096
Test name
Test status
Simulation time 40443706 ps
CPU time 0.7 seconds
Started Aug 07 04:57:48 PM PDT 24
Finished Aug 07 04:57:49 PM PDT 24
Peak memory 204176 kb
Host smart-60447473-d1a9-41e5-81c6-16bbc4d5cf62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751266159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
2751266159
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.4012838390
Short name T1077
Test name
Test status
Simulation time 793452475 ps
CPU time 3.91 seconds
Started Aug 07 04:57:44 PM PDT 24
Finished Aug 07 04:57:48 PM PDT 24
Peak memory 215656 kb
Host smart-c6e09f20-8f9a-4c13-9f30-5d949ebf00a0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012838390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.4012838390
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.2620839756
Short name T102
Test name
Test status
Simulation time 165157996 ps
CPU time 3.15 seconds
Started Aug 07 04:57:42 PM PDT 24
Finished Aug 07 04:57:45 PM PDT 24
Peak memory 215944 kb
Host smart-17772c81-edf0-458e-b4cb-30523f515e91
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620839756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
2620839756
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.2454431403
Short name T253
Test name
Test status
Simulation time 1322558494 ps
CPU time 14.48 seconds
Started Aug 07 04:57:44 PM PDT 24
Finished Aug 07 04:57:58 PM PDT 24
Peak memory 216148 kb
Host smart-bb23c324-d70c-4437-82b0-19bfe22f1591
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454431403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.2454431403
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.2542883443
Short name T1120
Test name
Test status
Simulation time 160736615 ps
CPU time 2.55 seconds
Started Aug 07 04:57:48 PM PDT 24
Finished Aug 07 04:57:51 PM PDT 24
Peak memory 216820 kb
Host smart-6a88d280-1c7c-4633-a6e6-a14cd3d65002
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542883443 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.2542883443
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.1585415056
Short name T114
Test name
Test status
Simulation time 273259019 ps
CPU time 3.19 seconds
Started Aug 07 04:57:35 PM PDT 24
Finished Aug 07 04:57:39 PM PDT 24
Peak memory 215748 kb
Host smart-51fb3b0a-3dbc-4bdf-89f1-e4c72b8be572
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585415056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
1585415056
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.3891521129
Short name T1055
Test name
Test status
Simulation time 28937791 ps
CPU time 0.77 seconds
Started Aug 07 04:57:37 PM PDT 24
Finished Aug 07 04:57:38 PM PDT 24
Peak memory 204528 kb
Host smart-7328a411-f93f-49b3-b603-02509ba51409
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891521129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
3891521129
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3524119286
Short name T1146
Test name
Test status
Simulation time 123159126 ps
CPU time 2.68 seconds
Started Aug 07 04:57:45 PM PDT 24
Finished Aug 07 04:57:48 PM PDT 24
Peak memory 215620 kb
Host smart-08b1ce26-ebbd-46dd-83db-3517bb37393e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524119286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.3524119286
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.4167738540
Short name T91
Test name
Test status
Simulation time 84733281 ps
CPU time 2.48 seconds
Started Aug 07 04:57:43 PM PDT 24
Finished Aug 07 04:57:45 PM PDT 24
Peak memory 215968 kb
Host smart-3471ea04-b21b-41d1-b500-6ef60cc0ffc0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167738540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
4167738540
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3781725343
Short name T1048
Test name
Test status
Simulation time 327097989 ps
CPU time 3.02 seconds
Started Aug 07 04:58:03 PM PDT 24
Finished Aug 07 04:58:06 PM PDT 24
Peak memory 218940 kb
Host smart-ef520030-82d5-4f17-afcc-786fe9cf79af
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781725343 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.3781725343
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.3745214625
Short name T120
Test name
Test status
Simulation time 86862482 ps
CPU time 2.11 seconds
Started Aug 07 04:57:59 PM PDT 24
Finished Aug 07 04:58:01 PM PDT 24
Peak memory 215740 kb
Host smart-cc2a9dfa-a531-4b4e-8f6f-c3666475a2c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745214625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
3745214625
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.3657949233
Short name T1078
Test name
Test status
Simulation time 42518299 ps
CPU time 0.78 seconds
Started Aug 07 04:57:57 PM PDT 24
Finished Aug 07 04:57:58 PM PDT 24
Peak memory 204228 kb
Host smart-91d1a849-c08d-4066-b865-4f08d244b574
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657949233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
3657949233
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1735503921
Short name T137
Test name
Test status
Simulation time 1014846465 ps
CPU time 4.29 seconds
Started Aug 07 04:57:50 PM PDT 24
Finished Aug 07 04:57:55 PM PDT 24
Peak memory 215896 kb
Host smart-020bbcf2-9c1c-4290-b21e-ad857acdf1c1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735503921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.1735503921
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3563665862
Short name T1140
Test name
Test status
Simulation time 208488672 ps
CPU time 3.34 seconds
Started Aug 07 04:57:49 PM PDT 24
Finished Aug 07 04:57:53 PM PDT 24
Peak memory 216012 kb
Host smart-98d4e7ba-ea89-438f-8b6e-d6981e981bc9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563665862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
3563665862
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.106815956
Short name T105
Test name
Test status
Simulation time 1067707354 ps
CPU time 3.65 seconds
Started Aug 07 04:57:40 PM PDT 24
Finished Aug 07 04:57:44 PM PDT 24
Peak memory 218224 kb
Host smart-3032b1ca-edc3-402d-8cf9-1aedc61c869c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106815956 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.106815956
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3569716036
Short name T1036
Test name
Test status
Simulation time 19036605 ps
CPU time 0.68 seconds
Started Aug 07 04:57:42 PM PDT 24
Finished Aug 07 04:57:43 PM PDT 24
Peak memory 204180 kb
Host smart-b1e0ad21-174c-470f-8acd-5957b1b1f1d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569716036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
3569716036
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.815904728
Short name T134
Test name
Test status
Simulation time 348547597 ps
CPU time 3.08 seconds
Started Aug 07 04:57:56 PM PDT 24
Finished Aug 07 04:57:59 PM PDT 24
Peak memory 215732 kb
Host smart-4f8e46b1-8a98-4cf1-a574-a29df4eff794
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815904728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.s
pi_device_same_csr_outstanding.815904728
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3036787581
Short name T1131
Test name
Test status
Simulation time 170123992 ps
CPU time 1.71 seconds
Started Aug 07 04:57:48 PM PDT 24
Finished Aug 07 04:57:50 PM PDT 24
Peak memory 216112 kb
Host smart-5606103f-918b-4132-9add-ecee4b9cd73e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036787581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
3036787581
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.2429789135
Short name T246
Test name
Test status
Simulation time 228037023 ps
CPU time 7.2 seconds
Started Aug 07 04:57:52 PM PDT 24
Finished Aug 07 04:57:59 PM PDT 24
Peak memory 215856 kb
Host smart-6c35750a-237b-43eb-b351-f93fcf8624ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429789135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.2429789135
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.941923935
Short name T1054
Test name
Test status
Simulation time 141248754 ps
CPU time 2.45 seconds
Started Aug 07 04:57:46 PM PDT 24
Finished Aug 07 04:57:49 PM PDT 24
Peak memory 217448 kb
Host smart-8f67c325-6ee1-49e6-b6c7-1ce48bfa3ec5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941923935 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.941923935
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.2001285461
Short name T110
Test name
Test status
Simulation time 385501173 ps
CPU time 2.51 seconds
Started Aug 07 04:57:53 PM PDT 24
Finished Aug 07 04:57:55 PM PDT 24
Peak memory 215748 kb
Host smart-b91793e7-1a6b-4923-a757-6bb326860b64
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001285461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
2001285461
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.129664498
Short name T1081
Test name
Test status
Simulation time 43687907 ps
CPU time 0.78 seconds
Started Aug 07 04:57:50 PM PDT 24
Finished Aug 07 04:57:52 PM PDT 24
Peak memory 204300 kb
Host smart-7fad6e50-ac98-4128-a373-73a36d395d90
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129664498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.129664498
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.1388001894
Short name T1082
Test name
Test status
Simulation time 1185631494 ps
CPU time 2.85 seconds
Started Aug 07 04:57:35 PM PDT 24
Finished Aug 07 04:57:38 PM PDT 24
Peak memory 215640 kb
Host smart-4eb218b3-f07e-4dd7-a170-7b30e19452f9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388001894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.1388001894
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.3980120145
Short name T94
Test name
Test status
Simulation time 97769530 ps
CPU time 6.11 seconds
Started Aug 07 04:57:59 PM PDT 24
Finished Aug 07 04:58:05 PM PDT 24
Peak memory 215832 kb
Host smart-16bb5c4f-3122-4ae4-af44-a12e79dea30e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980120145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.3980120145
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.53104731
Short name T1121
Test name
Test status
Simulation time 102498968 ps
CPU time 3.44 seconds
Started Aug 07 04:57:45 PM PDT 24
Finished Aug 07 04:57:49 PM PDT 24
Peak memory 217672 kb
Host smart-efa1000c-bf9c-420a-bfe4-df8e636e894c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53104731 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.53104731
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.438397353
Short name T1085
Test name
Test status
Simulation time 74413119 ps
CPU time 2.34 seconds
Started Aug 07 04:58:02 PM PDT 24
Finished Aug 07 04:58:04 PM PDT 24
Peak memory 215608 kb
Host smart-c0e4811d-1b14-449a-81af-9a4a0f3416d7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438397353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.438397353
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.600095388
Short name T1114
Test name
Test status
Simulation time 59476544 ps
CPU time 0.73 seconds
Started Aug 07 04:57:45 PM PDT 24
Finished Aug 07 04:57:46 PM PDT 24
Peak memory 204536 kb
Host smart-1bbb5b3a-98d7-4883-bcd2-c3eba799c027
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600095388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.600095388
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.1484242409
Short name T138
Test name
Test status
Simulation time 625291160 ps
CPU time 3.32 seconds
Started Aug 07 04:57:47 PM PDT 24
Finished Aug 07 04:57:50 PM PDT 24
Peak memory 215748 kb
Host smart-7bfabac4-8efb-4a58-992e-7d7e88244e4b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484242409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.1484242409
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.780480798
Short name T100
Test name
Test status
Simulation time 110137402 ps
CPU time 3.14 seconds
Started Aug 07 04:57:42 PM PDT 24
Finished Aug 07 04:57:45 PM PDT 24
Peak memory 216140 kb
Host smart-ebf070e7-6892-4fbe-9dfb-b832b3720a70
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780480798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.780480798
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.2334911222
Short name T1125
Test name
Test status
Simulation time 206087267 ps
CPU time 6.61 seconds
Started Aug 07 04:58:08 PM PDT 24
Finished Aug 07 04:58:15 PM PDT 24
Peak memory 215988 kb
Host smart-7cdff5a7-1efb-411a-8b88-1cd27e3c96a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334911222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.2334911222
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3842698789
Short name T88
Test name
Test status
Simulation time 868178202 ps
CPU time 2.71 seconds
Started Aug 07 04:57:54 PM PDT 24
Finished Aug 07 04:57:57 PM PDT 24
Peak memory 217000 kb
Host smart-d4db865c-67f9-4258-8345-dd4e3b823b64
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842698789 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.3842698789
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.3092913549
Short name T113
Test name
Test status
Simulation time 38490968 ps
CPU time 1.31 seconds
Started Aug 07 04:57:53 PM PDT 24
Finished Aug 07 04:57:55 PM PDT 24
Peak memory 207492 kb
Host smart-fc2b27d1-bac8-427c-8728-94da54078aef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092913549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
3092913549
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.1253653660
Short name T1097
Test name
Test status
Simulation time 17605611 ps
CPU time 0.69 seconds
Started Aug 07 04:57:48 PM PDT 24
Finished Aug 07 04:57:49 PM PDT 24
Peak memory 204188 kb
Host smart-dba53659-523b-4aac-9bcf-e72d8129a1a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253653660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
1253653660
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.721005759
Short name T1061
Test name
Test status
Simulation time 427366904 ps
CPU time 3.08 seconds
Started Aug 07 04:58:10 PM PDT 24
Finished Aug 07 04:58:13 PM PDT 24
Peak memory 215684 kb
Host smart-99b60b73-0a62-41b2-9332-7ed975942008
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721005759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.s
pi_device_same_csr_outstanding.721005759
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.3907422909
Short name T248
Test name
Test status
Simulation time 2636904681 ps
CPU time 14.44 seconds
Started Aug 07 04:57:49 PM PDT 24
Finished Aug 07 04:58:04 PM PDT 24
Peak memory 216140 kb
Host smart-455d30ae-a048-498e-8682-2248ef725e06
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907422909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.3907422909
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1397428885
Short name T1107
Test name
Test status
Simulation time 40630841 ps
CPU time 2.89 seconds
Started Aug 07 04:57:43 PM PDT 24
Finished Aug 07 04:57:46 PM PDT 24
Peak memory 217020 kb
Host smart-61e172b9-8e58-4c45-9f3d-10d021757a7a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397428885 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.1397428885
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.3126348763
Short name T1128
Test name
Test status
Simulation time 22591651 ps
CPU time 1.31 seconds
Started Aug 07 04:57:38 PM PDT 24
Finished Aug 07 04:57:39 PM PDT 24
Peak memory 215704 kb
Host smart-a01a24bb-75a0-41e3-9113-92b9a38c70ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126348763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
3126348763
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.488041328
Short name T1133
Test name
Test status
Simulation time 16406604 ps
CPU time 0.77 seconds
Started Aug 07 04:57:49 PM PDT 24
Finished Aug 07 04:57:49 PM PDT 24
Peak memory 204288 kb
Host smart-1d813795-47ee-412b-8ceb-004dbcaa20f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488041328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.488041328
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.3158827931
Short name T146
Test name
Test status
Simulation time 775608585 ps
CPU time 2.81 seconds
Started Aug 07 04:57:57 PM PDT 24
Finished Aug 07 04:58:00 PM PDT 24
Peak memory 215680 kb
Host smart-54411d57-e662-4917-ba58-64da9b2c94bf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158827931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.3158827931
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.922395150
Short name T1130
Test name
Test status
Simulation time 339634303 ps
CPU time 2.06 seconds
Started Aug 07 04:57:49 PM PDT 24
Finished Aug 07 04:57:52 PM PDT 24
Peak memory 215912 kb
Host smart-744478ad-a5fa-459b-967a-0be923482e68
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922395150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.922395150
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.1704643114
Short name T1080
Test name
Test status
Simulation time 613417674 ps
CPU time 2.86 seconds
Started Aug 07 04:57:43 PM PDT 24
Finished Aug 07 04:57:46 PM PDT 24
Peak memory 217196 kb
Host smart-9b1c28a3-8fb3-4ced-b175-dcd496072027
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704643114 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.1704643114
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3655933225
Short name T1079
Test name
Test status
Simulation time 112516923 ps
CPU time 1.19 seconds
Started Aug 07 04:57:41 PM PDT 24
Finished Aug 07 04:57:43 PM PDT 24
Peak memory 207640 kb
Host smart-73897264-fb8a-45fd-86af-6f4b15be6d7f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655933225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
3655933225
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.1811268356
Short name T1042
Test name
Test status
Simulation time 42059021 ps
CPU time 0.69 seconds
Started Aug 07 04:57:50 PM PDT 24
Finished Aug 07 04:57:51 PM PDT 24
Peak memory 204280 kb
Host smart-e9521411-1d83-406f-acb1-07271d9df936
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811268356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
1811268356
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.900071717
Short name T1049
Test name
Test status
Simulation time 75918774 ps
CPU time 2.86 seconds
Started Aug 07 04:57:42 PM PDT 24
Finished Aug 07 04:57:45 PM PDT 24
Peak memory 215988 kb
Host smart-84df834f-f40a-45d6-9290-2117f7575921
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900071717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.s
pi_device_same_csr_outstanding.900071717
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.3153876595
Short name T1098
Test name
Test status
Simulation time 70400631 ps
CPU time 2.56 seconds
Started Aug 07 04:57:53 PM PDT 24
Finished Aug 07 04:57:55 PM PDT 24
Peak memory 215992 kb
Host smart-a3d83701-e357-4189-9f39-f1d54025d5b1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153876595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
3153876595
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.3667872068
Short name T1075
Test name
Test status
Simulation time 622493286 ps
CPU time 14.36 seconds
Started Aug 07 04:57:49 PM PDT 24
Finished Aug 07 04:58:04 PM PDT 24
Peak memory 215864 kb
Host smart-5f114053-4eba-4dce-a60f-2534c24dc127
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667872068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.3667872068
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.3815970415
Short name T1070
Test name
Test status
Simulation time 458307711 ps
CPU time 1.72 seconds
Started Aug 07 04:57:49 PM PDT 24
Finished Aug 07 04:57:51 PM PDT 24
Peak memory 215832 kb
Host smart-bb490b0c-9bf3-4633-bd04-10d8d1e36f4d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815970415 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.3815970415
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.2028184047
Short name T1102
Test name
Test status
Simulation time 74186095 ps
CPU time 2.65 seconds
Started Aug 07 04:57:51 PM PDT 24
Finished Aug 07 04:57:54 PM PDT 24
Peak memory 207704 kb
Host smart-ec45f3c0-ba55-42ae-af80-a0ef12049057
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028184047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
2028184047
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.2990427759
Short name T1052
Test name
Test status
Simulation time 43367413 ps
CPU time 0.74 seconds
Started Aug 07 04:57:55 PM PDT 24
Finished Aug 07 04:57:56 PM PDT 24
Peak memory 204196 kb
Host smart-1db24814-5a89-4cb9-8d51-4838f79cc8d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990427759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
2990427759
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.278678073
Short name T1074
Test name
Test status
Simulation time 199176677 ps
CPU time 4.24 seconds
Started Aug 07 04:57:50 PM PDT 24
Finished Aug 07 04:57:54 PM PDT 24
Peak memory 215772 kb
Host smart-f08008bf-89e5-4e47-a4e0-d12ba8ee1015
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278678073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.s
pi_device_same_csr_outstanding.278678073
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.1061219908
Short name T1089
Test name
Test status
Simulation time 203596196 ps
CPU time 5.47 seconds
Started Aug 07 04:57:42 PM PDT 24
Finished Aug 07 04:57:47 PM PDT 24
Peak memory 216060 kb
Host smart-415fbbf3-1ab0-464e-91e3-2713e48ac402
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061219908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
1061219908
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.631648147
Short name T251
Test name
Test status
Simulation time 816396797 ps
CPU time 21.81 seconds
Started Aug 07 04:57:37 PM PDT 24
Finished Aug 07 04:58:04 PM PDT 24
Peak memory 216408 kb
Host smart-77bfe3e8-76f0-4d25-98f7-e370f828a826
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631648147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device
_tl_intg_err.631648147
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.2917380761
Short name T1090
Test name
Test status
Simulation time 314882135 ps
CPU time 8.38 seconds
Started Aug 07 04:57:39 PM PDT 24
Finished Aug 07 04:57:48 PM PDT 24
Peak memory 207372 kb
Host smart-eb6023ce-5e78-403c-a8b3-3c156863ef91
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917380761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.2917380761
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1909761895
Short name T1124
Test name
Test status
Simulation time 3069586218 ps
CPU time 36.22 seconds
Started Aug 07 04:57:44 PM PDT 24
Finished Aug 07 04:58:20 PM PDT 24
Peak memory 207600 kb
Host smart-bf8914b4-9d80-4cee-92ad-89c2ac2e909f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909761895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.1909761895
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2657672449
Short name T72
Test name
Test status
Simulation time 35431557 ps
CPU time 1.18 seconds
Started Aug 07 04:57:38 PM PDT 24
Finished Aug 07 04:57:39 PM PDT 24
Peak memory 207432 kb
Host smart-3a14828f-2d7c-495f-bb55-d6dd508c207e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657672449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.2657672449
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.397515897
Short name T1132
Test name
Test status
Simulation time 124889827 ps
CPU time 1.91 seconds
Started Aug 07 04:57:29 PM PDT 24
Finished Aug 07 04:57:31 PM PDT 24
Peak memory 215776 kb
Host smart-b846f8f5-bfeb-4cbe-9736-2792af89f857
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397515897 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.397515897
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.4279322654
Short name T112
Test name
Test status
Simulation time 91111756 ps
CPU time 2.43 seconds
Started Aug 07 04:57:42 PM PDT 24
Finished Aug 07 04:57:44 PM PDT 24
Peak memory 207584 kb
Host smart-9304b421-4586-4bf7-87f0-d3574bdad8c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279322654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.4
279322654
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.2624334679
Short name T1064
Test name
Test status
Simulation time 47833166 ps
CPU time 0.69 seconds
Started Aug 07 04:57:34 PM PDT 24
Finished Aug 07 04:57:35 PM PDT 24
Peak memory 204612 kb
Host smart-f47e8f31-367c-451b-866a-adcc2f6591a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624334679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.2
624334679
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2399806962
Short name T1088
Test name
Test status
Simulation time 21375924 ps
CPU time 1.6 seconds
Started Aug 07 04:57:41 PM PDT 24
Finished Aug 07 04:57:43 PM PDT 24
Peak memory 215820 kb
Host smart-e7b5de8e-54f9-44c9-a66e-281130359eb7
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399806962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.2399806962
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.404302125
Short name T1076
Test name
Test status
Simulation time 12640414 ps
CPU time 0.67 seconds
Started Aug 07 04:57:33 PM PDT 24
Finished Aug 07 04:57:34 PM PDT 24
Peak memory 204020 kb
Host smart-8605e071-263f-4df5-a45d-82086e04030c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404302125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_mem
_walk.404302125
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1871518365
Short name T135
Test name
Test status
Simulation time 276153322 ps
CPU time 2.87 seconds
Started Aug 07 04:57:38 PM PDT 24
Finished Aug 07 04:57:41 PM PDT 24
Peak memory 215648 kb
Host smart-7cbac205-68c0-47e6-a34d-69a70804ad2d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871518365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.1871518365
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.870715203
Short name T242
Test name
Test status
Simulation time 500242081 ps
CPU time 4.57 seconds
Started Aug 07 04:57:43 PM PDT 24
Finished Aug 07 04:57:48 PM PDT 24
Peak memory 216896 kb
Host smart-c6ea3d48-4441-4707-b064-b50c7c7b3f51
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870715203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.870715203
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.3494650323
Short name T245
Test name
Test status
Simulation time 3832119905 ps
CPU time 21.53 seconds
Started Aug 07 04:57:37 PM PDT 24
Finished Aug 07 04:57:59 PM PDT 24
Peak memory 215884 kb
Host smart-d24f2ffd-022a-4e97-aae8-7ee016e8686d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494650323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.3494650323
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.2193756392
Short name T1106
Test name
Test status
Simulation time 132644407 ps
CPU time 0.72 seconds
Started Aug 07 04:58:02 PM PDT 24
Finished Aug 07 04:58:03 PM PDT 24
Peak memory 204220 kb
Host smart-7558ba35-1269-4ee2-a657-5670eb65bb53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193756392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
2193756392
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.2165327592
Short name T1063
Test name
Test status
Simulation time 32871414 ps
CPU time 0.71 seconds
Started Aug 07 04:58:03 PM PDT 24
Finished Aug 07 04:58:04 PM PDT 24
Peak memory 204256 kb
Host smart-14ad5d1c-3452-4587-ab93-1c430f9c0d48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165327592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
2165327592
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.2588076721
Short name T1050
Test name
Test status
Simulation time 17114493 ps
CPU time 0.71 seconds
Started Aug 07 04:57:59 PM PDT 24
Finished Aug 07 04:58:00 PM PDT 24
Peak memory 204284 kb
Host smart-2521a552-8483-49b1-95f8-7f117d0ec991
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588076721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
2588076721
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2855905931
Short name T1041
Test name
Test status
Simulation time 204010152 ps
CPU time 0.76 seconds
Started Aug 07 04:57:44 PM PDT 24
Finished Aug 07 04:57:45 PM PDT 24
Peak memory 204276 kb
Host smart-fa864776-3cf2-4d7d-ad18-2c15475ae6ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855905931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
2855905931
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1563811580
Short name T1032
Test name
Test status
Simulation time 14911447 ps
CPU time 0.71 seconds
Started Aug 07 04:57:36 PM PDT 24
Finished Aug 07 04:57:42 PM PDT 24
Peak memory 204304 kb
Host smart-cde80acd-2fbd-47b2-9bd8-f5e01ba3a63c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563811580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
1563811580
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.1088739647
Short name T1101
Test name
Test status
Simulation time 10897360 ps
CPU time 0.75 seconds
Started Aug 07 04:57:50 PM PDT 24
Finished Aug 07 04:57:52 PM PDT 24
Peak memory 204312 kb
Host smart-e2b1a6ef-b816-4df4-91ca-0cdf628eca9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088739647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
1088739647
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2368403649
Short name T1072
Test name
Test status
Simulation time 14265044 ps
CPU time 0.71 seconds
Started Aug 07 04:57:50 PM PDT 24
Finished Aug 07 04:57:51 PM PDT 24
Peak memory 204324 kb
Host smart-3398be95-a42d-4aed-b6d4-e08369b71fb1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368403649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
2368403649
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.2296449049
Short name T1147
Test name
Test status
Simulation time 42721587 ps
CPU time 0.66 seconds
Started Aug 07 04:57:42 PM PDT 24
Finished Aug 07 04:57:43 PM PDT 24
Peak memory 204500 kb
Host smart-fe31d229-4e02-4688-9bd7-9bb8006da894
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296449049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
2296449049
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.754748158
Short name T1056
Test name
Test status
Simulation time 94504490 ps
CPU time 0.69 seconds
Started Aug 07 04:57:57 PM PDT 24
Finished Aug 07 04:57:58 PM PDT 24
Peak memory 204192 kb
Host smart-6248809d-23fa-458a-9bf2-568c39b27df4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754748158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.754748158
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.1272762337
Short name T1059
Test name
Test status
Simulation time 34732873 ps
CPU time 0.75 seconds
Started Aug 07 04:57:58 PM PDT 24
Finished Aug 07 04:57:59 PM PDT 24
Peak memory 204328 kb
Host smart-91dcff3e-e632-46e7-84ec-9b5e0937d222
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272762337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
1272762337
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.2337342661
Short name T1095
Test name
Test status
Simulation time 1478223591 ps
CPU time 8.23 seconds
Started Aug 07 04:57:33 PM PDT 24
Finished Aug 07 04:57:42 PM PDT 24
Peak memory 207544 kb
Host smart-0699c0c2-a448-4cec-8c5b-5a0b379a2603
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337342661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.2337342661
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3451941987
Short name T1118
Test name
Test status
Simulation time 306902037 ps
CPU time 10.98 seconds
Started Aug 07 04:57:42 PM PDT 24
Finished Aug 07 04:57:53 PM PDT 24
Peak memory 207396 kb
Host smart-3d03a57b-9aa2-4751-8994-60a633ea3876
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451941987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.3451941987
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.3781920145
Short name T121
Test name
Test status
Simulation time 47969854 ps
CPU time 1.46 seconds
Started Aug 07 04:57:59 PM PDT 24
Finished Aug 07 04:58:01 PM PDT 24
Peak memory 217800 kb
Host smart-aeb86f27-cdd8-44a7-afb6-ede4efccbd2b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781920145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.3781920145
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.860558727
Short name T90
Test name
Test status
Simulation time 88405689 ps
CPU time 1.83 seconds
Started Aug 07 04:57:34 PM PDT 24
Finished Aug 07 04:57:35 PM PDT 24
Peak memory 216028 kb
Host smart-2b94029d-bf0a-436f-bfd7-3fbc1c56c7d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860558727 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.860558727
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.3615205954
Short name T1122
Test name
Test status
Simulation time 230978182 ps
CPU time 1.23 seconds
Started Aug 07 04:57:42 PM PDT 24
Finished Aug 07 04:57:43 PM PDT 24
Peak memory 215760 kb
Host smart-4bdf01d7-2f15-4d9d-b425-80e4fc5b1f12
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615205954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.3
615205954
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.3497263586
Short name T1047
Test name
Test status
Simulation time 54994312 ps
CPU time 0.75 seconds
Started Aug 07 04:57:48 PM PDT 24
Finished Aug 07 04:57:49 PM PDT 24
Peak memory 204280 kb
Host smart-d10bf853-5c5a-4b8f-bd14-704ae2cf1b8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497263586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.3
497263586
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.1425029669
Short name T122
Test name
Test status
Simulation time 67954365 ps
CPU time 1.81 seconds
Started Aug 07 04:57:40 PM PDT 24
Finished Aug 07 04:57:42 PM PDT 24
Peak memory 215736 kb
Host smart-5c3511e0-3db5-4d3a-b6e2-9132510f3178
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425029669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.1425029669
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.313415272
Short name T1045
Test name
Test status
Simulation time 19108753 ps
CPU time 0.7 seconds
Started Aug 07 04:57:35 PM PDT 24
Finished Aug 07 04:57:36 PM PDT 24
Peak memory 204124 kb
Host smart-ec403fb4-0a5f-43c2-910d-c08ad8887d72
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313415272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_mem
_walk.313415272
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.1990573549
Short name T1135
Test name
Test status
Simulation time 402572360 ps
CPU time 2.63 seconds
Started Aug 07 04:57:40 PM PDT 24
Finished Aug 07 04:57:42 PM PDT 24
Peak memory 215760 kb
Host smart-022c7346-2a2e-44de-8971-a8c8f27fe4b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990573549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.1990573549
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.3666328775
Short name T1143
Test name
Test status
Simulation time 317642244 ps
CPU time 5.64 seconds
Started Aug 07 04:57:36 PM PDT 24
Finished Aug 07 04:57:42 PM PDT 24
Peak memory 215964 kb
Host smart-3acb7c53-c67d-4c5a-9ce7-d06a5a86d2d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666328775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.3
666328775
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.3784371182
Short name T1069
Test name
Test status
Simulation time 785559985 ps
CPU time 12.5 seconds
Started Aug 07 04:57:53 PM PDT 24
Finished Aug 07 04:58:06 PM PDT 24
Peak memory 215724 kb
Host smart-f8981987-9f55-480e-94cd-574f435aeeb7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784371182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.3784371182
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.2706896530
Short name T1127
Test name
Test status
Simulation time 27439028 ps
CPU time 0.69 seconds
Started Aug 07 04:57:55 PM PDT 24
Finished Aug 07 04:57:56 PM PDT 24
Peak memory 204524 kb
Host smart-12b87d50-83b1-4ef8-8b85-ee1db7b3ad7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706896530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
2706896530
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.3823545883
Short name T1051
Test name
Test status
Simulation time 15863618 ps
CPU time 0.75 seconds
Started Aug 07 04:57:57 PM PDT 24
Finished Aug 07 04:57:58 PM PDT 24
Peak memory 204304 kb
Host smart-dd0d02c9-fd5a-4c78-bb1c-ad9ee66fe8f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823545883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
3823545883
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.1402739730
Short name T1044
Test name
Test status
Simulation time 14712292 ps
CPU time 0.67 seconds
Started Aug 07 04:57:49 PM PDT 24
Finished Aug 07 04:57:49 PM PDT 24
Peak memory 204628 kb
Host smart-45c69f50-090a-4f93-ba0b-db49ed10e6b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402739730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
1402739730
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.3514083457
Short name T1083
Test name
Test status
Simulation time 19107297 ps
CPU time 0.71 seconds
Started Aug 07 04:58:43 PM PDT 24
Finished Aug 07 04:58:44 PM PDT 24
Peak memory 204288 kb
Host smart-ae37af8f-fe89-4471-8cbb-b2f1229870d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514083457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
3514083457
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.3391867094
Short name T1062
Test name
Test status
Simulation time 12356490 ps
CPU time 0.73 seconds
Started Aug 07 04:57:58 PM PDT 24
Finished Aug 07 04:57:59 PM PDT 24
Peak memory 204616 kb
Host smart-3b67b686-60b2-4d9f-8915-be400f636f29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391867094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
3391867094
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.657972991
Short name T1094
Test name
Test status
Simulation time 45324701 ps
CPU time 0.69 seconds
Started Aug 07 04:57:48 PM PDT 24
Finished Aug 07 04:57:49 PM PDT 24
Peak memory 204496 kb
Host smart-0478c368-65e9-4bdc-beda-a4129a80a24e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657972991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.657972991
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.3592530781
Short name T1038
Test name
Test status
Simulation time 18509905 ps
CPU time 0.68 seconds
Started Aug 07 04:57:52 PM PDT 24
Finished Aug 07 04:57:53 PM PDT 24
Peak memory 204536 kb
Host smart-e80d7826-cefc-4867-acec-fb3bc461cdb1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592530781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
3592530781
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.3427070234
Short name T1087
Test name
Test status
Simulation time 57401024 ps
CPU time 0.76 seconds
Started Aug 07 04:57:50 PM PDT 24
Finished Aug 07 04:57:51 PM PDT 24
Peak memory 204296 kb
Host smart-81bfc5f8-4c46-4a6d-9408-c8a00f3bc3d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427070234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
3427070234
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.3781310620
Short name T1093
Test name
Test status
Simulation time 49342160 ps
CPU time 0.75 seconds
Started Aug 07 04:57:47 PM PDT 24
Finished Aug 07 04:57:47 PM PDT 24
Peak memory 204288 kb
Host smart-69ba4046-429f-4ed5-9714-2877ef3d164a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781310620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
3781310620
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.2357153281
Short name T1084
Test name
Test status
Simulation time 16671774 ps
CPU time 0.74 seconds
Started Aug 07 04:57:50 PM PDT 24
Finished Aug 07 04:57:50 PM PDT 24
Peak memory 204276 kb
Host smart-4206be37-b32e-4aea-9f09-acf34bd9c103
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357153281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
2357153281
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.2764849960
Short name T1116
Test name
Test status
Simulation time 302568031 ps
CPU time 20.32 seconds
Started Aug 07 04:57:33 PM PDT 24
Finished Aug 07 04:57:54 PM PDT 24
Peak memory 215692 kb
Host smart-91f7b28a-2f87-4d73-adf0-a0be487f606d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764849960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.2764849960
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.713600029
Short name T1142
Test name
Test status
Simulation time 1253980613 ps
CPU time 25.84 seconds
Started Aug 07 04:57:34 PM PDT 24
Finished Aug 07 04:58:00 PM PDT 24
Peak memory 207616 kb
Host smart-af713dd7-9eb3-4b81-b3ad-cd5c3a0d6a20
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713600029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_bit_bash.713600029
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.1999329070
Short name T71
Test name
Test status
Simulation time 30586921 ps
CPU time 1.15 seconds
Started Aug 07 04:57:38 PM PDT 24
Finished Aug 07 04:57:40 PM PDT 24
Peak memory 207424 kb
Host smart-4a282f6a-98fb-4e30-9d8e-626f17e73f32
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999329070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.1999329070
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3074181318
Short name T1060
Test name
Test status
Simulation time 80825973 ps
CPU time 2.4 seconds
Started Aug 07 04:57:37 PM PDT 24
Finished Aug 07 04:57:40 PM PDT 24
Peak memory 218208 kb
Host smart-cc01363a-a919-4752-ae4f-ca05d9539014
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074181318 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.3074181318
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.2478954054
Short name T119
Test name
Test status
Simulation time 163778060 ps
CPU time 2.48 seconds
Started Aug 07 04:57:44 PM PDT 24
Finished Aug 07 04:57:47 PM PDT 24
Peak memory 207476 kb
Host smart-c2de8b2d-df67-42f7-a11c-2b81a646bd31
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478954054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.2
478954054
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.1027631424
Short name T1043
Test name
Test status
Simulation time 19474983 ps
CPU time 0.77 seconds
Started Aug 07 04:57:42 PM PDT 24
Finished Aug 07 04:57:43 PM PDT 24
Peak memory 204292 kb
Host smart-e989ecbb-054b-40b1-b9f5-7fa434d58ea7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027631424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.1
027631424
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.2139645503
Short name T116
Test name
Test status
Simulation time 189113146 ps
CPU time 1.74 seconds
Started Aug 07 04:57:39 PM PDT 24
Finished Aug 07 04:57:40 PM PDT 24
Peak memory 215720 kb
Host smart-73b3986e-d493-4f93-9131-2520ceb02baa
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139645503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.2139645503
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.2134909636
Short name T1058
Test name
Test status
Simulation time 13542509 ps
CPU time 0.69 seconds
Started Aug 07 04:57:47 PM PDT 24
Finished Aug 07 04:57:48 PM PDT 24
Peak memory 204472 kb
Host smart-3c85a284-f092-4d3b-b55d-b62ea98cdc95
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134909636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.2134909636
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.889453877
Short name T1112
Test name
Test status
Simulation time 583052297 ps
CPU time 3.9 seconds
Started Aug 07 04:57:42 PM PDT 24
Finished Aug 07 04:57:46 PM PDT 24
Peak memory 215672 kb
Host smart-5f685579-0cd0-4a46-8136-b5463b69b3ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889453877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sp
i_device_same_csr_outstanding.889453877
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2006060544
Short name T1138
Test name
Test status
Simulation time 123316452 ps
CPU time 3.9 seconds
Started Aug 07 04:57:45 PM PDT 24
Finished Aug 07 04:57:49 PM PDT 24
Peak memory 215864 kb
Host smart-6d1a2e81-e1f8-424b-9af7-4991b2bb650b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006060544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.2
006060544
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.654196617
Short name T250
Test name
Test status
Simulation time 843158017 ps
CPU time 20.82 seconds
Started Aug 07 04:57:39 PM PDT 24
Finished Aug 07 04:58:00 PM PDT 24
Peak memory 215776 kb
Host smart-44e3ea0a-1fce-41e4-99da-3be686570f1e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654196617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_
tl_intg_err.654196617
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2222567458
Short name T1139
Test name
Test status
Simulation time 14163826 ps
CPU time 0.74 seconds
Started Aug 07 04:57:50 PM PDT 24
Finished Aug 07 04:57:52 PM PDT 24
Peak memory 204300 kb
Host smart-3c1e1564-3a67-4d5f-a1fa-bdc4b48ca3c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222567458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
2222567458
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.3507749003
Short name T1035
Test name
Test status
Simulation time 38879275 ps
CPU time 0.78 seconds
Started Aug 07 04:57:50 PM PDT 24
Finished Aug 07 04:57:51 PM PDT 24
Peak memory 204444 kb
Host smart-e9430f06-4552-4ce5-9ce0-48a7912d429d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507749003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
3507749003
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.2675708820
Short name T1033
Test name
Test status
Simulation time 11902433 ps
CPU time 0.75 seconds
Started Aug 07 04:57:57 PM PDT 24
Finished Aug 07 04:57:58 PM PDT 24
Peak memory 204180 kb
Host smart-9a77524e-625d-4686-9e5a-28895d242d9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675708820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
2675708820
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.993389602
Short name T1123
Test name
Test status
Simulation time 32216407 ps
CPU time 0.68 seconds
Started Aug 07 04:58:08 PM PDT 24
Finished Aug 07 04:58:09 PM PDT 24
Peak memory 204196 kb
Host smart-bc2babfc-a1be-4cf7-9b0a-cb654d497647
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993389602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.993389602
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1674333330
Short name T1046
Test name
Test status
Simulation time 12135540 ps
CPU time 0.7 seconds
Started Aug 07 04:57:58 PM PDT 24
Finished Aug 07 04:57:59 PM PDT 24
Peak memory 204196 kb
Host smart-d773fb20-47fb-490a-82ee-510a168dd1bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674333330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
1674333330
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3192766349
Short name T1039
Test name
Test status
Simulation time 48933782 ps
CPU time 0.75 seconds
Started Aug 07 04:57:54 PM PDT 24
Finished Aug 07 04:57:55 PM PDT 24
Peak memory 204284 kb
Host smart-e646db9c-2adf-4e99-89f3-6b260e9d90af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192766349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
3192766349
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.1984873211
Short name T1119
Test name
Test status
Simulation time 17855211 ps
CPU time 0.75 seconds
Started Aug 07 04:58:38 PM PDT 24
Finished Aug 07 04:58:39 PM PDT 24
Peak memory 204304 kb
Host smart-6613e1a8-e824-4448-9fa9-07bfc31cbf30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984873211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
1984873211
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.1739919448
Short name T1066
Test name
Test status
Simulation time 56889836 ps
CPU time 0.75 seconds
Started Aug 07 04:58:04 PM PDT 24
Finished Aug 07 04:58:05 PM PDT 24
Peak memory 204196 kb
Host smart-2fbd0f14-9c15-412f-ad43-783b5a67c2fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739919448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
1739919448
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.3126021275
Short name T1110
Test name
Test status
Simulation time 136595844 ps
CPU time 0.71 seconds
Started Aug 07 04:57:47 PM PDT 24
Finished Aug 07 04:57:48 PM PDT 24
Peak memory 204308 kb
Host smart-06f71285-ba55-41c6-adce-1bee8ee49e13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126021275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
3126021275
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.1577261621
Short name T1100
Test name
Test status
Simulation time 18235345 ps
CPU time 0.77 seconds
Started Aug 07 04:57:57 PM PDT 24
Finished Aug 07 04:57:57 PM PDT 24
Peak memory 204300 kb
Host smart-166d615e-ad97-49db-9bb8-3ea898a09516
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577261621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
1577261621
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1328325269
Short name T103
Test name
Test status
Simulation time 84526018 ps
CPU time 2.85 seconds
Started Aug 07 04:57:34 PM PDT 24
Finished Aug 07 04:57:37 PM PDT 24
Peak memory 217152 kb
Host smart-b04f8930-328e-4e30-8662-fee54c78e77f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328325269 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.1328325269
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.2147353625
Short name T1057
Test name
Test status
Simulation time 113122426 ps
CPU time 1.86 seconds
Started Aug 07 04:57:35 PM PDT 24
Finished Aug 07 04:57:37 PM PDT 24
Peak memory 215688 kb
Host smart-262851c1-f1f5-42b3-9bc4-524b30b1976e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147353625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.2
147353625
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.4115233757
Short name T1086
Test name
Test status
Simulation time 101740401 ps
CPU time 0.68 seconds
Started Aug 07 04:57:33 PM PDT 24
Finished Aug 07 04:57:34 PM PDT 24
Peak memory 204188 kb
Host smart-a6d26eee-bc31-443c-aee8-7bf6d646e0ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115233757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.4
115233757
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.1738429191
Short name T136
Test name
Test status
Simulation time 235456137 ps
CPU time 1.84 seconds
Started Aug 07 04:57:35 PM PDT 24
Finished Aug 07 04:57:37 PM PDT 24
Peak memory 215620 kb
Host smart-1733aa3a-b3ea-442a-9b81-e6dc6bdcba57
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738429191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.1738429191
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.3107405486
Short name T97
Test name
Test status
Simulation time 1619962607 ps
CPU time 2.88 seconds
Started Aug 07 04:57:30 PM PDT 24
Finished Aug 07 04:57:33 PM PDT 24
Peak memory 216104 kb
Host smart-80b26545-c202-4dc0-8a42-d8f92b92aa37
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107405486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.3
107405486
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.3803472270
Short name T1099
Test name
Test status
Simulation time 436553679 ps
CPU time 7.47 seconds
Started Aug 07 04:57:35 PM PDT 24
Finished Aug 07 04:57:43 PM PDT 24
Peak memory 215712 kb
Host smart-fa5199ad-0057-43a8-9118-b4705c43d0db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803472270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.3803472270
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3725434310
Short name T1105
Test name
Test status
Simulation time 241547306 ps
CPU time 1.72 seconds
Started Aug 07 04:57:36 PM PDT 24
Finished Aug 07 04:57:38 PM PDT 24
Peak memory 215848 kb
Host smart-5f06b2e1-b2f4-4230-b92d-ba1e3adc9913
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725434310 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.3725434310
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.1866741297
Short name T1141
Test name
Test status
Simulation time 192511690 ps
CPU time 1.54 seconds
Started Aug 07 04:57:44 PM PDT 24
Finished Aug 07 04:57:46 PM PDT 24
Peak memory 207604 kb
Host smart-e5bf773c-b4b2-46a7-8bec-601e8632d127
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866741297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.1
866741297
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.3885427755
Short name T1117
Test name
Test status
Simulation time 20145978 ps
CPU time 0.81 seconds
Started Aug 07 04:57:40 PM PDT 24
Finished Aug 07 04:57:40 PM PDT 24
Peak memory 204300 kb
Host smart-2e2072c1-a9d9-411b-a602-fb4ba6022530
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885427755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.3
885427755
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.1139017003
Short name T1068
Test name
Test status
Simulation time 255697077 ps
CPU time 2.17 seconds
Started Aug 07 04:57:45 PM PDT 24
Finished Aug 07 04:57:47 PM PDT 24
Peak memory 207588 kb
Host smart-a32f3709-1fda-466d-98d8-2a96b6c55ec5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139017003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.1139017003
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2916004310
Short name T104
Test name
Test status
Simulation time 187719639 ps
CPU time 2.45 seconds
Started Aug 07 04:57:40 PM PDT 24
Finished Aug 07 04:57:42 PM PDT 24
Peak memory 215880 kb
Host smart-7d19b525-c28a-40de-9707-a1b3b634dcef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916004310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.2
916004310
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1034261547
Short name T1137
Test name
Test status
Simulation time 828566603 ps
CPU time 12.24 seconds
Started Aug 07 04:57:42 PM PDT 24
Finished Aug 07 04:57:54 PM PDT 24
Peak memory 215908 kb
Host smart-75650e68-d83f-4318-bc5d-725e11ca2d25
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034261547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.1034261547
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.447634759
Short name T1148
Test name
Test status
Simulation time 202762716 ps
CPU time 3.22 seconds
Started Aug 07 04:57:32 PM PDT 24
Finished Aug 07 04:57:35 PM PDT 24
Peak memory 217436 kb
Host smart-804ba428-a17a-454d-b075-fb8817367908
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447634759 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.447634759
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.3140847722
Short name T111
Test name
Test status
Simulation time 77081351 ps
CPU time 2 seconds
Started Aug 07 04:57:40 PM PDT 24
Finished Aug 07 04:57:42 PM PDT 24
Peak memory 215728 kb
Host smart-b20c696e-b2d8-4216-a59f-f8167f2b2dbf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140847722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.3
140847722
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.3781045125
Short name T1091
Test name
Test status
Simulation time 15445131 ps
CPU time 0.74 seconds
Started Aug 07 04:57:34 PM PDT 24
Finished Aug 07 04:57:35 PM PDT 24
Peak memory 204300 kb
Host smart-01a61826-3852-4462-b3d2-e191ff8a08ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781045125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.3
781045125
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.4151146057
Short name T1136
Test name
Test status
Simulation time 98260210 ps
CPU time 2.72 seconds
Started Aug 07 04:57:41 PM PDT 24
Finished Aug 07 04:57:43 PM PDT 24
Peak memory 215772 kb
Host smart-a2e71293-2a84-4b4d-b05b-a0df8f28c198
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151146057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.4151146057
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.2836096799
Short name T98
Test name
Test status
Simulation time 612781701 ps
CPU time 4.36 seconds
Started Aug 07 04:57:37 PM PDT 24
Finished Aug 07 04:57:42 PM PDT 24
Peak memory 215908 kb
Host smart-f0a8fd00-5362-4e0d-a09e-9ec1eb77ac98
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836096799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.2
836096799
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.2756305117
Short name T243
Test name
Test status
Simulation time 1204554355 ps
CPU time 20.6 seconds
Started Aug 07 04:57:34 PM PDT 24
Finished Aug 07 04:57:55 PM PDT 24
Peak memory 216208 kb
Host smart-c5fab54d-65ac-4fc8-b6d3-99e68b8fcc0f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756305117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.2756305117
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.1451158773
Short name T1073
Test name
Test status
Simulation time 387440693 ps
CPU time 1.85 seconds
Started Aug 07 04:57:44 PM PDT 24
Finished Aug 07 04:57:46 PM PDT 24
Peak memory 215892 kb
Host smart-8443da7e-69c8-4e9b-8d89-021310c80e86
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451158773 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.1451158773
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.467016901
Short name T1134
Test name
Test status
Simulation time 156410407 ps
CPU time 1.42 seconds
Started Aug 07 04:57:46 PM PDT 24
Finished Aug 07 04:57:48 PM PDT 24
Peak memory 207500 kb
Host smart-0562cb3b-ced1-4443-83ea-7f73bab80926
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467016901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.467016901
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.1006385565
Short name T1067
Test name
Test status
Simulation time 31105387 ps
CPU time 0.74 seconds
Started Aug 07 04:57:33 PM PDT 24
Finished Aug 07 04:57:34 PM PDT 24
Peak memory 204652 kb
Host smart-c74bbce8-d821-4110-82c2-a5900b90ad37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006385565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.1
006385565
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.3838337915
Short name T1109
Test name
Test status
Simulation time 131508638 ps
CPU time 1.87 seconds
Started Aug 07 04:57:42 PM PDT 24
Finished Aug 07 04:57:44 PM PDT 24
Peak memory 215676 kb
Host smart-c4bf3233-4582-4934-87a4-e5147c08affa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838337915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.3838337915
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.101161279
Short name T1149
Test name
Test status
Simulation time 91156104 ps
CPU time 2.4 seconds
Started Aug 07 04:57:45 PM PDT 24
Finished Aug 07 04:57:47 PM PDT 24
Peak memory 215900 kb
Host smart-2a87c0ff-5172-47a7-9525-66f6270269eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101161279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.101161279
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.4159023821
Short name T93
Test name
Test status
Simulation time 312543482 ps
CPU time 19.49 seconds
Started Aug 07 04:57:44 PM PDT 24
Finished Aug 07 04:58:04 PM PDT 24
Peak memory 215596 kb
Host smart-30fd407b-7bc2-40a7-9f4c-530bfcc715bd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159023821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.4159023821
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.4147216497
Short name T96
Test name
Test status
Simulation time 55972720 ps
CPU time 3.67 seconds
Started Aug 07 04:57:37 PM PDT 24
Finished Aug 07 04:57:41 PM PDT 24
Peak memory 218772 kb
Host smart-ba683eba-b40c-4c7e-9acc-0bfcaadac99a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147216497 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.4147216497
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.2257076519
Short name T1126
Test name
Test status
Simulation time 145404114 ps
CPU time 2.41 seconds
Started Aug 07 04:57:33 PM PDT 24
Finished Aug 07 04:57:36 PM PDT 24
Peak memory 207644 kb
Host smart-caf6a9d7-8ab1-4566-8212-8ca717fff6ee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257076519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.2
257076519
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.2598064748
Short name T1034
Test name
Test status
Simulation time 15463864 ps
CPU time 0.7 seconds
Started Aug 07 04:57:40 PM PDT 24
Finished Aug 07 04:57:41 PM PDT 24
Peak memory 204308 kb
Host smart-8a62b440-bf45-4336-9eb6-a367f8edcf83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598064748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.2
598064748
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.1174991811
Short name T1092
Test name
Test status
Simulation time 149268786 ps
CPU time 2.96 seconds
Started Aug 07 04:57:52 PM PDT 24
Finished Aug 07 04:57:55 PM PDT 24
Peak memory 215720 kb
Host smart-ecfc0c90-3f13-4630-af4d-6c2e733714a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174991811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.1174991811
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.2329613988
Short name T89
Test name
Test status
Simulation time 671518436 ps
CPU time 4.12 seconds
Started Aug 07 04:57:33 PM PDT 24
Finished Aug 07 04:57:37 PM PDT 24
Peak memory 216004 kb
Host smart-4efc8c1e-68d5-49f3-a819-ebee79edae79
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329613988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.2
329613988
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.1448306205
Short name T529
Test name
Test status
Simulation time 160360332 ps
CPU time 0.74 seconds
Started Aug 07 06:19:52 PM PDT 24
Finished Aug 07 06:19:53 PM PDT 24
Peak memory 205316 kb
Host smart-d08b2b0e-50b4-44c8-9e13-8043a028a196
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448306205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.1
448306205
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.3950959036
Short name T642
Test name
Test status
Simulation time 7678441770 ps
CPU time 8.37 seconds
Started Aug 07 06:19:47 PM PDT 24
Finished Aug 07 06:19:56 PM PDT 24
Peak memory 225320 kb
Host smart-d88c5fe4-c59c-437f-958b-9a46a6e5749a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950959036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.3950959036
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.3898619658
Short name T596
Test name
Test status
Simulation time 61038598 ps
CPU time 0.79 seconds
Started Aug 07 06:19:45 PM PDT 24
Finished Aug 07 06:19:46 PM PDT 24
Peak memory 207396 kb
Host smart-853267b3-c68e-447e-b48f-5b0e474089c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898619658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.3898619658
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.333543027
Short name T810
Test name
Test status
Simulation time 17914434359 ps
CPU time 35.16 seconds
Started Aug 07 06:19:49 PM PDT 24
Finished Aug 07 06:20:24 PM PDT 24
Peak memory 240252 kb
Host smart-bca589e3-517b-4dc6-965c-2880b9ec9fca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333543027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.333543027
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.181672524
Short name T518
Test name
Test status
Simulation time 16034586045 ps
CPU time 80.25 seconds
Started Aug 07 06:19:51 PM PDT 24
Finished Aug 07 06:21:12 PM PDT 24
Peak memory 257376 kb
Host smart-f41c6f33-88cd-469c-b6e9-280374ed0555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181672524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.181672524
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.1626117228
Short name T734
Test name
Test status
Simulation time 54280450429 ps
CPU time 478.19 seconds
Started Aug 07 06:19:52 PM PDT 24
Finished Aug 07 06:27:50 PM PDT 24
Peak memory 255708 kb
Host smart-5c6eb16a-56e6-45f7-9da3-409e86ce1e52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626117228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.1626117228
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.2919110484
Short name T899
Test name
Test status
Simulation time 261483792 ps
CPU time 3.16 seconds
Started Aug 07 06:19:51 PM PDT 24
Finished Aug 07 06:19:54 PM PDT 24
Peak memory 233336 kb
Host smart-8900e433-a6da-448a-a92b-71ce8c05be5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919110484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.2919110484
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.306152612
Short name T472
Test name
Test status
Simulation time 99968115491 ps
CPU time 211.32 seconds
Started Aug 07 06:19:50 PM PDT 24
Finished Aug 07 06:23:21 PM PDT 24
Peak memory 253728 kb
Host smart-441cb12a-fcf9-4d5d-affb-535e8114a5a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306152612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds.
306152612
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_intercept.1056528487
Short name T186
Test name
Test status
Simulation time 373976642 ps
CPU time 3.16 seconds
Started Aug 07 06:19:50 PM PDT 24
Finished Aug 07 06:19:53 PM PDT 24
Peak memory 233496 kb
Host smart-e67d6654-95e3-41a6-a0ca-145c05306928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056528487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.1056528487
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.4233499708
Short name T748
Test name
Test status
Simulation time 16806868377 ps
CPU time 83.1 seconds
Started Aug 07 06:19:51 PM PDT 24
Finished Aug 07 06:21:14 PM PDT 24
Peak memory 240536 kb
Host smart-21827610-c1a9-415f-87b1-55b8b96f5b0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233499708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.4233499708
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.381313009
Short name T616
Test name
Test status
Simulation time 78907170 ps
CPU time 1.06 seconds
Started Aug 07 06:19:46 PM PDT 24
Finished Aug 07 06:19:47 PM PDT 24
Peak memory 217240 kb
Host smart-db70b1a2-961c-404b-b902-b6a792b6316a
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381313009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.spi_device_mem_parity.381313009
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.396216556
Short name T820
Test name
Test status
Simulation time 1057022785 ps
CPU time 9.85 seconds
Started Aug 07 06:19:49 PM PDT 24
Finished Aug 07 06:19:59 PM PDT 24
Peak memory 225252 kb
Host smart-421f8b73-f37c-4f78-9f60-5dc279bad24f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396216556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap.
396216556
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.4169339155
Short name T374
Test name
Test status
Simulation time 2053467995 ps
CPU time 3.27 seconds
Started Aug 07 06:19:46 PM PDT 24
Finished Aug 07 06:19:49 PM PDT 24
Peak memory 225176 kb
Host smart-af728c37-fd21-4c40-8e76-ed9fc4331a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169339155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.4169339155
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.350280404
Short name T504
Test name
Test status
Simulation time 3885928535 ps
CPU time 7.79 seconds
Started Aug 07 06:19:51 PM PDT 24
Finished Aug 07 06:19:59 PM PDT 24
Peak memory 222924 kb
Host smart-19b8c0ca-9513-4722-9bd6-e73387d64ac3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=350280404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_direc
t.350280404
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.3880549753
Short name T208
Test name
Test status
Simulation time 554367829869 ps
CPU time 687.37 seconds
Started Aug 07 06:19:48 PM PDT 24
Finished Aug 07 06:31:15 PM PDT 24
Peak memory 262836 kb
Host smart-e28859ac-6afc-4a2f-b653-045afb4f2816
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880549753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.3880549753
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.938906622
Short name T505
Test name
Test status
Simulation time 58150907 ps
CPU time 0.74 seconds
Started Aug 07 06:19:46 PM PDT 24
Finished Aug 07 06:19:47 PM PDT 24
Peak memory 206188 kb
Host smart-523bf686-d8fe-45f4-99ff-d4f2b48c52fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938906622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.938906622
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.880987039
Short name T948
Test name
Test status
Simulation time 25683056198 ps
CPU time 16.57 seconds
Started Aug 07 06:19:44 PM PDT 24
Finished Aug 07 06:20:01 PM PDT 24
Peak memory 217020 kb
Host smart-2d57b352-1bb0-4090-b51a-74a9bcecafc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880987039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.880987039
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.3886277839
Short name T925
Test name
Test status
Simulation time 94586710 ps
CPU time 2.41 seconds
Started Aug 07 06:19:42 PM PDT 24
Finished Aug 07 06:19:45 PM PDT 24
Peak memory 216976 kb
Host smart-d661aa44-6a1a-45a8-9bba-fdf749314f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886277839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.3886277839
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.581850658
Short name T998
Test name
Test status
Simulation time 124399553 ps
CPU time 0.82 seconds
Started Aug 07 06:19:45 PM PDT 24
Finished Aug 07 06:19:46 PM PDT 24
Peak memory 206616 kb
Host smart-f38f455e-e478-485f-bfb0-9ecb7581bdb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581850658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.581850658
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.443054438
Short name T512
Test name
Test status
Simulation time 45648847341 ps
CPU time 17.57 seconds
Started Aug 07 06:19:53 PM PDT 24
Finished Aug 07 06:20:11 PM PDT 24
Peak memory 241716 kb
Host smart-05557e15-c0fd-423d-b107-e931affae8a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443054438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.443054438
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.782008446
Short name T961
Test name
Test status
Simulation time 2077870799 ps
CPU time 29.64 seconds
Started Aug 07 06:19:54 PM PDT 24
Finished Aug 07 06:20:24 PM PDT 24
Peak memory 225240 kb
Host smart-de47c965-7436-4020-9ce1-a08f785e5e6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782008446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.782008446
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.3742091152
Short name T367
Test name
Test status
Simulation time 17048815 ps
CPU time 0.82 seconds
Started Aug 07 06:19:50 PM PDT 24
Finished Aug 07 06:19:51 PM PDT 24
Peak memory 207064 kb
Host smart-b4f9270b-129c-41dc-a282-eb1dae8f9189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742091152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.3742091152
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.2431738801
Short name T226
Test name
Test status
Simulation time 12226681239 ps
CPU time 63.43 seconds
Started Aug 07 06:19:49 PM PDT 24
Finished Aug 07 06:20:53 PM PDT 24
Peak memory 249940 kb
Host smart-1258b542-1354-499a-80ff-2bec52d23d4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431738801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.2431738801
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.342076499
Short name T553
Test name
Test status
Simulation time 6480427502 ps
CPU time 102.65 seconds
Started Aug 07 06:19:51 PM PDT 24
Finished Aug 07 06:21:34 PM PDT 24
Peak memory 257288 kb
Host smart-ddbfaa0b-e588-4e32-a5be-49de7414b15c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342076499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle.
342076499
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.4008699199
Short name T295
Test name
Test status
Simulation time 12370438345 ps
CPU time 67.78 seconds
Started Aug 07 06:19:50 PM PDT 24
Finished Aug 07 06:20:58 PM PDT 24
Peak memory 248400 kb
Host smart-359db56c-4eaa-4a51-91fc-cd8d0e293b34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008699199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.4008699199
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.786694127
Short name T661
Test name
Test status
Simulation time 121351173197 ps
CPU time 432.48 seconds
Started Aug 07 06:19:51 PM PDT 24
Finished Aug 07 06:27:04 PM PDT 24
Peak memory 261644 kb
Host smart-e9c64356-700f-4c73-a4ad-3cf3d6ba33ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786694127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds.
786694127
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/1.spi_device_intercept.785967327
Short name T573
Test name
Test status
Simulation time 260061090 ps
CPU time 3.96 seconds
Started Aug 07 06:19:50 PM PDT 24
Finished Aug 07 06:19:55 PM PDT 24
Peak memory 233488 kb
Host smart-30808578-ca22-4757-ae97-3b06000c7e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785967327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.785967327
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.808815650
Short name T740
Test name
Test status
Simulation time 506783460 ps
CPU time 10.75 seconds
Started Aug 07 06:19:49 PM PDT 24
Finished Aug 07 06:20:00 PM PDT 24
Peak memory 241228 kb
Host smart-14e47bf1-a345-40a3-9a03-1a610475d39e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808815650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.808815650
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.2202879904
Short name T912
Test name
Test status
Simulation time 3639785148 ps
CPU time 6.96 seconds
Started Aug 07 06:19:54 PM PDT 24
Finished Aug 07 06:20:01 PM PDT 24
Peak memory 225352 kb
Host smart-ab12602c-830c-4cc2-8e6e-63125f2d29b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202879904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.2202879904
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.3644114355
Short name T612
Test name
Test status
Simulation time 1356317196 ps
CPU time 9.69 seconds
Started Aug 07 06:19:50 PM PDT 24
Finished Aug 07 06:20:00 PM PDT 24
Peak memory 233624 kb
Host smart-0cf97ccf-ef83-4e5d-9245-bfd9ec729450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644114355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.3644114355
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.351887859
Short name T465
Test name
Test status
Simulation time 775710907 ps
CPU time 9.77 seconds
Started Aug 07 06:19:51 PM PDT 24
Finished Aug 07 06:20:01 PM PDT 24
Peak memory 219308 kb
Host smart-881b289e-9192-44e8-ba2a-df7a02d50709
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=351887859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_direc
t.351887859
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.2818029515
Short name T55
Test name
Test status
Simulation time 294534310 ps
CPU time 1.19 seconds
Started Aug 07 06:19:51 PM PDT 24
Finished Aug 07 06:19:52 PM PDT 24
Peak memory 235612 kb
Host smart-5e5d83ae-bea4-454d-b033-e6f0f536341f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818029515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.2818029515
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.1333031572
Short name T304
Test name
Test status
Simulation time 7473880807 ps
CPU time 36.96 seconds
Started Aug 07 06:19:48 PM PDT 24
Finished Aug 07 06:20:25 PM PDT 24
Peak memory 221664 kb
Host smart-e2100ece-d181-4b69-8824-fc35e8839710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333031572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.1333031572
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.3050922574
Short name T461
Test name
Test status
Simulation time 11005673945 ps
CPU time 3.12 seconds
Started Aug 07 06:19:49 PM PDT 24
Finished Aug 07 06:19:52 PM PDT 24
Peak memory 216768 kb
Host smart-df3cae72-c9ef-4aaa-8056-9cc25fc035e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050922574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.3050922574
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.2980118257
Short name T825
Test name
Test status
Simulation time 39460214 ps
CPU time 1.26 seconds
Started Aug 07 06:19:50 PM PDT 24
Finished Aug 07 06:19:52 PM PDT 24
Peak memory 217056 kb
Host smart-8143c888-0096-491e-8976-3131fd777d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980118257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.2980118257
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.1650166207
Short name T696
Test name
Test status
Simulation time 31733194 ps
CPU time 0.84 seconds
Started Aug 07 06:19:51 PM PDT 24
Finished Aug 07 06:19:52 PM PDT 24
Peak memory 206564 kb
Host smart-5a65ed33-da51-419d-ac01-43c122fccb08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650166207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.1650166207
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.2970034029
Short name T654
Test name
Test status
Simulation time 5674943799 ps
CPU time 17.81 seconds
Started Aug 07 06:19:48 PM PDT 24
Finished Aug 07 06:20:06 PM PDT 24
Peak memory 233508 kb
Host smart-c31ca6fb-5ee0-4619-914d-082428e35eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970034029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.2970034029
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.1730788984
Short name T676
Test name
Test status
Simulation time 14013087 ps
CPU time 0.76 seconds
Started Aug 07 06:20:18 PM PDT 24
Finished Aug 07 06:20:18 PM PDT 24
Peak memory 205292 kb
Host smart-2c045c11-0610-4c43-8766-81275f281c0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730788984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
1730788984
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.2904846751
Short name T82
Test name
Test status
Simulation time 94173007 ps
CPU time 2.27 seconds
Started Aug 07 06:20:19 PM PDT 24
Finished Aug 07 06:20:21 PM PDT 24
Peak memory 225220 kb
Host smart-48297ff7-b597-45a3-bdca-5536d4fd2c2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904846751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.2904846751
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.1536423160
Short name T395
Test name
Test status
Simulation time 129206650 ps
CPU time 0.76 seconds
Started Aug 07 06:20:16 PM PDT 24
Finished Aug 07 06:20:17 PM PDT 24
Peak memory 207068 kb
Host smart-4a643155-eca9-42c9-8e5f-685db4b3c7b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536423160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.1536423160
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.85615169
Short name T363
Test name
Test status
Simulation time 16640244452 ps
CPU time 109.61 seconds
Started Aug 07 06:20:27 PM PDT 24
Finished Aug 07 06:22:17 PM PDT 24
Peak memory 252196 kb
Host smart-368fa0c8-79de-444a-8cad-824abb592668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85615169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.85615169
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.3610956737
Short name T517
Test name
Test status
Simulation time 3554025607 ps
CPU time 43.38 seconds
Started Aug 07 06:20:19 PM PDT 24
Finished Aug 07 06:21:02 PM PDT 24
Peak memory 249984 kb
Host smart-0c845e0f-ede5-49e1-947e-13ab2e2fe87a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610956737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.3610956737
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.3313730025
Short name T284
Test name
Test status
Simulation time 3579605344 ps
CPU time 44.05 seconds
Started Aug 07 06:20:26 PM PDT 24
Finished Aug 07 06:21:11 PM PDT 24
Peak memory 233580 kb
Host smart-f769b574-2ed7-4560-b7c2-ea0c5657e411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313730025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.3313730025
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.4060807834
Short name T816
Test name
Test status
Simulation time 6595537251 ps
CPU time 54.78 seconds
Started Aug 07 06:20:22 PM PDT 24
Finished Aug 07 06:21:17 PM PDT 24
Peak memory 249932 kb
Host smart-578bf53c-92b6-4b61-9c64-8e3ea84982aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060807834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmd
s.4060807834
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/10.spi_device_intercept.2404799133
Short name T637
Test name
Test status
Simulation time 108054223 ps
CPU time 2.38 seconds
Started Aug 07 06:20:24 PM PDT 24
Finished Aug 07 06:20:27 PM PDT 24
Peak memory 225212 kb
Host smart-7c97acc8-7032-41dc-9e82-f7ec58ca7240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404799133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.2404799133
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.1635123602
Short name T546
Test name
Test status
Simulation time 1668420553 ps
CPU time 10.19 seconds
Started Aug 07 06:20:20 PM PDT 24
Finished Aug 07 06:20:30 PM PDT 24
Peak memory 233472 kb
Host smart-ab6dbcac-49fc-49f5-9cea-1ba7b494eca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635123602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.1635123602
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.3688907262
Short name T1007
Test name
Test status
Simulation time 30517156 ps
CPU time 0.97 seconds
Started Aug 07 06:20:25 PM PDT 24
Finished Aug 07 06:20:26 PM PDT 24
Peak memory 218424 kb
Host smart-10075d22-cf60-4f13-966d-ba9afeec758b
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688907262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.spi_device_mem_parity.3688907262
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.1170091234
Short name T572
Test name
Test status
Simulation time 255775827 ps
CPU time 3.98 seconds
Started Aug 07 06:20:21 PM PDT 24
Finished Aug 07 06:20:25 PM PDT 24
Peak memory 225224 kb
Host smart-1d1b5cac-8458-451f-815c-1fa27f9dee06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170091234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.1170091234
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.3143431165
Short name T282
Test name
Test status
Simulation time 317106127 ps
CPU time 2.72 seconds
Started Aug 07 06:20:20 PM PDT 24
Finished Aug 07 06:20:22 PM PDT 24
Peak memory 225116 kb
Host smart-d4963a5d-4324-491b-9b00-a7b8b9c4ac1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143431165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.3143431165
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.1748161104
Short name T666
Test name
Test status
Simulation time 1142317983 ps
CPU time 5.16 seconds
Started Aug 07 06:20:19 PM PDT 24
Finished Aug 07 06:20:24 PM PDT 24
Peak memory 223244 kb
Host smart-00784941-e9e9-4779-9fe2-137243489959
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1748161104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.1748161104
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.2921543525
Short name T705
Test name
Test status
Simulation time 25204424270 ps
CPU time 150.45 seconds
Started Aug 07 06:20:19 PM PDT 24
Finished Aug 07 06:22:50 PM PDT 24
Peak memory 266348 kb
Host smart-cacb0053-3198-46cb-8e1f-b50f04d38022
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921543525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.2921543525
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.3258470455
Short name T125
Test name
Test status
Simulation time 4089202226 ps
CPU time 18.38 seconds
Started Aug 07 06:20:25 PM PDT 24
Finished Aug 07 06:20:43 PM PDT 24
Peak memory 217148 kb
Host smart-d89ced38-ea5b-4b22-b85b-4eef2c9d70af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258470455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.3258470455
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.2357599573
Short name T507
Test name
Test status
Simulation time 98609578 ps
CPU time 1.6 seconds
Started Aug 07 06:20:20 PM PDT 24
Finished Aug 07 06:20:22 PM PDT 24
Peak memory 207508 kb
Host smart-35ae5c1d-a0d1-4973-afce-01af9c9f1803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357599573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.2357599573
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.4161920700
Short name T608
Test name
Test status
Simulation time 64535171 ps
CPU time 1.18 seconds
Started Aug 07 06:20:27 PM PDT 24
Finished Aug 07 06:20:28 PM PDT 24
Peak memory 208532 kb
Host smart-4831082e-67a0-45a8-ab54-071728b4f61b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161920700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.4161920700
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.2221159513
Short name T919
Test name
Test status
Simulation time 50236956 ps
CPU time 0.91 seconds
Started Aug 07 06:20:26 PM PDT 24
Finished Aug 07 06:20:27 PM PDT 24
Peak memory 207660 kb
Host smart-12728790-a804-49e7-803a-9cf9f84475bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221159513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.2221159513
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.3370073784
Short name T829
Test name
Test status
Simulation time 10750631380 ps
CPU time 11.21 seconds
Started Aug 07 06:20:21 PM PDT 24
Finished Aug 07 06:20:32 PM PDT 24
Peak memory 233484 kb
Host smart-cbf0d1a6-7cf2-45eb-abd6-e96833db0989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370073784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.3370073784
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.1478598232
Short name T947
Test name
Test status
Simulation time 13336381 ps
CPU time 0.7 seconds
Started Aug 07 06:20:26 PM PDT 24
Finished Aug 07 06:20:27 PM PDT 24
Peak memory 205264 kb
Host smart-ae7ec27a-ed54-4e43-9204-0c904298b6d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478598232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
1478598232
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.2847750945
Short name T258
Test name
Test status
Simulation time 865791006 ps
CPU time 10.52 seconds
Started Aug 07 06:20:26 PM PDT 24
Finished Aug 07 06:20:36 PM PDT 24
Peak memory 233444 kb
Host smart-0bdf4d48-b5bf-4642-9a53-a5a78eb575f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847750945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.2847750945
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.1260874725
Short name T324
Test name
Test status
Simulation time 22263858 ps
CPU time 0.83 seconds
Started Aug 07 06:20:19 PM PDT 24
Finished Aug 07 06:20:20 PM PDT 24
Peak memory 207392 kb
Host smart-03cb33c8-b84b-4b40-8856-6b0c722a6910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260874725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.1260874725
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.1297031203
Short name T560
Test name
Test status
Simulation time 10995462421 ps
CPU time 74 seconds
Started Aug 07 06:20:30 PM PDT 24
Finished Aug 07 06:21:44 PM PDT 24
Peak memory 255956 kb
Host smart-f7e01404-6b96-4fcd-83ab-93d900e6225e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297031203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.1297031203
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.2962371347
Short name T271
Test name
Test status
Simulation time 5186042635 ps
CPU time 72.54 seconds
Started Aug 07 06:20:27 PM PDT 24
Finished Aug 07 06:21:39 PM PDT 24
Peak memory 266152 kb
Host smart-bd9674a8-486c-4a66-a506-4157c912df98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962371347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.2962371347
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.2757290330
Short name T1014
Test name
Test status
Simulation time 6485039702 ps
CPU time 8.72 seconds
Started Aug 07 06:20:26 PM PDT 24
Finished Aug 07 06:20:35 PM PDT 24
Peak memory 225320 kb
Host smart-861dc52c-db2c-4a66-9e06-8fcd107087e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757290330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.2757290330
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.3457989433
Short name T228
Test name
Test status
Simulation time 29822258010 ps
CPU time 93.54 seconds
Started Aug 07 06:20:24 PM PDT 24
Finished Aug 07 06:21:57 PM PDT 24
Peak memory 256604 kb
Host smart-56ab92b8-79b8-4dd0-9992-c83d42f4afe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457989433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmd
s.3457989433
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_intercept.2261206240
Short name T383
Test name
Test status
Simulation time 722482402 ps
CPU time 2.92 seconds
Started Aug 07 06:20:22 PM PDT 24
Finished Aug 07 06:20:25 PM PDT 24
Peak memory 233444 kb
Host smart-9db1bfad-69c1-4d33-a63f-712639af0557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261206240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.2261206240
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.590487528
Short name T345
Test name
Test status
Simulation time 1403949133 ps
CPU time 2.88 seconds
Started Aug 07 06:20:25 PM PDT 24
Finished Aug 07 06:20:28 PM PDT 24
Peak memory 225136 kb
Host smart-c5e5ebfe-9425-4a2a-9fd7-da13a7f363df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590487528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.590487528
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.3613014584
Short name T35
Test name
Test status
Simulation time 16085101 ps
CPU time 1.04 seconds
Started Aug 07 06:20:19 PM PDT 24
Finished Aug 07 06:20:20 PM PDT 24
Peak memory 217228 kb
Host smart-28e7bac3-15a7-4622-9257-f88240d5578e
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613014584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.spi_device_mem_parity.3613014584
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.924273544
Short name T570
Test name
Test status
Simulation time 124889467 ps
CPU time 2.92 seconds
Started Aug 07 06:20:21 PM PDT 24
Finished Aug 07 06:20:24 PM PDT 24
Peak memory 233432 kb
Host smart-a6cbbed7-afdd-4973-91b2-e5bf1a50ef7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924273544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swap
.924273544
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.1454277994
Short name T460
Test name
Test status
Simulation time 366275637 ps
CPU time 2.63 seconds
Started Aug 07 06:20:24 PM PDT 24
Finished Aug 07 06:20:27 PM PDT 24
Peak memory 225216 kb
Host smart-83537ed9-2c32-4a10-916e-8425880e0326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454277994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.1454277994
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.90789236
Short name T895
Test name
Test status
Simulation time 1126303122 ps
CPU time 5.34 seconds
Started Aug 07 06:20:23 PM PDT 24
Finished Aug 07 06:20:28 PM PDT 24
Peak memory 220580 kb
Host smart-d83c801b-bb41-42a2-aaa0-c0b2b89fdd40
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=90789236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_direc
t.90789236
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.4090984344
Short name T31
Test name
Test status
Simulation time 62676329 ps
CPU time 1.15 seconds
Started Aug 07 06:20:26 PM PDT 24
Finished Aug 07 06:20:27 PM PDT 24
Peak memory 208244 kb
Host smart-5e86d869-70e5-4b7f-8d8b-7909a1e9db92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090984344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.4090984344
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.3906809676
Short name T858
Test name
Test status
Simulation time 391854198 ps
CPU time 6.84 seconds
Started Aug 07 06:20:20 PM PDT 24
Finished Aug 07 06:20:27 PM PDT 24
Peak memory 217028 kb
Host smart-3c222f45-0644-4c5d-80bc-82356a0fee33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906809676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.3906809676
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.1233249885
Short name T609
Test name
Test status
Simulation time 1156478570 ps
CPU time 5.54 seconds
Started Aug 07 06:20:21 PM PDT 24
Finished Aug 07 06:20:27 PM PDT 24
Peak memory 216952 kb
Host smart-e78e9e07-c1dd-4295-a9ec-cecf7a57b8d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233249885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.1233249885
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.1451175991
Short name T334
Test name
Test status
Simulation time 407888268 ps
CPU time 1.8 seconds
Started Aug 07 06:20:23 PM PDT 24
Finished Aug 07 06:20:25 PM PDT 24
Peak memory 216992 kb
Host smart-d9aa2c19-098c-482b-848e-5f4aafa1cf70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451175991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.1451175991
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.1821363360
Short name T744
Test name
Test status
Simulation time 21709792 ps
CPU time 0.72 seconds
Started Aug 07 06:20:25 PM PDT 24
Finished Aug 07 06:20:26 PM PDT 24
Peak memory 206588 kb
Host smart-077a70b1-4080-4522-b9e2-60892e2bee5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821363360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.1821363360
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.1986005479
Short name T898
Test name
Test status
Simulation time 147897929 ps
CPU time 2.82 seconds
Started Aug 07 06:20:21 PM PDT 24
Finished Aug 07 06:20:24 PM PDT 24
Peak memory 233456 kb
Host smart-2c5445b5-0002-4f04-8bab-fa36a1cd9c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986005479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.1986005479
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.3644211971
Short name T711
Test name
Test status
Simulation time 13989645 ps
CPU time 0.73 seconds
Started Aug 07 06:20:25 PM PDT 24
Finished Aug 07 06:20:26 PM PDT 24
Peak memory 205880 kb
Host smart-4941b9be-7e83-4d71-ae9b-95d4e6f87efe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644211971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
3644211971
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.3079082236
Short name T190
Test name
Test status
Simulation time 709114861 ps
CPU time 4.55 seconds
Started Aug 07 06:20:32 PM PDT 24
Finished Aug 07 06:20:37 PM PDT 24
Peak memory 233384 kb
Host smart-69bfad81-0075-4f91-9d8a-b736fa7df512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079082236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.3079082236
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.529723617
Short name T621
Test name
Test status
Simulation time 41756937 ps
CPU time 0.76 seconds
Started Aug 07 06:20:31 PM PDT 24
Finished Aug 07 06:20:32 PM PDT 24
Peak memory 205988 kb
Host smart-4c261ae9-6ff3-46bd-bafd-d882674cde88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529723617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.529723617
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.1015436170
Short name T875
Test name
Test status
Simulation time 4777203745 ps
CPU time 18.79 seconds
Started Aug 07 06:20:26 PM PDT 24
Finished Aug 07 06:20:45 PM PDT 24
Peak memory 235312 kb
Host smart-b034c01e-cc35-47f4-b72d-37a7b3e880ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015436170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.1015436170
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.3260547764
Short name T684
Test name
Test status
Simulation time 21793017850 ps
CPU time 56.81 seconds
Started Aug 07 06:20:25 PM PDT 24
Finished Aug 07 06:21:22 PM PDT 24
Peak memory 258028 kb
Host smart-2d006977-1cfd-4bfa-8273-bb135537fa52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260547764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.3260547764
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.1775969003
Short name T944
Test name
Test status
Simulation time 2492969761 ps
CPU time 11.14 seconds
Started Aug 07 06:20:26 PM PDT 24
Finished Aug 07 06:20:37 PM PDT 24
Peak memory 233492 kb
Host smart-90d1b752-892a-40bf-b68a-5e29d5d7c02e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775969003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.1775969003
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.2407581580
Short name T851
Test name
Test status
Simulation time 14712257570 ps
CPU time 28.26 seconds
Started Aug 07 06:20:31 PM PDT 24
Finished Aug 07 06:21:00 PM PDT 24
Peak memory 233508 kb
Host smart-6c6dabfd-2270-4ea9-9e9a-85f67cce74ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407581580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmd
s.2407581580
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_intercept.3905077384
Short name T262
Test name
Test status
Simulation time 494166872 ps
CPU time 6.25 seconds
Started Aug 07 06:20:27 PM PDT 24
Finished Aug 07 06:20:33 PM PDT 24
Peak memory 233460 kb
Host smart-3916b418-ecb4-4db7-ace1-e4c8e37e0712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905077384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.3905077384
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.2252705552
Short name T432
Test name
Test status
Simulation time 31163962 ps
CPU time 2.2 seconds
Started Aug 07 06:20:27 PM PDT 24
Finished Aug 07 06:20:29 PM PDT 24
Peak memory 233088 kb
Host smart-1ebf13d9-a019-42fc-ac27-0b3754e25013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252705552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.2252705552
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.1719467022
Short name T931
Test name
Test status
Simulation time 117245633 ps
CPU time 1.11 seconds
Started Aug 07 06:20:27 PM PDT 24
Finished Aug 07 06:20:28 PM PDT 24
Peak memory 217208 kb
Host smart-aa5dda27-bd5c-406b-bcab-42cad8997754
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719467022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.spi_device_mem_parity.1719467022
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.3843050648
Short name T952
Test name
Test status
Simulation time 11021925667 ps
CPU time 31.16 seconds
Started Aug 07 06:20:25 PM PDT 24
Finished Aug 07 06:20:56 PM PDT 24
Peak memory 239720 kb
Host smart-4f2488cb-7afb-4d30-abbb-f94239e6ddde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843050648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.3843050648
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.2328115821
Short name T978
Test name
Test status
Simulation time 3522904564 ps
CPU time 7.94 seconds
Started Aug 07 06:20:33 PM PDT 24
Finished Aug 07 06:20:41 PM PDT 24
Peak memory 234824 kb
Host smart-1bb0ab73-d100-4f6a-a918-eaf97379482f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328115821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.2328115821
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.3450366719
Short name T406
Test name
Test status
Simulation time 881476793 ps
CPU time 9.3 seconds
Started Aug 07 06:20:25 PM PDT 24
Finished Aug 07 06:20:35 PM PDT 24
Peak memory 222388 kb
Host smart-26ee3fca-c159-4d97-85f4-a2631eb3872b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3450366719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.3450366719
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.280004015
Short name T817
Test name
Test status
Simulation time 84629352697 ps
CPU time 227.25 seconds
Started Aug 07 06:20:27 PM PDT 24
Finished Aug 07 06:24:15 PM PDT 24
Peak memory 265820 kb
Host smart-11dccfca-7469-4d28-9a8e-0e9ae22d25ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280004015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stres
s_all.280004015
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.3168408376
Short name T970
Test name
Test status
Simulation time 6324713337 ps
CPU time 31.64 seconds
Started Aug 07 06:20:27 PM PDT 24
Finished Aug 07 06:20:59 PM PDT 24
Peak memory 217080 kb
Host smart-be99b03d-3e7e-4647-a95c-4996ba99414a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168408376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.3168408376
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.851111012
Short name T77
Test name
Test status
Simulation time 280727193 ps
CPU time 2.61 seconds
Started Aug 07 06:20:25 PM PDT 24
Finished Aug 07 06:20:28 PM PDT 24
Peak memory 217012 kb
Host smart-b0af1cdc-7134-4b97-94de-674fae035af3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851111012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.851111012
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.1026421849
Short name T352
Test name
Test status
Simulation time 146874356 ps
CPU time 0.86 seconds
Started Aug 07 06:20:26 PM PDT 24
Finished Aug 07 06:20:27 PM PDT 24
Peak memory 207148 kb
Host smart-52978ef1-6a10-457e-8eeb-c387d1ad055f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026421849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.1026421849
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.2643369345
Short name T665
Test name
Test status
Simulation time 160281624 ps
CPU time 0.85 seconds
Started Aug 07 06:20:27 PM PDT 24
Finished Aug 07 06:20:28 PM PDT 24
Peak memory 206580 kb
Host smart-d4ee59bc-4113-415b-b5ff-bd402e0be436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643369345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.2643369345
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.2909787051
Short name T451
Test name
Test status
Simulation time 10419705022 ps
CPU time 9.62 seconds
Started Aug 07 06:20:30 PM PDT 24
Finished Aug 07 06:20:40 PM PDT 24
Peak memory 225244 kb
Host smart-e2c2fb7c-e45c-47a6-96ee-e379f43d7698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909787051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.2909787051
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.3668260177
Short name T999
Test name
Test status
Simulation time 22108901 ps
CPU time 0.71 seconds
Started Aug 07 06:20:31 PM PDT 24
Finished Aug 07 06:20:32 PM PDT 24
Peak memory 205896 kb
Host smart-0925fd2b-3509-4a19-bfe4-f4430079c8c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668260177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
3668260177
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.2647617854
Short name T48
Test name
Test status
Simulation time 501025465 ps
CPU time 3.04 seconds
Started Aug 07 06:20:30 PM PDT 24
Finished Aug 07 06:20:34 PM PDT 24
Peak memory 225268 kb
Host smart-4f9c5507-1599-4006-a337-fda77d9998de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647617854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.2647617854
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.2858865640
Short name T935
Test name
Test status
Simulation time 15296730 ps
CPU time 0.76 seconds
Started Aug 07 06:20:30 PM PDT 24
Finished Aug 07 06:20:31 PM PDT 24
Peak memory 206036 kb
Host smart-d8a426a0-baf6-4d28-869f-2a144b0ac333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858865640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.2858865640
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.3968474763
Short name T824
Test name
Test status
Simulation time 1853526443 ps
CPU time 53.18 seconds
Started Aug 07 06:20:30 PM PDT 24
Finished Aug 07 06:21:24 PM PDT 24
Peak memory 250112 kb
Host smart-4779192b-ea6b-420c-bae2-47bdb60e02ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968474763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.3968474763
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.1838688168
Short name T69
Test name
Test status
Simulation time 6751762864 ps
CPU time 77.07 seconds
Started Aug 07 06:20:31 PM PDT 24
Finished Aug 07 06:21:48 PM PDT 24
Peak memory 249976 kb
Host smart-cdb0bebc-a2b5-4129-9c48-b75bb87a474f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838688168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.1838688168
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.4032453203
Short name T297
Test name
Test status
Simulation time 207552320 ps
CPU time 7.33 seconds
Started Aug 07 06:20:29 PM PDT 24
Finished Aug 07 06:20:36 PM PDT 24
Peak memory 225288 kb
Host smart-0c878f3d-81d2-4528-a945-5eb77290bc0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032453203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.4032453203
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_intercept.3233814854
Short name T567
Test name
Test status
Simulation time 10665907430 ps
CPU time 19.88 seconds
Started Aug 07 06:20:25 PM PDT 24
Finished Aug 07 06:20:45 PM PDT 24
Peak memory 220868 kb
Host smart-415c599f-88ff-4ad4-a28d-96655b7d9cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233814854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.3233814854
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.3233534832
Short name T180
Test name
Test status
Simulation time 514788311 ps
CPU time 14.11 seconds
Started Aug 07 06:20:32 PM PDT 24
Finished Aug 07 06:20:47 PM PDT 24
Peak memory 239084 kb
Host smart-c5a4db4d-1fb1-47c5-a590-7224027382c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233534832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.3233534832
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.2432215062
Short name T758
Test name
Test status
Simulation time 133469503 ps
CPU time 1.16 seconds
Started Aug 07 06:20:34 PM PDT 24
Finished Aug 07 06:20:35 PM PDT 24
Peak memory 217204 kb
Host smart-ea593a31-237a-4dfb-b53b-dfb53e304070
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432215062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.spi_device_mem_parity.2432215062
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.2187213591
Short name T181
Test name
Test status
Simulation time 990667072 ps
CPU time 4.05 seconds
Started Aug 07 06:20:26 PM PDT 24
Finished Aug 07 06:20:31 PM PDT 24
Peak memory 225256 kb
Host smart-6dd54d07-baf2-46d1-bee1-ead6f29dee12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187213591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.2187213591
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.2329001758
Short name T640
Test name
Test status
Simulation time 1140318860 ps
CPU time 5.28 seconds
Started Aug 07 06:20:29 PM PDT 24
Finished Aug 07 06:20:34 PM PDT 24
Peak memory 225284 kb
Host smart-5c28b0f9-eb79-474d-9130-7d0768d6464d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329001758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.2329001758
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.196606947
Short name T865
Test name
Test status
Simulation time 501285859 ps
CPU time 5.09 seconds
Started Aug 07 06:20:25 PM PDT 24
Finished Aug 07 06:20:30 PM PDT 24
Peak memory 223720 kb
Host smart-e5af2f53-bbe4-4f32-814f-b2247ca2370e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=196606947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dire
ct.196606947
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.310230493
Short name T20
Test name
Test status
Simulation time 13422086203 ps
CPU time 53.74 seconds
Started Aug 07 06:20:33 PM PDT 24
Finished Aug 07 06:21:27 PM PDT 24
Peak memory 233596 kb
Host smart-6bbdcde4-1f2e-494e-b2a8-f271ada76629
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310230493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stres
s_all.310230493
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.2294863223
Short name T60
Test name
Test status
Simulation time 665187155 ps
CPU time 2.99 seconds
Started Aug 07 06:20:25 PM PDT 24
Finished Aug 07 06:20:28 PM PDT 24
Peak memory 217312 kb
Host smart-e43ed45d-eb21-4e08-a28e-702ac82a7daf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294863223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.2294863223
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.3961043559
Short name T1001
Test name
Test status
Simulation time 4889668189 ps
CPU time 14.24 seconds
Started Aug 07 06:20:29 PM PDT 24
Finished Aug 07 06:20:44 PM PDT 24
Peak memory 217048 kb
Host smart-ba14d5cb-db63-49a7-9810-f3615a36e63b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961043559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.3961043559
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.876700032
Short name T991
Test name
Test status
Simulation time 121236012 ps
CPU time 1.43 seconds
Started Aug 07 06:20:28 PM PDT 24
Finished Aug 07 06:20:29 PM PDT 24
Peak memory 207940 kb
Host smart-d9db2440-2de1-41fd-b4cc-55365dbbe53d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876700032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.876700032
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.1806489162
Short name T955
Test name
Test status
Simulation time 75083335 ps
CPU time 0.75 seconds
Started Aug 07 06:20:26 PM PDT 24
Finished Aug 07 06:20:27 PM PDT 24
Peak memory 206592 kb
Host smart-1c5d0371-eaf9-4f34-885b-5fb3ae373d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806489162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.1806489162
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.1155977756
Short name T901
Test name
Test status
Simulation time 9011931450 ps
CPU time 12.43 seconds
Started Aug 07 06:20:31 PM PDT 24
Finished Aug 07 06:20:43 PM PDT 24
Peak memory 233556 kb
Host smart-59e30b36-5552-4fcd-bc3b-81a60cf6dd05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155977756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.1155977756
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.731608480
Short name T408
Test name
Test status
Simulation time 27518146 ps
CPU time 0.72 seconds
Started Aug 07 06:20:32 PM PDT 24
Finished Aug 07 06:20:33 PM PDT 24
Peak memory 205868 kb
Host smart-93168721-8ba0-431e-a552-96d48cd8a6ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731608480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.731608480
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.2549519398
Short name T897
Test name
Test status
Simulation time 2156320021 ps
CPU time 6.14 seconds
Started Aug 07 06:20:33 PM PDT 24
Finished Aug 07 06:20:39 PM PDT 24
Peak memory 233492 kb
Host smart-f72f411d-3c2c-4312-bf26-05f748ef1a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549519398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.2549519398
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.299023697
Short name T320
Test name
Test status
Simulation time 20744848 ps
CPU time 0.78 seconds
Started Aug 07 06:20:36 PM PDT 24
Finished Aug 07 06:20:37 PM PDT 24
Peak memory 206408 kb
Host smart-960b34b2-ef1b-4e58-afd2-b26476d6be88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299023697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.299023697
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.3843525715
Short name T1028
Test name
Test status
Simulation time 108099138360 ps
CPU time 116.64 seconds
Started Aug 07 06:20:32 PM PDT 24
Finished Aug 07 06:22:29 PM PDT 24
Peak memory 249912 kb
Host smart-f01c5497-9b9c-45c3-b657-3c7c6be9a585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843525715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.3843525715
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.3852205378
Short name T158
Test name
Test status
Simulation time 48276829776 ps
CPU time 151.98 seconds
Started Aug 07 06:20:31 PM PDT 24
Finished Aug 07 06:23:03 PM PDT 24
Peak memory 257920 kb
Host smart-99da3b0f-dea6-465f-8e0d-9e2c0b191a93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852205378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.3852205378
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.3065354102
Short name T857
Test name
Test status
Simulation time 388699879 ps
CPU time 3.24 seconds
Started Aug 07 06:20:33 PM PDT 24
Finished Aug 07 06:20:36 PM PDT 24
Peak memory 225188 kb
Host smart-b50345ca-685a-43be-a75e-edc2669e8bd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065354102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.3065354102
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.2161094074
Short name T487
Test name
Test status
Simulation time 52239962316 ps
CPU time 22.47 seconds
Started Aug 07 06:20:29 PM PDT 24
Finished Aug 07 06:20:51 PM PDT 24
Peak memory 225324 kb
Host smart-4863196c-6833-4b25-83da-3aa340c5b7bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161094074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmd
s.2161094074
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/14.spi_device_intercept.3708955469
Short name T628
Test name
Test status
Simulation time 833555454 ps
CPU time 10.34 seconds
Started Aug 07 06:20:34 PM PDT 24
Finished Aug 07 06:20:44 PM PDT 24
Peak memory 233464 kb
Host smart-0013081a-d74f-40f6-bfd1-4ecddc1b7762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708955469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.3708955469
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.1930657734
Short name T281
Test name
Test status
Simulation time 1952528437 ps
CPU time 3.81 seconds
Started Aug 07 06:20:33 PM PDT 24
Finished Aug 07 06:20:37 PM PDT 24
Peak memory 233500 kb
Host smart-d680e0e9-9125-4058-9fc6-f7ea27c800f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930657734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.1930657734
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.4114482510
Short name T904
Test name
Test status
Simulation time 27928514 ps
CPU time 1.1 seconds
Started Aug 07 06:20:36 PM PDT 24
Finished Aug 07 06:20:37 PM PDT 24
Peak memory 218676 kb
Host smart-c0c9c6ef-249a-40fb-9a95-ffd1a65309e1
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114482510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.spi_device_mem_parity.4114482510
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.3117350729
Short name T53
Test name
Test status
Simulation time 31735261097 ps
CPU time 17.9 seconds
Started Aug 07 06:20:30 PM PDT 24
Finished Aug 07 06:20:48 PM PDT 24
Peak memory 225264 kb
Host smart-41f92868-edf5-4caf-8897-f2da186962d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117350729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.3117350729
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.3625722436
Short name T156
Test name
Test status
Simulation time 5673692947 ps
CPU time 17.49 seconds
Started Aug 07 06:20:33 PM PDT 24
Finished Aug 07 06:20:51 PM PDT 24
Peak memory 241620 kb
Host smart-9fb03de9-6779-47c7-99bc-bf57355a58b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625722436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.3625722436
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.364952903
Short name T443
Test name
Test status
Simulation time 375630195 ps
CPU time 6.02 seconds
Started Aug 07 06:20:37 PM PDT 24
Finished Aug 07 06:20:44 PM PDT 24
Peak memory 221044 kb
Host smart-e9b108f6-8a5a-4e1c-bf2b-f1cb59871a57
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=364952903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dire
ct.364952903
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.1246066297
Short name T975
Test name
Test status
Simulation time 58723704 ps
CPU time 1.12 seconds
Started Aug 07 06:20:30 PM PDT 24
Finished Aug 07 06:20:32 PM PDT 24
Peak memory 207568 kb
Host smart-9faa8887-b5cb-487b-ac03-58d63b2278f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246066297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.1246066297
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.632460124
Short name T756
Test name
Test status
Simulation time 15590793572 ps
CPU time 11.8 seconds
Started Aug 07 06:20:31 PM PDT 24
Finished Aug 07 06:20:43 PM PDT 24
Peak memory 217040 kb
Host smart-d6467ee7-3e36-4331-a9be-22ed16eb7c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632460124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.632460124
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.3868100626
Short name T313
Test name
Test status
Simulation time 185652551 ps
CPU time 2.57 seconds
Started Aug 07 06:20:33 PM PDT 24
Finished Aug 07 06:20:35 PM PDT 24
Peak memory 217036 kb
Host smart-e776f34b-46f6-49e1-90b0-fd6bf4399c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868100626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.3868100626
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.2502324992
Short name T742
Test name
Test status
Simulation time 28004992 ps
CPU time 0.72 seconds
Started Aug 07 06:20:30 PM PDT 24
Finished Aug 07 06:20:31 PM PDT 24
Peak memory 206556 kb
Host smart-31e12cea-0508-4489-864c-10d4391c7665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502324992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.2502324992
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.1550709848
Short name T942
Test name
Test status
Simulation time 307674470 ps
CPU time 3.93 seconds
Started Aug 07 06:20:31 PM PDT 24
Finished Aug 07 06:20:35 PM PDT 24
Peak memory 233464 kb
Host smart-983f1375-cf71-4e42-8171-aa8bc92f9ded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550709848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.1550709848
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.2080742985
Short name T440
Test name
Test status
Simulation time 11688246 ps
CPU time 0.7 seconds
Started Aug 07 06:20:43 PM PDT 24
Finished Aug 07 06:20:44 PM PDT 24
Peak memory 205864 kb
Host smart-f143b293-b9d5-4756-a6a6-127e30945cf7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080742985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
2080742985
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.2357804232
Short name T463
Test name
Test status
Simulation time 170416547 ps
CPU time 2.62 seconds
Started Aug 07 06:20:43 PM PDT 24
Finished Aug 07 06:20:45 PM PDT 24
Peak memory 233428 kb
Host smart-cbf74607-7932-4b23-b523-32bc150474b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357804232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.2357804232
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.2902469877
Short name T326
Test name
Test status
Simulation time 36814324 ps
CPU time 0.74 seconds
Started Aug 07 06:20:33 PM PDT 24
Finished Aug 07 06:20:33 PM PDT 24
Peak memory 207076 kb
Host smart-0e65b645-8347-4e89-891a-332b77773273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902469877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.2902469877
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.1352168035
Short name T884
Test name
Test status
Simulation time 13730735 ps
CPU time 0.8 seconds
Started Aug 07 06:20:37 PM PDT 24
Finished Aug 07 06:20:38 PM PDT 24
Peak memory 216444 kb
Host smart-72d682bd-356e-456b-b71c-9799c0f33292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352168035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.1352168035
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.3705035839
Short name T286
Test name
Test status
Simulation time 4690279698 ps
CPU time 68.2 seconds
Started Aug 07 06:20:46 PM PDT 24
Finished Aug 07 06:21:55 PM PDT 24
Peak memory 264328 kb
Host smart-bfd1da17-993c-49a7-86b4-a0718057a75a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705035839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.3705035839
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.3283271251
Short name T849
Test name
Test status
Simulation time 245849491741 ps
CPU time 413.11 seconds
Started Aug 07 06:20:37 PM PDT 24
Finished Aug 07 06:27:30 PM PDT 24
Peak memory 274456 kb
Host smart-4fda1a8c-7f69-4b1a-ba04-6f68668c3c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283271251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.3283271251
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.1962530606
Short name T927
Test name
Test status
Simulation time 307641277 ps
CPU time 4.06 seconds
Started Aug 07 06:20:41 PM PDT 24
Finished Aug 07 06:20:45 PM PDT 24
Peak memory 235416 kb
Host smart-7be696cd-58c7-4dd6-b98b-4cd8c0d07993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962530606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.1962530606
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_intercept.3257069373
Short name T470
Test name
Test status
Simulation time 145920056 ps
CPU time 3.31 seconds
Started Aug 07 06:20:34 PM PDT 24
Finished Aug 07 06:20:37 PM PDT 24
Peak memory 225208 kb
Host smart-bf6084b3-889f-4e89-bb6c-4ef5ad5821b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257069373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.3257069373
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.3557051599
Short name T8
Test name
Test status
Simulation time 17479475595 ps
CPU time 56.26 seconds
Started Aug 07 06:20:38 PM PDT 24
Finished Aug 07 06:21:34 PM PDT 24
Peak memory 233416 kb
Host smart-0b29195b-fe26-4087-b107-aa01949fdf7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557051599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.3557051599
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.132179462
Short name T538
Test name
Test status
Simulation time 34573401 ps
CPU time 1.08 seconds
Started Aug 07 06:20:34 PM PDT 24
Finished Aug 07 06:20:36 PM PDT 24
Peak memory 217200 kb
Host smart-ccdc2a9c-956a-4138-b3e6-21c565426f9f
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132179462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.spi_device_mem_parity.132179462
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.1234005637
Short name T889
Test name
Test status
Simulation time 2711223895 ps
CPU time 8.89 seconds
Started Aug 07 06:20:35 PM PDT 24
Finished Aug 07 06:20:44 PM PDT 24
Peak memory 225200 kb
Host smart-dc885746-8a6b-4cb8-be30-56ad60aafafa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234005637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.1234005637
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.192310299
Short name T770
Test name
Test status
Simulation time 706460371 ps
CPU time 6.91 seconds
Started Aug 07 06:20:31 PM PDT 24
Finished Aug 07 06:20:38 PM PDT 24
Peak memory 225252 kb
Host smart-eb7d1cd7-291c-403e-a0f6-a0e2c0ddec20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192310299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.192310299
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.1636656512
Short name T142
Test name
Test status
Simulation time 307603063 ps
CPU time 5.04 seconds
Started Aug 07 06:20:43 PM PDT 24
Finished Aug 07 06:20:48 PM PDT 24
Peak memory 222924 kb
Host smart-28ea136a-6341-46ab-911c-26fd621c9b2b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1636656512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.1636656512
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.1256429038
Short name T302
Test name
Test status
Simulation time 15631533303 ps
CPU time 20.38 seconds
Started Aug 07 06:20:33 PM PDT 24
Finished Aug 07 06:20:53 PM PDT 24
Peak memory 217080 kb
Host smart-24af6443-6d5e-4950-92f1-f3a033c2c536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256429038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.1256429038
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.1447498755
Short name T531
Test name
Test status
Simulation time 7984510136 ps
CPU time 8.78 seconds
Started Aug 07 06:20:33 PM PDT 24
Finished Aug 07 06:20:42 PM PDT 24
Peak memory 217000 kb
Host smart-030b9a7b-648d-4dbb-83b8-420c1ad665d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447498755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.1447498755
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.486979701
Short name T404
Test name
Test status
Simulation time 36263159 ps
CPU time 0.95 seconds
Started Aug 07 06:20:37 PM PDT 24
Finished Aug 07 06:20:38 PM PDT 24
Peak memory 208016 kb
Host smart-3d60f623-a847-426a-8174-b6b3a181bd2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486979701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.486979701
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.2441858280
Short name T856
Test name
Test status
Simulation time 132712025 ps
CPU time 0.86 seconds
Started Aug 07 06:20:37 PM PDT 24
Finished Aug 07 06:20:37 PM PDT 24
Peak memory 206628 kb
Host smart-2450d975-061b-4796-978d-e235c27273be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441858280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.2441858280
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.1873050240
Short name T679
Test name
Test status
Simulation time 9543550338 ps
CPU time 16.74 seconds
Started Aug 07 06:20:42 PM PDT 24
Finished Aug 07 06:20:58 PM PDT 24
Peak memory 233532 kb
Host smart-8f77abcb-aea3-4a16-b05a-0b680da91245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873050240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.1873050240
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.2097315621
Short name T429
Test name
Test status
Simulation time 18478306 ps
CPU time 0.74 seconds
Started Aug 07 06:20:42 PM PDT 24
Finished Aug 07 06:20:43 PM PDT 24
Peak memory 205328 kb
Host smart-bd928ec5-e3e8-4027-a0e9-5ab6554e5513
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097315621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
2097315621
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.4266504041
Short name T581
Test name
Test status
Simulation time 391384708 ps
CPU time 3.96 seconds
Started Aug 07 06:20:38 PM PDT 24
Finished Aug 07 06:20:42 PM PDT 24
Peak memory 233428 kb
Host smart-b9c84d24-09dd-4406-ba1b-9c7f58c89995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266504041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.4266504041
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.3427131516
Short name T587
Test name
Test status
Simulation time 17356708 ps
CPU time 0.76 seconds
Started Aug 07 06:20:35 PM PDT 24
Finished Aug 07 06:20:36 PM PDT 24
Peak memory 206384 kb
Host smart-50fb056b-2a47-4f87-975a-ba49b6623498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427131516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.3427131516
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.3561185091
Short name T960
Test name
Test status
Simulation time 6776322088 ps
CPU time 35.22 seconds
Started Aug 07 06:20:48 PM PDT 24
Finished Aug 07 06:21:24 PM PDT 24
Peak memory 252592 kb
Host smart-922e0d39-e207-4bb6-a770-d85a3c749aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561185091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.3561185091
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.1352750757
Short name T768
Test name
Test status
Simulation time 31977660397 ps
CPU time 35.95 seconds
Started Aug 07 06:20:48 PM PDT 24
Finished Aug 07 06:21:25 PM PDT 24
Peak memory 218448 kb
Host smart-8e48c2eb-219d-46d7-8ca4-3fb837eeb98d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352750757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.1352750757
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.2831218064
Short name T346
Test name
Test status
Simulation time 33513537300 ps
CPU time 87.42 seconds
Started Aug 07 06:20:43 PM PDT 24
Finished Aug 07 06:22:10 PM PDT 24
Peak memory 258412 kb
Host smart-0eb5c2fe-a085-4d12-ace0-46ba3c9b84bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831218064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.2831218064
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.4286001429
Short name T365
Test name
Test status
Simulation time 203870299 ps
CPU time 4.44 seconds
Started Aug 07 06:20:45 PM PDT 24
Finished Aug 07 06:20:49 PM PDT 24
Peak memory 241652 kb
Host smart-f54f49a9-697a-4a1e-92f6-9bb1eec0b996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286001429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.4286001429
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.830308083
Short name T496
Test name
Test status
Simulation time 26478565 ps
CPU time 0.77 seconds
Started Aug 07 06:20:36 PM PDT 24
Finished Aug 07 06:20:37 PM PDT 24
Peak memory 216468 kb
Host smart-7492e5b7-0967-4424-a14a-aba221f12ee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830308083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmds
.830308083
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/16.spi_device_intercept.944791131
Short name T268
Test name
Test status
Simulation time 1911429572 ps
CPU time 16.35 seconds
Started Aug 07 06:20:37 PM PDT 24
Finished Aug 07 06:20:54 PM PDT 24
Peak memory 225236 kb
Host smart-0c5ec867-6590-447c-a97a-2d30bf7418cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944791131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.944791131
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.3539124809
Short name T263
Test name
Test status
Simulation time 22038470083 ps
CPU time 45.05 seconds
Started Aug 07 06:20:36 PM PDT 24
Finished Aug 07 06:21:21 PM PDT 24
Peak memory 233484 kb
Host smart-d6875c0e-02b2-46a2-a77b-f5caefc1283f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539124809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.3539124809
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.448015661
Short name T582
Test name
Test status
Simulation time 32481762 ps
CPU time 1.08 seconds
Started Aug 07 06:20:36 PM PDT 24
Finished Aug 07 06:20:37 PM PDT 24
Peak memory 217180 kb
Host smart-b185c451-8efb-48b1-96dc-5103cda7110d
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448015661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.spi_device_mem_parity.448015661
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.1248993634
Short name T821
Test name
Test status
Simulation time 10314178264 ps
CPU time 9.63 seconds
Started Aug 07 06:20:37 PM PDT 24
Finished Aug 07 06:20:47 PM PDT 24
Peak memory 233540 kb
Host smart-8ee018ee-2dbb-45f7-a2df-347ccbafe8d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248993634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.1248993634
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.3529429706
Short name T688
Test name
Test status
Simulation time 2339879376 ps
CPU time 14.86 seconds
Started Aug 07 06:20:41 PM PDT 24
Finished Aug 07 06:20:56 PM PDT 24
Peak memory 233376 kb
Host smart-45c9dcd1-b484-4fed-968b-4b415bf35dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529429706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.3529429706
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.3844855836
Short name T454
Test name
Test status
Simulation time 450164515 ps
CPU time 5.3 seconds
Started Aug 07 06:20:44 PM PDT 24
Finished Aug 07 06:20:50 PM PDT 24
Peak memory 220592 kb
Host smart-9849de5e-269f-4e74-a3ba-4c66a1e8471d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3844855836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.3844855836
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.3959433245
Short name T212
Test name
Test status
Simulation time 43544283017 ps
CPU time 394.36 seconds
Started Aug 07 06:20:46 PM PDT 24
Finished Aug 07 06:27:21 PM PDT 24
Peak memory 249872 kb
Host smart-d9f1f4ba-d23d-423b-a47c-860c9672ae2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959433245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.3959433245
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.4250772620
Short name T709
Test name
Test status
Simulation time 1764704524 ps
CPU time 15.62 seconds
Started Aug 07 06:20:43 PM PDT 24
Finished Aug 07 06:20:58 PM PDT 24
Peak memory 217208 kb
Host smart-5706be48-0183-42fd-96e3-b99dcb2e3a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250772620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.4250772620
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.3509148000
Short name T373
Test name
Test status
Simulation time 2743594403 ps
CPU time 6.66 seconds
Started Aug 07 06:20:35 PM PDT 24
Finished Aug 07 06:20:42 PM PDT 24
Peak memory 217060 kb
Host smart-def59a43-d769-449c-b985-230cf76e494a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509148000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.3509148000
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.706835281
Short name T358
Test name
Test status
Simulation time 48656794 ps
CPU time 0.85 seconds
Started Aug 07 06:20:48 PM PDT 24
Finished Aug 07 06:20:49 PM PDT 24
Peak memory 207532 kb
Host smart-af45cd1c-aa7e-4271-abca-a8627893f5c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706835281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.706835281
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.3099895518
Short name T401
Test name
Test status
Simulation time 12520620 ps
CPU time 0.72 seconds
Started Aug 07 06:20:36 PM PDT 24
Finished Aug 07 06:20:36 PM PDT 24
Peak memory 206112 kb
Host smart-3a062d7e-41e7-4a1a-9849-4e524ae67c6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099895518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.3099895518
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.1682112238
Short name T823
Test name
Test status
Simulation time 20644242143 ps
CPU time 20.16 seconds
Started Aug 07 06:20:40 PM PDT 24
Finished Aug 07 06:21:01 PM PDT 24
Peak memory 242412 kb
Host smart-187b4a58-eaf5-4e31-9999-7f9dee1b7857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682112238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.1682112238
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.2878931007
Short name T497
Test name
Test status
Simulation time 38830627 ps
CPU time 0.81 seconds
Started Aug 07 06:20:41 PM PDT 24
Finished Aug 07 06:20:42 PM PDT 24
Peak memory 205308 kb
Host smart-01b87aec-951b-4187-80a7-93cbf3c7b88a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878931007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
2878931007
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.1691285091
Short name T673
Test name
Test status
Simulation time 307196198 ps
CPU time 2.97 seconds
Started Aug 07 06:20:42 PM PDT 24
Finished Aug 07 06:20:45 PM PDT 24
Peak memory 225200 kb
Host smart-e1a59317-5664-4d2c-a755-cd4d8e81d788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691285091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.1691285091
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.1707345298
Short name T340
Test name
Test status
Simulation time 13268480 ps
CPU time 0.78 seconds
Started Aug 07 06:20:49 PM PDT 24
Finished Aug 07 06:20:50 PM PDT 24
Peak memory 207076 kb
Host smart-b1258369-12e1-4b70-9283-cccfa3437ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707345298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.1707345298
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.1004596511
Short name T605
Test name
Test status
Simulation time 8199816191 ps
CPU time 58.95 seconds
Started Aug 07 06:20:45 PM PDT 24
Finished Aug 07 06:21:44 PM PDT 24
Peak memory 249964 kb
Host smart-58e43839-269f-41ab-b412-e13a95d7987e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004596511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.1004596511
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.1017165114
Short name T996
Test name
Test status
Simulation time 45111614334 ps
CPU time 176.01 seconds
Started Aug 07 06:20:44 PM PDT 24
Finished Aug 07 06:23:40 PM PDT 24
Peak memory 251972 kb
Host smart-3d5de687-c241-4a23-8be0-5dfd28660bb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017165114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.1017165114
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.4093183675
Short name T593
Test name
Test status
Simulation time 48949008 ps
CPU time 3.13 seconds
Started Aug 07 06:20:50 PM PDT 24
Finished Aug 07 06:20:53 PM PDT 24
Peak memory 225192 kb
Host smart-34abd6a5-5b1b-426c-b9d3-7e72ce286371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093183675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.4093183675
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_intercept.149061811
Short name T672
Test name
Test status
Simulation time 283482779 ps
CPU time 5.34 seconds
Started Aug 07 06:20:45 PM PDT 24
Finished Aug 07 06:20:50 PM PDT 24
Peak memory 233460 kb
Host smart-2eb90847-43a7-45f0-91a6-f2eca6ae0fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149061811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.149061811
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.2194623449
Short name T259
Test name
Test status
Simulation time 19806214071 ps
CPU time 38.81 seconds
Started Aug 07 06:20:48 PM PDT 24
Finished Aug 07 06:21:27 PM PDT 24
Peak memory 233436 kb
Host smart-a759b583-db7e-4b16-a6ea-88f9dc4d3f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194623449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.2194623449
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.1552090343
Short name T766
Test name
Test status
Simulation time 106150350 ps
CPU time 1 seconds
Started Aug 07 06:20:41 PM PDT 24
Finished Aug 07 06:20:42 PM PDT 24
Peak memory 218488 kb
Host smart-6cae3f9f-f21d-4b73-8cdf-27ea0472ec55
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552090343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.spi_device_mem_parity.1552090343
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.2515337837
Short name T166
Test name
Test status
Simulation time 2910091927 ps
CPU time 7.1 seconds
Started Aug 07 06:20:47 PM PDT 24
Finished Aug 07 06:20:54 PM PDT 24
Peak memory 233460 kb
Host smart-3feee342-3e95-484c-9701-e67053b18ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515337837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.2515337837
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.1722473708
Short name T623
Test name
Test status
Simulation time 22739911489 ps
CPU time 20.18 seconds
Started Aug 07 06:20:48 PM PDT 24
Finished Aug 07 06:21:08 PM PDT 24
Peak memory 233528 kb
Host smart-1ab89a72-a07c-4df8-bfae-553cc32bce05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722473708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.1722473708
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.2051966791
Short name T66
Test name
Test status
Simulation time 671383597 ps
CPU time 3.63 seconds
Started Aug 07 06:20:43 PM PDT 24
Finished Aug 07 06:20:47 PM PDT 24
Peak memory 222164 kb
Host smart-b7e3e950-0a72-4658-a9d8-6e2fd2c85555
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2051966791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.2051966791
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.3555993866
Short name T17
Test name
Test status
Simulation time 65397925 ps
CPU time 1.07 seconds
Started Aug 07 06:20:48 PM PDT 24
Finished Aug 07 06:20:49 PM PDT 24
Peak memory 207576 kb
Host smart-6edd94a3-2397-49eb-872f-51b97dfd3e1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555993866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.3555993866
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.1148351341
Short name T318
Test name
Test status
Simulation time 3667244245 ps
CPU time 19.26 seconds
Started Aug 07 06:20:45 PM PDT 24
Finished Aug 07 06:21:05 PM PDT 24
Peak memory 217228 kb
Host smart-2fbbec2f-7eee-47e3-b101-073ece64de04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148351341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.1148351341
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.1863974608
Short name T909
Test name
Test status
Simulation time 12445271827 ps
CPU time 17.16 seconds
Started Aug 07 06:20:50 PM PDT 24
Finished Aug 07 06:21:07 PM PDT 24
Peak memory 217104 kb
Host smart-dc267d9b-6e54-4b1f-b76b-95bac39c04e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863974608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.1863974608
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.2246650991
Short name T1013
Test name
Test status
Simulation time 147208429 ps
CPU time 1.53 seconds
Started Aug 07 06:20:42 PM PDT 24
Finished Aug 07 06:20:44 PM PDT 24
Peak memory 216904 kb
Host smart-3b7badf9-b392-4f83-8b72-92f6bf9b8b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246650991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.2246650991
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.4259962220
Short name T826
Test name
Test status
Simulation time 63734358 ps
CPU time 0.93 seconds
Started Aug 07 06:20:45 PM PDT 24
Finished Aug 07 06:20:46 PM PDT 24
Peak memory 206588 kb
Host smart-3ea24c68-55c2-4ad1-8c9c-35dbf68d757b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259962220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.4259962220
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.2390819820
Short name T750
Test name
Test status
Simulation time 21204253792 ps
CPU time 22.53 seconds
Started Aug 07 06:20:42 PM PDT 24
Finished Aug 07 06:21:04 PM PDT 24
Peak memory 235152 kb
Host smart-e0653e90-3a4f-482b-a4e5-ad58b23f9250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390819820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.2390819820
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.2147961537
Short name T707
Test name
Test status
Simulation time 42562772 ps
CPU time 0.73 seconds
Started Aug 07 06:20:48 PM PDT 24
Finished Aug 07 06:20:49 PM PDT 24
Peak memory 205228 kb
Host smart-b5cb8aab-f1e7-4a61-a4e7-0d1399653eab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147961537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
2147961537
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.1207125706
Short name T715
Test name
Test status
Simulation time 898889313 ps
CPU time 4.01 seconds
Started Aug 07 06:20:42 PM PDT 24
Finished Aug 07 06:20:46 PM PDT 24
Peak memory 225196 kb
Host smart-42c151f4-ad2a-417d-888d-be61a536c2a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207125706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.1207125706
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.2202410370
Short name T795
Test name
Test status
Simulation time 18305789 ps
CPU time 0.85 seconds
Started Aug 07 06:20:52 PM PDT 24
Finished Aug 07 06:20:53 PM PDT 24
Peak memory 207052 kb
Host smart-b6429228-4f9b-43a3-a758-90fa4ecd788a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202410370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.2202410370
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.3980565379
Short name T274
Test name
Test status
Simulation time 1856879542 ps
CPU time 35.09 seconds
Started Aug 07 06:20:47 PM PDT 24
Finished Aug 07 06:21:22 PM PDT 24
Peak memory 250892 kb
Host smart-0e6369d3-3069-430f-ace1-f9c84b58763d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980565379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.3980565379
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.980431423
Short name T556
Test name
Test status
Simulation time 89399078598 ps
CPU time 187.27 seconds
Started Aug 07 06:20:51 PM PDT 24
Finished Aug 07 06:23:59 PM PDT 24
Peak memory 241660 kb
Host smart-32fe8246-f942-4406-a44e-df62baa7d642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980431423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.980431423
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.96118250
Short name T183
Test name
Test status
Simulation time 12359710410 ps
CPU time 135.69 seconds
Started Aug 07 06:20:47 PM PDT 24
Finished Aug 07 06:23:03 PM PDT 24
Peak memory 250000 kb
Host smart-72688136-f855-46c6-ab16-b0c12d5d1f18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96118250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idle.96118250
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.3192667334
Short name T591
Test name
Test status
Simulation time 2178774757 ps
CPU time 12.85 seconds
Started Aug 07 06:20:49 PM PDT 24
Finished Aug 07 06:21:02 PM PDT 24
Peak memory 225308 kb
Host smart-5a44d690-28c5-4bb0-ae95-fb335788651e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192667334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.3192667334
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.3276613231
Short name T260
Test name
Test status
Simulation time 12198924382 ps
CPU time 102.94 seconds
Started Aug 07 06:20:48 PM PDT 24
Finished Aug 07 06:22:31 PM PDT 24
Peak memory 249896 kb
Host smart-a3ce8fdb-f11a-4e01-83c6-78097d17916b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276613231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmd
s.3276613231
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/18.spi_device_intercept.652983226
Short name T273
Test name
Test status
Simulation time 2375951998 ps
CPU time 20.44 seconds
Started Aug 07 06:20:43 PM PDT 24
Finished Aug 07 06:21:03 PM PDT 24
Peak memory 233520 kb
Host smart-c4be1636-7518-4f7f-9f08-abbbaace1970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652983226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.652983226
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.1089119606
Short name T757
Test name
Test status
Simulation time 2257651247 ps
CPU time 26.73 seconds
Started Aug 07 06:20:41 PM PDT 24
Finished Aug 07 06:21:08 PM PDT 24
Peak memory 240444 kb
Host smart-1d2892a1-69a3-4851-9fb9-98a20b582b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089119606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.1089119606
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.3026951202
Short name T737
Test name
Test status
Simulation time 33292000 ps
CPU time 1.07 seconds
Started Aug 07 06:20:52 PM PDT 24
Finished Aug 07 06:20:53 PM PDT 24
Peak memory 217116 kb
Host smart-c7186329-6de9-4319-831f-54d15b5bffa5
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026951202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.spi_device_mem_parity.3026951202
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.494353722
Short name T292
Test name
Test status
Simulation time 2658057522 ps
CPU time 3.83 seconds
Started Aug 07 06:20:47 PM PDT 24
Finished Aug 07 06:20:51 PM PDT 24
Peak memory 225364 kb
Host smart-fece741e-6222-4601-a3f1-3a08f81b4abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494353722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swap
.494353722
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.402912553
Short name T983
Test name
Test status
Simulation time 83689376 ps
CPU time 2.53 seconds
Started Aug 07 06:20:43 PM PDT 24
Finished Aug 07 06:20:46 PM PDT 24
Peak memory 225088 kb
Host smart-c668e3e1-e07a-4310-a0ab-2cf6c77046cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402912553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.402912553
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.2989082479
Short name T987
Test name
Test status
Simulation time 495344490 ps
CPU time 3.74 seconds
Started Aug 07 06:20:47 PM PDT 24
Finished Aug 07 06:20:51 PM PDT 24
Peak memory 223764 kb
Host smart-3e3eca7f-9662-43cf-b0fa-72ea62d36c71
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2989082479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.2989082479
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.3089427794
Short name T148
Test name
Test status
Simulation time 188553703 ps
CPU time 0.98 seconds
Started Aug 07 06:20:49 PM PDT 24
Finished Aug 07 06:20:50 PM PDT 24
Peak memory 207360 kb
Host smart-f44fd50d-57ab-4bce-9027-7579307d9a8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089427794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.3089427794
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.3715956190
Short name T128
Test name
Test status
Simulation time 13000781424 ps
CPU time 20.94 seconds
Started Aug 07 06:20:49 PM PDT 24
Finished Aug 07 06:21:10 PM PDT 24
Peak memory 217052 kb
Host smart-8f78e4af-5a2d-43bf-8127-f48f32439b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715956190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.3715956190
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.3293624283
Short name T613
Test name
Test status
Simulation time 2235757704 ps
CPU time 5.44 seconds
Started Aug 07 06:20:45 PM PDT 24
Finished Aug 07 06:20:50 PM PDT 24
Peak memory 217032 kb
Host smart-c1f7de18-2185-407d-b8e8-3c7af53d1b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293624283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.3293624283
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.3856732273
Short name T382
Test name
Test status
Simulation time 873261921 ps
CPU time 2.16 seconds
Started Aug 07 06:20:46 PM PDT 24
Finished Aug 07 06:20:48 PM PDT 24
Peak memory 216964 kb
Host smart-ae3534fd-6817-49e0-bf7c-bdd0bd5de540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856732273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.3856732273
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.2847424454
Short name T452
Test name
Test status
Simulation time 75996136 ps
CPU time 0.96 seconds
Started Aug 07 06:20:52 PM PDT 24
Finished Aug 07 06:20:53 PM PDT 24
Peak memory 206624 kb
Host smart-653b539d-13f2-43e2-8ddc-b935384c9132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847424454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.2847424454
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.3502579044
Short name T279
Test name
Test status
Simulation time 3969446868 ps
CPU time 4.76 seconds
Started Aug 07 06:20:44 PM PDT 24
Finished Aug 07 06:20:49 PM PDT 24
Peak memory 225280 kb
Host smart-de3e749a-8e59-4fe5-ab0a-0bf035296561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502579044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.3502579044
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.3188919143
Short name T321
Test name
Test status
Simulation time 13493858 ps
CPU time 0.74 seconds
Started Aug 07 06:20:54 PM PDT 24
Finished Aug 07 06:20:55 PM PDT 24
Peak memory 205284 kb
Host smart-db05834a-338d-40f8-a70b-375d2a2043e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188919143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
3188919143
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.2826809956
Short name T930
Test name
Test status
Simulation time 1237087384 ps
CPU time 9.68 seconds
Started Aug 07 06:20:47 PM PDT 24
Finished Aug 07 06:20:57 PM PDT 24
Peak memory 233308 kb
Host smart-1178bf75-bf03-4453-af3a-233b7279105c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826809956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.2826809956
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.160967055
Short name T348
Test name
Test status
Simulation time 45437631 ps
CPU time 0.79 seconds
Started Aug 07 06:20:49 PM PDT 24
Finished Aug 07 06:20:50 PM PDT 24
Peak memory 207108 kb
Host smart-16e0bd75-90ee-442e-b869-f4ea1ed8d4c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160967055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.160967055
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.3606269991
Short name T874
Test name
Test status
Simulation time 84633327870 ps
CPU time 229.99 seconds
Started Aug 07 06:20:57 PM PDT 24
Finished Aug 07 06:24:47 PM PDT 24
Peak memory 252832 kb
Host smart-74cf2787-14f8-46c4-8d97-b26452b3cf27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606269991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.3606269991
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.256817894
Short name T133
Test name
Test status
Simulation time 16559955490 ps
CPU time 145.87 seconds
Started Aug 07 06:20:57 PM PDT 24
Finished Aug 07 06:23:23 PM PDT 24
Peak memory 274132 kb
Host smart-f9a4b3e1-0652-48c0-9545-5257c9f418e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256817894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idle
.256817894
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.487219961
Short name T484
Test name
Test status
Simulation time 107788541 ps
CPU time 4.53 seconds
Started Aug 07 06:20:49 PM PDT 24
Finished Aug 07 06:20:53 PM PDT 24
Peak memory 225288 kb
Host smart-3b92be55-e374-40f9-8f4e-7b22f7b4094b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487219961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.487219961
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.2579606611
Short name T61
Test name
Test status
Simulation time 2649842646 ps
CPU time 28.18 seconds
Started Aug 07 06:20:55 PM PDT 24
Finished Aug 07 06:21:24 PM PDT 24
Peak memory 236040 kb
Host smart-517f097c-8802-4d97-aaf0-275aee00dd0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579606611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmd
s.2579606611
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/19.spi_device_intercept.4119389355
Short name T834
Test name
Test status
Simulation time 384019286 ps
CPU time 2.75 seconds
Started Aug 07 06:20:49 PM PDT 24
Finished Aug 07 06:20:52 PM PDT 24
Peak memory 225064 kb
Host smart-3bf46c7c-1264-4579-8f20-180c7f387f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119389355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.4119389355
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.2178868829
Short name T743
Test name
Test status
Simulation time 4653490361 ps
CPU time 6.96 seconds
Started Aug 07 06:20:47 PM PDT 24
Finished Aug 07 06:20:55 PM PDT 24
Peak memory 225340 kb
Host smart-c25654c7-fba1-4d4c-a64a-fd3314100d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178868829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.2178868829
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.761445929
Short name T477
Test name
Test status
Simulation time 26514560 ps
CPU time 1.07 seconds
Started Aug 07 06:20:54 PM PDT 24
Finished Aug 07 06:20:55 PM PDT 24
Peak memory 217220 kb
Host smart-4287aac9-df8f-4834-88da-db4d45ffe922
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761445929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.spi_device_mem_parity.761445929
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.2211512247
Short name T652
Test name
Test status
Simulation time 350915832 ps
CPU time 3.27 seconds
Started Aug 07 06:20:48 PM PDT 24
Finished Aug 07 06:20:51 PM PDT 24
Peak memory 225184 kb
Host smart-28f15f94-99f5-4d51-9580-0e6fa36605d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211512247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.2211512247
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.2413865257
Short name T984
Test name
Test status
Simulation time 7015028514 ps
CPU time 7.19 seconds
Started Aug 07 06:20:51 PM PDT 24
Finished Aug 07 06:20:59 PM PDT 24
Peak memory 233600 kb
Host smart-0f56f5d5-4063-4c54-94b7-c3af8e930d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413865257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.2413865257
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.3333292127
Short name T667
Test name
Test status
Simulation time 471003149 ps
CPU time 5.46 seconds
Started Aug 07 06:20:50 PM PDT 24
Finished Aug 07 06:20:55 PM PDT 24
Peak memory 223188 kb
Host smart-075a6953-df1b-4308-b705-bb2e08a61ad0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3333292127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.3333292127
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.1487562591
Short name T577
Test name
Test status
Simulation time 1035535967 ps
CPU time 7.66 seconds
Started Aug 07 06:20:49 PM PDT 24
Finished Aug 07 06:20:57 PM PDT 24
Peak memory 216984 kb
Host smart-15b54004-14ed-423c-b090-f8454ab2d669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487562591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.1487562591
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.2579192411
Short name T355
Test name
Test status
Simulation time 856853980 ps
CPU time 5.92 seconds
Started Aug 07 06:20:51 PM PDT 24
Finished Aug 07 06:20:57 PM PDT 24
Peak memory 216956 kb
Host smart-dcbe8f33-2aa7-420c-8128-605814974b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579192411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.2579192411
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.3572484331
Short name T1018
Test name
Test status
Simulation time 10905493 ps
CPU time 0.69 seconds
Started Aug 07 06:20:53 PM PDT 24
Finished Aug 07 06:20:53 PM PDT 24
Peak memory 206096 kb
Host smart-e57acff5-d7df-45dc-b53a-cfebf675dbee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572484331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.3572484331
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.3328043088
Short name T385
Test name
Test status
Simulation time 62835239 ps
CPU time 0.79 seconds
Started Aug 07 06:20:48 PM PDT 24
Finished Aug 07 06:20:49 PM PDT 24
Peak memory 206568 kb
Host smart-aeba19e8-2a05-48fc-baee-6d7e0ce15e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328043088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.3328043088
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.1923954885
Short name T1026
Test name
Test status
Simulation time 1329678032 ps
CPU time 6.03 seconds
Started Aug 07 06:20:50 PM PDT 24
Finished Aug 07 06:20:56 PM PDT 24
Peak memory 233440 kb
Host smart-775555f3-86cf-4f59-bc28-b1993aeefebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923954885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.1923954885
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.3619553957
Short name T435
Test name
Test status
Simulation time 20350035 ps
CPU time 0.72 seconds
Started Aug 07 06:19:56 PM PDT 24
Finished Aug 07 06:19:57 PM PDT 24
Peak memory 205752 kb
Host smart-fc741079-f278-45a6-8a76-c20d7977a3fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619553957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.3
619553957
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.180865422
Short name T468
Test name
Test status
Simulation time 304322837 ps
CPU time 2.27 seconds
Started Aug 07 06:19:55 PM PDT 24
Finished Aug 07 06:19:57 PM PDT 24
Peak memory 225248 kb
Host smart-f7ab50a4-24e7-457f-96fb-745785262757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180865422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.180865422
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.2703764652
Short name T51
Test name
Test status
Simulation time 70082795 ps
CPU time 0.83 seconds
Started Aug 07 06:19:48 PM PDT 24
Finished Aug 07 06:19:49 PM PDT 24
Peak memory 207084 kb
Host smart-2bd787f0-ba53-4c9e-b3cd-b16546adf4b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703764652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.2703764652
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.2072272218
Short name T425
Test name
Test status
Simulation time 2797163268 ps
CPU time 44.1 seconds
Started Aug 07 06:20:05 PM PDT 24
Finished Aug 07 06:20:49 PM PDT 24
Peak memory 249996 kb
Host smart-3f35f58f-0297-41b0-bcd8-0b5776882549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072272218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.2072272218
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.2227423790
Short name T123
Test name
Test status
Simulation time 576184183805 ps
CPU time 674.84 seconds
Started Aug 07 06:19:54 PM PDT 24
Finished Aug 07 06:31:09 PM PDT 24
Peak memory 274248 kb
Host smart-36396004-790f-4462-a2a8-442d7000a80e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227423790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.2227423790
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.163506685
Short name T786
Test name
Test status
Simulation time 144747632 ps
CPU time 8.2 seconds
Started Aug 07 06:19:56 PM PDT 24
Finished Aug 07 06:20:05 PM PDT 24
Peak memory 241656 kb
Host smart-fa4a13aa-238c-42a1-9d13-c5f5564060e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163506685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.163506685
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.986236672
Short name T207
Test name
Test status
Simulation time 38343875456 ps
CPU time 136.36 seconds
Started Aug 07 06:19:55 PM PDT 24
Finished Aug 07 06:22:12 PM PDT 24
Peak memory 257232 kb
Host smart-29860ac7-df19-4bd6-a6ae-38ff60f60e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986236672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds.
986236672
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_intercept.349997990
Short name T736
Test name
Test status
Simulation time 74626573 ps
CPU time 3.3 seconds
Started Aug 07 06:19:58 PM PDT 24
Finished Aug 07 06:20:01 PM PDT 24
Peak memory 233440 kb
Host smart-fb615dc3-1540-4cda-867c-219ea0a85dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349997990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.349997990
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.1914591032
Short name T870
Test name
Test status
Simulation time 52956228464 ps
CPU time 44.93 seconds
Started Aug 07 06:19:55 PM PDT 24
Finished Aug 07 06:20:40 PM PDT 24
Peak memory 249552 kb
Host smart-e9bfbdab-8de0-46b3-8942-78b3b1a0f71b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914591032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.1914591032
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.3697488320
Short name T589
Test name
Test status
Simulation time 161468545 ps
CPU time 1.07 seconds
Started Aug 07 06:19:58 PM PDT 24
Finished Aug 07 06:19:59 PM PDT 24
Peak memory 218416 kb
Host smart-37957b1d-89c4-41da-aef8-ba9eb5e905a3
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697488320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.spi_device_mem_parity.3697488320
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.529228999
Short name T604
Test name
Test status
Simulation time 265192845 ps
CPU time 2.33 seconds
Started Aug 07 06:19:54 PM PDT 24
Finished Aug 07 06:19:57 PM PDT 24
Peak memory 223580 kb
Host smart-caf36911-84f4-45d7-84d8-c4ae88469f42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529228999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap.
529228999
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.4267437624
Short name T261
Test name
Test status
Simulation time 75526088 ps
CPU time 3.19 seconds
Started Aug 07 06:19:55 PM PDT 24
Finished Aug 07 06:19:58 PM PDT 24
Peak memory 225140 kb
Host smart-874327cf-5654-42e6-a07c-2c4d0c272152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267437624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.4267437624
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.111422135
Short name T391
Test name
Test status
Simulation time 1496323437 ps
CPU time 5.68 seconds
Started Aug 07 06:19:56 PM PDT 24
Finished Aug 07 06:20:02 PM PDT 24
Peak memory 223064 kb
Host smart-ca597c38-c30c-4468-880e-bc6a57ff4961
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=111422135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_direc
t.111422135
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.3365881206
Short name T59
Test name
Test status
Simulation time 119690549 ps
CPU time 0.97 seconds
Started Aug 07 06:19:55 PM PDT 24
Finished Aug 07 06:19:56 PM PDT 24
Peak memory 234508 kb
Host smart-8634bcac-e169-44f8-b3a2-564b5fd333e9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365881206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.3365881206
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.2750186025
Short name T150
Test name
Test status
Simulation time 45089199469 ps
CPU time 130.6 seconds
Started Aug 07 06:19:55 PM PDT 24
Finished Aug 07 06:22:06 PM PDT 24
Peak memory 254888 kb
Host smart-c172ccb6-a6e3-4380-aaa4-46a90ac1c66b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750186025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.2750186025
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.3121420676
Short name T306
Test name
Test status
Simulation time 408582625 ps
CPU time 1.77 seconds
Started Aug 07 06:20:01 PM PDT 24
Finished Aug 07 06:20:03 PM PDT 24
Peak memory 217280 kb
Host smart-6a4eff8c-3372-4f02-8fd9-03a9f85b48ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121420676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.3121420676
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.413827413
Short name T908
Test name
Test status
Simulation time 4728176054 ps
CPU time 8.15 seconds
Started Aug 07 06:19:58 PM PDT 24
Finished Aug 07 06:20:07 PM PDT 24
Peak memory 217088 kb
Host smart-7097a474-8d3f-4bc3-a95b-dacfc7a33477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413827413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.413827413
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.3527164587
Short name T585
Test name
Test status
Simulation time 333301304 ps
CPU time 1.86 seconds
Started Aug 07 06:20:01 PM PDT 24
Finished Aug 07 06:20:03 PM PDT 24
Peak memory 217024 kb
Host smart-2b2c9d48-ed35-4bfa-b12e-abd8a5a62333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527164587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.3527164587
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.1392492813
Short name T431
Test name
Test status
Simulation time 422678005 ps
CPU time 1.05 seconds
Started Aug 07 06:20:05 PM PDT 24
Finished Aug 07 06:20:06 PM PDT 24
Peak memory 207624 kb
Host smart-0900c389-80cb-4e4e-af34-a93af3feb95c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392492813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.1392492813
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.645258219
Short name T903
Test name
Test status
Simulation time 199009922 ps
CPU time 2.52 seconds
Started Aug 07 06:20:01 PM PDT 24
Finished Aug 07 06:20:04 PM PDT 24
Peak memory 233060 kb
Host smart-ce261c65-4cb8-4652-8d2b-8c3f50789d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645258219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.645258219
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.4078839383
Short name T473
Test name
Test status
Simulation time 102914282 ps
CPU time 0.7 seconds
Started Aug 07 06:20:58 PM PDT 24
Finished Aug 07 06:20:59 PM PDT 24
Peak memory 205860 kb
Host smart-35527e4f-554a-4d25-ad7b-1d2aad7a0b2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078839383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
4078839383
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.4117307450
Short name T434
Test name
Test status
Simulation time 1790763633 ps
CPU time 7.09 seconds
Started Aug 07 06:20:58 PM PDT 24
Finished Aug 07 06:21:06 PM PDT 24
Peak memory 225276 kb
Host smart-274deaad-8553-496a-9fb6-56e848e2e5ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117307450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.4117307450
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.1259577489
Short name T880
Test name
Test status
Simulation time 18619372 ps
CPU time 0.84 seconds
Started Aug 07 06:21:01 PM PDT 24
Finished Aug 07 06:21:02 PM PDT 24
Peak memory 207088 kb
Host smart-3c801e05-f9db-46d2-b7bb-5695c7f804cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259577489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.1259577489
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.3240829168
Short name T206
Test name
Test status
Simulation time 371282227347 ps
CPU time 468.75 seconds
Started Aug 07 06:20:56 PM PDT 24
Finished Aug 07 06:28:45 PM PDT 24
Peak memory 274472 kb
Host smart-17465690-e516-476b-981c-47c74fe210fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240829168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.3240829168
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.1833052682
Short name T649
Test name
Test status
Simulation time 5754395136 ps
CPU time 9.28 seconds
Started Aug 07 06:20:54 PM PDT 24
Finished Aug 07 06:21:03 PM PDT 24
Peak memory 225304 kb
Host smart-54b8a300-cb19-46ba-96b8-ccd344e9a4cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833052682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.1833052682
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.795033440
Short name T599
Test name
Test status
Simulation time 2161428600 ps
CPU time 31.61 seconds
Started Aug 07 06:20:55 PM PDT 24
Finished Aug 07 06:21:27 PM PDT 24
Peak memory 241304 kb
Host smart-eeebd67b-b5ad-4270-b147-0fa8f4ac3293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795033440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idle
.795033440
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.45030339
Short name T63
Test name
Test status
Simulation time 454060281 ps
CPU time 5.37 seconds
Started Aug 07 06:20:55 PM PDT 24
Finished Aug 07 06:21:01 PM PDT 24
Peak memory 241684 kb
Host smart-25162e04-04ba-4878-ba77-7edaf500302c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45030339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.45030339
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.3258421281
Short name T519
Test name
Test status
Simulation time 73272502168 ps
CPU time 128.64 seconds
Started Aug 07 06:20:55 PM PDT 24
Finished Aug 07 06:23:04 PM PDT 24
Peak memory 249924 kb
Host smart-05340db9-7a5a-4ffd-bfb6-5bc9e0a73ce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258421281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmd
s.3258421281
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/20.spi_device_intercept.954899424
Short name T131
Test name
Test status
Simulation time 31404532 ps
CPU time 2.36 seconds
Started Aug 07 06:20:55 PM PDT 24
Finished Aug 07 06:20:57 PM PDT 24
Peak memory 233112 kb
Host smart-3d7bfce0-1ee2-4f8a-8652-2270daf9e71d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954899424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.954899424
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.2348405304
Short name T812
Test name
Test status
Simulation time 1180626871 ps
CPU time 7.31 seconds
Started Aug 07 06:20:54 PM PDT 24
Finished Aug 07 06:21:02 PM PDT 24
Peak memory 225232 kb
Host smart-f484a794-606b-4fd2-95e9-535dfb2ac4c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348405304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.2348405304
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.1502151510
Short name T224
Test name
Test status
Simulation time 13056523042 ps
CPU time 24.8 seconds
Started Aug 07 06:20:55 PM PDT 24
Finished Aug 07 06:21:20 PM PDT 24
Peak memory 242260 kb
Host smart-a0457803-8ff2-413c-8a7a-447cb889eb12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502151510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.1502151510
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.2127490707
Short name T647
Test name
Test status
Simulation time 1122823937 ps
CPU time 5.87 seconds
Started Aug 07 06:20:55 PM PDT 24
Finished Aug 07 06:21:01 PM PDT 24
Peak memory 233452 kb
Host smart-78f50174-024e-44a4-b50b-62397511687a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127490707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.2127490707
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.1135756510
Short name T485
Test name
Test status
Simulation time 3992095883 ps
CPU time 12.2 seconds
Started Aug 07 06:20:53 PM PDT 24
Finished Aug 07 06:21:05 PM PDT 24
Peak memory 223460 kb
Host smart-73b9e76a-0ef2-42ef-838c-0e9baed42c96
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1135756510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.1135756510
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.987432801
Short name T906
Test name
Test status
Simulation time 1609502688 ps
CPU time 17.23 seconds
Started Aug 07 06:20:56 PM PDT 24
Finished Aug 07 06:21:14 PM PDT 24
Peak memory 217056 kb
Host smart-db18b3e2-edab-427a-8d18-f8c2b7d8ea2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987432801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.987432801
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.2775377355
Short name T693
Test name
Test status
Simulation time 595209338 ps
CPU time 4.52 seconds
Started Aug 07 06:20:53 PM PDT 24
Finished Aug 07 06:20:57 PM PDT 24
Peak memory 216936 kb
Host smart-bfa822e0-03b3-48c0-a71f-932083042e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775377355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.2775377355
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.4170320158
Short name T722
Test name
Test status
Simulation time 1080564113 ps
CPU time 1.93 seconds
Started Aug 07 06:20:55 PM PDT 24
Finished Aug 07 06:20:57 PM PDT 24
Peak memory 216960 kb
Host smart-461f9608-615b-44b9-8625-4989bde57981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170320158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.4170320158
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.2925036494
Short name T68
Test name
Test status
Simulation time 62544058 ps
CPU time 0.89 seconds
Started Aug 07 06:20:56 PM PDT 24
Finished Aug 07 06:20:57 PM PDT 24
Peak memory 206576 kb
Host smart-3ae03ef1-5620-4fc5-93be-c1312422f8b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925036494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.2925036494
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.985489104
Short name T493
Test name
Test status
Simulation time 384391294 ps
CPU time 6.89 seconds
Started Aug 07 06:20:55 PM PDT 24
Finished Aug 07 06:21:03 PM PDT 24
Peak memory 233480 kb
Host smart-42563480-2f2f-48a9-85a0-2369dee89fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985489104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.985489104
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.3998711769
Short name T725
Test name
Test status
Simulation time 31808828 ps
CPU time 0.7 seconds
Started Aug 07 06:20:59 PM PDT 24
Finished Aug 07 06:21:00 PM PDT 24
Peak memory 206228 kb
Host smart-370f29d8-d7d7-4e53-a74c-b040082e8d4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998711769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
3998711769
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.1104954120
Short name T176
Test name
Test status
Simulation time 2403074106 ps
CPU time 9.56 seconds
Started Aug 07 06:21:01 PM PDT 24
Finished Aug 07 06:21:11 PM PDT 24
Peak memory 233448 kb
Host smart-d0d2b26b-0135-4f46-8dfa-92618cb859a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104954120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.1104954120
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.778661418
Short name T390
Test name
Test status
Simulation time 74375234 ps
CPU time 0.75 seconds
Started Aug 07 06:20:54 PM PDT 24
Finished Aug 07 06:20:55 PM PDT 24
Peak memory 207056 kb
Host smart-c6a11ecc-ed66-4c58-94a1-433327bbe697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778661418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.778661418
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.2482172084
Short name T510
Test name
Test status
Simulation time 177322267432 ps
CPU time 261.5 seconds
Started Aug 07 06:21:06 PM PDT 24
Finished Aug 07 06:25:28 PM PDT 24
Peak memory 253580 kb
Host smart-69b65c8e-851d-48b8-b6a8-e9503e4e1d66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482172084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.2482172084
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.2128573308
Short name T697
Test name
Test status
Simulation time 18903157143 ps
CPU time 84.41 seconds
Started Aug 07 06:21:00 PM PDT 24
Finished Aug 07 06:22:24 PM PDT 24
Peak memory 250948 kb
Host smart-134a903e-5f73-4743-95e2-5a2979e6e98b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128573308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.2128573308
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.1745150061
Short name T210
Test name
Test status
Simulation time 98567459904 ps
CPU time 1059.85 seconds
Started Aug 07 06:21:02 PM PDT 24
Finished Aug 07 06:38:42 PM PDT 24
Peak memory 271840 kb
Host smart-1c835d94-3b59-4496-821b-52cedc061b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745150061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.1745150061
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.337827920
Short name T524
Test name
Test status
Simulation time 7545893364 ps
CPU time 99.7 seconds
Started Aug 07 06:21:03 PM PDT 24
Finished Aug 07 06:22:43 PM PDT 24
Peak memory 249960 kb
Host smart-f982a300-ec9f-474d-bab3-e2e82e8d91c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337827920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.337827920
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.285065208
Short name T635
Test name
Test status
Simulation time 229263715 ps
CPU time 7.36 seconds
Started Aug 07 06:21:01 PM PDT 24
Finished Aug 07 06:21:09 PM PDT 24
Peak memory 233488 kb
Host smart-86322053-6da4-43ad-acdc-cabd503abde7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285065208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmds
.285065208
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_intercept.2896049675
Short name T797
Test name
Test status
Simulation time 2171266320 ps
CPU time 21.87 seconds
Started Aug 07 06:21:01 PM PDT 24
Finished Aug 07 06:21:23 PM PDT 24
Peak memory 233524 kb
Host smart-4863eba0-f6f8-4674-bd0c-0096c53c5aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896049675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.2896049675
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.2173575548
Short name T201
Test name
Test status
Simulation time 51993891900 ps
CPU time 36.4 seconds
Started Aug 07 06:21:01 PM PDT 24
Finished Aug 07 06:21:37 PM PDT 24
Peak memory 233504 kb
Host smart-ae04565a-9507-46f8-801e-1d160779ad16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173575548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.2173575548
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.2145549567
Short name T575
Test name
Test status
Simulation time 31067844010 ps
CPU time 13.76 seconds
Started Aug 07 06:21:08 PM PDT 24
Finished Aug 07 06:21:22 PM PDT 24
Peak memory 225316 kb
Host smart-3cb0c70c-334f-4728-ad93-e43a48f44abc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145549567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.2145549567
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.4179970780
Short name T420
Test name
Test status
Simulation time 124385128 ps
CPU time 2.27 seconds
Started Aug 07 06:20:57 PM PDT 24
Finished Aug 07 06:21:00 PM PDT 24
Peak memory 233056 kb
Host smart-35ba4c9e-558a-4a7f-bd2c-84cd79827de0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179970780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.4179970780
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.1367388007
Short name T630
Test name
Test status
Simulation time 705371672 ps
CPU time 8.45 seconds
Started Aug 07 06:21:04 PM PDT 24
Finished Aug 07 06:21:12 PM PDT 24
Peak memory 219876 kb
Host smart-790a0a14-d998-4028-aaa1-e4b09d7667f0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1367388007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.1367388007
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.4198116850
Short name T151
Test name
Test status
Simulation time 529758121 ps
CPU time 1 seconds
Started Aug 07 06:21:00 PM PDT 24
Finished Aug 07 06:21:01 PM PDT 24
Peak memory 207636 kb
Host smart-0d49a6ec-853d-44c6-aec2-34a1706196c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198116850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.4198116850
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.1125807994
Short name T717
Test name
Test status
Simulation time 3252511230 ps
CPU time 5.13 seconds
Started Aug 07 06:20:54 PM PDT 24
Finished Aug 07 06:21:00 PM PDT 24
Peak memory 217060 kb
Host smart-97c30a3c-80f5-4599-b644-355c64362819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125807994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.1125807994
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.3018456987
Short name T643
Test name
Test status
Simulation time 898984908 ps
CPU time 4.29 seconds
Started Aug 07 06:20:59 PM PDT 24
Finished Aug 07 06:21:04 PM PDT 24
Peak memory 216984 kb
Host smart-052f555c-a3a7-4fad-a996-881841b829ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018456987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.3018456987
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.220508034
Short name T951
Test name
Test status
Simulation time 130331989 ps
CPU time 2.18 seconds
Started Aug 07 06:20:56 PM PDT 24
Finished Aug 07 06:20:59 PM PDT 24
Peak memory 216908 kb
Host smart-c21bbced-b5fa-4aba-9491-9ab5836f6104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220508034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.220508034
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.131013351
Short name T399
Test name
Test status
Simulation time 37200534 ps
CPU time 0.83 seconds
Started Aug 07 06:20:56 PM PDT 24
Finished Aug 07 06:20:57 PM PDT 24
Peak memory 206576 kb
Host smart-b619f374-2c98-46ec-bef4-53e8ecbe79a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131013351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.131013351
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.4007158528
Short name T108
Test name
Test status
Simulation time 112149720 ps
CPU time 2.78 seconds
Started Aug 07 06:21:01 PM PDT 24
Finished Aug 07 06:21:04 PM PDT 24
Peak memory 224904 kb
Host smart-32cb2157-fba1-4698-aa14-c9bb07ec786d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007158528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.4007158528
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.1578445990
Short name T950
Test name
Test status
Simulation time 31627343 ps
CPU time 0.77 seconds
Started Aug 07 06:21:01 PM PDT 24
Finished Aug 07 06:21:02 PM PDT 24
Peak memory 205844 kb
Host smart-2e77cd68-17ac-44c1-8be9-74b55b16ed44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578445990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
1578445990
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.229654298
Short name T601
Test name
Test status
Simulation time 258710687 ps
CPU time 6.51 seconds
Started Aug 07 06:21:03 PM PDT 24
Finished Aug 07 06:21:09 PM PDT 24
Peak memory 225288 kb
Host smart-37636f43-0dbd-48fa-9b4a-66675d1a5bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229654298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.229654298
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.710648507
Short name T639
Test name
Test status
Simulation time 40663337 ps
CPU time 0.85 seconds
Started Aug 07 06:21:01 PM PDT 24
Finished Aug 07 06:21:02 PM PDT 24
Peak memory 207004 kb
Host smart-ef3a9564-7b5b-44a6-8fc4-5ef7573c416c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710648507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.710648507
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.2299038049
Short name T237
Test name
Test status
Simulation time 4700942019 ps
CPU time 39.39 seconds
Started Aug 07 06:21:04 PM PDT 24
Finished Aug 07 06:21:43 PM PDT 24
Peak memory 235420 kb
Host smart-976ee3ce-7971-4c28-9dfc-f6ddd68969c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299038049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.2299038049
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.1878651118
Short name T745
Test name
Test status
Simulation time 3095580890 ps
CPU time 48.36 seconds
Started Aug 07 06:21:08 PM PDT 24
Finished Aug 07 06:21:57 PM PDT 24
Peak memory 258112 kb
Host smart-50d07722-40a1-4682-8649-361fabe59d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878651118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.1878651118
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.1611287695
Short name T695
Test name
Test status
Simulation time 1560254154 ps
CPU time 22.51 seconds
Started Aug 07 06:21:08 PM PDT 24
Finished Aug 07 06:21:31 PM PDT 24
Peak memory 225308 kb
Host smart-c5f282d5-6929-4e69-ab34-52162b2754be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611287695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.1611287695
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.608508903
Short name T15
Test name
Test status
Simulation time 91585512 ps
CPU time 3.46 seconds
Started Aug 07 06:21:02 PM PDT 24
Finished Aug 07 06:21:05 PM PDT 24
Peak memory 241632 kb
Host smart-e76eeaf2-eb01-4a96-9d22-f50c4a08112f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608508903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.608508903
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.4261767324
Short name T624
Test name
Test status
Simulation time 12649597412 ps
CPU time 46.37 seconds
Started Aug 07 06:21:01 PM PDT 24
Finished Aug 07 06:21:47 PM PDT 24
Peak memory 225316 kb
Host smart-e6a29d96-1929-4202-abc2-d3f5dbaa4df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261767324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmd
s.4261767324
Directory /workspace/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/22.spi_device_intercept.3295122131
Short name T269
Test name
Test status
Simulation time 836539532 ps
CPU time 3.17 seconds
Started Aug 07 06:21:08 PM PDT 24
Finished Aug 07 06:21:12 PM PDT 24
Peak memory 219520 kb
Host smart-f5ac2923-2691-4d20-8e3e-7c221587bb17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295122131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.3295122131
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.2690796100
Short name T458
Test name
Test status
Simulation time 2204210881 ps
CPU time 11.41 seconds
Started Aug 07 06:21:04 PM PDT 24
Finished Aug 07 06:21:16 PM PDT 24
Peak memory 233492 kb
Host smart-0c765e14-2bde-4be2-8256-43ed90fb5ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690796100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.2690796100
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.2630461052
Short name T293
Test name
Test status
Simulation time 554528628 ps
CPU time 2.93 seconds
Started Aug 07 06:21:03 PM PDT 24
Finished Aug 07 06:21:06 PM PDT 24
Peak memory 225288 kb
Host smart-8ae0fd38-0834-4d7d-80fa-f743244e9646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630461052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.2630461052
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.1379463048
Short name T289
Test name
Test status
Simulation time 36146100545 ps
CPU time 27.97 seconds
Started Aug 07 06:21:00 PM PDT 24
Finished Aug 07 06:21:28 PM PDT 24
Peak memory 225348 kb
Host smart-5a79e897-b847-46cd-bc0e-d057baecb816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379463048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.1379463048
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.1491940628
Short name T426
Test name
Test status
Simulation time 1649821520 ps
CPU time 7.98 seconds
Started Aug 07 06:21:08 PM PDT 24
Finished Aug 07 06:21:16 PM PDT 24
Peak memory 222960 kb
Host smart-594a3285-5e74-4490-94f0-e5855dc20511
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1491940628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.1491940628
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.1965464893
Short name T650
Test name
Test status
Simulation time 30506719852 ps
CPU time 107.71 seconds
Started Aug 07 06:21:07 PM PDT 24
Finished Aug 07 06:22:55 PM PDT 24
Peak memory 235584 kb
Host smart-8e5db474-c6f9-415d-ae2b-5029604bd5fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965464893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.1965464893
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.2702423903
Short name T466
Test name
Test status
Simulation time 6441595386 ps
CPU time 42.65 seconds
Started Aug 07 06:21:02 PM PDT 24
Finished Aug 07 06:21:44 PM PDT 24
Peak memory 216888 kb
Host smart-f588351b-9d3d-4dcc-ab28-3b06729d121a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702423903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.2702423903
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.3598126343
Short name T892
Test name
Test status
Simulation time 2416835896 ps
CPU time 11.13 seconds
Started Aug 07 06:21:03 PM PDT 24
Finished Aug 07 06:21:14 PM PDT 24
Peak memory 217036 kb
Host smart-eefdf1d2-7e7a-4e63-84bd-dac4fd1bdd35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598126343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.3598126343
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.3420894317
Short name T308
Test name
Test status
Simulation time 142731119 ps
CPU time 2.75 seconds
Started Aug 07 06:21:02 PM PDT 24
Finished Aug 07 06:21:05 PM PDT 24
Peak memory 217028 kb
Host smart-b9a47bae-4076-4972-a9bb-611c78553126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420894317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.3420894317
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.1653167372
Short name T747
Test name
Test status
Simulation time 142405065 ps
CPU time 0.88 seconds
Started Aug 07 06:21:02 PM PDT 24
Finished Aug 07 06:21:03 PM PDT 24
Peak memory 206936 kb
Host smart-08df5fe6-1958-454f-ac49-bf4841681fb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653167372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.1653167372
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.2130903438
Short name T107
Test name
Test status
Simulation time 95094383 ps
CPU time 2.33 seconds
Started Aug 07 06:21:02 PM PDT 24
Finished Aug 07 06:21:04 PM PDT 24
Peak memory 233464 kb
Host smart-5d61ec49-9f60-4b1f-9580-8b3f542253f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130903438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.2130903438
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.2329408966
Short name T335
Test name
Test status
Simulation time 14505923 ps
CPU time 0.73 seconds
Started Aug 07 06:21:09 PM PDT 24
Finished Aug 07 06:21:10 PM PDT 24
Peak memory 205852 kb
Host smart-90ed0f94-43c5-47a6-89b7-36f18adf6543
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329408966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
2329408966
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.363568791
Short name T422
Test name
Test status
Simulation time 1033402722 ps
CPU time 4.65 seconds
Started Aug 07 06:21:12 PM PDT 24
Finished Aug 07 06:21:17 PM PDT 24
Peak memory 233340 kb
Host smart-c0f5c9e9-1636-4c50-ad99-ba2a4b038e97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363568791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.363568791
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.1309880887
Short name T336
Test name
Test status
Simulation time 109176973 ps
CPU time 0.8 seconds
Started Aug 07 06:21:01 PM PDT 24
Finished Aug 07 06:21:02 PM PDT 24
Peak memory 207044 kb
Host smart-4d201402-7b0f-4e42-906c-cfe417f004c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309880887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.1309880887
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.3205741354
Short name T562
Test name
Test status
Simulation time 14826064991 ps
CPU time 53.54 seconds
Started Aug 07 06:21:11 PM PDT 24
Finished Aug 07 06:22:04 PM PDT 24
Peak memory 249944 kb
Host smart-05f3fa9c-78dd-474a-98f1-51a923f095db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205741354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.3205741354
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.2477516229
Short name T846
Test name
Test status
Simulation time 39759405077 ps
CPU time 372.97 seconds
Started Aug 07 06:21:08 PM PDT 24
Finished Aug 07 06:27:21 PM PDT 24
Peak memory 255348 kb
Host smart-ffb4c0c0-816a-4d32-aa7f-c9a48bfce82c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477516229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.2477516229
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.4151934738
Short name T547
Test name
Test status
Simulation time 141131976755 ps
CPU time 304.17 seconds
Started Aug 07 06:21:08 PM PDT 24
Finished Aug 07 06:26:12 PM PDT 24
Peak memory 249976 kb
Host smart-46af29df-81bc-4e0e-88b9-310f22876d69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151934738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.4151934738
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.2702158189
Short name T300
Test name
Test status
Simulation time 8534426484 ps
CPU time 18.25 seconds
Started Aug 07 06:21:11 PM PDT 24
Finished Aug 07 06:21:29 PM PDT 24
Peak memory 233564 kb
Host smart-b71d13fc-b15e-4bcb-8152-f5d3e32c389a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702158189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.2702158189
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.3403848026
Short name T42
Test name
Test status
Simulation time 18755801699 ps
CPU time 133.63 seconds
Started Aug 07 06:21:08 PM PDT 24
Finished Aug 07 06:23:21 PM PDT 24
Peak memory 254776 kb
Host smart-b2ed7156-c08d-4747-bef5-dfc0bd4e3a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403848026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmd
s.3403848026
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.47400517
Short name T402
Test name
Test status
Simulation time 19599789322 ps
CPU time 50.77 seconds
Started Aug 07 06:21:12 PM PDT 24
Finished Aug 07 06:22:03 PM PDT 24
Peak memory 233428 kb
Host smart-702f8bd4-aa85-4638-beaf-aae6d7995d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47400517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.47400517
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.1466862180
Short name T733
Test name
Test status
Simulation time 67273905 ps
CPU time 2.13 seconds
Started Aug 07 06:21:10 PM PDT 24
Finished Aug 07 06:21:13 PM PDT 24
Peak memory 225152 kb
Host smart-4c90ab97-0bd2-4f9b-9935-43ac51286a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466862180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.1466862180
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.1485891441
Short name T887
Test name
Test status
Simulation time 2483302889 ps
CPU time 3.99 seconds
Started Aug 07 06:21:04 PM PDT 24
Finished Aug 07 06:21:08 PM PDT 24
Peak memory 225276 kb
Host smart-c9fe4659-f20d-4769-b79a-5e85fcf317e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485891441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.1485891441
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.3373305468
Short name T1003
Test name
Test status
Simulation time 4442129662 ps
CPU time 7.71 seconds
Started Aug 07 06:21:10 PM PDT 24
Finished Aug 07 06:21:18 PM PDT 24
Peak memory 219960 kb
Host smart-3e08320a-c4f6-4fb2-ba10-25fe743e45f7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3373305468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.3373305468
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.65699076
Short name T19
Test name
Test status
Simulation time 2119713640 ps
CPU time 46.94 seconds
Started Aug 07 06:21:10 PM PDT 24
Finished Aug 07 06:21:57 PM PDT 24
Peak memory 258092 kb
Host smart-b0b2431f-7b24-4f56-b386-59009a144540
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65699076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stress
_all.65699076
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.2276308821
Short name T310
Test name
Test status
Simulation time 12082224698 ps
CPU time 34.69 seconds
Started Aug 07 06:21:01 PM PDT 24
Finished Aug 07 06:21:36 PM PDT 24
Peak memory 217028 kb
Host smart-cae590d7-4e8f-4e6e-904c-cd20b0bf758b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276308821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.2276308821
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.740106551
Short name T25
Test name
Test status
Simulation time 836868298 ps
CPU time 6.04 seconds
Started Aug 07 06:21:01 PM PDT 24
Finished Aug 07 06:21:07 PM PDT 24
Peak memory 216980 kb
Host smart-e909fb5f-d2d7-4001-ae9d-50ba7cea1d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740106551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.740106551
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.2166836647
Short name T793
Test name
Test status
Simulation time 82690912 ps
CPU time 1.55 seconds
Started Aug 07 06:21:06 PM PDT 24
Finished Aug 07 06:21:08 PM PDT 24
Peak memory 208716 kb
Host smart-b6ff990a-71a9-44f2-b6f3-3a1f240798d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166836647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.2166836647
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.1520026913
Short name T682
Test name
Test status
Simulation time 79319023 ps
CPU time 0.83 seconds
Started Aug 07 06:21:03 PM PDT 24
Finished Aug 07 06:21:04 PM PDT 24
Peak memory 206536 kb
Host smart-bf7bc4ef-0a8f-44a4-af06-6d78613016f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520026913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.1520026913
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.4087046761
Short name T780
Test name
Test status
Simulation time 16354377106 ps
CPU time 15.19 seconds
Started Aug 07 06:21:11 PM PDT 24
Finished Aug 07 06:21:26 PM PDT 24
Peak memory 233520 kb
Host smart-e0dfd0da-ba38-4cb8-a827-543ba93a7930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087046761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.4087046761
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.3469159053
Short name T361
Test name
Test status
Simulation time 23801770 ps
CPU time 0.75 seconds
Started Aug 07 06:21:10 PM PDT 24
Finished Aug 07 06:21:11 PM PDT 24
Peak memory 205868 kb
Host smart-74576117-cf77-4ddb-b7ac-263c1a6e1a6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469159053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
3469159053
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.3623460922
Short name T993
Test name
Test status
Simulation time 960863553 ps
CPU time 4.05 seconds
Started Aug 07 06:21:11 PM PDT 24
Finished Aug 07 06:21:15 PM PDT 24
Peak memory 233432 kb
Host smart-97932485-3f46-4f1d-b302-beea30d26a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623460922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.3623460922
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.548282396
Short name T801
Test name
Test status
Simulation time 18357414 ps
CPU time 0.76 seconds
Started Aug 07 06:21:10 PM PDT 24
Finished Aug 07 06:21:11 PM PDT 24
Peak memory 207060 kb
Host smart-8b616117-7258-451e-b1d3-2c65ddccd890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548282396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.548282396
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.1867534974
Short name T231
Test name
Test status
Simulation time 81490376872 ps
CPU time 205.66 seconds
Started Aug 07 06:21:13 PM PDT 24
Finished Aug 07 06:24:39 PM PDT 24
Peak memory 258104 kb
Host smart-b5246e9d-5257-43b6-a1cc-0fd7c5d2f6ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867534974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.1867534974
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.1915448686
Short name T5
Test name
Test status
Simulation time 9443680311 ps
CPU time 65.11 seconds
Started Aug 07 06:21:10 PM PDT 24
Finished Aug 07 06:22:16 PM PDT 24
Peak memory 241804 kb
Host smart-1afb97f5-656b-4e63-86d1-93e5a66440e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915448686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.1915448686
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.297089359
Short name T569
Test name
Test status
Simulation time 5321282453 ps
CPU time 34.54 seconds
Started Aug 07 06:21:14 PM PDT 24
Finished Aug 07 06:21:49 PM PDT 24
Peak memory 233632 kb
Host smart-5f8454bd-5918-462f-a83d-7a04fef3df6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297089359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idle
.297089359
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.2337644884
Short name T1010
Test name
Test status
Simulation time 1054791260 ps
CPU time 11.24 seconds
Started Aug 07 06:21:09 PM PDT 24
Finished Aug 07 06:21:20 PM PDT 24
Peak memory 233448 kb
Host smart-efcea3b5-2478-4eab-957c-e071c477b0d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337644884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.2337644884
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.204811650
Short name T911
Test name
Test status
Simulation time 8823232729 ps
CPU time 60.2 seconds
Started Aug 07 06:21:12 PM PDT 24
Finished Aug 07 06:22:12 PM PDT 24
Peak memory 257400 kb
Host smart-b3957586-805d-4500-b306-3bffd02db058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204811650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmds
.204811650
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/24.spi_device_intercept.2331879404
Short name T900
Test name
Test status
Simulation time 415651419 ps
CPU time 5.88 seconds
Started Aug 07 06:21:08 PM PDT 24
Finished Aug 07 06:21:14 PM PDT 24
Peak memory 225132 kb
Host smart-d569641c-21b0-4807-a386-1ee7c071b8ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331879404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.2331879404
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.1035254152
Short name T850
Test name
Test status
Simulation time 3405588675 ps
CPU time 8.39 seconds
Started Aug 07 06:21:10 PM PDT 24
Finished Aug 07 06:21:19 PM PDT 24
Peak memory 233572 kb
Host smart-dd32f377-b2b7-4a9f-abf0-c53db5e08f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035254152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.1035254152
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.1336839862
Short name T641
Test name
Test status
Simulation time 1213133587 ps
CPU time 6.97 seconds
Started Aug 07 06:21:09 PM PDT 24
Finished Aug 07 06:21:16 PM PDT 24
Peak memory 233464 kb
Host smart-62b8a060-4fb6-4bd5-9666-a6ba0cb9866d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336839862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.1336839862
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.410000584
Short name T64
Test name
Test status
Simulation time 5687996193 ps
CPU time 8.01 seconds
Started Aug 07 06:21:10 PM PDT 24
Finished Aug 07 06:21:19 PM PDT 24
Peak memory 233500 kb
Host smart-382f0009-02d5-44c5-bc30-a05a0e79a9b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410000584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.410000584
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.107756051
Short name T141
Test name
Test status
Simulation time 580737921 ps
CPU time 7.66 seconds
Started Aug 07 06:21:08 PM PDT 24
Finished Aug 07 06:21:16 PM PDT 24
Peak memory 222844 kb
Host smart-937260d4-2fa1-4f35-9042-23ee18b0583f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=107756051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dire
ct.107756051
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.605139863
Short name T467
Test name
Test status
Simulation time 59122031 ps
CPU time 0.97 seconds
Started Aug 07 06:21:11 PM PDT 24
Finished Aug 07 06:21:12 PM PDT 24
Peak memory 208024 kb
Host smart-a654755f-5445-485b-8b35-85dfede26a6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605139863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stres
s_all.605139863
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.271074187
Short name T1020
Test name
Test status
Simulation time 18289673084 ps
CPU time 16.06 seconds
Started Aug 07 06:21:10 PM PDT 24
Finished Aug 07 06:21:26 PM PDT 24
Peak memory 218116 kb
Host smart-3004efdc-60ab-4aef-ac0d-8cf6f1fee3ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271074187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.271074187
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.4255457420
Short name T353
Test name
Test status
Simulation time 1679446328 ps
CPU time 4.37 seconds
Started Aug 07 06:21:10 PM PDT 24
Finished Aug 07 06:21:14 PM PDT 24
Peak memory 216928 kb
Host smart-ebeab4c8-ba2b-4729-8828-ec792669427a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255457420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.4255457420
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.3227878940
Short name T783
Test name
Test status
Simulation time 17881127 ps
CPU time 1.12 seconds
Started Aug 07 06:21:08 PM PDT 24
Finished Aug 07 06:21:09 PM PDT 24
Peak memory 216972 kb
Host smart-04bc1fa1-3474-4472-8ec9-70c27b6fb25e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227878940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.3227878940
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.2866368962
Short name T381
Test name
Test status
Simulation time 76274506 ps
CPU time 0.88 seconds
Started Aug 07 06:21:09 PM PDT 24
Finished Aug 07 06:21:10 PM PDT 24
Peak memory 206588 kb
Host smart-93206d7c-2733-4433-ba5f-fd990aeeff5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866368962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.2866368962
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.1959147274
Short name T506
Test name
Test status
Simulation time 40486620262 ps
CPU time 33.52 seconds
Started Aug 07 06:21:07 PM PDT 24
Finished Aug 07 06:21:40 PM PDT 24
Peak memory 240584 kb
Host smart-da2a4e5d-974e-4a23-b775-a8988e41ae5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959147274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.1959147274
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.2469193008
Short name T586
Test name
Test status
Simulation time 40625500 ps
CPU time 0.75 seconds
Started Aug 07 06:21:16 PM PDT 24
Finished Aug 07 06:21:17 PM PDT 24
Peak memory 206224 kb
Host smart-e937b24f-c949-4d37-918d-9f0d385876b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469193008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
2469193008
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.3589792371
Short name T864
Test name
Test status
Simulation time 267637181 ps
CPU time 3.36 seconds
Started Aug 07 06:21:14 PM PDT 24
Finished Aug 07 06:21:17 PM PDT 24
Peak memory 233336 kb
Host smart-f3536260-df03-4b09-b147-22fc13b96d62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589792371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.3589792371
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.3183761164
Short name T511
Test name
Test status
Simulation time 14165870 ps
CPU time 0.78 seconds
Started Aug 07 06:21:12 PM PDT 24
Finished Aug 07 06:21:13 PM PDT 24
Peak memory 207408 kb
Host smart-d0009257-6301-4baf-82e7-0c97b76e0df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183761164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.3183761164
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.2143863341
Short name T37
Test name
Test status
Simulation time 10702332922 ps
CPU time 143.91 seconds
Started Aug 07 06:21:16 PM PDT 24
Finished Aug 07 06:23:40 PM PDT 24
Peak memory 254360 kb
Host smart-199d7989-2309-4f03-92b4-23b6bcedcec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143863341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.2143863341
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.4159852229
Short name T127
Test name
Test status
Simulation time 8802251801 ps
CPU time 139.87 seconds
Started Aug 07 06:21:25 PM PDT 24
Finished Aug 07 06:23:45 PM PDT 24
Peak memory 257240 kb
Host smart-f20f916b-8d9c-4d0c-9f66-adac0e6b8a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159852229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.4159852229
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.294549205
Short name T437
Test name
Test status
Simulation time 12927085846 ps
CPU time 77.73 seconds
Started Aug 07 06:21:18 PM PDT 24
Finished Aug 07 06:22:36 PM PDT 24
Peak memory 259976 kb
Host smart-d4311316-001d-41dd-b2c6-f3a4bb466b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294549205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idle
.294549205
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.36037845
Short name T755
Test name
Test status
Simulation time 16551130268 ps
CPU time 10.91 seconds
Started Aug 07 06:21:14 PM PDT 24
Finished Aug 07 06:21:25 PM PDT 24
Peak memory 225344 kb
Host smart-11e168f2-45ff-4b53-b739-9762933aa9d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36037845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.36037845
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.1907016519
Short name T994
Test name
Test status
Simulation time 75858643396 ps
CPU time 253.62 seconds
Started Aug 07 06:21:13 PM PDT 24
Finished Aug 07 06:25:27 PM PDT 24
Peak memory 257656 kb
Host smart-a6143392-a532-48e5-9485-fb833944aa1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907016519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmd
s.1907016519
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/25.spi_device_intercept.148091285
Short name T583
Test name
Test status
Simulation time 439428475 ps
CPU time 4.71 seconds
Started Aug 07 06:21:14 PM PDT 24
Finished Aug 07 06:21:19 PM PDT 24
Peak memory 233428 kb
Host smart-4913eb48-02f4-48e0-82a9-cce0afd82cf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148091285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.148091285
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.2009149076
Short name T804
Test name
Test status
Simulation time 6134869696 ps
CPU time 16.73 seconds
Started Aug 07 06:21:15 PM PDT 24
Finished Aug 07 06:21:32 PM PDT 24
Peak memory 233520 kb
Host smart-55f5672e-3a30-4e65-8e71-a0f9c9f3a1c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009149076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.2009149076
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.1929054406
Short name T192
Test name
Test status
Simulation time 283404820 ps
CPU time 3.19 seconds
Started Aug 07 06:21:15 PM PDT 24
Finished Aug 07 06:21:19 PM PDT 24
Peak memory 225388 kb
Host smart-a3a5341f-6ce8-4506-84d2-bd5a33f42cc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929054406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.1929054406
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.2773919980
Short name T447
Test name
Test status
Simulation time 22007511419 ps
CPU time 12.56 seconds
Started Aug 07 06:21:15 PM PDT 24
Finished Aug 07 06:21:27 PM PDT 24
Peak memory 233520 kb
Host smart-8b775e62-3510-4856-b112-e60252958b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773919980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.2773919980
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.2831822788
Short name T423
Test name
Test status
Simulation time 120377840 ps
CPU time 3.52 seconds
Started Aug 07 06:21:17 PM PDT 24
Finished Aug 07 06:21:21 PM PDT 24
Peak memory 219628 kb
Host smart-080fcfff-b52c-49ad-9994-82d555036df9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2831822788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.2831822788
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.1713655660
Short name T309
Test name
Test status
Simulation time 15700168492 ps
CPU time 25.19 seconds
Started Aug 07 06:21:09 PM PDT 24
Finished Aug 07 06:21:35 PM PDT 24
Peak memory 217220 kb
Host smart-731a2a98-2255-4308-afd5-9e048f615e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713655660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.1713655660
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.1162490954
Short name T617
Test name
Test status
Simulation time 2531159675 ps
CPU time 10.36 seconds
Started Aug 07 06:21:09 PM PDT 24
Finished Aug 07 06:21:20 PM PDT 24
Peak memory 217004 kb
Host smart-bf766a49-0c95-4730-bb28-770a94a04d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162490954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.1162490954
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.2379738959
Short name T439
Test name
Test status
Simulation time 1252443277 ps
CPU time 3.11 seconds
Started Aug 07 06:21:14 PM PDT 24
Finished Aug 07 06:21:18 PM PDT 24
Peak memory 216980 kb
Host smart-a1009d8e-187c-4cfc-8e27-f20233f4734e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379738959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.2379738959
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.1526189949
Short name T366
Test name
Test status
Simulation time 107824533 ps
CPU time 0.78 seconds
Started Aug 07 06:21:11 PM PDT 24
Finished Aug 07 06:21:12 PM PDT 24
Peak memory 206556 kb
Host smart-fb4f17bc-bff0-4575-b8af-99cf74b3e80b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526189949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.1526189949
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.1068915136
Short name T1019
Test name
Test status
Simulation time 2993049348 ps
CPU time 9.66 seconds
Started Aug 07 06:21:17 PM PDT 24
Finished Aug 07 06:21:27 PM PDT 24
Peak memory 233548 kb
Host smart-214575d8-1dfe-4f08-8092-af34a01648cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068915136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.1068915136
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.583542996
Short name T9
Test name
Test status
Simulation time 32408799 ps
CPU time 0.7 seconds
Started Aug 07 06:21:14 PM PDT 24
Finished Aug 07 06:21:15 PM PDT 24
Peak memory 205264 kb
Host smart-b1c98549-1109-4638-a5c4-e49e690a854a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583542996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.583542996
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.302161703
Short name T798
Test name
Test status
Simulation time 90661293 ps
CPU time 2.22 seconds
Started Aug 07 06:21:16 PM PDT 24
Finished Aug 07 06:21:19 PM PDT 24
Peak memory 224380 kb
Host smart-d93ae582-e8b4-41dd-a99d-2e24bc674d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302161703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.302161703
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.3392867323
Short name T830
Test name
Test status
Simulation time 25634811 ps
CPU time 0.76 seconds
Started Aug 07 06:21:14 PM PDT 24
Finished Aug 07 06:21:15 PM PDT 24
Peak memory 207048 kb
Host smart-53f18f29-ce70-4b87-a848-c0c622d82bc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392867323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.3392867323
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.4130283474
Short name T689
Test name
Test status
Simulation time 494360493 ps
CPU time 11.45 seconds
Started Aug 07 06:21:14 PM PDT 24
Finished Aug 07 06:21:25 PM PDT 24
Peak memory 249868 kb
Host smart-a7a23fc1-f692-4c78-8782-2bee8405dbbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130283474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.4130283474
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.2057652413
Short name T578
Test name
Test status
Simulation time 16795995063 ps
CPU time 81.35 seconds
Started Aug 07 06:21:16 PM PDT 24
Finished Aug 07 06:22:37 PM PDT 24
Peak memory 241776 kb
Host smart-ac73b93b-892a-46a4-a36c-ef7640fedeb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057652413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.2057652413
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.479846666
Short name T488
Test name
Test status
Simulation time 1100563888 ps
CPU time 17.02 seconds
Started Aug 07 06:21:15 PM PDT 24
Finished Aug 07 06:21:32 PM PDT 24
Peak memory 238364 kb
Host smart-bb76e962-0958-4615-a7ba-f85323741557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479846666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.479846666
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.3722868607
Short name T254
Test name
Test status
Simulation time 3765568840 ps
CPU time 40.32 seconds
Started Aug 07 06:21:15 PM PDT 24
Finished Aug 07 06:21:55 PM PDT 24
Peak memory 241732 kb
Host smart-d5eb4d3c-cb2f-4d91-adc6-ccc3950bd3a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722868607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmd
s.3722868607
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_intercept.2833189957
Short name T516
Test name
Test status
Simulation time 1234223597 ps
CPU time 4.29 seconds
Started Aug 07 06:21:14 PM PDT 24
Finished Aug 07 06:21:18 PM PDT 24
Peak memory 225268 kb
Host smart-48ed13b4-9c67-4235-bb0e-f7618f0c6e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833189957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.2833189957
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.1420853640
Short name T704
Test name
Test status
Simulation time 282151058 ps
CPU time 8.88 seconds
Started Aug 07 06:21:25 PM PDT 24
Finished Aug 07 06:21:34 PM PDT 24
Peak memory 240368 kb
Host smart-e0780500-e58c-4169-a8f5-61c9b670a6dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420853640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.1420853640
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.449479799
Short name T179
Test name
Test status
Simulation time 7305486287 ps
CPU time 24.3 seconds
Started Aug 07 06:21:14 PM PDT 24
Finished Aug 07 06:21:38 PM PDT 24
Peak memory 241548 kb
Host smart-0693876f-9430-4869-9386-7917be44db66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449479799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swap
.449479799
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.662895948
Short name T67
Test name
Test status
Simulation time 109198325 ps
CPU time 2.13 seconds
Started Aug 07 06:21:17 PM PDT 24
Finished Aug 07 06:21:19 PM PDT 24
Peak memory 224384 kb
Host smart-c5d4c8b3-b52c-42d0-b335-4c69c1a6270a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662895948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.662895948
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.3388173703
Short name T831
Test name
Test status
Simulation time 1102207438 ps
CPU time 5.92 seconds
Started Aug 07 06:21:15 PM PDT 24
Finished Aug 07 06:21:21 PM PDT 24
Peak memory 220916 kb
Host smart-b0cc274d-2ab2-440d-8d61-92fdcfab579c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3388173703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.3388173703
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.1311123737
Short name T193
Test name
Test status
Simulation time 944324997 ps
CPU time 25.5 seconds
Started Aug 07 06:21:15 PM PDT 24
Finished Aug 07 06:21:41 PM PDT 24
Peak memory 238404 kb
Host smart-14d853b5-a842-4538-a972-8ed8f17b4297
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311123737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.1311123737
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.1283940147
Short name T312
Test name
Test status
Simulation time 29747122567 ps
CPU time 39.34 seconds
Started Aug 07 06:21:13 PM PDT 24
Finished Aug 07 06:21:53 PM PDT 24
Peak memory 217068 kb
Host smart-ff98235d-338d-4066-8a87-bd1b008f68fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283940147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.1283940147
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.2468386127
Short name T474
Test name
Test status
Simulation time 1457597411 ps
CPU time 6.03 seconds
Started Aug 07 06:21:15 PM PDT 24
Finished Aug 07 06:21:21 PM PDT 24
Peak memory 216984 kb
Host smart-6634ee0c-ed7f-465f-a6c8-cd918e0a1739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468386127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.2468386127
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.743960018
Short name T631
Test name
Test status
Simulation time 99238170 ps
CPU time 1.14 seconds
Started Aug 07 06:21:15 PM PDT 24
Finished Aug 07 06:21:17 PM PDT 24
Peak memory 216976 kb
Host smart-440dec40-7ca8-453f-adfc-7098a8c27f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743960018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.743960018
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.1416340863
Short name T982
Test name
Test status
Simulation time 52114251 ps
CPU time 0.88 seconds
Started Aug 07 06:21:17 PM PDT 24
Finished Aug 07 06:21:17 PM PDT 24
Peak memory 206572 kb
Host smart-feb5a9bd-b7c4-4001-8ac8-a53221490bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416340863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.1416340863
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.3694151181
Short name T774
Test name
Test status
Simulation time 1679543208 ps
CPU time 2.4 seconds
Started Aug 07 06:21:23 PM PDT 24
Finished Aug 07 06:21:26 PM PDT 24
Peak memory 225200 kb
Host smart-272064c0-221c-43bc-89f5-35773d47dd6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694151181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.3694151181
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.4130168182
Short name T542
Test name
Test status
Simulation time 16094248 ps
CPU time 0.74 seconds
Started Aug 07 06:21:21 PM PDT 24
Finished Aug 07 06:21:22 PM PDT 24
Peak memory 205204 kb
Host smart-9b0acab1-ee37-49b1-8f06-94c5ae687ff9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130168182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
4130168182
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.1105976580
Short name T160
Test name
Test status
Simulation time 1366481538 ps
CPU time 12.38 seconds
Started Aug 07 06:21:25 PM PDT 24
Finished Aug 07 06:21:37 PM PDT 24
Peak memory 225224 kb
Host smart-0473faff-b949-43fb-af92-926259c80cff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105976580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.1105976580
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.224117741
Short name T342
Test name
Test status
Simulation time 14676326 ps
CPU time 0.76 seconds
Started Aug 07 06:21:12 PM PDT 24
Finished Aug 07 06:21:13 PM PDT 24
Peak memory 207040 kb
Host smart-50bf9509-bfe8-447f-9241-508c3a0607c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224117741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.224117741
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.984818091
Short name T275
Test name
Test status
Simulation time 11540729899 ps
CPU time 18.81 seconds
Started Aug 07 06:21:20 PM PDT 24
Finished Aug 07 06:21:39 PM PDT 24
Peak memory 225328 kb
Host smart-7170fbc0-77e5-46ee-a1d5-33adef272a79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984818091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.984818091
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.3261301109
Short name T861
Test name
Test status
Simulation time 91645277468 ps
CPU time 416.18 seconds
Started Aug 07 06:21:22 PM PDT 24
Finished Aug 07 06:28:18 PM PDT 24
Peak memory 266084 kb
Host smart-cbda178b-61f7-457e-bbee-55f57c1baa22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261301109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.3261301109
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.3902097492
Short name T543
Test name
Test status
Simulation time 2797387246 ps
CPU time 26.59 seconds
Started Aug 07 06:21:19 PM PDT 24
Finished Aug 07 06:21:46 PM PDT 24
Peak memory 241792 kb
Host smart-152e6db9-6f6b-44f1-8cae-ca4a55277215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902097492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.3902097492
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.3238974073
Short name T943
Test name
Test status
Simulation time 147014379 ps
CPU time 5.64 seconds
Started Aug 07 06:21:14 PM PDT 24
Finished Aug 07 06:21:20 PM PDT 24
Peak memory 225256 kb
Host smart-0550f2c8-6093-4639-8784-8eb39c8f14cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238974073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.3238974073
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.2983198625
Short name T428
Test name
Test status
Simulation time 6243337326 ps
CPU time 57.71 seconds
Started Aug 07 06:21:14 PM PDT 24
Finished Aug 07 06:22:12 PM PDT 24
Peak memory 252160 kb
Host smart-144d47e2-5585-44bb-883b-e3fc7c4385c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983198625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmd
s.2983198625
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/27.spi_device_intercept.1196244078
Short name T540
Test name
Test status
Simulation time 97566658 ps
CPU time 2.11 seconds
Started Aug 07 06:21:14 PM PDT 24
Finished Aug 07 06:21:17 PM PDT 24
Peak memory 223588 kb
Host smart-8b6bc0e3-8650-4e8c-ba17-d33782cb6971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196244078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.1196244078
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.3173052490
Short name T446
Test name
Test status
Simulation time 36110931956 ps
CPU time 61.49 seconds
Started Aug 07 06:21:17 PM PDT 24
Finished Aug 07 06:22:18 PM PDT 24
Peak memory 237116 kb
Host smart-4d052311-f185-4cc5-b7ef-6ad0331dc454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173052490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.3173052490
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.2669732649
Short name T938
Test name
Test status
Simulation time 2039292056 ps
CPU time 9.19 seconds
Started Aug 07 06:21:16 PM PDT 24
Finished Aug 07 06:21:25 PM PDT 24
Peak memory 241520 kb
Host smart-8b8662ae-7c9e-4628-8a65-82122c6c2785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669732649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.2669732649
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.1781873051
Short name T732
Test name
Test status
Simulation time 119621687 ps
CPU time 2.6 seconds
Started Aug 07 06:21:15 PM PDT 24
Finished Aug 07 06:21:17 PM PDT 24
Peak memory 225216 kb
Host smart-a55d5086-7714-42f5-8464-f1f7e3a618eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781873051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.1781873051
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.1183089134
Short name T533
Test name
Test status
Simulation time 5608445456 ps
CPU time 14.45 seconds
Started Aug 07 06:21:19 PM PDT 24
Finished Aug 07 06:21:34 PM PDT 24
Peak memory 219948 kb
Host smart-2a6ebe1a-80ae-4cbc-8f88-3c65641a3d67
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1183089134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.1183089134
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.1540961597
Short name T4
Test name
Test status
Simulation time 170620434 ps
CPU time 0.99 seconds
Started Aug 07 06:21:25 PM PDT 24
Finished Aug 07 06:21:26 PM PDT 24
Peak memory 216524 kb
Host smart-ff62b203-c322-46d2-903a-3fc3dfafae6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540961597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.1540961597
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.1991822202
Short name T986
Test name
Test status
Simulation time 23131128 ps
CPU time 0.72 seconds
Started Aug 07 06:21:17 PM PDT 24
Finished Aug 07 06:21:18 PM PDT 24
Peak memory 206176 kb
Host smart-b49fad6f-4a21-492b-a273-c76f810c0f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991822202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.1991822202
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.92418941
Short name T848
Test name
Test status
Simulation time 68520256 ps
CPU time 0.72 seconds
Started Aug 07 06:21:19 PM PDT 24
Finished Aug 07 06:21:20 PM PDT 24
Peak memory 206156 kb
Host smart-9a0203d0-e58a-4779-842a-d6c4fa4d9b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92418941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.92418941
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.3745529510
Short name T534
Test name
Test status
Simulation time 15343356 ps
CPU time 0.77 seconds
Started Aug 07 06:21:17 PM PDT 24
Finished Aug 07 06:21:18 PM PDT 24
Peak memory 206600 kb
Host smart-c9f95a8f-4236-4245-bee8-f37aba9b844f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745529510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.3745529510
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.4031945909
Short name T362
Test name
Test status
Simulation time 137753470 ps
CPU time 0.79 seconds
Started Aug 07 06:21:16 PM PDT 24
Finished Aug 07 06:21:17 PM PDT 24
Peak memory 206580 kb
Host smart-bd0e6892-e2d1-4248-b188-8c958a8439f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031945909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.4031945909
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.202178502
Short name T760
Test name
Test status
Simulation time 2855005091 ps
CPU time 6.91 seconds
Started Aug 07 06:21:19 PM PDT 24
Finished Aug 07 06:21:26 PM PDT 24
Peak memory 233488 kb
Host smart-80bdbfcd-33c2-492f-980f-9ba649ad1e4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202178502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.202178502
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.3189575300
Short name T322
Test name
Test status
Simulation time 10738219 ps
CPU time 0.7 seconds
Started Aug 07 06:21:18 PM PDT 24
Finished Aug 07 06:21:19 PM PDT 24
Peak memory 205276 kb
Host smart-b152bf1b-0d2d-4978-99d6-a5bae063d76b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189575300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
3189575300
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.1272146883
Short name T195
Test name
Test status
Simulation time 1778183738 ps
CPU time 11.83 seconds
Started Aug 07 06:21:20 PM PDT 24
Finished Aug 07 06:21:32 PM PDT 24
Peak memory 233492 kb
Host smart-38c8864f-7d6e-43ec-8015-df3845e540e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272146883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.1272146883
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.2710241852
Short name T761
Test name
Test status
Simulation time 55184134 ps
CPU time 0.8 seconds
Started Aug 07 06:21:24 PM PDT 24
Finished Aug 07 06:21:25 PM PDT 24
Peak memory 207044 kb
Host smart-861b0bc4-3ff7-4f7f-be3f-698bdd8fb75f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710241852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.2710241852
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.2659247195
Short name T700
Test name
Test status
Simulation time 5383421283 ps
CPU time 85.15 seconds
Started Aug 07 06:21:23 PM PDT 24
Finished Aug 07 06:22:48 PM PDT 24
Peak memory 255296 kb
Host smart-a64c20f2-1591-477a-8cd4-1074694db0f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659247195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.2659247195
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.400906546
Short name T445
Test name
Test status
Simulation time 26664679005 ps
CPU time 214.42 seconds
Started Aug 07 06:21:20 PM PDT 24
Finished Aug 07 06:24:55 PM PDT 24
Peak memory 256684 kb
Host smart-939f1179-bf52-4a77-bf49-c58249a57e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400906546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idle
.400906546
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.2192841203
Short name T532
Test name
Test status
Simulation time 133251754 ps
CPU time 6.13 seconds
Started Aug 07 06:21:20 PM PDT 24
Finished Aug 07 06:21:26 PM PDT 24
Peak memory 249760 kb
Host smart-f65030dd-57ea-46aa-b8e6-8418f505be8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192841203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.2192841203
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.1995854985
Short name T464
Test name
Test status
Simulation time 8218708297 ps
CPU time 40.9 seconds
Started Aug 07 06:21:20 PM PDT 24
Finished Aug 07 06:22:01 PM PDT 24
Peak memory 251012 kb
Host smart-8a4dfb6b-eabd-4361-9c82-7f9a8788584b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995854985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmd
s.1995854985
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/28.spi_device_intercept.3584129258
Short name T369
Test name
Test status
Simulation time 1945848890 ps
CPU time 14.6 seconds
Started Aug 07 06:21:21 PM PDT 24
Finished Aug 07 06:21:36 PM PDT 24
Peak memory 225288 kb
Host smart-305a1fec-ffa5-4db2-82e3-830e11abc7ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584129258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.3584129258
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.591768021
Short name T873
Test name
Test status
Simulation time 5703489444 ps
CPU time 32.46 seconds
Started Aug 07 06:21:22 PM PDT 24
Finished Aug 07 06:21:54 PM PDT 24
Peak memory 241712 kb
Host smart-4d1dd6b9-466e-4381-8ce7-b079a8d348b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591768021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.591768021
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.1372512855
Short name T189
Test name
Test status
Simulation time 16646127944 ps
CPU time 17.56 seconds
Started Aug 07 06:21:20 PM PDT 24
Finished Aug 07 06:21:38 PM PDT 24
Peak memory 257380 kb
Host smart-2a2f43d3-2d0b-4ae8-be92-f76667ca7330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372512855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.1372512855
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.761138382
Short name T957
Test name
Test status
Simulation time 1621385570 ps
CPU time 5.36 seconds
Started Aug 07 06:21:20 PM PDT 24
Finished Aug 07 06:21:25 PM PDT 24
Peak memory 225244 kb
Host smart-e5ec8a04-484d-4d69-a08e-15ccff9fdc82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761138382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.761138382
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.1986282255
Short name T526
Test name
Test status
Simulation time 270489892 ps
CPU time 4.91 seconds
Started Aug 07 06:21:19 PM PDT 24
Finished Aug 07 06:21:24 PM PDT 24
Peak memory 223664 kb
Host smart-40e25805-2731-401b-9e49-c4edfe3c89ed
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1986282255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.1986282255
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.3895575063
Short name T303
Test name
Test status
Simulation time 1667850116 ps
CPU time 12.16 seconds
Started Aug 07 06:21:24 PM PDT 24
Finished Aug 07 06:21:36 PM PDT 24
Peak memory 218236 kb
Host smart-102eac47-bef1-4d5e-b2c9-7ce5c5537ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895575063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.3895575063
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.3762041970
Short name T799
Test name
Test status
Simulation time 13622735190 ps
CPU time 13.92 seconds
Started Aug 07 06:21:20 PM PDT 24
Finished Aug 07 06:21:35 PM PDT 24
Peak memory 217040 kb
Host smart-447299c6-319c-453c-be1d-a024495d9f1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762041970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.3762041970
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.3130936862
Short name T776
Test name
Test status
Simulation time 72118502 ps
CPU time 0.88 seconds
Started Aug 07 06:21:20 PM PDT 24
Finished Aug 07 06:21:21 PM PDT 24
Peak memory 207736 kb
Host smart-48bd3313-1c8f-4c8d-99d4-68720699fc2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130936862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.3130936862
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.1993475248
Short name T356
Test name
Test status
Simulation time 51706430 ps
CPU time 0.77 seconds
Started Aug 07 06:21:22 PM PDT 24
Finished Aug 07 06:21:23 PM PDT 24
Peak memory 206564 kb
Host smart-cd0795e3-a606-46ad-b75c-f8685757244e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993475248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.1993475248
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.872308877
Short name T46
Test name
Test status
Simulation time 4321431381 ps
CPU time 19.24 seconds
Started Aug 07 06:21:20 PM PDT 24
Finished Aug 07 06:21:39 PM PDT 24
Peak memory 233468 kb
Host smart-9b44b719-daad-4656-968b-bb3f32a3ed5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872308877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.872308877
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.2503398837
Short name T855
Test name
Test status
Simulation time 14032475 ps
CPU time 0.74 seconds
Started Aug 07 06:21:26 PM PDT 24
Finished Aug 07 06:21:27 PM PDT 24
Peak memory 205364 kb
Host smart-9ead42cd-7bab-41b5-a0eb-09a43669b577
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503398837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
2503398837
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.2071738595
Short name T972
Test name
Test status
Simulation time 112487348 ps
CPU time 2.21 seconds
Started Aug 07 06:21:25 PM PDT 24
Finished Aug 07 06:21:28 PM PDT 24
Peak memory 225268 kb
Host smart-5d37f5a6-00ac-4dbe-a438-e32bd3793af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071738595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.2071738595
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.489814427
Short name T614
Test name
Test status
Simulation time 32453575 ps
CPU time 0.74 seconds
Started Aug 07 06:21:24 PM PDT 24
Finished Aug 07 06:21:24 PM PDT 24
Peak memory 206024 kb
Host smart-72fd4002-bbe4-4d21-8faf-12f72a20baea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489814427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.489814427
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.3998454826
Short name T762
Test name
Test status
Simulation time 27347390180 ps
CPU time 40.88 seconds
Started Aug 07 06:21:26 PM PDT 24
Finished Aug 07 06:22:07 PM PDT 24
Peak memory 236688 kb
Host smart-4e60c7ef-6617-4772-a101-94b87594f3f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998454826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.3998454826
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.3467552915
Short name T954
Test name
Test status
Simulation time 10220220210 ps
CPU time 98.2 seconds
Started Aug 07 06:21:26 PM PDT 24
Finished Aug 07 06:23:04 PM PDT 24
Peak memory 241820 kb
Host smart-1441123c-d973-499b-be9e-bdcf333b8bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467552915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.3467552915
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.876791782
Short name T513
Test name
Test status
Simulation time 5679522355 ps
CPU time 85.24 seconds
Started Aug 07 06:21:28 PM PDT 24
Finished Aug 07 06:22:54 PM PDT 24
Peak memory 257876 kb
Host smart-70c23975-9ac3-4eaf-8251-766d78fc36f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876791782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idle
.876791782
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.4240302674
Short name T918
Test name
Test status
Simulation time 36110888 ps
CPU time 2.74 seconds
Started Aug 07 06:21:29 PM PDT 24
Finished Aug 07 06:21:32 PM PDT 24
Peak memory 233400 kb
Host smart-75b409f8-e324-444e-abf2-83e5fcd492cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240302674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.4240302674
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.1511082916
Short name T255
Test name
Test status
Simulation time 2081352762 ps
CPU time 16.39 seconds
Started Aug 07 06:21:26 PM PDT 24
Finished Aug 07 06:21:42 PM PDT 24
Peak memory 222128 kb
Host smart-82ca2286-1300-422c-88a4-7e9e15c22430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511082916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmd
s.1511082916
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/29.spi_device_intercept.1977652858
Short name T144
Test name
Test status
Simulation time 10438681667 ps
CPU time 13.11 seconds
Started Aug 07 06:21:24 PM PDT 24
Finished Aug 07 06:21:37 PM PDT 24
Peak memory 229400 kb
Host smart-438b2b0e-c75e-40ba-b0db-ffdd70a28dd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977652858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.1977652858
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.422974102
Short name T1025
Test name
Test status
Simulation time 40300736630 ps
CPU time 106.45 seconds
Started Aug 07 06:21:23 PM PDT 24
Finished Aug 07 06:23:09 PM PDT 24
Peak memory 233488 kb
Host smart-56dc9d1a-8db2-4d99-a717-62ae5946cdc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422974102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.422974102
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.3583561545
Short name T934
Test name
Test status
Simulation time 4916973199 ps
CPU time 3.56 seconds
Started Aug 07 06:21:20 PM PDT 24
Finished Aug 07 06:21:24 PM PDT 24
Peak memory 225152 kb
Host smart-4c2a9bec-9ce8-49cb-ab6a-54623139020d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583561545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.3583561545
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.1969368020
Short name T595
Test name
Test status
Simulation time 661079155 ps
CPU time 3.82 seconds
Started Aug 07 06:21:19 PM PDT 24
Finished Aug 07 06:21:23 PM PDT 24
Peak memory 225184 kb
Host smart-4e282bca-d6bf-4f25-9cb7-0a3d770a21d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969368020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.1969368020
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.3664727686
Short name T376
Test name
Test status
Simulation time 3127250201 ps
CPU time 9.84 seconds
Started Aug 07 06:21:25 PM PDT 24
Finished Aug 07 06:21:35 PM PDT 24
Peak memory 220020 kb
Host smart-d564bc80-2e21-49d9-863d-1d7b27af50ff
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3664727686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.3664727686
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.2086834209
Short name T896
Test name
Test status
Simulation time 10855902457 ps
CPU time 34.64 seconds
Started Aug 07 06:21:25 PM PDT 24
Finished Aug 07 06:22:00 PM PDT 24
Peak memory 216996 kb
Host smart-c7b8e7be-85a4-4aef-8af9-ac4663a4cb60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086834209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.2086834209
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.3128559989
Short name T669
Test name
Test status
Simulation time 2189794699 ps
CPU time 4.96 seconds
Started Aug 07 06:21:19 PM PDT 24
Finished Aug 07 06:21:24 PM PDT 24
Peak memory 217012 kb
Host smart-1200fe47-0ab1-4415-ad8a-cce67774c1d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128559989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.3128559989
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.2006625127
Short name T499
Test name
Test status
Simulation time 19469581 ps
CPU time 0.9 seconds
Started Aug 07 06:21:21 PM PDT 24
Finished Aug 07 06:21:22 PM PDT 24
Peak memory 207824 kb
Host smart-dce581e0-09f2-4778-a0f0-72f19a60e7b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006625127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.2006625127
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.2050270680
Short name T775
Test name
Test status
Simulation time 32357568 ps
CPU time 0.86 seconds
Started Aug 07 06:21:21 PM PDT 24
Finished Aug 07 06:21:22 PM PDT 24
Peak memory 206576 kb
Host smart-f73baaf5-5593-4857-ba9b-468f4171a155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050270680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.2050270680
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.3643812869
Short name T427
Test name
Test status
Simulation time 4080898864 ps
CPU time 6.75 seconds
Started Aug 07 06:21:24 PM PDT 24
Finished Aug 07 06:21:31 PM PDT 24
Peak memory 233476 kb
Host smart-cc427ab4-c79a-4398-bb71-9ce39f4f43bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643812869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.3643812869
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.1013905169
Short name T503
Test name
Test status
Simulation time 18490159 ps
CPU time 0.76 seconds
Started Aug 07 06:20:03 PM PDT 24
Finished Aug 07 06:20:04 PM PDT 24
Peak memory 205912 kb
Host smart-d6269333-fd47-41e0-92ba-85d1226cde89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013905169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.1
013905169
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.1694004111
Short name T660
Test name
Test status
Simulation time 1892199611 ps
CPU time 8.94 seconds
Started Aug 07 06:20:05 PM PDT 24
Finished Aug 07 06:20:14 PM PDT 24
Peak memory 225288 kb
Host smart-00ec1c7b-3814-4b9a-b91a-d37b06a106b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694004111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.1694004111
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.3681236538
Short name T24
Test name
Test status
Simulation time 51988556 ps
CPU time 0.78 seconds
Started Aug 07 06:20:01 PM PDT 24
Finished Aug 07 06:20:02 PM PDT 24
Peak memory 207384 kb
Host smart-239754d5-3429-444f-8b87-a393d47fa2f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681236538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.3681236538
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.593217548
Short name T209
Test name
Test status
Simulation time 21001053423 ps
CPU time 100.53 seconds
Started Aug 07 06:19:58 PM PDT 24
Finished Aug 07 06:21:39 PM PDT 24
Peak memory 249868 kb
Host smart-7aa18a0b-a4c6-40b3-97d9-29616f1fa468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593217548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.593217548
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.1099546587
Short name T33
Test name
Test status
Simulation time 15835548943 ps
CPU time 160.87 seconds
Started Aug 07 06:19:55 PM PDT 24
Finished Aug 07 06:22:36 PM PDT 24
Peak memory 256876 kb
Host smart-c34ea487-3f5d-4507-a8b0-a3a9ead689d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099546587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.1099546587
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.3460581750
Short name T629
Test name
Test status
Simulation time 6331056116 ps
CPU time 80.03 seconds
Started Aug 07 06:19:55 PM PDT 24
Finished Aug 07 06:21:15 PM PDT 24
Peak memory 249972 kb
Host smart-313b0bd3-6bcb-41be-ad44-138d0177839c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460581750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.3460581750
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.2576503119
Short name T299
Test name
Test status
Simulation time 278163426 ps
CPU time 6.03 seconds
Started Aug 07 06:19:57 PM PDT 24
Finished Aug 07 06:20:03 PM PDT 24
Peak memory 234508 kb
Host smart-c4a1e51b-72cd-4426-852a-54c2a40bedf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576503119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.2576503119
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.1796871106
Short name T671
Test name
Test status
Simulation time 13087080 ps
CPU time 0.75 seconds
Started Aug 07 06:19:56 PM PDT 24
Finished Aug 07 06:19:57 PM PDT 24
Peak memory 216468 kb
Host smart-310344b5-9a37-429b-899c-698bab787de0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796871106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds
.1796871106
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/3.spi_device_intercept.29780743
Short name T828
Test name
Test status
Simulation time 671825504 ps
CPU time 8.5 seconds
Started Aug 07 06:19:56 PM PDT 24
Finished Aug 07 06:20:05 PM PDT 24
Peak memory 233444 kb
Host smart-a43af2e1-f2be-4594-b713-fc50a216f9f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29780743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.29780743
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.960133004
Short name T973
Test name
Test status
Simulation time 993499044 ps
CPU time 14.24 seconds
Started Aug 07 06:19:53 PM PDT 24
Finished Aug 07 06:20:08 PM PDT 24
Peak memory 249440 kb
Host smart-f90af7ee-f614-44c3-aec8-036e90866730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960133004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.960133004
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.3527987871
Short name T421
Test name
Test status
Simulation time 142907156 ps
CPU time 1.05 seconds
Started Aug 07 06:19:55 PM PDT 24
Finished Aug 07 06:19:56 PM PDT 24
Peak memory 217088 kb
Host smart-8c733dd9-755f-4f88-b62a-6bd8aa0a9603
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527987871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.spi_device_mem_parity.3527987871
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.3475820977
Short name T177
Test name
Test status
Simulation time 3550706616 ps
CPU time 4.65 seconds
Started Aug 07 06:19:55 PM PDT 24
Finished Aug 07 06:19:59 PM PDT 24
Peak memory 233448 kb
Host smart-6e4df947-aa07-41bb-8acc-61759ce8dea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475820977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.3475820977
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.1525475110
Short name T749
Test name
Test status
Simulation time 529121073 ps
CPU time 3.85 seconds
Started Aug 07 06:19:55 PM PDT 24
Finished Aug 07 06:19:59 PM PDT 24
Peak memory 225232 kb
Host smart-e48e7660-de46-4124-b560-54b4a3be43f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525475110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.1525475110
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.2081462769
Short name T866
Test name
Test status
Simulation time 2841371992 ps
CPU time 14.58 seconds
Started Aug 07 06:19:54 PM PDT 24
Finished Aug 07 06:20:08 PM PDT 24
Peak memory 220988 kb
Host smart-fbaefa4b-d3c3-4d70-b5fc-119a6b203f8e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2081462769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.2081462769
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.2067553806
Short name T56
Test name
Test status
Simulation time 138795011 ps
CPU time 1.04 seconds
Started Aug 07 06:20:02 PM PDT 24
Finished Aug 07 06:20:04 PM PDT 24
Peak memory 235592 kb
Host smart-b07aa8f1-7203-4dca-b7d0-fe205929f31b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067553806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.2067553806
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.4136109398
Short name T384
Test name
Test status
Simulation time 196319343 ps
CPU time 1.05 seconds
Started Aug 07 06:19:59 PM PDT 24
Finished Aug 07 06:20:00 PM PDT 24
Peak memory 207480 kb
Host smart-ad6b594c-6a5a-48ef-a80c-d924a458798a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136109398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.4136109398
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.4222264669
Short name T305
Test name
Test status
Simulation time 14799968394 ps
CPU time 20.12 seconds
Started Aug 07 06:19:54 PM PDT 24
Finished Aug 07 06:20:14 PM PDT 24
Peak memory 217040 kb
Host smart-b2641ec3-15c6-46c2-b7eb-120430557739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222264669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.4222264669
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.973681102
Short name T433
Test name
Test status
Simulation time 9817192299 ps
CPU time 7.9 seconds
Started Aug 07 06:20:05 PM PDT 24
Finished Aug 07 06:20:13 PM PDT 24
Peak memory 217140 kb
Host smart-67889529-94c8-42ef-b22a-90d8defc6197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973681102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.973681102
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.1646533047
Short name T1024
Test name
Test status
Simulation time 83658029 ps
CPU time 1.25 seconds
Started Aug 07 06:20:05 PM PDT 24
Finished Aug 07 06:20:06 PM PDT 24
Peak memory 207976 kb
Host smart-7483a50d-9384-4b95-93ea-9b938ee3a4dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646533047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.1646533047
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.3133121162
Short name T419
Test name
Test status
Simulation time 620138614 ps
CPU time 0.93 seconds
Started Aug 07 06:19:56 PM PDT 24
Finished Aug 07 06:19:57 PM PDT 24
Peak memory 207608 kb
Host smart-47ee2729-0b89-4d0d-a0b9-8e270f69f2d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133121162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.3133121162
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.2260959793
Short name T272
Test name
Test status
Simulation time 804088766 ps
CPU time 4.57 seconds
Started Aug 07 06:19:56 PM PDT 24
Finished Aug 07 06:20:00 PM PDT 24
Peak memory 233444 kb
Host smart-d05413e0-f414-4582-aa4b-274415919640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260959793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.2260959793
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.2787220228
Short name T52
Test name
Test status
Simulation time 16490851 ps
CPU time 0.71 seconds
Started Aug 07 06:21:30 PM PDT 24
Finished Aug 07 06:21:31 PM PDT 24
Peak memory 205848 kb
Host smart-4dbaea61-163f-4b90-9a11-90542e0e3108
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787220228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
2787220228
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.434883241
Short name T727
Test name
Test status
Simulation time 826866870 ps
CPU time 2.6 seconds
Started Aug 07 06:21:27 PM PDT 24
Finished Aug 07 06:21:29 PM PDT 24
Peak memory 225132 kb
Host smart-9cbf090c-05fa-45c9-a887-4a062c5d69c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434883241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.434883241
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.1909664786
Short name T330
Test name
Test status
Simulation time 15041204 ps
CPU time 0.77 seconds
Started Aug 07 06:21:26 PM PDT 24
Finished Aug 07 06:21:27 PM PDT 24
Peak memory 206040 kb
Host smart-8418373f-1ad0-4c11-8031-03bb6dfd9c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909664786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.1909664786
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.3332836798
Short name T236
Test name
Test status
Simulation time 69429170808 ps
CPU time 162.08 seconds
Started Aug 07 06:21:29 PM PDT 24
Finished Aug 07 06:24:11 PM PDT 24
Peak memory 249912 kb
Host smart-30acdf21-86cc-4599-bee0-955c6b06d60e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332836798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.3332836798
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.1589331388
Short name T905
Test name
Test status
Simulation time 15921757354 ps
CPU time 167.3 seconds
Started Aug 07 06:21:33 PM PDT 24
Finished Aug 07 06:24:21 PM PDT 24
Peak memory 253932 kb
Host smart-aa5187d7-2007-42a5-b03a-51829bd8c2d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589331388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.1589331388
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.718046496
Short name T735
Test name
Test status
Simulation time 1154119791 ps
CPU time 6.52 seconds
Started Aug 07 06:21:27 PM PDT 24
Finished Aug 07 06:21:34 PM PDT 24
Peak memory 233592 kb
Host smart-6bdb7704-1346-4492-ac29-9df0a7b4186c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718046496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.718046496
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.2333645492
Short name T953
Test name
Test status
Simulation time 56420601356 ps
CPU time 382.38 seconds
Started Aug 07 06:21:27 PM PDT 24
Finished Aug 07 06:27:49 PM PDT 24
Peak memory 252964 kb
Host smart-5f7eb8b0-93dc-4f4c-9312-6da074a6a49c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333645492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmd
s.2333645492
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/30.spi_device_intercept.1883973141
Short name T509
Test name
Test status
Simulation time 1213567332 ps
CPU time 13.45 seconds
Started Aug 07 06:21:25 PM PDT 24
Finished Aug 07 06:21:39 PM PDT 24
Peak memory 233392 kb
Host smart-e6f70773-4224-4ee4-9a19-43fbb5ec16c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883973141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.1883973141
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.924828749
Short name T6
Test name
Test status
Simulation time 6555023696 ps
CPU time 40.44 seconds
Started Aug 07 06:21:25 PM PDT 24
Finished Aug 07 06:22:05 PM PDT 24
Peak memory 233516 kb
Host smart-84d6ab72-c935-438b-b109-437329ca267a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924828749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.924828749
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.2616083852
Short name T132
Test name
Test status
Simulation time 3578883225 ps
CPU time 9.79 seconds
Started Aug 07 06:21:28 PM PDT 24
Finished Aug 07 06:21:38 PM PDT 24
Peak memory 225256 kb
Host smart-1ff71613-c960-4fdd-b297-b5825c40647d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616083852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.2616083852
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.1798737272
Short name T739
Test name
Test status
Simulation time 1285769262 ps
CPU time 6.66 seconds
Started Aug 07 06:21:26 PM PDT 24
Finished Aug 07 06:21:33 PM PDT 24
Peak memory 225196 kb
Host smart-b0f174ff-39ca-4c26-920e-53f9b27635e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798737272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.1798737272
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.4284388303
Short name T751
Test name
Test status
Simulation time 2402750308 ps
CPU time 8.1 seconds
Started Aug 07 06:21:27 PM PDT 24
Finished Aug 07 06:21:35 PM PDT 24
Peak memory 223440 kb
Host smart-27defce6-6868-4b98-90d3-73f03d4ea657
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4284388303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.4284388303
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.506183223
Short name T16
Test name
Test status
Simulation time 190997813 ps
CPU time 1.04 seconds
Started Aug 07 06:21:31 PM PDT 24
Finished Aug 07 06:21:32 PM PDT 24
Peak memory 206236 kb
Host smart-b3bedf2f-ec3d-4916-b582-ba9d396f898d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506183223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stres
s_all.506183223
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.2430422495
Short name T746
Test name
Test status
Simulation time 15172155223 ps
CPU time 38.45 seconds
Started Aug 07 06:21:27 PM PDT 24
Finished Aug 07 06:22:05 PM PDT 24
Peak memory 217080 kb
Host smart-c99863f2-9b99-4117-a301-0e3d44b2fa15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430422495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.2430422495
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.863041585
Short name T677
Test name
Test status
Simulation time 5703048675 ps
CPU time 3.44 seconds
Started Aug 07 06:21:27 PM PDT 24
Finished Aug 07 06:21:31 PM PDT 24
Peak memory 217076 kb
Host smart-1e8d0163-7118-4a3a-9015-46be9f097901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863041585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.863041585
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.487925257
Short name T359
Test name
Test status
Simulation time 36800532 ps
CPU time 0.74 seconds
Started Aug 07 06:21:27 PM PDT 24
Finished Aug 07 06:21:28 PM PDT 24
Peak memory 206484 kb
Host smart-54c31634-958f-4420-a610-f501239b4b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487925257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.487925257
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.2228232838
Short name T350
Test name
Test status
Simulation time 1537039524 ps
CPU time 1.1 seconds
Started Aug 07 06:21:27 PM PDT 24
Finished Aug 07 06:21:28 PM PDT 24
Peak memory 207592 kb
Host smart-eb7ce6ba-7225-445f-92bb-54e10de8fbe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228232838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.2228232838
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.186006611
Short name T863
Test name
Test status
Simulation time 3114773061 ps
CPU time 7.27 seconds
Started Aug 07 06:21:25 PM PDT 24
Finished Aug 07 06:21:32 PM PDT 24
Peak memory 233492 kb
Host smart-45cdb94a-0205-4828-aacd-051e082ba360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186006611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.186006611
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.2721459038
Short name T416
Test name
Test status
Simulation time 30365676 ps
CPU time 0.71 seconds
Started Aug 07 06:21:32 PM PDT 24
Finished Aug 07 06:21:33 PM PDT 24
Peak memory 205328 kb
Host smart-a68b57b0-1b4b-456a-b2ae-94e38b14e994
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721459038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
2721459038
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.3848639285
Short name T625
Test name
Test status
Simulation time 375539085 ps
CPU time 5.32 seconds
Started Aug 07 06:21:36 PM PDT 24
Finished Aug 07 06:21:41 PM PDT 24
Peak memory 225228 kb
Host smart-b60f6d67-8f37-46b0-b99d-7ebbc109c8b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848639285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.3848639285
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.1502728943
Short name T375
Test name
Test status
Simulation time 19753337 ps
CPU time 0.78 seconds
Started Aug 07 06:21:32 PM PDT 24
Finished Aug 07 06:21:33 PM PDT 24
Peak memory 207056 kb
Host smart-57c50831-83ad-4e8a-9b26-0763629ea1fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502728943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.1502728943
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.4029386541
Short name T928
Test name
Test status
Simulation time 3126234545 ps
CPU time 53.51 seconds
Started Aug 07 06:21:34 PM PDT 24
Finished Aug 07 06:22:28 PM PDT 24
Peak memory 253156 kb
Host smart-8e4fb5e4-1b32-41cc-b1b5-c716f75fe14c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029386541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.4029386541
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.4012581774
Short name T594
Test name
Test status
Simulation time 23071918424 ps
CPU time 219.18 seconds
Started Aug 07 06:21:30 PM PDT 24
Finished Aug 07 06:25:10 PM PDT 24
Peak memory 249968 kb
Host smart-cc8b5617-6809-47d3-b022-715cbd1a0bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012581774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.4012581774
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.1706784026
Short name T1006
Test name
Test status
Simulation time 50574184015 ps
CPU time 98.12 seconds
Started Aug 07 06:21:33 PM PDT 24
Finished Aug 07 06:23:11 PM PDT 24
Peak memory 231980 kb
Host smart-41522b0d-4575-4698-9742-1d2dc1f688d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706784026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.1706784026
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.3997486033
Short name T867
Test name
Test status
Simulation time 1863969071 ps
CPU time 12.49 seconds
Started Aug 07 06:21:33 PM PDT 24
Finished Aug 07 06:21:46 PM PDT 24
Peak memory 233460 kb
Host smart-d340f1cf-4b3b-4137-9085-50080d0b7422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997486033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.3997486033
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.741019250
Short name T606
Test name
Test status
Simulation time 2828085968 ps
CPU time 19.89 seconds
Started Aug 07 06:21:41 PM PDT 24
Finished Aug 07 06:22:01 PM PDT 24
Peak memory 241728 kb
Host smart-3bccb773-e902-452a-98e4-957cfcf310ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741019250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmds
.741019250
Directory /workspace/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/31.spi_device_intercept.1148963240
Short name T559
Test name
Test status
Simulation time 4544860303 ps
CPU time 11.83 seconds
Started Aug 07 06:21:33 PM PDT 24
Finished Aug 07 06:21:45 PM PDT 24
Peak memory 225272 kb
Host smart-2939fda8-b340-4fff-9425-1b7f4f15b502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148963240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.1148963240
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.3659449114
Short name T2
Test name
Test status
Simulation time 449166130 ps
CPU time 6.87 seconds
Started Aug 07 06:21:35 PM PDT 24
Finished Aug 07 06:21:42 PM PDT 24
Peak memory 239936 kb
Host smart-27a69127-3385-4b18-b144-6441db9be87d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659449114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.3659449114
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.369213479
Short name T370
Test name
Test status
Simulation time 5139228712 ps
CPU time 13.07 seconds
Started Aug 07 06:21:34 PM PDT 24
Finished Aug 07 06:21:47 PM PDT 24
Peak memory 233664 kb
Host smart-1b2e4c7d-fce4-4d26-897c-972ddb739998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369213479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swap
.369213479
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.1655335912
Short name T675
Test name
Test status
Simulation time 1015395829 ps
CPU time 5.93 seconds
Started Aug 07 06:21:34 PM PDT 24
Finished Aug 07 06:21:40 PM PDT 24
Peak memory 233432 kb
Host smart-fb77a2c3-da26-4d3b-bc58-c0ac07861746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655335912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.1655335912
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.1440495963
Short name T791
Test name
Test status
Simulation time 994553814 ps
CPU time 3.59 seconds
Started Aug 07 06:21:31 PM PDT 24
Finished Aug 07 06:21:35 PM PDT 24
Peak memory 223176 kb
Host smart-2a01d2e2-caf2-40db-9177-be1b282d8ec6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1440495963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.1440495963
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.1590428336
Short name T992
Test name
Test status
Simulation time 709479696 ps
CPU time 3.05 seconds
Started Aug 07 06:21:31 PM PDT 24
Finished Aug 07 06:21:34 PM PDT 24
Peak memory 216932 kb
Host smart-f2b169fd-a38b-47d5-b8ae-c74085861760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590428336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.1590428336
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.1974873637
Short name T634
Test name
Test status
Simulation time 7678975042 ps
CPU time 22 seconds
Started Aug 07 06:21:34 PM PDT 24
Finished Aug 07 06:21:56 PM PDT 24
Peak memory 217012 kb
Host smart-fcc12f49-2538-4f25-9360-2773f0499b75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974873637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.1974873637
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.3976923332
Short name T886
Test name
Test status
Simulation time 78832497 ps
CPU time 0.98 seconds
Started Aug 07 06:21:32 PM PDT 24
Finished Aug 07 06:21:33 PM PDT 24
Peak memory 207932 kb
Host smart-072b8666-814d-4047-b0b8-f10b9602fa35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976923332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.3976923332
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.3847521801
Short name T551
Test name
Test status
Simulation time 29683270 ps
CPU time 0.76 seconds
Started Aug 07 06:21:31 PM PDT 24
Finished Aug 07 06:21:32 PM PDT 24
Peak memory 206596 kb
Host smart-a5510597-179c-435e-bcfe-0a3c6a9e6899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847521801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.3847521801
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.3540715846
Short name T941
Test name
Test status
Simulation time 2515920280 ps
CPU time 7.1 seconds
Started Aug 07 06:21:33 PM PDT 24
Finished Aug 07 06:21:40 PM PDT 24
Peak memory 233540 kb
Host smart-0482d096-d944-4819-bd73-5a52597c0489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540715846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.3540715846
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.4144668298
Short name T347
Test name
Test status
Simulation time 141838300 ps
CPU time 0.75 seconds
Started Aug 07 06:21:38 PM PDT 24
Finished Aug 07 06:21:39 PM PDT 24
Peak memory 205872 kb
Host smart-4271435a-521f-4d8d-b984-4ccc76ef0a03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144668298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
4144668298
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.445956012
Short name T721
Test name
Test status
Simulation time 345166577 ps
CPU time 3.65 seconds
Started Aug 07 06:21:35 PM PDT 24
Finished Aug 07 06:21:39 PM PDT 24
Peak memory 233468 kb
Host smart-75bc0a15-5a30-4f23-bc89-9bf2f41b612d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445956012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.445956012
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.2514047628
Short name T368
Test name
Test status
Simulation time 49036743 ps
CPU time 0.79 seconds
Started Aug 07 06:21:35 PM PDT 24
Finished Aug 07 06:21:36 PM PDT 24
Peak memory 206400 kb
Host smart-b0e4ce25-2135-4c0b-81f0-0c7d3a4f75b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514047628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.2514047628
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.3979924230
Short name T124
Test name
Test status
Simulation time 24350224939 ps
CPU time 42.98 seconds
Started Aug 07 06:21:35 PM PDT 24
Finished Aug 07 06:22:18 PM PDT 24
Peak memory 241704 kb
Host smart-45a19df2-73ba-4ed9-9f11-63a58288180f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979924230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.3979924230
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.945132049
Short name T270
Test name
Test status
Simulation time 10962660465 ps
CPU time 156.64 seconds
Started Aug 07 06:21:38 PM PDT 24
Finished Aug 07 06:24:15 PM PDT 24
Peak memory 268788 kb
Host smart-2450ec2f-a261-4c95-bba6-11c910e5da9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945132049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.945132049
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.836351968
Short name T165
Test name
Test status
Simulation time 30905901299 ps
CPU time 189.52 seconds
Started Aug 07 06:21:34 PM PDT 24
Finished Aug 07 06:24:44 PM PDT 24
Peak memory 257808 kb
Host smart-c0def4c7-15c0-4ed2-b41c-af50c323cde2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836351968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idle
.836351968
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.463162926
Short name T40
Test name
Test status
Simulation time 359697199 ps
CPU time 5.06 seconds
Started Aug 07 06:21:39 PM PDT 24
Finished Aug 07 06:21:44 PM PDT 24
Peak memory 225240 kb
Host smart-e8a47866-c9d4-450a-af18-c5a8ab55aa76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463162926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.463162926
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.36753207
Short name T388
Test name
Test status
Simulation time 11727871648 ps
CPU time 93.27 seconds
Started Aug 07 06:21:38 PM PDT 24
Finished Aug 07 06:23:11 PM PDT 24
Peak memory 236756 kb
Host smart-85a453ab-3415-4158-b381-51e0c45d7188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36753207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmds.36753207
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/32.spi_device_intercept.807135493
Short name T690
Test name
Test status
Simulation time 541838394 ps
CPU time 9.47 seconds
Started Aug 07 06:21:32 PM PDT 24
Finished Aug 07 06:21:42 PM PDT 24
Peak memory 225196 kb
Host smart-17f903eb-3832-442c-b72a-720bb3c05528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807135493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.807135493
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.318787878
Short name T448
Test name
Test status
Simulation time 565031501 ps
CPU time 4.72 seconds
Started Aug 07 06:21:35 PM PDT 24
Finished Aug 07 06:21:40 PM PDT 24
Peak memory 225304 kb
Host smart-1d780fdc-2a34-4732-8a64-5ab35684bfab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318787878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.318787878
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.1385077062
Short name T196
Test name
Test status
Simulation time 4214724055 ps
CPU time 11.98 seconds
Started Aug 07 06:21:33 PM PDT 24
Finished Aug 07 06:21:45 PM PDT 24
Peak memory 233476 kb
Host smart-b75d0615-e496-4d78-83b7-9f524d31879e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385077062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.1385077062
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.2917555031
Short name T558
Test name
Test status
Simulation time 3148753480 ps
CPU time 11.64 seconds
Started Aug 07 06:21:31 PM PDT 24
Finished Aug 07 06:21:43 PM PDT 24
Peak memory 228920 kb
Host smart-0a58dcdc-3956-495e-ab6d-5c202a1b64ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917555031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.2917555031
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.1018359710
Short name T1016
Test name
Test status
Simulation time 270303594 ps
CPU time 3.27 seconds
Started Aug 07 06:21:39 PM PDT 24
Finished Aug 07 06:21:42 PM PDT 24
Peak memory 221308 kb
Host smart-716b3866-5d08-4bd9-a5bf-7d4212a74671
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1018359710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.1018359710
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.3907616203
Short name T730
Test name
Test status
Simulation time 8651581356 ps
CPU time 16.57 seconds
Started Aug 07 06:21:31 PM PDT 24
Finished Aug 07 06:21:48 PM PDT 24
Peak memory 217384 kb
Host smart-77d93b5a-0e57-490a-b899-dff9dd3478d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907616203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.3907616203
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.2342324128
Short name T860
Test name
Test status
Simulation time 1314087126 ps
CPU time 2.7 seconds
Started Aug 07 06:21:32 PM PDT 24
Finished Aug 07 06:21:35 PM PDT 24
Peak memory 216792 kb
Host smart-03fd8dfd-f387-4e7e-a9c3-9e207b12946d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342324128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.2342324128
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.815301606
Short name T314
Test name
Test status
Simulation time 215201536 ps
CPU time 1.3 seconds
Started Aug 07 06:21:31 PM PDT 24
Finished Aug 07 06:21:32 PM PDT 24
Peak memory 216876 kb
Host smart-cb7f66d7-1d2d-4d27-ac48-49bb87bb04d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815301606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.815301606
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.3188504100
Short name T883
Test name
Test status
Simulation time 249102134 ps
CPU time 0.75 seconds
Started Aug 07 06:21:41 PM PDT 24
Finished Aug 07 06:21:42 PM PDT 24
Peak memory 206584 kb
Host smart-f94d9908-b9cd-4fa1-b7db-08ce66f0d1bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188504100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.3188504100
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.1310035752
Short name T155
Test name
Test status
Simulation time 1364027738 ps
CPU time 6.18 seconds
Started Aug 07 06:21:36 PM PDT 24
Finished Aug 07 06:21:42 PM PDT 24
Peak memory 233432 kb
Host smart-d9e8d431-0440-4084-86cd-f5a5bf5c71e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310035752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.1310035752
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.1802156652
Short name T907
Test name
Test status
Simulation time 10680449 ps
CPU time 0.7 seconds
Started Aug 07 06:21:41 PM PDT 24
Finished Aug 07 06:21:42 PM PDT 24
Peak memory 205256 kb
Host smart-2ee42cac-9b1a-40a3-8795-42b7d344fbd6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802156652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
1802156652
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.1164493266
Short name T162
Test name
Test status
Simulation time 2009841282 ps
CPU time 3.76 seconds
Started Aug 07 06:21:37 PM PDT 24
Finished Aug 07 06:21:41 PM PDT 24
Peak memory 233432 kb
Host smart-0bcb4f2c-2f11-47d7-a2b9-980a07bf83f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164493266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.1164493266
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.1650940101
Short name T771
Test name
Test status
Simulation time 51178501 ps
CPU time 0.79 seconds
Started Aug 07 06:21:36 PM PDT 24
Finished Aug 07 06:21:37 PM PDT 24
Peak memory 207056 kb
Host smart-5b08020f-9eed-48ac-8371-a1934a49ef3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650940101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.1650940101
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.2653783732
Short name T152
Test name
Test status
Simulation time 1064120867 ps
CPU time 23.57 seconds
Started Aug 07 06:21:39 PM PDT 24
Finished Aug 07 06:22:03 PM PDT 24
Peak memory 254644 kb
Host smart-ee0d2640-bd0c-4503-91be-0e1461ffd33f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653783732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.2653783732
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.2840099557
Short name T307
Test name
Test status
Simulation time 190544936007 ps
CPU time 90.35 seconds
Started Aug 07 06:21:40 PM PDT 24
Finished Aug 07 06:23:10 PM PDT 24
Peak memory 249956 kb
Host smart-c2cc4e41-98c6-47b2-88ce-255f739b301e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840099557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.2840099557
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.827631488
Short name T877
Test name
Test status
Simulation time 19741813563 ps
CPU time 200.31 seconds
Started Aug 07 06:21:42 PM PDT 24
Finished Aug 07 06:25:02 PM PDT 24
Peak memory 251884 kb
Host smart-346cb02c-8f5f-4d18-b105-7cf4e8f601d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827631488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idle
.827631488
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.2558569720
Short name T807
Test name
Test status
Simulation time 445209822 ps
CPU time 3.85 seconds
Started Aug 07 06:21:38 PM PDT 24
Finished Aug 07 06:21:42 PM PDT 24
Peak memory 233440 kb
Host smart-fa4c534c-72b1-4eb9-a17d-535aa7fe9535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558569720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.2558569720
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_intercept.689608459
Short name T276
Test name
Test status
Simulation time 655861433 ps
CPU time 3.78 seconds
Started Aug 07 06:21:37 PM PDT 24
Finished Aug 07 06:21:41 PM PDT 24
Peak memory 225220 kb
Host smart-270b94f9-2980-4714-acbf-285e26ce52f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689608459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.689608459
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.1909961514
Short name T500
Test name
Test status
Simulation time 739177297 ps
CPU time 11.11 seconds
Started Aug 07 06:21:41 PM PDT 24
Finished Aug 07 06:21:52 PM PDT 24
Peak memory 225280 kb
Host smart-6703bffa-ed19-4c47-97b5-55e6ddfa5f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909961514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.1909961514
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.3720247048
Short name T438
Test name
Test status
Simulation time 1402922625 ps
CPU time 3.64 seconds
Started Aug 07 06:21:46 PM PDT 24
Finished Aug 07 06:21:50 PM PDT 24
Peak memory 225256 kb
Host smart-2e8db762-d9ea-4c02-a600-a410ebbb6488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720247048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.3720247048
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.4023253917
Short name T871
Test name
Test status
Simulation time 926715854 ps
CPU time 4.74 seconds
Started Aug 07 06:21:35 PM PDT 24
Finished Aug 07 06:21:40 PM PDT 24
Peak memory 241132 kb
Host smart-856e07f2-841f-4b7d-bcae-980d78231120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023253917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.4023253917
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.2801969470
Short name T796
Test name
Test status
Simulation time 1123956413 ps
CPU time 3.78 seconds
Started Aug 07 06:21:39 PM PDT 24
Finished Aug 07 06:21:43 PM PDT 24
Peak memory 221764 kb
Host smart-208d9a2d-ad1d-40f2-bdab-2ed80ad32480
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2801969470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.2801969470
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.635598054
Short name T602
Test name
Test status
Simulation time 31592935685 ps
CPU time 257.52 seconds
Started Aug 07 06:21:37 PM PDT 24
Finished Aug 07 06:25:55 PM PDT 24
Peak memory 255092 kb
Host smart-5dd860e2-b4b3-4e1f-bf73-e775f14e87c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635598054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stres
s_all.635598054
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.265438724
Short name T881
Test name
Test status
Simulation time 3206278223 ps
CPU time 12.28 seconds
Started Aug 07 06:21:38 PM PDT 24
Finished Aug 07 06:21:50 PM PDT 24
Peak memory 217380 kb
Host smart-25fd7098-96e9-400d-90a4-67ae0e0db246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265438724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.265438724
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.3892586173
Short name T785
Test name
Test status
Simulation time 5792398081 ps
CPU time 18.34 seconds
Started Aug 07 06:21:40 PM PDT 24
Finished Aug 07 06:21:58 PM PDT 24
Peak memory 217072 kb
Host smart-f4752488-3535-45e6-bdeb-0402f742fac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892586173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.3892586173
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.1164542921
Short name T879
Test name
Test status
Simulation time 27196241 ps
CPU time 1.02 seconds
Started Aug 07 06:21:36 PM PDT 24
Finished Aug 07 06:21:37 PM PDT 24
Peak memory 208088 kb
Host smart-4f88c5d9-6c3e-4ed4-a61e-10a8a4a746db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164542921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.1164542921
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.311486943
Short name T1029
Test name
Test status
Simulation time 76834624 ps
CPU time 0.84 seconds
Started Aug 07 06:21:38 PM PDT 24
Finished Aug 07 06:21:38 PM PDT 24
Peak memory 206588 kb
Host smart-64c6bd04-a861-4be0-a31e-6ced03d47dfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311486943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.311486943
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.612404362
Short name T838
Test name
Test status
Simulation time 324377081 ps
CPU time 4.52 seconds
Started Aug 07 06:21:39 PM PDT 24
Finished Aug 07 06:21:43 PM PDT 24
Peak memory 233476 kb
Host smart-92e49ab1-2ecc-48ef-af60-0b4e65492196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612404362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.612404362
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.3804509576
Short name T386
Test name
Test status
Simulation time 26243146 ps
CPU time 0.76 seconds
Started Aug 07 06:21:49 PM PDT 24
Finished Aug 07 06:21:50 PM PDT 24
Peak memory 205296 kb
Host smart-189dab40-df12-4d99-a7b3-230a7dcf65e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804509576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
3804509576
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.3313905023
Short name T283
Test name
Test status
Simulation time 1148796106 ps
CPU time 2.7 seconds
Started Aug 07 06:21:49 PM PDT 24
Finished Aug 07 06:21:52 PM PDT 24
Peak memory 225204 kb
Host smart-04417980-cb29-44df-afae-4a812e7b5d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313905023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.3313905023
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.2244989
Short name T584
Test name
Test status
Simulation time 22481536 ps
CPU time 0.81 seconds
Started Aug 07 06:21:42 PM PDT 24
Finished Aug 07 06:21:43 PM PDT 24
Peak memory 207056 kb
Host smart-ffd5d19b-a14a-4dc2-aecf-4fe72e8f95f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.2244989
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.4149545509
Short name T476
Test name
Test status
Simulation time 3575983720 ps
CPU time 38.28 seconds
Started Aug 07 06:21:42 PM PDT 24
Finished Aug 07 06:22:20 PM PDT 24
Peak memory 249920 kb
Host smart-8c9464de-8ae3-4060-8236-415f76657ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149545509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.4149545509
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.1468199396
Short name T170
Test name
Test status
Simulation time 83864165310 ps
CPU time 224.51 seconds
Started Aug 07 06:21:43 PM PDT 24
Finished Aug 07 06:25:28 PM PDT 24
Peak memory 249968 kb
Host smart-fb188e93-a545-42a3-8a64-1ab0b770ebe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468199396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.1468199396
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.2140620987
Short name T668
Test name
Test status
Simulation time 309977703 ps
CPU time 6.91 seconds
Started Aug 07 06:21:42 PM PDT 24
Finished Aug 07 06:21:49 PM PDT 24
Peak memory 225272 kb
Host smart-a3b70726-5376-4e30-ad1a-236647599a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140620987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.2140620987
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.2361978084
Short name T221
Test name
Test status
Simulation time 1978547436 ps
CPU time 26.45 seconds
Started Aug 07 06:21:51 PM PDT 24
Finished Aug 07 06:22:18 PM PDT 24
Peak memory 241680 kb
Host smart-db6cb15a-8ca4-4e17-ab7e-f17f665658ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361978084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmd
s.2361978084
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/34.spi_device_intercept.281423309
Short name T644
Test name
Test status
Simulation time 3575581759 ps
CPU time 4.03 seconds
Started Aug 07 06:21:43 PM PDT 24
Finished Aug 07 06:21:47 PM PDT 24
Peak memory 225268 kb
Host smart-8738e947-7cbf-4545-b987-dacee3d07aa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281423309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.281423309
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.3230282460
Short name T981
Test name
Test status
Simulation time 4553440291 ps
CPU time 7.64 seconds
Started Aug 07 06:21:41 PM PDT 24
Finished Aug 07 06:21:49 PM PDT 24
Peak memory 225300 kb
Host smart-ad9b48de-570e-4229-a97f-f1008f8f2e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230282460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.3230282460
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.1960872447
Short name T670
Test name
Test status
Simulation time 5166900997 ps
CPU time 8.82 seconds
Started Aug 07 06:21:42 PM PDT 24
Finished Aug 07 06:21:51 PM PDT 24
Peak memory 241416 kb
Host smart-0b5761ca-945a-49d4-8a08-839d1e6b3551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960872447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.1960872447
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.844755578
Short name T720
Test name
Test status
Simulation time 4700406608 ps
CPU time 15.15 seconds
Started Aug 07 06:21:42 PM PDT 24
Finished Aug 07 06:21:57 PM PDT 24
Peak memory 233460 kb
Host smart-edfa7237-b4ca-4cb8-b2cc-d9b8adfd117a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844755578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.844755578
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.3373372334
Short name T568
Test name
Test status
Simulation time 4327360383 ps
CPU time 15.91 seconds
Started Aug 07 06:21:51 PM PDT 24
Finished Aug 07 06:22:07 PM PDT 24
Peak memory 219972 kb
Host smart-33d2de53-6339-44c3-9eb3-7139fb141dd1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3373372334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.3373372334
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.1662341076
Short name T1009
Test name
Test status
Simulation time 172454297325 ps
CPU time 441.93 seconds
Started Aug 07 06:21:51 PM PDT 24
Finished Aug 07 06:29:13 PM PDT 24
Peak memory 255400 kb
Host smart-7231bfd4-e4b3-44ed-862b-37a65b59f540
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662341076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.1662341076
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.427360395
Short name T315
Test name
Test status
Simulation time 3387568435 ps
CPU time 14.91 seconds
Started Aug 07 06:21:35 PM PDT 24
Finished Aug 07 06:21:50 PM PDT 24
Peak memory 217168 kb
Host smart-a386e42e-a375-4f33-8c7e-92c68fd64aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427360395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.427360395
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.2812671745
Short name T738
Test name
Test status
Simulation time 8608051776 ps
CPU time 24.79 seconds
Started Aug 07 06:21:39 PM PDT 24
Finished Aug 07 06:22:04 PM PDT 24
Peak memory 217012 kb
Host smart-4c8480ee-fd43-43c2-9e48-38d57a75ca5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812671745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.2812671745
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.1407837068
Short name T11
Test name
Test status
Simulation time 47983590 ps
CPU time 1.19 seconds
Started Aug 07 06:21:40 PM PDT 24
Finished Aug 07 06:21:42 PM PDT 24
Peak memory 208572 kb
Host smart-bafea408-f68a-40ed-ab27-e953e5d41921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407837068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.1407837068
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.422483156
Short name T379
Test name
Test status
Simulation time 60570903 ps
CPU time 0.79 seconds
Started Aug 07 06:21:40 PM PDT 24
Finished Aug 07 06:21:41 PM PDT 24
Peak memory 206584 kb
Host smart-98e51626-afd5-4452-a8b2-7e93fd8ee574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422483156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.422483156
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.1477662109
Short name T396
Test name
Test status
Simulation time 551348857 ps
CPU time 3.83 seconds
Started Aug 07 06:21:50 PM PDT 24
Finished Aug 07 06:21:54 PM PDT 24
Peak memory 233440 kb
Host smart-14e47ae1-3b7e-4922-b886-e374f33abee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477662109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.1477662109
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.316403050
Short name T833
Test name
Test status
Simulation time 40893045 ps
CPU time 0.76 seconds
Started Aug 07 06:21:51 PM PDT 24
Finished Aug 07 06:21:52 PM PDT 24
Peak memory 205848 kb
Host smart-f767ac9b-fcdc-46d1-914c-32fed487485d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316403050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.316403050
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.1188484594
Short name T341
Test name
Test status
Simulation time 487764479 ps
CPU time 5.74 seconds
Started Aug 07 06:21:52 PM PDT 24
Finished Aug 07 06:21:58 PM PDT 24
Peak memory 233464 kb
Host smart-1c68d835-4e3c-4084-acda-46885ef33e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188484594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.1188484594
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.292575113
Short name T475
Test name
Test status
Simulation time 19232308 ps
CPU time 0.78 seconds
Started Aug 07 06:21:52 PM PDT 24
Finished Aug 07 06:21:53 PM PDT 24
Peak memory 206036 kb
Host smart-f9b881b5-3bc8-4c4a-b88b-a9894d27de83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292575113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.292575113
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.986997325
Short name T971
Test name
Test status
Simulation time 13500746423 ps
CPU time 60.15 seconds
Started Aug 07 06:21:51 PM PDT 24
Finished Aug 07 06:22:51 PM PDT 24
Peak memory 251668 kb
Host smart-860c5431-7167-437f-a403-41afcf4617c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986997325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.986997325
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.3190404615
Short name T835
Test name
Test status
Simulation time 1913451824 ps
CPU time 47.03 seconds
Started Aug 07 06:21:53 PM PDT 24
Finished Aug 07 06:22:40 PM PDT 24
Peak memory 250908 kb
Host smart-0c0b20f2-344a-481c-8fbe-686431a98392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190404615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.3190404615
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.2593247589
Short name T692
Test name
Test status
Simulation time 2486970134 ps
CPU time 42.32 seconds
Started Aug 07 06:21:52 PM PDT 24
Finished Aug 07 06:22:35 PM PDT 24
Peak memory 241700 kb
Host smart-f0bd447e-4686-4a68-88e9-9fbe3f966552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593247589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.2593247589
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.3185375507
Short name T62
Test name
Test status
Simulation time 112817504 ps
CPU time 4.11 seconds
Started Aug 07 06:21:52 PM PDT 24
Finished Aug 07 06:21:56 PM PDT 24
Peak memory 233632 kb
Host smart-61864079-89ee-4d03-b7bd-a579b12db86e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185375507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmd
s.3185375507
Directory /workspace/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/35.spi_device_intercept.1991178768
Short name T680
Test name
Test status
Simulation time 16108414182 ps
CPU time 34.16 seconds
Started Aug 07 06:21:54 PM PDT 24
Finished Aug 07 06:22:28 PM PDT 24
Peak memory 225300 kb
Host smart-0f0e8049-0ae8-46bb-b3f3-e00d7d4e4940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991178768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.1991178768
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.352087658
Short name T759
Test name
Test status
Simulation time 1068757898 ps
CPU time 8.13 seconds
Started Aug 07 06:21:48 PM PDT 24
Finished Aug 07 06:21:56 PM PDT 24
Peak memory 233376 kb
Host smart-73145a7b-f8a7-49d8-818d-8c1399d26023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352087658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.352087658
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.1503227694
Short name T580
Test name
Test status
Simulation time 4368681907 ps
CPU time 12.34 seconds
Started Aug 07 06:21:50 PM PDT 24
Finished Aug 07 06:22:03 PM PDT 24
Peak memory 240500 kb
Host smart-7bdb4105-5ae8-44cf-9bb3-462ee524944c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503227694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.1503227694
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.1133294990
Short name T646
Test name
Test status
Simulation time 3706376427 ps
CPU time 4.43 seconds
Started Aug 07 06:21:42 PM PDT 24
Finished Aug 07 06:21:46 PM PDT 24
Peak memory 225252 kb
Host smart-663b537a-639c-4843-8803-d822ee317800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133294990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.1133294990
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.827535569
Short name T936
Test name
Test status
Simulation time 180368798 ps
CPU time 4.35 seconds
Started Aug 07 06:21:50 PM PDT 24
Finished Aug 07 06:21:54 PM PDT 24
Peak memory 223760 kb
Host smart-4df0a0e7-acd6-4fa1-999c-2940a4dc8855
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=827535569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dire
ct.827535569
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.3702858969
Short name T803
Test name
Test status
Simulation time 56197785 ps
CPU time 0.99 seconds
Started Aug 07 06:21:51 PM PDT 24
Finished Aug 07 06:21:52 PM PDT 24
Peak memory 207344 kb
Host smart-04d4cea1-9799-4274-b251-fd64a2a8ae60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702858969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.3702858969
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.37424227
Short name T805
Test name
Test status
Simulation time 4081342586 ps
CPU time 18.98 seconds
Started Aug 07 06:21:51 PM PDT 24
Finished Aug 07 06:22:10 PM PDT 24
Peak memory 220600 kb
Host smart-b19641b5-4dd0-4d62-9f1c-3d6deaccc4ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37424227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.37424227
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.965556955
Short name T794
Test name
Test status
Simulation time 13768083 ps
CPU time 0.72 seconds
Started Aug 07 06:21:41 PM PDT 24
Finished Aug 07 06:21:42 PM PDT 24
Peak memory 206088 kb
Host smart-6a82f5ed-c414-43b3-8278-5fbddb3d2950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965556955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.965556955
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.3914258013
Short name T885
Test name
Test status
Simulation time 230456041 ps
CPU time 2.8 seconds
Started Aug 07 06:21:45 PM PDT 24
Finished Aug 07 06:21:48 PM PDT 24
Peak memory 217012 kb
Host smart-da0a094a-e6a7-482b-8f3b-4be47bd41504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914258013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.3914258013
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.4016588304
Short name T811
Test name
Test status
Simulation time 32450860 ps
CPU time 0.75 seconds
Started Aug 07 06:21:51 PM PDT 24
Finished Aug 07 06:21:51 PM PDT 24
Peak memory 206548 kb
Host smart-656b634b-10cd-4e86-96ef-7a4155c97f51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016588304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.4016588304
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.2155318296
Short name T597
Test name
Test status
Simulation time 17805142749 ps
CPU time 15.21 seconds
Started Aug 07 06:21:53 PM PDT 24
Finished Aug 07 06:22:08 PM PDT 24
Peak memory 233464 kb
Host smart-9deb2227-4b70-466a-85ec-1cdc2a3bb915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155318296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.2155318296
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.3077976811
Short name T719
Test name
Test status
Simulation time 47134985 ps
CPU time 0.71 seconds
Started Aug 07 06:21:58 PM PDT 24
Finished Aug 07 06:21:59 PM PDT 24
Peak memory 205852 kb
Host smart-9f5e9837-f94d-4043-a1ae-0be04bc0399c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077976811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
3077976811
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.4032745934
Short name T713
Test name
Test status
Simulation time 463839884 ps
CPU time 2.65 seconds
Started Aug 07 06:21:51 PM PDT 24
Finished Aug 07 06:21:54 PM PDT 24
Peak memory 225236 kb
Host smart-71138cbf-6180-4ab4-9cc5-6142c4ad807c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032745934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.4032745934
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.2251821395
Short name T430
Test name
Test status
Simulation time 44901955 ps
CPU time 0.74 seconds
Started Aug 07 06:21:51 PM PDT 24
Finished Aug 07 06:21:52 PM PDT 24
Peak memory 207360 kb
Host smart-78f58706-5b11-423a-8471-cc6941f2db35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251821395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.2251821395
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.2984633887
Short name T1022
Test name
Test status
Simulation time 14036308816 ps
CPU time 96.58 seconds
Started Aug 07 06:21:51 PM PDT 24
Finished Aug 07 06:23:28 PM PDT 24
Peak memory 252088 kb
Host smart-e0cdfd57-34ec-4cd3-a039-5e92dfce803d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984633887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.2984633887
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.125409025
Short name T545
Test name
Test status
Simulation time 9307921723 ps
CPU time 70.22 seconds
Started Aug 07 06:21:55 PM PDT 24
Finished Aug 07 06:23:06 PM PDT 24
Peak memory 250148 kb
Host smart-fa466603-4c66-4ee3-8cec-125c58ae8ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125409025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.125409025
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.2422156106
Short name T265
Test name
Test status
Simulation time 29737388378 ps
CPU time 275.98 seconds
Started Aug 07 06:21:55 PM PDT 24
Finished Aug 07 06:26:32 PM PDT 24
Peak memory 250140 kb
Host smart-54004b45-5f58-40d3-b3f1-a0abcc21655c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422156106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.2422156106
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.2187399855
Short name T1012
Test name
Test status
Simulation time 511377183 ps
CPU time 4.92 seconds
Started Aug 07 06:21:51 PM PDT 24
Finished Aug 07 06:21:56 PM PDT 24
Peak memory 225204 kb
Host smart-51544320-7e6e-4df8-8eb1-bdc0925a7d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187399855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.2187399855
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.3698217014
Short name T83
Test name
Test status
Simulation time 1987829945 ps
CPU time 42.13 seconds
Started Aug 07 06:21:51 PM PDT 24
Finished Aug 07 06:22:33 PM PDT 24
Peak memory 254588 kb
Host smart-79dfe2df-7fae-45cb-9876-056652d84cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698217014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmd
s.3698217014
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_intercept.3253286923
Short name T167
Test name
Test status
Simulation time 798398385 ps
CPU time 6.95 seconds
Started Aug 07 06:21:49 PM PDT 24
Finished Aug 07 06:21:56 PM PDT 24
Peak memory 233396 kb
Host smart-b1044640-4187-4042-85ee-6ea921f02594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253286923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.3253286923
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.2582017624
Short name T194
Test name
Test status
Simulation time 2140921113 ps
CPU time 18.28 seconds
Started Aug 07 06:21:51 PM PDT 24
Finished Aug 07 06:22:10 PM PDT 24
Peak memory 225212 kb
Host smart-7189fb8f-902e-4e36-9775-c249a6621295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582017624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.2582017624
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.637417167
Short name T701
Test name
Test status
Simulation time 145192029 ps
CPU time 2.23 seconds
Started Aug 07 06:21:52 PM PDT 24
Finished Aug 07 06:21:54 PM PDT 24
Peak memory 224480 kb
Host smart-28be0432-8063-4f25-b83a-38fc7b8f06a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637417167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swap
.637417167
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.3295858092
Short name T364
Test name
Test status
Simulation time 386086597 ps
CPU time 5.59 seconds
Started Aug 07 06:21:54 PM PDT 24
Finished Aug 07 06:22:00 PM PDT 24
Peak memory 233412 kb
Host smart-e2f581f4-df8e-4520-bb9c-0abe9d0fb343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295858092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.3295858092
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.3309025974
Short name T143
Test name
Test status
Simulation time 683903477 ps
CPU time 7.64 seconds
Started Aug 07 06:21:51 PM PDT 24
Finished Aug 07 06:21:59 PM PDT 24
Peak memory 222876 kb
Host smart-f23e4f5a-69e0-4c4d-b0a6-4be0521a750a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3309025974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.3309025974
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.1381550289
Short name T495
Test name
Test status
Simulation time 3012283963 ps
CPU time 15.01 seconds
Started Aug 07 06:21:51 PM PDT 24
Finished Aug 07 06:22:06 PM PDT 24
Peak memory 217140 kb
Host smart-5fdb4be7-c7e8-43fc-bfd8-63b4143b0f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381550289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.1381550289
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.1443801938
Short name T990
Test name
Test status
Simulation time 2127841092 ps
CPU time 6.28 seconds
Started Aug 07 06:21:50 PM PDT 24
Finished Aug 07 06:21:57 PM PDT 24
Peak memory 217020 kb
Host smart-7b9f5be0-fe5c-490f-a6b9-bc4bbf18d845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443801938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.1443801938
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.3717232252
Short name T498
Test name
Test status
Simulation time 107419065 ps
CPU time 1.17 seconds
Started Aug 07 06:21:52 PM PDT 24
Finished Aug 07 06:21:53 PM PDT 24
Peak memory 208548 kb
Host smart-ca4e1de7-a8fb-438d-8af7-de41358269e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717232252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.3717232252
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.3104362702
Short name T360
Test name
Test status
Simulation time 117680560 ps
CPU time 1.04 seconds
Started Aug 07 06:21:50 PM PDT 24
Finished Aug 07 06:21:51 PM PDT 24
Peak memory 207628 kb
Host smart-25f01a39-1ef8-40ba-923e-76ec23fe22ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104362702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.3104362702
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.753931800
Short name T453
Test name
Test status
Simulation time 58099755226 ps
CPU time 36.9 seconds
Started Aug 07 06:21:53 PM PDT 24
Finished Aug 07 06:22:30 PM PDT 24
Peak memory 253300 kb
Host smart-cd1ae869-f866-4bb1-b05b-b356116f7665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753931800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.753931800
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.1953590892
Short name T566
Test name
Test status
Simulation time 32442162 ps
CPU time 0.7 seconds
Started Aug 07 06:21:56 PM PDT 24
Finished Aug 07 06:21:57 PM PDT 24
Peak memory 205284 kb
Host smart-70a71c6a-083c-4280-9d7b-92b6afb2f4f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953590892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
1953590892
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.1328368627
Short name T882
Test name
Test status
Simulation time 265843698 ps
CPU time 7.02 seconds
Started Aug 07 06:21:56 PM PDT 24
Finished Aug 07 06:22:03 PM PDT 24
Peak memory 233404 kb
Host smart-6eadee6d-b0bb-497e-b814-35ce6a4b75ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328368627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.1328368627
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.1748746360
Short name T699
Test name
Test status
Simulation time 46104984 ps
CPU time 0.78 seconds
Started Aug 07 06:21:56 PM PDT 24
Finished Aug 07 06:21:57 PM PDT 24
Peak memory 206900 kb
Host smart-f8da4ec9-f626-45d5-91a8-07d37125e91c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748746360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.1748746360
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.1151492336
Short name T678
Test name
Test status
Simulation time 19829583704 ps
CPU time 76.47 seconds
Started Aug 07 06:21:55 PM PDT 24
Finished Aug 07 06:23:11 PM PDT 24
Peak memory 257052 kb
Host smart-3a9cba78-d798-4d87-a70c-0e1078109de3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151492336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.1151492336
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.614051642
Short name T225
Test name
Test status
Simulation time 6874577338 ps
CPU time 48.54 seconds
Started Aug 07 06:21:53 PM PDT 24
Finished Aug 07 06:22:42 PM PDT 24
Peak memory 257432 kb
Host smart-0520254a-87bc-4060-8035-fd7bccbb9292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614051642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.614051642
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.137114580
Short name T837
Test name
Test status
Simulation time 27919711 ps
CPU time 0.84 seconds
Started Aug 07 06:21:55 PM PDT 24
Finished Aug 07 06:21:56 PM PDT 24
Peak memory 216708 kb
Host smart-e24decc6-ed7d-4f37-8ea0-f24d41c54f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137114580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmds
.137114580
Directory /workspace/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/37.spi_device_intercept.2529670013
Short name T525
Test name
Test status
Simulation time 131617230 ps
CPU time 3.74 seconds
Started Aug 07 06:21:54 PM PDT 24
Finished Aug 07 06:21:57 PM PDT 24
Peak memory 225224 kb
Host smart-3a187d91-6e56-4423-912d-00df190279ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529670013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.2529670013
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.574434229
Short name T280
Test name
Test status
Simulation time 4526637416 ps
CPU time 37.02 seconds
Started Aug 07 06:21:56 PM PDT 24
Finished Aug 07 06:22:34 PM PDT 24
Peak memory 233472 kb
Host smart-09c5f14d-d627-4db3-9bf8-2b698bbd30f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574434229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.574434229
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.1028276924
Short name T227
Test name
Test status
Simulation time 8370116303 ps
CPU time 14.12 seconds
Started Aug 07 06:21:55 PM PDT 24
Finished Aug 07 06:22:10 PM PDT 24
Peak memory 225316 kb
Host smart-427030d9-b85c-472d-ba8d-eea5abd77f9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028276924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.1028276924
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.3692339315
Short name T413
Test name
Test status
Simulation time 2118710355 ps
CPU time 5.51 seconds
Started Aug 07 06:21:56 PM PDT 24
Finished Aug 07 06:22:02 PM PDT 24
Peak memory 225208 kb
Host smart-44d27193-e12c-4283-a65b-837157b5ffff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692339315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.3692339315
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.801828870
Short name T50
Test name
Test status
Simulation time 5509841377 ps
CPU time 19.25 seconds
Started Aug 07 06:21:54 PM PDT 24
Finished Aug 07 06:22:13 PM PDT 24
Peak memory 222732 kb
Host smart-e2810df1-d3b9-4df4-a8ab-9855254e4a2a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=801828870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dire
ct.801828870
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.311704086
Short name T868
Test name
Test status
Simulation time 4866042573 ps
CPU time 77.81 seconds
Started Aug 07 06:21:54 PM PDT 24
Finished Aug 07 06:23:12 PM PDT 24
Peak memory 263808 kb
Host smart-c044b979-664c-446e-9efa-440d2e9070d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311704086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stres
s_all.311704086
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.86115382
Short name T765
Test name
Test status
Simulation time 1628837816 ps
CPU time 8.16 seconds
Started Aug 07 06:21:55 PM PDT 24
Finished Aug 07 06:22:04 PM PDT 24
Peak memory 217340 kb
Host smart-48c3a8c2-b129-4d86-99e5-28e516751fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86115382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.86115382
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.2187716507
Short name T541
Test name
Test status
Simulation time 4681055240 ps
CPU time 11.78 seconds
Started Aug 07 06:21:58 PM PDT 24
Finished Aug 07 06:22:10 PM PDT 24
Peak memory 217052 kb
Host smart-5ed9ca19-dab1-4a5e-b80d-2c9d35efcedf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187716507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.2187716507
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.3580366532
Short name T920
Test name
Test status
Simulation time 46566651 ps
CPU time 0.88 seconds
Started Aug 07 06:21:55 PM PDT 24
Finished Aug 07 06:21:56 PM PDT 24
Peak memory 207196 kb
Host smart-2682fb7d-76f9-4997-94f0-5cd679c53b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580366532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.3580366532
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.2003924863
Short name T331
Test name
Test status
Simulation time 60574174 ps
CPU time 0.88 seconds
Started Aug 07 06:21:56 PM PDT 24
Finished Aug 07 06:21:57 PM PDT 24
Peak memory 207620 kb
Host smart-8154bc44-bcf8-4abd-a2a4-fac5c9d10dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003924863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.2003924863
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.3512706702
Short name T592
Test name
Test status
Simulation time 292753740 ps
CPU time 3.49 seconds
Started Aug 07 06:21:56 PM PDT 24
Finished Aug 07 06:22:00 PM PDT 24
Peak memory 233436 kb
Host smart-59ab87ce-3116-4936-b3ae-32f5f29efb73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512706702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.3512706702
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.1507719998
Short name T400
Test name
Test status
Simulation time 40695773 ps
CPU time 0.67 seconds
Started Aug 07 06:21:59 PM PDT 24
Finished Aug 07 06:22:00 PM PDT 24
Peak memory 206168 kb
Host smart-dcc9071c-8410-4fe3-bed4-96bc3d1ed749
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507719998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
1507719998
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.3060888171
Short name T651
Test name
Test status
Simulation time 154605215 ps
CPU time 3.68 seconds
Started Aug 07 06:22:00 PM PDT 24
Finished Aug 07 06:22:04 PM PDT 24
Peak memory 233420 kb
Host smart-89fbe9c6-8566-4ff1-900d-d0b0f16f7eb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060888171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.3060888171
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.1769141088
Short name T869
Test name
Test status
Simulation time 12195183 ps
CPU time 0.76 seconds
Started Aug 07 06:21:56 PM PDT 24
Finished Aug 07 06:21:56 PM PDT 24
Peak memory 207044 kb
Host smart-9a79275f-14d1-4a83-9dfb-1cbfc6f16118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769141088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.1769141088
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.2292404963
Short name T731
Test name
Test status
Simulation time 19065707650 ps
CPU time 137.58 seconds
Started Aug 07 06:21:57 PM PDT 24
Finished Aug 07 06:24:14 PM PDT 24
Peak memory 249924 kb
Host smart-3e56d6d7-de72-463e-9804-a6424bcb36dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292404963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.2292404963
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.1689003169
Short name T240
Test name
Test status
Simulation time 64898698818 ps
CPU time 606.7 seconds
Started Aug 07 06:21:56 PM PDT 24
Finished Aug 07 06:32:02 PM PDT 24
Peak memory 250036 kb
Host smart-537d0064-4a82-4e77-9e48-a67160614461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689003169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.1689003169
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.2302854877
Short name T168
Test name
Test status
Simulation time 3386388760 ps
CPU time 83.68 seconds
Started Aug 07 06:21:56 PM PDT 24
Finished Aug 07 06:23:20 PM PDT 24
Peak memory 249988 kb
Host smart-ea63107a-2705-4dd2-af52-8a96596a87aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302854877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.2302854877
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.1123231503
Short name T876
Test name
Test status
Simulation time 37261051930 ps
CPU time 44.7 seconds
Started Aug 07 06:21:56 PM PDT 24
Finished Aug 07 06:22:41 PM PDT 24
Peak memory 225208 kb
Host smart-a3d682c3-4968-4dbf-b58f-158e5771f0fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123231503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.1123231503
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.2095407197
Short name T611
Test name
Test status
Simulation time 8090385910 ps
CPU time 63.03 seconds
Started Aug 07 06:22:00 PM PDT 24
Finished Aug 07 06:23:03 PM PDT 24
Peak memory 249844 kb
Host smart-246128c9-47af-4a20-96fc-48380269f57f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095407197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmd
s.2095407197
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/38.spi_device_intercept.2851579522
Short name T80
Test name
Test status
Simulation time 2067101747 ps
CPU time 23.43 seconds
Started Aug 07 06:21:56 PM PDT 24
Finished Aug 07 06:22:20 PM PDT 24
Peak memory 225232 kb
Host smart-38b104b8-1c33-46a1-9515-54f31f482c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851579522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.2851579522
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.2894738009
Short name T294
Test name
Test status
Simulation time 357944192 ps
CPU time 8.55 seconds
Started Aug 07 06:21:55 PM PDT 24
Finished Aug 07 06:22:03 PM PDT 24
Peak memory 233420 kb
Host smart-8e3342ff-ecfc-49da-9bfe-298f7ef295bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894738009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.2894738009
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.1296075601
Short name T523
Test name
Test status
Simulation time 715575259 ps
CPU time 4.59 seconds
Started Aug 07 06:21:57 PM PDT 24
Finished Aug 07 06:22:01 PM PDT 24
Peak memory 225248 kb
Host smart-b8f49dd4-10b3-4729-9ff5-fa2266a5b2df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296075601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.1296075601
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.431309685
Short name T344
Test name
Test status
Simulation time 38132821 ps
CPU time 2.34 seconds
Started Aug 07 06:21:55 PM PDT 24
Finished Aug 07 06:21:58 PM PDT 24
Peak memory 233096 kb
Host smart-0e7501af-be02-481e-973b-9cd0b14eb59c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431309685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.431309685
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.3156813853
Short name T412
Test name
Test status
Simulation time 2780105668 ps
CPU time 7.1 seconds
Started Aug 07 06:22:00 PM PDT 24
Finished Aug 07 06:22:07 PM PDT 24
Peak memory 220908 kb
Host smart-40ae8114-3883-4216-8b37-20ba972be926
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3156813853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.3156813853
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.158363669
Short name T217
Test name
Test status
Simulation time 24140086044 ps
CPU time 231.81 seconds
Started Aug 07 06:21:55 PM PDT 24
Finished Aug 07 06:25:47 PM PDT 24
Peak memory 270088 kb
Host smart-d6fddc3e-bf10-46ea-aa49-19fa11347aa2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158363669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stres
s_all.158363669
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.3690892145
Short name T130
Test name
Test status
Simulation time 18983709475 ps
CPU time 30.29 seconds
Started Aug 07 06:21:56 PM PDT 24
Finished Aug 07 06:22:26 PM PDT 24
Peak memory 217224 kb
Host smart-36338062-acdb-4fa5-9c7f-bd642ceba342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690892145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.3690892145
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.3387308472
Short name T457
Test name
Test status
Simulation time 11930956262 ps
CPU time 10.41 seconds
Started Aug 07 06:21:55 PM PDT 24
Finished Aug 07 06:22:06 PM PDT 24
Peak memory 217276 kb
Host smart-8a64fa76-3130-4198-958b-a6f452e5dd1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387308472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.3387308472
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.722532518
Short name T683
Test name
Test status
Simulation time 1181916506 ps
CPU time 3.32 seconds
Started Aug 07 06:21:55 PM PDT 24
Finished Aug 07 06:21:58 PM PDT 24
Peak memory 216980 kb
Host smart-ef1f0bb3-733a-4a60-91a1-52a131da5585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722532518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.722532518
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.2735261931
Short name T815
Test name
Test status
Simulation time 43216260 ps
CPU time 0.82 seconds
Started Aug 07 06:21:58 PM PDT 24
Finished Aug 07 06:21:59 PM PDT 24
Peak memory 206600 kb
Host smart-6d30f573-94f1-4572-a421-bbe6cbb91ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735261931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.2735261931
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.3263765875
Short name T859
Test name
Test status
Simulation time 5513680602 ps
CPU time 5.63 seconds
Started Aug 07 06:21:56 PM PDT 24
Finished Aug 07 06:22:02 PM PDT 24
Peak memory 225316 kb
Host smart-ef80e638-e6ed-49fb-96bb-fffe0ea479c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263765875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.3263765875
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.706087888
Short name T65
Test name
Test status
Simulation time 22176770 ps
CPU time 0.74 seconds
Started Aug 07 06:22:09 PM PDT 24
Finished Aug 07 06:22:10 PM PDT 24
Peak memory 205824 kb
Host smart-7aa5088b-0546-4354-ad63-905ec1614799
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706087888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.706087888
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.1645301889
Short name T287
Test name
Test status
Simulation time 224757736 ps
CPU time 2.81 seconds
Started Aug 07 06:22:07 PM PDT 24
Finished Aug 07 06:22:10 PM PDT 24
Peak memory 225244 kb
Host smart-e4bfd1fa-9fb1-4cf4-a58a-c98e58eb3a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645301889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.1645301889
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.2138381279
Short name T657
Test name
Test status
Simulation time 17639664 ps
CPU time 0.79 seconds
Started Aug 07 06:21:59 PM PDT 24
Finished Aug 07 06:22:00 PM PDT 24
Peak memory 207064 kb
Host smart-42950f19-cab3-4176-9b68-3ed6f84e322a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138381279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.2138381279
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.1851395889
Short name T378
Test name
Test status
Simulation time 2746931919 ps
CPU time 52.42 seconds
Started Aug 07 06:21:59 PM PDT 24
Finished Aug 07 06:22:52 PM PDT 24
Peak memory 253376 kb
Host smart-5e033409-3d34-4eae-a611-ef8c82500848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851395889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.1851395889
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.2540597261
Short name T174
Test name
Test status
Simulation time 11048689378 ps
CPU time 64.08 seconds
Started Aug 07 06:21:59 PM PDT 24
Finished Aug 07 06:23:03 PM PDT 24
Peak memory 254100 kb
Host smart-0b96fcbf-da5b-44bc-b72f-d0ea240b9f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540597261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.2540597261
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.888872969
Short name T301
Test name
Test status
Simulation time 1825002810 ps
CPU time 18.48 seconds
Started Aug 07 06:21:59 PM PDT 24
Finished Aug 07 06:22:17 PM PDT 24
Peak memory 233496 kb
Host smart-823d5fb8-aad7-4d54-b135-a99201a7bbbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888872969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.888872969
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.45238450
Short name T256
Test name
Test status
Simulation time 290552133 ps
CPU time 4.75 seconds
Started Aug 07 06:22:00 PM PDT 24
Finished Aug 07 06:22:05 PM PDT 24
Peak memory 225260 kb
Host smart-c76477d1-f40e-4c77-b011-c3f327b1f4ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45238450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmds.45238450
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/39.spi_device_intercept.633370774
Short name T501
Test name
Test status
Simulation time 8546194963 ps
CPU time 23.84 seconds
Started Aug 07 06:21:59 PM PDT 24
Finished Aug 07 06:22:23 PM PDT 24
Peak memory 233504 kb
Host smart-84a0336b-535e-4042-967c-30675c6bddb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633370774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.633370774
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.2518810001
Short name T75
Test name
Test status
Simulation time 73310661506 ps
CPU time 44.4 seconds
Started Aug 07 06:22:01 PM PDT 24
Finished Aug 07 06:22:45 PM PDT 24
Peak memory 249848 kb
Host smart-945b8c8e-d584-4e49-8ae9-f7535b871ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518810001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.2518810001
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.4108485163
Short name T199
Test name
Test status
Simulation time 1412373211 ps
CPU time 5.39 seconds
Started Aug 07 06:22:02 PM PDT 24
Finished Aug 07 06:22:08 PM PDT 24
Peak memory 233460 kb
Host smart-0405b378-c61b-4761-851d-72fa0f6b1317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108485163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.4108485163
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.2969495410
Short name T792
Test name
Test status
Simulation time 2246735742 ps
CPU time 9.11 seconds
Started Aug 07 06:22:02 PM PDT 24
Finished Aug 07 06:22:11 PM PDT 24
Peak memory 249832 kb
Host smart-a11af4c1-e455-4616-b7ec-e3fbf8d4bfb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969495410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.2969495410
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.4108505915
Short name T915
Test name
Test status
Simulation time 842306667 ps
CPU time 4.37 seconds
Started Aug 07 06:21:58 PM PDT 24
Finished Aug 07 06:22:02 PM PDT 24
Peak memory 221224 kb
Host smart-e64ba261-5a33-4401-acb2-91be0605bc65
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4108505915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.4108505915
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.1236951857
Short name T800
Test name
Test status
Simulation time 2690870121 ps
CPU time 63.62 seconds
Started Aug 07 06:22:01 PM PDT 24
Finished Aug 07 06:23:05 PM PDT 24
Peak memory 265360 kb
Host smart-8dc4944b-d322-44f0-b058-9ef381d8a840
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236951857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.1236951857
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.1476808251
Short name T576
Test name
Test status
Simulation time 17137549277 ps
CPU time 29.16 seconds
Started Aug 07 06:22:01 PM PDT 24
Finished Aug 07 06:22:30 PM PDT 24
Peak memory 217044 kb
Host smart-ff0e9973-38c5-41c2-b019-14b92f2eb7de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476808251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.1476808251
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.234844836
Short name T414
Test name
Test status
Simulation time 2064174569 ps
CPU time 4.21 seconds
Started Aug 07 06:21:57 PM PDT 24
Finished Aug 07 06:22:01 PM PDT 24
Peak memory 216960 kb
Host smart-7104d941-922a-41f1-8119-ecbcb056b1b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234844836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.234844836
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.3896144241
Short name T394
Test name
Test status
Simulation time 71147730 ps
CPU time 1.3 seconds
Started Aug 07 06:22:05 PM PDT 24
Finished Aug 07 06:22:06 PM PDT 24
Peak memory 216956 kb
Host smart-feb64c13-41cf-4a87-bd29-375fc7a793d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896144241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.3896144241
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.3051206
Short name T486
Test name
Test status
Simulation time 50689934 ps
CPU time 0.8 seconds
Started Aug 07 06:22:04 PM PDT 24
Finished Aug 07 06:22:05 PM PDT 24
Peak memory 207620 kb
Host smart-7f3141fc-769d-4bbf-8ba3-a7eb9f463b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.3051206
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.252314790
Short name T645
Test name
Test status
Simulation time 977604439 ps
CPU time 6.97 seconds
Started Aug 07 06:22:10 PM PDT 24
Finished Aug 07 06:22:17 PM PDT 24
Peak memory 233444 kb
Host smart-90c382cb-7916-4dce-bec0-836dc4930ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252314790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.252314790
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.1419052927
Short name T1
Test name
Test status
Simulation time 33814888 ps
CPU time 0.73 seconds
Started Aug 07 06:20:04 PM PDT 24
Finished Aug 07 06:20:05 PM PDT 24
Peak memory 205268 kb
Host smart-a61ed815-b62b-414d-bd66-990b4d0b65e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419052927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.1
419052927
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.506593134
Short name T979
Test name
Test status
Simulation time 424047883 ps
CPU time 3.94 seconds
Started Aug 07 06:20:02 PM PDT 24
Finished Aug 07 06:20:06 PM PDT 24
Peak memory 225288 kb
Host smart-dcd4f38b-dfcc-4240-8324-a4ae269d6704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506593134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.506593134
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.585459603
Short name T959
Test name
Test status
Simulation time 32643277 ps
CPU time 0.82 seconds
Started Aug 07 06:20:02 PM PDT 24
Finished Aug 07 06:20:03 PM PDT 24
Peak memory 207044 kb
Host smart-706d28fb-a169-48c4-a47c-32e4d206226f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585459603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.585459603
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.3529305865
Short name T215
Test name
Test status
Simulation time 19015447471 ps
CPU time 50.19 seconds
Started Aug 07 06:20:01 PM PDT 24
Finished Aug 07 06:20:51 PM PDT 24
Peak memory 251772 kb
Host smart-024dc53e-a4cf-4585-85c3-c28ef3ea3c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529305865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.3529305865
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.4062153794
Short name T238
Test name
Test status
Simulation time 35096953600 ps
CPU time 73.33 seconds
Started Aug 07 06:20:01 PM PDT 24
Finished Aug 07 06:21:15 PM PDT 24
Peak memory 254664 kb
Host smart-06982f61-0ea6-40e0-a598-e6a8e83e8051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062153794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.4062153794
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.1804846526
Short name T974
Test name
Test status
Simulation time 37536468516 ps
CPU time 77.46 seconds
Started Aug 07 06:20:01 PM PDT 24
Finished Aug 07 06:21:19 PM PDT 24
Peak memory 234356 kb
Host smart-f1a219ff-7cc4-46f1-ba43-1270ddd2a360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804846526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.1804846526
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.899512424
Short name T278
Test name
Test status
Simulation time 59010260 ps
CPU time 3.82 seconds
Started Aug 07 06:20:01 PM PDT 24
Finished Aug 07 06:20:05 PM PDT 24
Peak memory 225272 kb
Host smart-e1265e8a-c555-4e2a-85d7-7cf5dd1f974c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899512424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.899512424
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.392913589
Short name T1030
Test name
Test status
Simulation time 38594998 ps
CPU time 0.89 seconds
Started Aug 07 06:20:06 PM PDT 24
Finished Aug 07 06:20:07 PM PDT 24
Peak memory 216560 kb
Host smart-0d79a609-fe01-4109-b4de-95987dc299d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392913589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds.
392913589
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/4.spi_device_intercept.1593053970
Short name T819
Test name
Test status
Simulation time 759581095 ps
CPU time 3.66 seconds
Started Aug 07 06:20:03 PM PDT 24
Finished Aug 07 06:20:07 PM PDT 24
Peak memory 225108 kb
Host smart-6b1f0f2b-c667-49bf-9ff5-89c6d8297399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593053970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.1593053970
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.4140795971
Short name T845
Test name
Test status
Simulation time 3605065072 ps
CPU time 34.62 seconds
Started Aug 07 06:19:59 PM PDT 24
Finished Aug 07 06:20:34 PM PDT 24
Peak memory 225280 kb
Host smart-d0ddf882-bdc4-4ca0-ae06-753b5f6d8421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140795971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.4140795971
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.1554900936
Short name T34
Test name
Test status
Simulation time 62801989 ps
CPU time 1.05 seconds
Started Aug 07 06:20:07 PM PDT 24
Finished Aug 07 06:20:09 PM PDT 24
Peak memory 218420 kb
Host smart-3fedbbc0-87f5-4ba2-ac11-d596fceed283
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554900936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.spi_device_mem_parity.1554900936
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.2678404464
Short name T202
Test name
Test status
Simulation time 186798236 ps
CPU time 4.83 seconds
Started Aug 07 06:20:05 PM PDT 24
Finished Aug 07 06:20:10 PM PDT 24
Peak memory 225236 kb
Host smart-5efac377-3661-4fed-b6f6-472a50e36cec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678404464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.2678404464
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.2262573589
Short name T288
Test name
Test status
Simulation time 1377817968 ps
CPU time 6.83 seconds
Started Aug 07 06:20:05 PM PDT 24
Finished Aug 07 06:20:12 PM PDT 24
Peak memory 233456 kb
Host smart-14818c80-f649-4103-b547-0a1a37bdfa98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262573589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.2262573589
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.3285876414
Short name T916
Test name
Test status
Simulation time 1469818685 ps
CPU time 15.78 seconds
Started Aug 07 06:20:01 PM PDT 24
Finished Aug 07 06:20:17 PM PDT 24
Peak memory 222824 kb
Host smart-ef41785f-ff96-4eb8-a64c-e5750e3c6f66
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3285876414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.3285876414
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.959772661
Short name T58
Test name
Test status
Simulation time 167671505 ps
CPU time 1.28 seconds
Started Aug 07 06:20:00 PM PDT 24
Finished Aug 07 06:20:02 PM PDT 24
Peak memory 235580 kb
Host smart-7188a9bf-8147-4404-b4fd-efcf14c2ce53
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959772661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.959772661
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.3998249314
Short name T70
Test name
Test status
Simulation time 4737240853 ps
CPU time 103.21 seconds
Started Aug 07 06:20:06 PM PDT 24
Finished Aug 07 06:21:49 PM PDT 24
Peak memory 269608 kb
Host smart-e05bd26b-1545-4420-9734-64f60d25c92b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998249314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.3998249314
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.1267819722
Short name T417
Test name
Test status
Simulation time 2338394312 ps
CPU time 21.55 seconds
Started Aug 07 06:20:03 PM PDT 24
Finished Aug 07 06:20:24 PM PDT 24
Peak memory 220600 kb
Host smart-803a9cad-949c-4bf7-b98c-b5bb85175c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267819722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.1267819722
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.2665725699
Short name T544
Test name
Test status
Simulation time 2621508501 ps
CPU time 4.71 seconds
Started Aug 07 06:20:01 PM PDT 24
Finished Aug 07 06:20:06 PM PDT 24
Peak memory 217052 kb
Host smart-80bd058f-080c-4c60-9741-1b4ef0a5d346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665725699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.2665725699
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.2469988152
Short name T622
Test name
Test status
Simulation time 163324487 ps
CPU time 2.17 seconds
Started Aug 07 06:20:03 PM PDT 24
Finished Aug 07 06:20:05 PM PDT 24
Peak memory 217024 kb
Host smart-86a4a011-ace5-4496-92f4-fc29e0154b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469988152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.2469988152
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.2297964093
Short name T357
Test name
Test status
Simulation time 375387039 ps
CPU time 0.81 seconds
Started Aug 07 06:20:06 PM PDT 24
Finished Aug 07 06:20:07 PM PDT 24
Peak memory 206564 kb
Host smart-1964805b-5d8e-42b8-89ba-f1555c67c3da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297964093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.2297964093
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.703155636
Short name T891
Test name
Test status
Simulation time 10155601394 ps
CPU time 21.13 seconds
Started Aug 07 06:20:02 PM PDT 24
Finished Aug 07 06:20:23 PM PDT 24
Peak memory 238084 kb
Host smart-0c982190-fb97-45a4-9bc6-65d57630a34e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703155636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.703155636
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.363971594
Short name T371
Test name
Test status
Simulation time 31605752 ps
CPU time 0.74 seconds
Started Aug 07 06:22:07 PM PDT 24
Finished Aug 07 06:22:08 PM PDT 24
Peak memory 205272 kb
Host smart-e3390dd9-6fa6-494d-8ce0-3583444c3e51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363971594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.363971594
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.2183958995
Short name T424
Test name
Test status
Simulation time 36991882 ps
CPU time 2.39 seconds
Started Aug 07 06:22:09 PM PDT 24
Finished Aug 07 06:22:11 PM PDT 24
Peak memory 233492 kb
Host smart-c1fa71ff-58a0-45fa-b615-3851b8f34a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183958995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.2183958995
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.835866424
Short name T839
Test name
Test status
Simulation time 16340002 ps
CPU time 0.72 seconds
Started Aug 07 06:21:58 PM PDT 24
Finished Aug 07 06:21:59 PM PDT 24
Peak memory 206048 kb
Host smart-9393acc2-7641-4ee3-97ee-93d3cd49ca11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835866424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.835866424
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.2546291322
Short name T980
Test name
Test status
Simulation time 3672000693 ps
CPU time 62.87 seconds
Started Aug 07 06:22:04 PM PDT 24
Finished Aug 07 06:23:07 PM PDT 24
Peak memory 251812 kb
Host smart-d9ae3c7a-17f3-4ae7-b5a3-21738adbb756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546291322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.2546291322
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.2463978661
Short name T632
Test name
Test status
Simulation time 7093356937 ps
CPU time 79.24 seconds
Started Aug 07 06:22:06 PM PDT 24
Finished Aug 07 06:23:25 PM PDT 24
Peak memory 251360 kb
Host smart-0f484d97-55b4-46fc-9301-5a6abb3021e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463978661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.2463978661
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.2159233832
Short name T969
Test name
Test status
Simulation time 9187683943 ps
CPU time 71.69 seconds
Started Aug 07 06:22:03 PM PDT 24
Finished Aug 07 06:23:15 PM PDT 24
Peak memory 223312 kb
Host smart-d913a458-e380-40d8-b5dc-7fc08a66e7a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159233832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.2159233832
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.1346690410
Short name T687
Test name
Test status
Simulation time 1094195639 ps
CPU time 22.03 seconds
Started Aug 07 06:22:09 PM PDT 24
Finished Aug 07 06:22:31 PM PDT 24
Peak memory 225276 kb
Host smart-41f81b56-0033-4bfc-945c-c5c8031675f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346690410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.1346690410
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.539569711
Short name T38
Test name
Test status
Simulation time 45438140546 ps
CPU time 157.12 seconds
Started Aug 07 06:22:05 PM PDT 24
Finished Aug 07 06:24:42 PM PDT 24
Peak memory 249936 kb
Host smart-5bcb6832-d416-4f88-94ff-74f1580acc0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539569711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmds
.539569711
Directory /workspace/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/40.spi_device_intercept.1862254189
Short name T764
Test name
Test status
Simulation time 98575771 ps
CPU time 4.24 seconds
Started Aug 07 06:21:59 PM PDT 24
Finished Aug 07 06:22:03 PM PDT 24
Peak memory 233496 kb
Host smart-2932dd33-723e-46af-a6ff-88ed9146efa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862254189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.1862254189
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.1578276900
Short name T87
Test name
Test status
Simulation time 498646935 ps
CPU time 9.61 seconds
Started Aug 07 06:22:01 PM PDT 24
Finished Aug 07 06:22:11 PM PDT 24
Peak memory 241312 kb
Host smart-03538a7e-9645-4726-b145-d38f6aeb9436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578276900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.1578276900
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.391280189
Short name T291
Test name
Test status
Simulation time 712871478 ps
CPU time 2.98 seconds
Started Aug 07 06:22:09 PM PDT 24
Finished Aug 07 06:22:12 PM PDT 24
Peak memory 233492 kb
Host smart-2900a2e7-0468-4d92-a159-361a97d63a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391280189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swap
.391280189
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.1870965131
Short name T349
Test name
Test status
Simulation time 1191972339 ps
CPU time 2.49 seconds
Started Aug 07 06:22:09 PM PDT 24
Finished Aug 07 06:22:12 PM PDT 24
Peak memory 225208 kb
Host smart-c6b21dbf-1a09-4688-b5df-f0a40801a017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870965131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.1870965131
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.3534436827
Short name T778
Test name
Test status
Simulation time 246208298 ps
CPU time 5.04 seconds
Started Aug 07 06:21:56 PM PDT 24
Finished Aug 07 06:22:02 PM PDT 24
Peak memory 219928 kb
Host smart-dfc4af97-15fb-4791-8d91-68bcd029f47c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3534436827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.3534436827
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.532023029
Short name T555
Test name
Test status
Simulation time 118120308930 ps
CPU time 240.27 seconds
Started Aug 07 06:22:04 PM PDT 24
Finished Aug 07 06:26:05 PM PDT 24
Peak memory 249912 kb
Host smart-3ea71b47-c477-40e0-8178-d1128291809c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532023029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stres
s_all.532023029
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.4254402487
Short name T910
Test name
Test status
Simulation time 2182230032 ps
CPU time 33.05 seconds
Started Aug 07 06:22:05 PM PDT 24
Finished Aug 07 06:22:38 PM PDT 24
Peak memory 217136 kb
Host smart-c36744cf-b696-4eec-b01c-c2c950ef2a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254402487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.4254402487
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.1179483693
Short name T407
Test name
Test status
Simulation time 3779131784 ps
CPU time 15.96 seconds
Started Aug 07 06:21:59 PM PDT 24
Finished Aug 07 06:22:15 PM PDT 24
Peak memory 217000 kb
Host smart-298ea165-0ff0-42eb-8fce-908fa0543046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179483693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.1179483693
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.709586438
Short name T28
Test name
Test status
Simulation time 602049663 ps
CPU time 9.17 seconds
Started Aug 07 06:22:04 PM PDT 24
Finished Aug 07 06:22:14 PM PDT 24
Peak memory 216976 kb
Host smart-b1a01c50-0bf7-4cd8-8388-f3b185e6781f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709586438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.709586438
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.3546481261
Short name T923
Test name
Test status
Simulation time 112382060 ps
CPU time 0.96 seconds
Started Aug 07 06:22:01 PM PDT 24
Finished Aug 07 06:22:02 PM PDT 24
Peak memory 206600 kb
Host smart-25fda540-da08-434a-a47f-7b035d39dc8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546481261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.3546481261
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.1792882118
Short name T161
Test name
Test status
Simulation time 2736377077 ps
CPU time 14.1 seconds
Started Aug 07 06:22:04 PM PDT 24
Finished Aug 07 06:22:19 PM PDT 24
Peak memory 225320 kb
Host smart-526bf118-d2fc-47c2-8cb8-bcffb2193b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792882118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.1792882118
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.2663624330
Short name T853
Test name
Test status
Simulation time 11937873 ps
CPU time 0.76 seconds
Started Aug 07 06:22:06 PM PDT 24
Finished Aug 07 06:22:07 PM PDT 24
Peak memory 205280 kb
Host smart-eecc6ad0-b2fe-4180-b07f-def29beceb26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663624330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
2663624330
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.1790553991
Short name T789
Test name
Test status
Simulation time 277793472 ps
CPU time 2.19 seconds
Started Aug 07 06:22:06 PM PDT 24
Finished Aug 07 06:22:08 PM PDT 24
Peak memory 224796 kb
Host smart-1951f614-b607-42b1-9a49-038c6a553393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790553991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.1790553991
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.3067246892
Short name T325
Test name
Test status
Simulation time 27983995 ps
CPU time 0.81 seconds
Started Aug 07 06:22:06 PM PDT 24
Finished Aug 07 06:22:07 PM PDT 24
Peak memory 207280 kb
Host smart-c6742d69-f8f5-47f1-8e4d-3726d3af8c85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067246892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.3067246892
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.1494927382
Short name T854
Test name
Test status
Simulation time 39591252354 ps
CPU time 305.22 seconds
Started Aug 07 06:22:04 PM PDT 24
Finished Aug 07 06:27:10 PM PDT 24
Peak memory 258104 kb
Host smart-ed10295e-f5ef-4cca-8606-e1398de01cf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494927382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.1494927382
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.2952085135
Short name T30
Test name
Test status
Simulation time 7010459224 ps
CPU time 76.18 seconds
Started Aug 07 06:22:06 PM PDT 24
Finished Aug 07 06:23:22 PM PDT 24
Peak memory 249884 kb
Host smart-3e6e379f-82be-4dd6-80ad-101d665effde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952085135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.2952085135
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.731940346
Short name T1008
Test name
Test status
Simulation time 147453313 ps
CPU time 2.91 seconds
Started Aug 07 06:22:06 PM PDT 24
Finished Aug 07 06:22:09 PM PDT 24
Peak memory 233416 kb
Host smart-27395f1d-3bc6-4b4b-86f2-bccf3dceadf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731940346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.731940346
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.1354976121
Short name T988
Test name
Test status
Simulation time 3402141591 ps
CPU time 66.68 seconds
Started Aug 07 06:22:04 PM PDT 24
Finished Aug 07 06:23:11 PM PDT 24
Peak memory 273580 kb
Host smart-3a340f3e-744e-4f74-8c9a-6fdbc330c330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354976121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmd
s.1354976121
Directory /workspace/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/41.spi_device_intercept.2050299395
Short name T894
Test name
Test status
Simulation time 2296369587 ps
CPU time 5.61 seconds
Started Aug 07 06:22:07 PM PDT 24
Finished Aug 07 06:22:13 PM PDT 24
Peak memory 225328 kb
Host smart-a65d2347-ffe8-4a84-9fe8-876a3a2c8c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050299395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.2050299395
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.2797076108
Short name T806
Test name
Test status
Simulation time 72238882167 ps
CPU time 103.4 seconds
Started Aug 07 06:22:06 PM PDT 24
Finished Aug 07 06:23:49 PM PDT 24
Peak memory 241540 kb
Host smart-fe0fa7ba-3139-49d5-b224-9f2d064cef2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797076108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.2797076108
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.2523136391
Short name T966
Test name
Test status
Simulation time 35285695 ps
CPU time 2.46 seconds
Started Aug 07 06:22:03 PM PDT 24
Finished Aug 07 06:22:06 PM PDT 24
Peak memory 233072 kb
Host smart-aa611fea-66b4-4870-ae43-8d43c9fac265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523136391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.2523136391
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.2126179057
Short name T1005
Test name
Test status
Simulation time 47791784709 ps
CPU time 14.34 seconds
Started Aug 07 06:22:05 PM PDT 24
Finished Aug 07 06:22:19 PM PDT 24
Peak memory 225224 kb
Host smart-880fad30-c329-4273-ac3b-8b09672d652f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126179057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.2126179057
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.2374863469
Short name T924
Test name
Test status
Simulation time 334992508 ps
CPU time 3.62 seconds
Started Aug 07 06:22:06 PM PDT 24
Finished Aug 07 06:22:10 PM PDT 24
Peak memory 223648 kb
Host smart-f73f9a12-57f3-4e67-ba05-19f556973a79
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2374863469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.2374863469
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.2017798708
Short name T230
Test name
Test status
Simulation time 95780840701 ps
CPU time 454.81 seconds
Started Aug 07 06:22:07 PM PDT 24
Finished Aug 07 06:29:42 PM PDT 24
Peak memory 266372 kb
Host smart-c13dbeaf-2bcb-4959-bc54-d7d771ec1df8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017798708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.2017798708
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.227118936
Short name T779
Test name
Test status
Simulation time 1025636237 ps
CPU time 3.22 seconds
Started Aug 07 06:22:04 PM PDT 24
Finished Aug 07 06:22:07 PM PDT 24
Peak memory 217240 kb
Host smart-9d79f1d5-5249-4a9f-89e6-c94ce9a092be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227118936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.227118936
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.4188881809
Short name T997
Test name
Test status
Simulation time 3061277931 ps
CPU time 11.21 seconds
Started Aug 07 06:22:06 PM PDT 24
Finished Aug 07 06:22:17 PM PDT 24
Peak memory 217060 kb
Host smart-f40b33b9-3e6b-4498-8392-5e5127f5b875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188881809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.4188881809
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.2640194881
Short name T450
Test name
Test status
Simulation time 213800792 ps
CPU time 1.29 seconds
Started Aug 07 06:22:06 PM PDT 24
Finished Aug 07 06:22:07 PM PDT 24
Peak memory 216976 kb
Host smart-3b332d95-1a49-4baa-9c05-12a2f0789fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640194881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.2640194881
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.3622337241
Short name T752
Test name
Test status
Simulation time 50065023 ps
CPU time 0.87 seconds
Started Aug 07 06:22:05 PM PDT 24
Finished Aug 07 06:22:06 PM PDT 24
Peak memory 206596 kb
Host smart-7dec8b2c-aa5f-4b12-82a0-2e6334d5ff27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622337241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.3622337241
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.2223347664
Short name T185
Test name
Test status
Simulation time 2226617181 ps
CPU time 4.85 seconds
Started Aug 07 06:22:04 PM PDT 24
Finished Aug 07 06:22:09 PM PDT 24
Peak memory 233544 kb
Host smart-f4c75c39-849a-466c-aaad-d2a8490aaf2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223347664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.2223347664
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.645363034
Short name T836
Test name
Test status
Simulation time 19243997 ps
CPU time 0.7 seconds
Started Aug 07 06:22:10 PM PDT 24
Finished Aug 07 06:22:11 PM PDT 24
Peak memory 205800 kb
Host smart-ba055348-46c1-4072-b36c-c2b7425a9199
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645363034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.645363034
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.740441947
Short name T1000
Test name
Test status
Simulation time 997316235 ps
CPU time 7.41 seconds
Started Aug 07 06:22:12 PM PDT 24
Finished Aug 07 06:22:19 PM PDT 24
Peak memory 233440 kb
Host smart-f8b44b47-5693-4fa7-a5aa-962fbf1034a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740441947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.740441947
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.542355646
Short name T554
Test name
Test status
Simulation time 30427723 ps
CPU time 0.77 seconds
Started Aug 07 06:22:04 PM PDT 24
Finished Aug 07 06:22:05 PM PDT 24
Peak memory 206040 kb
Host smart-72ec8759-eb55-42ab-99ab-cf54dd163254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542355646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.542355646
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.4249700513
Short name T808
Test name
Test status
Simulation time 37393657248 ps
CPU time 67.34 seconds
Started Aug 07 06:22:12 PM PDT 24
Finished Aug 07 06:23:19 PM PDT 24
Peak memory 241716 kb
Host smart-96a54bfc-3c6f-45c0-8e20-ba5e138e93fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249700513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.4249700513
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.3443162044
Short name T508
Test name
Test status
Simulation time 59581330265 ps
CPU time 261.41 seconds
Started Aug 07 06:22:10 PM PDT 24
Finished Aug 07 06:26:31 PM PDT 24
Peak memory 249956 kb
Host smart-244422a0-8243-4da0-8bc3-7970518394b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443162044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.3443162044
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.1710002217
Short name T32
Test name
Test status
Simulation time 55762645411 ps
CPU time 71.24 seconds
Started Aug 07 06:22:09 PM PDT 24
Finished Aug 07 06:23:20 PM PDT 24
Peak memory 252160 kb
Host smart-19a62b07-aef6-4b59-a8fe-e5f7a5c92d24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710002217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.1710002217
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.3279204563
Short name T769
Test name
Test status
Simulation time 330841166 ps
CPU time 2.68 seconds
Started Aug 07 06:22:11 PM PDT 24
Finished Aug 07 06:22:13 PM PDT 24
Peak memory 225280 kb
Host smart-54084b89-7ab5-4542-8aaa-eb6affe93e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279204563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.3279204563
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.3533904835
Short name T223
Test name
Test status
Simulation time 1869049705 ps
CPU time 47.5 seconds
Started Aug 07 06:22:10 PM PDT 24
Finished Aug 07 06:22:58 PM PDT 24
Peak memory 254200 kb
Host smart-e26d4a2e-e4d6-412e-b2d9-6ebece4c81ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533904835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmd
s.3533904835
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/42.spi_device_intercept.371511157
Short name T590
Test name
Test status
Simulation time 9384014394 ps
CPU time 16.15 seconds
Started Aug 07 06:22:10 PM PDT 24
Finished Aug 07 06:22:26 PM PDT 24
Peak memory 225220 kb
Host smart-808fb899-f7d3-4ab1-b31c-fcbb75c68cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371511157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.371511157
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.2451112565
Short name T548
Test name
Test status
Simulation time 31519530135 ps
CPU time 130.28 seconds
Started Aug 07 06:22:11 PM PDT 24
Finished Aug 07 06:24:22 PM PDT 24
Peak memory 233400 kb
Host smart-201a000d-2a29-4e13-a7e6-a908cfcf213a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451112565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.2451112565
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.2219482071
Short name T232
Test name
Test status
Simulation time 184271293 ps
CPU time 4.71 seconds
Started Aug 07 06:22:11 PM PDT 24
Finished Aug 07 06:22:16 PM PDT 24
Peak memory 241300 kb
Host smart-d8cd8608-15c2-4ad6-881b-92b65fbe881c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219482071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.2219482071
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.1946048871
Short name T86
Test name
Test status
Simulation time 524185137 ps
CPU time 8.94 seconds
Started Aug 07 06:22:10 PM PDT 24
Finished Aug 07 06:22:19 PM PDT 24
Peak memory 233452 kb
Host smart-c3c3e805-e83a-4d43-91a6-9cb2c9f1bb12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946048871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.1946048871
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.1086389332
Short name T741
Test name
Test status
Simulation time 6017226216 ps
CPU time 6.42 seconds
Started Aug 07 06:22:17 PM PDT 24
Finished Aug 07 06:22:24 PM PDT 24
Peak memory 220764 kb
Host smart-aaaa6bc6-0b87-4533-a652-da6874b8d3fe
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1086389332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.1086389332
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.3085386218
Short name T149
Test name
Test status
Simulation time 326916736 ps
CPU time 1.05 seconds
Started Aug 07 06:22:10 PM PDT 24
Finished Aug 07 06:22:12 PM PDT 24
Peak memory 207244 kb
Host smart-56d61f0e-174a-4b9f-b7e7-01936f44dfc5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085386218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.3085386218
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.429921729
Short name T1021
Test name
Test status
Simulation time 11399887369 ps
CPU time 46.31 seconds
Started Aug 07 06:22:08 PM PDT 24
Finished Aug 07 06:22:54 PM PDT 24
Peak memory 217072 kb
Host smart-3c5ee28a-743a-473e-81b5-f777a5668151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429921729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.429921729
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.2783014818
Short name T380
Test name
Test status
Simulation time 2775934431 ps
CPU time 4.54 seconds
Started Aug 07 06:22:06 PM PDT 24
Finished Aug 07 06:22:11 PM PDT 24
Peak memory 217000 kb
Host smart-3663dce0-026e-4fbc-a548-63695971a7a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783014818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.2783014818
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.1525598254
Short name T327
Test name
Test status
Simulation time 14816127 ps
CPU time 0.77 seconds
Started Aug 07 06:22:10 PM PDT 24
Finished Aug 07 06:22:11 PM PDT 24
Peak memory 206564 kb
Host smart-8d4f7657-2a1f-4f61-9237-d74e10b77949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525598254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.1525598254
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.1305288076
Short name T483
Test name
Test status
Simulation time 36299577 ps
CPU time 0.77 seconds
Started Aug 07 06:22:10 PM PDT 24
Finished Aug 07 06:22:11 PM PDT 24
Peak memory 206580 kb
Host smart-d94c9877-2a3e-40eb-823d-1854d6132abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305288076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.1305288076
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.2310261910
Short name T716
Test name
Test status
Simulation time 19139182669 ps
CPU time 17.57 seconds
Started Aug 07 06:22:17 PM PDT 24
Finished Aug 07 06:22:35 PM PDT 24
Peak memory 225304 kb
Host smart-89db2fe0-9398-4173-9eb3-0afcee6856ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310261910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.2310261910
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.4122612584
Short name T890
Test name
Test status
Simulation time 13018340 ps
CPU time 0.72 seconds
Started Aug 07 06:22:16 PM PDT 24
Finished Aug 07 06:22:17 PM PDT 24
Peak memory 205188 kb
Host smart-e0928f66-31ba-4c3d-898d-4595c3d4e2be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122612584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
4122612584
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.1812634488
Short name T946
Test name
Test status
Simulation time 1833350892 ps
CPU time 7.9 seconds
Started Aug 07 06:22:10 PM PDT 24
Finished Aug 07 06:22:18 PM PDT 24
Peak memory 225276 kb
Host smart-cc9e4353-7b95-446c-a314-0e70eb1b13ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812634488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.1812634488
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.3018306690
Short name T832
Test name
Test status
Simulation time 16975671 ps
CPU time 0.78 seconds
Started Aug 07 06:22:12 PM PDT 24
Finished Aug 07 06:22:12 PM PDT 24
Peak memory 206976 kb
Host smart-2fafaf98-7a22-4da8-ba8c-24077faaeb53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018306690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.3018306690
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.3546537667
Short name T479
Test name
Test status
Simulation time 5339223942 ps
CPU time 49.19 seconds
Started Aug 07 06:22:15 PM PDT 24
Finished Aug 07 06:23:04 PM PDT 24
Peak memory 249872 kb
Host smart-03ee0d61-85ac-4e4b-bdc8-abd9dc5f37f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546537667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.3546537667
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.1680458963
Short name T410
Test name
Test status
Simulation time 59014784675 ps
CPU time 31.27 seconds
Started Aug 07 06:22:15 PM PDT 24
Finished Aug 07 06:22:47 PM PDT 24
Peak memory 241768 kb
Host smart-5a884936-8bc7-440e-b6fb-b8648d582c25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680458963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.1680458963
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.3963697990
Short name T813
Test name
Test status
Simulation time 3977734202 ps
CPU time 20.67 seconds
Started Aug 07 06:22:15 PM PDT 24
Finished Aug 07 06:22:36 PM PDT 24
Peak memory 249684 kb
Host smart-4f9348cb-a926-4847-a635-599ef94e92ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963697990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.3963697990
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.4053587737
Short name T39
Test name
Test status
Simulation time 1453087751 ps
CPU time 27.68 seconds
Started Aug 07 06:22:10 PM PDT 24
Finished Aug 07 06:22:38 PM PDT 24
Peak memory 233640 kb
Host smart-dc0b0f15-96b2-480a-8dae-63828cd1bfe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053587737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.4053587737
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.915078075
Short name T491
Test name
Test status
Simulation time 2868526771 ps
CPU time 53.75 seconds
Started Aug 07 06:22:09 PM PDT 24
Finished Aug 07 06:23:03 PM PDT 24
Peak memory 255064 kb
Host smart-a92a2a54-3f70-45a0-b80b-033037d28562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915078075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmds
.915078075
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/43.spi_device_intercept.3771636844
Short name T653
Test name
Test status
Simulation time 2647026979 ps
CPU time 5.21 seconds
Started Aug 07 06:22:11 PM PDT 24
Finished Aug 07 06:22:16 PM PDT 24
Peak memory 233544 kb
Host smart-1314e12e-a197-43f6-aa87-151234ead7d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771636844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.3771636844
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.3554052092
Short name T726
Test name
Test status
Simulation time 3502333536 ps
CPU time 29.78 seconds
Started Aug 07 06:22:14 PM PDT 24
Finished Aug 07 06:22:44 PM PDT 24
Peak memory 249356 kb
Host smart-4693d862-a5ad-4990-9333-113fe95e238e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554052092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.3554052092
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.785303264
Short name T958
Test name
Test status
Simulation time 2733961917 ps
CPU time 6.71 seconds
Started Aug 07 06:22:13 PM PDT 24
Finished Aug 07 06:22:20 PM PDT 24
Peak memory 233532 kb
Host smart-fbf014f2-6383-4d25-a1b7-dc23834fb99d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785303264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swap
.785303264
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.724742815
Short name T1023
Test name
Test status
Simulation time 2481009472 ps
CPU time 7.14 seconds
Started Aug 07 06:22:18 PM PDT 24
Finished Aug 07 06:22:25 PM PDT 24
Peak memory 233508 kb
Host smart-f2bc7d9f-11f8-41f7-b637-3e420f8955fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724742815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.724742815
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.1312972666
Short name T663
Test name
Test status
Simulation time 2901431731 ps
CPU time 15.4 seconds
Started Aug 07 06:22:16 PM PDT 24
Finished Aug 07 06:22:31 PM PDT 24
Peak memory 222716 kb
Host smart-289fa1b7-65ad-45d9-bae8-c1737cf3ef98
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1312972666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.1312972666
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.3950781137
Short name T852
Test name
Test status
Simulation time 4547644410 ps
CPU time 35.73 seconds
Started Aug 07 06:22:15 PM PDT 24
Finished Aug 07 06:22:51 PM PDT 24
Peak memory 233576 kb
Host smart-68fffc4c-cc65-4978-bb7f-af6ba89329b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950781137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.3950781137
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.1698414831
Short name T949
Test name
Test status
Simulation time 4971104410 ps
CPU time 28.2 seconds
Started Aug 07 06:22:13 PM PDT 24
Finished Aug 07 06:22:41 PM PDT 24
Peak memory 216996 kb
Host smart-57dd5388-6da9-4c42-89f7-2a99f14e2fc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698414831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.1698414831
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.1272316294
Short name T418
Test name
Test status
Simulation time 352922145 ps
CPU time 2.06 seconds
Started Aug 07 06:22:10 PM PDT 24
Finished Aug 07 06:22:12 PM PDT 24
Peak memory 216936 kb
Host smart-b363b24e-77ec-42fe-9ff3-ec7729d90fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272316294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.1272316294
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.3314200692
Short name T1002
Test name
Test status
Simulation time 61326200 ps
CPU time 0.84 seconds
Started Aug 07 06:22:12 PM PDT 24
Finished Aug 07 06:22:13 PM PDT 24
Peak memory 207592 kb
Host smart-6799b67f-adad-49e8-926e-f38885f62e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314200692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.3314200692
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.1397500480
Short name T610
Test name
Test status
Simulation time 330203214 ps
CPU time 0.96 seconds
Started Aug 07 06:22:18 PM PDT 24
Finished Aug 07 06:22:19 PM PDT 24
Peak memory 206532 kb
Host smart-e9f7314e-83a0-4bc1-a328-5fa4375ee901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397500480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.1397500480
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.2599850270
Short name T963
Test name
Test status
Simulation time 19452887318 ps
CPU time 35.01 seconds
Started Aug 07 06:22:09 PM PDT 24
Finished Aug 07 06:22:44 PM PDT 24
Peak memory 240644 kb
Host smart-3f0cbfb6-5cdf-40bc-b733-6b81a055bdac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599850270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.2599850270
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.816587500
Short name T502
Test name
Test status
Simulation time 23886531 ps
CPU time 0.75 seconds
Started Aug 07 06:22:18 PM PDT 24
Finished Aug 07 06:22:19 PM PDT 24
Peak memory 205852 kb
Host smart-285937fe-9183-4671-9e9b-38f074fc7218
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816587500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.816587500
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.3082036277
Short name T802
Test name
Test status
Simulation time 737707550 ps
CPU time 6.66 seconds
Started Aug 07 06:22:13 PM PDT 24
Finished Aug 07 06:22:20 PM PDT 24
Peak memory 225280 kb
Host smart-77d3f7c0-71f5-486f-a8e0-2588baa807f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082036277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.3082036277
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.441313479
Short name T902
Test name
Test status
Simulation time 14705937 ps
CPU time 0.79 seconds
Started Aug 07 06:22:15 PM PDT 24
Finished Aug 07 06:22:16 PM PDT 24
Peak memory 206384 kb
Host smart-a4f4c09f-3eaa-4cdf-9d20-b830558a284a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441313479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.441313479
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.3451373355
Short name T218
Test name
Test status
Simulation time 355957357698 ps
CPU time 321.63 seconds
Started Aug 07 06:22:24 PM PDT 24
Finished Aug 07 06:27:46 PM PDT 24
Peak memory 264356 kb
Host smart-e3b9c204-1fab-41f8-ad04-fb01ef7770c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451373355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.3451373355
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.204285178
Short name T154
Test name
Test status
Simulation time 25606179280 ps
CPU time 125.88 seconds
Started Aug 07 06:22:15 PM PDT 24
Finished Aug 07 06:24:21 PM PDT 24
Peak memory 257220 kb
Host smart-0f879dbe-fad4-45df-a7b1-c3dec666fc51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204285178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idle
.204285178
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.1480474401
Short name T296
Test name
Test status
Simulation time 2019060257 ps
CPU time 25.79 seconds
Started Aug 07 06:22:16 PM PDT 24
Finished Aug 07 06:22:42 PM PDT 24
Peak memory 234928 kb
Host smart-0a693679-bcf4-4089-ab50-5df33544618c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480474401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.1480474401
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.2035638867
Short name T84
Test name
Test status
Simulation time 12397743398 ps
CPU time 46.05 seconds
Started Aug 07 06:22:19 PM PDT 24
Finished Aug 07 06:23:05 PM PDT 24
Peak memory 249960 kb
Host smart-5aa4947d-bda9-4c7c-b2b3-8fcf3a6860ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035638867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmd
s.2035638867
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/44.spi_device_intercept.2240536925
Short name T536
Test name
Test status
Simulation time 393473678 ps
CPU time 7.73 seconds
Started Aug 07 06:22:18 PM PDT 24
Finished Aug 07 06:22:26 PM PDT 24
Peak memory 225240 kb
Host smart-1cd18246-0264-40ae-9ec8-45564497742d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240536925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.2240536925
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.1740875869
Short name T784
Test name
Test status
Simulation time 2576350816 ps
CPU time 11.59 seconds
Started Aug 07 06:22:16 PM PDT 24
Finished Aug 07 06:22:27 PM PDT 24
Peak memory 241756 kb
Host smart-8718d379-2fa4-40c9-a1ef-fe812f7313ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740875869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.1740875869
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.2301541774
Short name T939
Test name
Test status
Simulation time 4155668523 ps
CPU time 9.07 seconds
Started Aug 07 06:22:18 PM PDT 24
Finished Aug 07 06:22:27 PM PDT 24
Peak memory 225284 kb
Host smart-753dfd99-f379-44dc-bd2c-8f6b57a1c641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301541774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.2301541774
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.1727873177
Short name T490
Test name
Test status
Simulation time 21159698676 ps
CPU time 7.29 seconds
Started Aug 07 06:22:15 PM PDT 24
Finished Aug 07 06:22:22 PM PDT 24
Peak memory 233488 kb
Host smart-29e8bcc0-50d9-46b0-946f-47cd76323424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727873177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.1727873177
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.1910180078
Short name T603
Test name
Test status
Simulation time 6105442779 ps
CPU time 16.43 seconds
Started Aug 07 06:22:16 PM PDT 24
Finished Aug 07 06:22:32 PM PDT 24
Peak memory 222384 kb
Host smart-d800088d-1fe5-4dcb-ab68-765866cb8855
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1910180078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.1910180078
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.1194573233
Short name T213
Test name
Test status
Simulation time 55040680748 ps
CPU time 198.68 seconds
Started Aug 07 06:22:19 PM PDT 24
Finished Aug 07 06:25:38 PM PDT 24
Peak memory 270572 kb
Host smart-19cf9ec9-4a51-451b-bcc2-df622bd149b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194573233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.1194573233
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.4056458666
Short name T913
Test name
Test status
Simulation time 5665877541 ps
CPU time 7.05 seconds
Started Aug 07 06:22:18 PM PDT 24
Finished Aug 07 06:22:25 PM PDT 24
Peak memory 220648 kb
Host smart-eced4fcb-a906-47dd-95ed-8754fba0b5c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056458666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.4056458666
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.2202619354
Short name T328
Test name
Test status
Simulation time 7970242587 ps
CPU time 6.79 seconds
Started Aug 07 06:22:15 PM PDT 24
Finished Aug 07 06:22:21 PM PDT 24
Peak memory 217036 kb
Host smart-f0e68230-53b5-4b04-93bb-e0accb39ab6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202619354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.2202619354
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.1176547459
Short name T405
Test name
Test status
Simulation time 146908168 ps
CPU time 3.09 seconds
Started Aug 07 06:22:24 PM PDT 24
Finished Aug 07 06:22:28 PM PDT 24
Peak memory 216892 kb
Host smart-af6f83e4-3542-4089-928b-07a347493cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176547459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.1176547459
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.270971301
Short name T442
Test name
Test status
Simulation time 59449148 ps
CPU time 0.85 seconds
Started Aug 07 06:22:15 PM PDT 24
Finished Aug 07 06:22:17 PM PDT 24
Peak memory 206568 kb
Host smart-02f56407-540a-4dbb-8cb6-cf33d915bed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270971301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.270971301
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.1105253413
Short name T658
Test name
Test status
Simulation time 534666411 ps
CPU time 5.23 seconds
Started Aug 07 06:22:16 PM PDT 24
Finished Aug 07 06:22:21 PM PDT 24
Peak memory 233480 kb
Host smart-6c01a582-8786-49c1-994a-60f4cbb45d42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105253413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.1105253413
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.1542970013
Short name T482
Test name
Test status
Simulation time 17429627 ps
CPU time 0.74 seconds
Started Aug 07 06:22:18 PM PDT 24
Finished Aug 07 06:22:19 PM PDT 24
Peak memory 205824 kb
Host smart-e844c962-3cf9-48aa-8992-44e87e5afb16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542970013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
1542970013
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.371052107
Short name T563
Test name
Test status
Simulation time 2844724318 ps
CPU time 20.51 seconds
Started Aug 07 06:22:26 PM PDT 24
Finished Aug 07 06:22:47 PM PDT 24
Peak memory 233440 kb
Host smart-7e2f7982-3f09-438d-a3a3-2539c1380d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371052107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.371052107
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.2772494141
Short name T337
Test name
Test status
Simulation time 57120841 ps
CPU time 0.82 seconds
Started Aug 07 06:22:18 PM PDT 24
Finished Aug 07 06:22:20 PM PDT 24
Peak memory 207060 kb
Host smart-41a81025-f9da-4802-b98b-6a5f94329abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772494141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.2772494141
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.2105013905
Short name T229
Test name
Test status
Simulation time 12874283986 ps
CPU time 44.36 seconds
Started Aug 07 06:22:25 PM PDT 24
Finished Aug 07 06:23:09 PM PDT 24
Peak memory 249852 kb
Host smart-60dabcc9-4e9e-4953-a1ee-1a1abe14b68c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105013905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.2105013905
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.1861488377
Short name T698
Test name
Test status
Simulation time 18689617492 ps
CPU time 142.28 seconds
Started Aug 07 06:22:23 PM PDT 24
Finished Aug 07 06:24:45 PM PDT 24
Peak memory 239888 kb
Host smart-21853f34-ea9b-43e1-ac3d-9f980b418411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861488377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.1861488377
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.1350542790
Short name T967
Test name
Test status
Simulation time 26833545583 ps
CPU time 112.21 seconds
Started Aug 07 06:22:19 PM PDT 24
Finished Aug 07 06:24:12 PM PDT 24
Peak memory 255752 kb
Host smart-b3687e13-f363-43ce-8525-b39beac88c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350542790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.1350542790
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.1090312739
Short name T790
Test name
Test status
Simulation time 30695410258 ps
CPU time 223.2 seconds
Started Aug 07 06:22:23 PM PDT 24
Finished Aug 07 06:26:06 PM PDT 24
Peak memory 249904 kb
Host smart-e4abeb6e-1d2f-4fd3-99fb-1a22bd46ed98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090312739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmd
s.1090312739
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_intercept.1273329942
Short name T527
Test name
Test status
Simulation time 1075670771 ps
CPU time 8.43 seconds
Started Aug 07 06:22:15 PM PDT 24
Finished Aug 07 06:22:24 PM PDT 24
Peak memory 233476 kb
Host smart-be1c0886-0c7d-4e1a-af24-db7347ea2344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273329942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.1273329942
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.1004542711
Short name T968
Test name
Test status
Simulation time 547962572 ps
CPU time 12.97 seconds
Started Aug 07 06:22:16 PM PDT 24
Finished Aug 07 06:22:29 PM PDT 24
Peak memory 225312 kb
Host smart-78f76eb5-d7f7-4e27-9b73-22b48847d3b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004542711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.1004542711
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.2403912288
Short name T729
Test name
Test status
Simulation time 8728151135 ps
CPU time 25.28 seconds
Started Aug 07 06:22:24 PM PDT 24
Finished Aug 07 06:22:50 PM PDT 24
Peak memory 240216 kb
Host smart-b1cf172b-ca50-4b13-b7e8-edb5b0e42fcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403912288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.2403912288
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.3239286219
Short name T3
Test name
Test status
Simulation time 2074686338 ps
CPU time 4.53 seconds
Started Aug 07 06:22:15 PM PDT 24
Finished Aug 07 06:22:20 PM PDT 24
Peak memory 225292 kb
Host smart-c6ebe0f5-9c87-4faa-be54-c0848b41162a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239286219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.3239286219
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.2550109029
Short name T633
Test name
Test status
Simulation time 4434410735 ps
CPU time 4.16 seconds
Started Aug 07 06:22:25 PM PDT 24
Finished Aug 07 06:22:30 PM PDT 24
Peak memory 219708 kb
Host smart-6bdb0b32-eb74-4d7b-818d-0c10e37998f4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2550109029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.2550109029
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.1186101936
Short name T530
Test name
Test status
Simulation time 30080697391 ps
CPU time 89.6 seconds
Started Aug 07 06:22:23 PM PDT 24
Finished Aug 07 06:23:53 PM PDT 24
Peak memory 273772 kb
Host smart-7208f824-a0c4-4671-b122-622ab96044c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186101936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.1186101936
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.1333266898
Short name T317
Test name
Test status
Simulation time 5581964764 ps
CPU time 37.04 seconds
Started Aug 07 06:22:15 PM PDT 24
Finished Aug 07 06:22:53 PM PDT 24
Peak memory 217052 kb
Host smart-bb6abf4d-f887-44a9-a909-1b0f4eacde56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333266898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.1333266898
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.1248277155
Short name T921
Test name
Test status
Simulation time 1246916480 ps
CPU time 8.33 seconds
Started Aug 07 06:22:18 PM PDT 24
Finished Aug 07 06:22:26 PM PDT 24
Peak memory 216908 kb
Host smart-51947149-a614-4dd7-96dc-1318c58d1b92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248277155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.1248277155
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.824253267
Short name T814
Test name
Test status
Simulation time 829364203 ps
CPU time 6.45 seconds
Started Aug 07 06:22:15 PM PDT 24
Finished Aug 07 06:22:22 PM PDT 24
Peak memory 216920 kb
Host smart-6e4c4e5f-48a8-4909-ac38-f7ce9479e5d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824253267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.824253267
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.1084405386
Short name T411
Test name
Test status
Simulation time 78153032 ps
CPU time 0.77 seconds
Started Aug 07 06:22:24 PM PDT 24
Finished Aug 07 06:22:25 PM PDT 24
Peak memory 206540 kb
Host smart-f38e992d-3136-48cd-9074-182a52ab0d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084405386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.1084405386
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.306782587
Short name T535
Test name
Test status
Simulation time 885552727 ps
CPU time 11.01 seconds
Started Aug 07 06:22:23 PM PDT 24
Finished Aug 07 06:22:34 PM PDT 24
Peak memory 225232 kb
Host smart-2f0a8014-ac19-4729-9756-a128145ff162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306782587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.306782587
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.2303490084
Short name T681
Test name
Test status
Simulation time 21560126 ps
CPU time 0.74 seconds
Started Aug 07 06:22:27 PM PDT 24
Finished Aug 07 06:22:28 PM PDT 24
Peak memory 205272 kb
Host smart-2e409f16-a708-4a74-873f-e0c5333e7793
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303490084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
2303490084
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.2012375472
Short name T989
Test name
Test status
Simulation time 3773326675 ps
CPU time 11.14 seconds
Started Aug 07 06:22:25 PM PDT 24
Finished Aug 07 06:22:36 PM PDT 24
Peak memory 233516 kb
Host smart-0247d99f-cb96-4339-acb7-b685dc61744b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012375472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.2012375472
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.3973347604
Short name T922
Test name
Test status
Simulation time 19614672 ps
CPU time 0.74 seconds
Started Aug 07 06:22:21 PM PDT 24
Finished Aug 07 06:22:21 PM PDT 24
Peak memory 207396 kb
Host smart-b171e629-e2ca-416c-8300-9c35da9c3b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973347604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.3973347604
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.1745710154
Short name T937
Test name
Test status
Simulation time 171203889279 ps
CPU time 309.01 seconds
Started Aug 07 06:22:29 PM PDT 24
Finished Aug 07 06:27:38 PM PDT 24
Peak memory 256100 kb
Host smart-9cf27310-32d0-4227-a6ac-68506f4334a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745710154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.1745710154
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.626930176
Short name T277
Test name
Test status
Simulation time 26202910333 ps
CPU time 252.43 seconds
Started Aug 07 06:22:28 PM PDT 24
Finished Aug 07 06:26:41 PM PDT 24
Peak memory 255120 kb
Host smart-2058e27b-d999-48ac-baed-507b639d7349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626930176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.626930176
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.2225987944
Short name T550
Test name
Test status
Simulation time 3821542400 ps
CPU time 41.08 seconds
Started Aug 07 06:22:28 PM PDT 24
Finished Aug 07 06:23:09 PM PDT 24
Peak memory 234576 kb
Host smart-a4ad5ae8-9624-48ac-91a4-3df50e8ed257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225987944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.2225987944
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.296744280
Short name T659
Test name
Test status
Simulation time 133473432 ps
CPU time 2.32 seconds
Started Aug 07 06:22:23 PM PDT 24
Finished Aug 07 06:22:26 PM PDT 24
Peak memory 233424 kb
Host smart-36dea3e9-dbdd-4fb3-89c4-3f413a30c0df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296744280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.296744280
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.4106041861
Short name T962
Test name
Test status
Simulation time 11787394545 ps
CPU time 79.71 seconds
Started Aug 07 06:22:27 PM PDT 24
Finished Aug 07 06:23:47 PM PDT 24
Peak memory 250340 kb
Host smart-c5d56e63-15f6-4879-8290-17c4c6dcf2de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106041861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmd
s.4106041861
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_intercept.1508503501
Short name T626
Test name
Test status
Simulation time 232325142 ps
CPU time 3.59 seconds
Started Aug 07 06:22:26 PM PDT 24
Finished Aug 07 06:22:30 PM PDT 24
Peak memory 225200 kb
Host smart-9779c47d-abc4-47db-ad31-298e3459b183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508503501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.1508503501
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.804100713
Short name T1017
Test name
Test status
Simulation time 683727893 ps
CPU time 14.51 seconds
Started Aug 07 06:22:19 PM PDT 24
Finished Aug 07 06:22:33 PM PDT 24
Peak memory 233428 kb
Host smart-a879ef38-217e-458f-8fae-39c195e5c872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804100713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.804100713
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.151713326
Short name T965
Test name
Test status
Simulation time 3366201674 ps
CPU time 9.74 seconds
Started Aug 07 06:22:22 PM PDT 24
Finished Aug 07 06:22:32 PM PDT 24
Peak memory 225308 kb
Host smart-420ecfa3-7770-4656-8573-ca685afc1e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151713326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swap
.151713326
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.2793694880
Short name T329
Test name
Test status
Simulation time 1631019415 ps
CPU time 5.28 seconds
Started Aug 07 06:22:21 PM PDT 24
Finished Aug 07 06:22:26 PM PDT 24
Peak memory 225204 kb
Host smart-e2c22bbb-1a7f-4917-89fa-b4cdc4e1eea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793694880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.2793694880
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.1564431129
Short name T618
Test name
Test status
Simulation time 607668000 ps
CPU time 4.7 seconds
Started Aug 07 06:22:27 PM PDT 24
Finished Aug 07 06:22:32 PM PDT 24
Peak memory 223572 kb
Host smart-3d38ca16-1094-464c-894a-f90400221ac8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1564431129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.1564431129
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.1943802834
Short name T976
Test name
Test status
Simulation time 140163396 ps
CPU time 1.05 seconds
Started Aug 07 06:22:29 PM PDT 24
Finished Aug 07 06:22:30 PM PDT 24
Peak memory 207636 kb
Host smart-5799449f-3fcf-429e-aa33-e4d700e783e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943802834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.1943802834
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.1935025423
Short name T872
Test name
Test status
Simulation time 21404511 ps
CPU time 0.72 seconds
Started Aug 07 06:22:20 PM PDT 24
Finished Aug 07 06:22:21 PM PDT 24
Peak memory 206200 kb
Host smart-49312ee3-e5b2-46bd-9c21-0671d1fc2ccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935025423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.1935025423
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.212493996
Short name T977
Test name
Test status
Simulation time 5428810489 ps
CPU time 12.1 seconds
Started Aug 07 06:22:21 PM PDT 24
Finished Aug 07 06:22:33 PM PDT 24
Peak memory 217032 kb
Host smart-92101a04-60cb-4231-953f-a7f7be3cfd83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212493996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.212493996
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.1050544275
Short name T459
Test name
Test status
Simulation time 272617959 ps
CPU time 2.44 seconds
Started Aug 07 06:22:21 PM PDT 24
Finished Aug 07 06:22:24 PM PDT 24
Peak memory 216972 kb
Host smart-7d4c665e-05b5-42a4-9123-75da9afba63f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050544275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.1050544275
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.507836837
Short name T888
Test name
Test status
Simulation time 47226192 ps
CPU time 0.93 seconds
Started Aug 07 06:22:22 PM PDT 24
Finished Aug 07 06:22:23 PM PDT 24
Peak memory 206492 kb
Host smart-fc9b000b-3baf-4004-8d76-d718b9ff697d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507836837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.507836837
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.3452470773
Short name T188
Test name
Test status
Simulation time 34125357035 ps
CPU time 16.98 seconds
Started Aug 07 06:22:22 PM PDT 24
Finished Aug 07 06:22:39 PM PDT 24
Peak memory 225280 kb
Host smart-89255ad4-1c26-4cc0-be38-ff1da8ae3fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452470773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.3452470773
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.3153927079
Short name T964
Test name
Test status
Simulation time 14420207 ps
CPU time 0.71 seconds
Started Aug 07 06:22:31 PM PDT 24
Finished Aug 07 06:22:32 PM PDT 24
Peak memory 205856 kb
Host smart-c32256b4-9ca5-4708-b84e-5c47d8fbabd4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153927079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
3153927079
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.2154878659
Short name T674
Test name
Test status
Simulation time 103532784 ps
CPU time 2.58 seconds
Started Aug 07 06:22:29 PM PDT 24
Finished Aug 07 06:22:32 PM PDT 24
Peak memory 233432 kb
Host smart-9a251e99-ea3d-4a1d-8864-660952812402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154878659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.2154878659
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.2183807270
Short name T619
Test name
Test status
Simulation time 48915490 ps
CPU time 0.8 seconds
Started Aug 07 06:22:26 PM PDT 24
Finished Aug 07 06:22:26 PM PDT 24
Peak memory 207072 kb
Host smart-7be4feb2-eb52-4af2-93ef-210efbcf67e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183807270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.2183807270
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.2464062893
Short name T753
Test name
Test status
Simulation time 1888261233 ps
CPU time 36.39 seconds
Started Aug 07 06:22:30 PM PDT 24
Finished Aug 07 06:23:06 PM PDT 24
Peak memory 249824 kb
Host smart-041b2aa2-5160-40ec-b118-367838dffb53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464062893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.2464062893
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.683371542
Short name T469
Test name
Test status
Simulation time 67517535425 ps
CPU time 175.12 seconds
Started Aug 07 06:22:30 PM PDT 24
Finished Aug 07 06:25:25 PM PDT 24
Peak memory 255880 kb
Host smart-99d53692-b780-47d6-a80c-eb0b77a33d97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683371542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.683371542
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.362304659
Short name T311
Test name
Test status
Simulation time 5998630268 ps
CPU time 8.46 seconds
Started Aug 07 06:22:33 PM PDT 24
Finished Aug 07 06:22:41 PM PDT 24
Peak memory 218420 kb
Host smart-fdb28933-1389-4895-9635-a5944c9b2788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362304659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idle
.362304659
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.935381181
Short name T397
Test name
Test status
Simulation time 1657747230 ps
CPU time 24.5 seconds
Started Aug 07 06:22:26 PM PDT 24
Finished Aug 07 06:22:50 PM PDT 24
Peak memory 233452 kb
Host smart-b1a69ed7-ae2f-47d7-9b9e-4ccac40eb6d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935381181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.935381181
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.2496418354
Short name T607
Test name
Test status
Simulation time 2395987729 ps
CPU time 20.15 seconds
Started Aug 07 06:22:27 PM PDT 24
Finished Aug 07 06:22:47 PM PDT 24
Peak memory 233588 kb
Host smart-560bb149-6725-4dda-b928-8acdeb5cb044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496418354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmd
s.2496418354
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/47.spi_device_intercept.2214604025
Short name T129
Test name
Test status
Simulation time 427572868 ps
CPU time 2.77 seconds
Started Aug 07 06:22:30 PM PDT 24
Finished Aug 07 06:22:33 PM PDT 24
Peak memory 225232 kb
Host smart-0ec01079-b799-4330-845f-1038f7e71306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214604025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.2214604025
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.2212804690
Short name T579
Test name
Test status
Simulation time 105255392 ps
CPU time 2.44 seconds
Started Aug 07 06:22:29 PM PDT 24
Finished Aug 07 06:22:31 PM PDT 24
Peak memory 219148 kb
Host smart-c4bf80c4-fc76-4cbb-81d0-270ff63ed8c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212804690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.2212804690
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.2430874126
Short name T393
Test name
Test status
Simulation time 7171004389 ps
CPU time 24.77 seconds
Started Aug 07 06:22:29 PM PDT 24
Finished Aug 07 06:22:54 PM PDT 24
Peak memory 233512 kb
Host smart-e8158d31-a6d3-4e60-8e9b-f8d26c71bf96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430874126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.2430874126
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.1605000073
Short name T706
Test name
Test status
Simulation time 1153938580 ps
CPU time 5.92 seconds
Started Aug 07 06:22:28 PM PDT 24
Finished Aug 07 06:22:34 PM PDT 24
Peak memory 233432 kb
Host smart-237b7c8f-9a65-4287-8397-8f83ae80f73e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605000073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.1605000073
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.558801101
Short name T13
Test name
Test status
Simulation time 1149587341 ps
CPU time 5.72 seconds
Started Aug 07 06:22:31 PM PDT 24
Finished Aug 07 06:22:37 PM PDT 24
Peak memory 219276 kb
Host smart-e4bdefef-a89f-4be6-a0ef-444a9f8ba9b3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=558801101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dire
ct.558801101
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.51749864
Short name T985
Test name
Test status
Simulation time 3010866946 ps
CPU time 19.49 seconds
Started Aug 07 06:22:40 PM PDT 24
Finished Aug 07 06:23:00 PM PDT 24
Peak memory 233564 kb
Host smart-0c5f5bca-347e-4ed4-8d2c-0ce80b44227b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51749864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stress
_all.51749864
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.1938316042
Short name T377
Test name
Test status
Simulation time 18839397966 ps
CPU time 26.93 seconds
Started Aug 07 06:22:29 PM PDT 24
Finished Aug 07 06:22:56 PM PDT 24
Peak memory 220416 kb
Host smart-5ef8e193-ef83-4126-88ee-7b7078619672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938316042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.1938316042
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.3283904034
Short name T409
Test name
Test status
Simulation time 9222366417 ps
CPU time 12.4 seconds
Started Aug 07 06:22:28 PM PDT 24
Finished Aug 07 06:22:40 PM PDT 24
Peak memory 217020 kb
Host smart-f6d20d15-5efa-4143-809e-8f781d4ee86a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283904034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.3283904034
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.3128367634
Short name T333
Test name
Test status
Simulation time 318237970 ps
CPU time 3.73 seconds
Started Aug 07 06:22:27 PM PDT 24
Finished Aug 07 06:22:31 PM PDT 24
Peak memory 216968 kb
Host smart-73c4affd-dd59-4fb3-9f78-aca190ee79a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128367634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.3128367634
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.3833948975
Short name T656
Test name
Test status
Simulation time 24228136 ps
CPU time 0.77 seconds
Started Aug 07 06:22:29 PM PDT 24
Finished Aug 07 06:22:30 PM PDT 24
Peak memory 206584 kb
Host smart-93e0772d-918a-4aaa-833f-a542667c82d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833948975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.3833948975
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.2296191219
Short name T552
Test name
Test status
Simulation time 4302059045 ps
CPU time 14.97 seconds
Started Aug 07 06:22:26 PM PDT 24
Finished Aug 07 06:22:41 PM PDT 24
Peak memory 233532 kb
Host smart-1f62baed-7f23-4400-9591-a3bf914f8d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296191219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.2296191219
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.1290664170
Short name T788
Test name
Test status
Simulation time 132358594 ps
CPU time 0.75 seconds
Started Aug 07 06:22:34 PM PDT 24
Finished Aug 07 06:22:35 PM PDT 24
Peak memory 205748 kb
Host smart-6db20f31-4fb1-44cb-8bc7-4997d8b0e64f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290664170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
1290664170
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.3929569807
Short name T163
Test name
Test status
Simulation time 141503968 ps
CPU time 2.72 seconds
Started Aug 07 06:22:40 PM PDT 24
Finished Aug 07 06:22:43 PM PDT 24
Peak memory 225252 kb
Host smart-c8b746ef-fbae-48ce-a040-dabb001171c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929569807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.3929569807
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.704756552
Short name T841
Test name
Test status
Simulation time 48110613 ps
CPU time 0.74 seconds
Started Aug 07 06:22:38 PM PDT 24
Finished Aug 07 06:22:39 PM PDT 24
Peak memory 206416 kb
Host smart-c707c03d-c879-4bac-92a6-a225a255ae6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704756552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.704756552
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.703039223
Short name T235
Test name
Test status
Simulation time 37120080145 ps
CPU time 251.11 seconds
Started Aug 07 06:22:29 PM PDT 24
Finished Aug 07 06:26:40 PM PDT 24
Peak memory 255380 kb
Host smart-e11ed6ac-8a14-42b4-adef-a908ea88d8d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703039223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.703039223
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.1340718535
Short name T926
Test name
Test status
Simulation time 43343400766 ps
CPU time 104.04 seconds
Started Aug 07 06:22:32 PM PDT 24
Finished Aug 07 06:24:17 PM PDT 24
Peak memory 250936 kb
Host smart-5d54c1c6-f317-4525-a8d2-6085d8f6e19c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340718535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.1340718535
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.86067513
Short name T638
Test name
Test status
Simulation time 94542374609 ps
CPU time 35.9 seconds
Started Aug 07 06:22:43 PM PDT 24
Finished Aug 07 06:23:19 PM PDT 24
Peak memory 218408 kb
Host smart-6fe4a26d-6dc6-43ec-ba0b-a57f235689d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86067513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idle.86067513
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.3959975976
Short name T767
Test name
Test status
Simulation time 1212829251 ps
CPU time 8.55 seconds
Started Aug 07 06:22:30 PM PDT 24
Finished Aug 07 06:22:39 PM PDT 24
Peak memory 249876 kb
Host smart-836d6325-f0b3-43bc-b6ce-0bb7be797b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959975976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.3959975976
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.215618879
Short name T843
Test name
Test status
Simulation time 9211055772 ps
CPU time 89.77 seconds
Started Aug 07 06:22:31 PM PDT 24
Finished Aug 07 06:24:01 PM PDT 24
Peak memory 249952 kb
Host smart-a8eded8c-9fbd-48a4-91b2-52616970669d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215618879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmds
.215618879
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/48.spi_device_intercept.1092272921
Short name T197
Test name
Test status
Simulation time 541418422 ps
CPU time 3.62 seconds
Started Aug 07 06:22:33 PM PDT 24
Finished Aug 07 06:22:37 PM PDT 24
Peak memory 225204 kb
Host smart-bf3f4bed-290d-46e2-ba27-f238e4975ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092272921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.1092272921
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.383089719
Short name T728
Test name
Test status
Simulation time 19433959326 ps
CPU time 43.62 seconds
Started Aug 07 06:22:40 PM PDT 24
Finished Aug 07 06:23:24 PM PDT 24
Peak memory 233408 kb
Host smart-43611e83-7e2f-4e21-b987-84e313540470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383089719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.383089719
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.146767222
Short name T449
Test name
Test status
Simulation time 117811527 ps
CPU time 2.57 seconds
Started Aug 07 06:22:32 PM PDT 24
Finished Aug 07 06:22:34 PM PDT 24
Peak memory 233040 kb
Host smart-8b7d8e00-7b70-4b90-a086-e4f6f34f19b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146767222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swap
.146767222
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.1525197039
Short name T290
Test name
Test status
Simulation time 252308677 ps
CPU time 2.63 seconds
Started Aug 07 06:22:38 PM PDT 24
Finished Aug 07 06:22:41 PM PDT 24
Peak memory 233360 kb
Host smart-8cfe458c-288f-44a1-b8ae-19c466d8c293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525197039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.1525197039
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.3886375107
Short name T492
Test name
Test status
Simulation time 832896815 ps
CPU time 5.32 seconds
Started Aug 07 06:22:31 PM PDT 24
Finished Aug 07 06:22:36 PM PDT 24
Peak memory 223252 kb
Host smart-1100e175-0a7b-4c5f-9627-9b68e36064dc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3886375107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.3886375107
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.2915719841
Short name T655
Test name
Test status
Simulation time 88239554837 ps
CPU time 137.69 seconds
Started Aug 07 06:22:31 PM PDT 24
Finished Aug 07 06:24:49 PM PDT 24
Peak memory 267472 kb
Host smart-e17e9587-44e2-4045-9a8f-c4c0d52f6850
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915719841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.2915719841
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.1150083226
Short name T777
Test name
Test status
Simulation time 3382857061 ps
CPU time 17.26 seconds
Started Aug 07 06:22:31 PM PDT 24
Finished Aug 07 06:22:48 PM PDT 24
Peak memory 217172 kb
Host smart-8406f654-f311-44d9-b468-0b781a61170c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150083226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.1150083226
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.2557671004
Short name T712
Test name
Test status
Simulation time 2985802181 ps
CPU time 5.53 seconds
Started Aug 07 06:22:39 PM PDT 24
Finished Aug 07 06:22:45 PM PDT 24
Peak memory 217116 kb
Host smart-45800a9b-da58-423e-8d8a-e59748b22f59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557671004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.2557671004
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.979574287
Short name T338
Test name
Test status
Simulation time 135787171 ps
CPU time 0.96 seconds
Started Aug 07 06:22:30 PM PDT 24
Finished Aug 07 06:22:31 PM PDT 24
Peak memory 208480 kb
Host smart-1467d4fe-b12e-4edc-9a10-1193bbd1a511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979574287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.979574287
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.2820673424
Short name T520
Test name
Test status
Simulation time 25414357 ps
CPU time 0.83 seconds
Started Aug 07 06:22:40 PM PDT 24
Finished Aug 07 06:22:41 PM PDT 24
Peak memory 206580 kb
Host smart-affeeaf7-77fa-4515-98a8-f685f85e1b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820673424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.2820673424
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.1142777466
Short name T827
Test name
Test status
Simulation time 4802021020 ps
CPU time 5.22 seconds
Started Aug 07 06:22:39 PM PDT 24
Finished Aug 07 06:22:45 PM PDT 24
Peak memory 225312 kb
Host smart-b1f3a62b-26ec-4723-9201-4a7819950e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142777466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.1142777466
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.3457813303
Short name T917
Test name
Test status
Simulation time 39378557 ps
CPU time 0.7 seconds
Started Aug 07 06:22:43 PM PDT 24
Finished Aug 07 06:22:44 PM PDT 24
Peak memory 205824 kb
Host smart-6111511c-f8bc-4f9e-806b-804be3fd3aea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457813303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
3457813303
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.3216428805
Short name T471
Test name
Test status
Simulation time 415200579 ps
CPU time 2.38 seconds
Started Aug 07 06:22:41 PM PDT 24
Finished Aug 07 06:22:43 PM PDT 24
Peak memory 223904 kb
Host smart-8f8e2fd3-cea1-496a-9ca4-8339fa97a380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216428805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.3216428805
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.60497145
Short name T549
Test name
Test status
Simulation time 41493917 ps
CPU time 0.73 seconds
Started Aug 07 06:22:38 PM PDT 24
Finished Aug 07 06:22:39 PM PDT 24
Peak memory 206024 kb
Host smart-7f330565-660d-4d78-a219-44e931bcf62b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60497145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.60497145
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.385089302
Short name T940
Test name
Test status
Simulation time 14880675642 ps
CPU time 108.61 seconds
Started Aug 07 06:22:38 PM PDT 24
Finished Aug 07 06:24:27 PM PDT 24
Peak memory 250008 kb
Host smart-599c2482-6c24-4665-b929-4331084ba92a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385089302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.385089302
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.1324922907
Short name T893
Test name
Test status
Simulation time 33059049345 ps
CPU time 317.35 seconds
Started Aug 07 06:22:36 PM PDT 24
Finished Aug 07 06:27:54 PM PDT 24
Peak memory 253788 kb
Host smart-70ef182b-031f-45bf-9478-37af070c907b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324922907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.1324922907
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.4245807984
Short name T205
Test name
Test status
Simulation time 97018566258 ps
CPU time 555.89 seconds
Started Aug 07 06:22:41 PM PDT 24
Finished Aug 07 06:31:57 PM PDT 24
Peak memory 266360 kb
Host smart-a4581be8-f08d-4ee2-91ee-238475bb7c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245807984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.4245807984
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.3901992056
Short name T620
Test name
Test status
Simulation time 2090806424 ps
CPU time 35.46 seconds
Started Aug 07 06:22:42 PM PDT 24
Finished Aug 07 06:23:18 PM PDT 24
Peak memory 233476 kb
Host smart-38cb1469-9406-42ff-88c5-216c8819d369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901992056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.3901992056
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.920902817
Short name T204
Test name
Test status
Simulation time 46462653821 ps
CPU time 309.74 seconds
Started Aug 07 06:22:42 PM PDT 24
Finished Aug 07 06:27:52 PM PDT 24
Peak memory 249772 kb
Host smart-ca4a6f6b-41e0-4e66-8936-8f19fbdf25d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920902817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmds
.920902817
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/49.spi_device_intercept.791235461
Short name T598
Test name
Test status
Simulation time 2194018282 ps
CPU time 5.08 seconds
Started Aug 07 06:22:32 PM PDT 24
Finished Aug 07 06:22:37 PM PDT 24
Peak memory 225460 kb
Host smart-5c787c53-4337-4f23-808c-f185a73aa582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791235461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.791235461
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.2475565629
Short name T588
Test name
Test status
Simulation time 189498527 ps
CPU time 6.13 seconds
Started Aug 07 06:22:33 PM PDT 24
Finished Aug 07 06:22:39 PM PDT 24
Peak memory 234476 kb
Host smart-70f761db-7b2d-459d-98cf-c270a7733d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475565629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.2475565629
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.3460629607
Short name T14
Test name
Test status
Simulation time 433547973 ps
CPU time 3.22 seconds
Started Aug 07 06:22:38 PM PDT 24
Finished Aug 07 06:22:42 PM PDT 24
Peak memory 225224 kb
Host smart-a7a8e28e-331e-4e20-8bdb-82a0434c9d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460629607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.3460629607
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.780777862
Short name T781
Test name
Test status
Simulation time 8920222592 ps
CPU time 12.64 seconds
Started Aug 07 06:22:36 PM PDT 24
Finished Aug 07 06:22:49 PM PDT 24
Peak memory 225276 kb
Host smart-09789c34-4a51-4191-83d6-368ed7c0ff5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780777862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.780777862
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.2180509598
Short name T564
Test name
Test status
Simulation time 1908276026 ps
CPU time 9.07 seconds
Started Aug 07 06:22:41 PM PDT 24
Finished Aug 07 06:22:50 PM PDT 24
Peak memory 222896 kb
Host smart-0d88a666-52f9-4e57-8479-1f26d16c55e0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2180509598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.2180509598
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.2122581659
Short name T685
Test name
Test status
Simulation time 735183422702 ps
CPU time 721.53 seconds
Started Aug 07 06:22:40 PM PDT 24
Finished Aug 07 06:34:42 PM PDT 24
Peak memory 285596 kb
Host smart-c6df16b5-9e61-4d21-b7e3-615a53271bbf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122581659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.2122581659
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.3927565883
Short name T842
Test name
Test status
Simulation time 11900173100 ps
CPU time 63.79 seconds
Started Aug 07 06:22:33 PM PDT 24
Finished Aug 07 06:23:37 PM PDT 24
Peak memory 216996 kb
Host smart-48e6fad2-57e7-4ad3-b7de-88375387a561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927565883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.3927565883
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.3836493094
Short name T10
Test name
Test status
Simulation time 8152814668 ps
CPU time 5.88 seconds
Started Aug 07 06:22:39 PM PDT 24
Finished Aug 07 06:22:45 PM PDT 24
Peak memory 217036 kb
Host smart-3e57399d-8d86-4c35-8f51-c03632206e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836493094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.3836493094
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.551571624
Short name T787
Test name
Test status
Simulation time 146882065 ps
CPU time 1.56 seconds
Started Aug 07 06:22:31 PM PDT 24
Finished Aug 07 06:22:33 PM PDT 24
Peak memory 216888 kb
Host smart-a292e14e-4940-4588-bb9f-21946a7c93c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551571624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.551571624
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.563628855
Short name T415
Test name
Test status
Simulation time 18731653 ps
CPU time 0.82 seconds
Started Aug 07 06:22:30 PM PDT 24
Finished Aug 07 06:22:31 PM PDT 24
Peak memory 206564 kb
Host smart-b305a760-656d-436e-a4d0-c16121f6a384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563628855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.563628855
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.2219383651
Short name T914
Test name
Test status
Simulation time 712256186 ps
CPU time 2.56 seconds
Started Aug 07 06:22:31 PM PDT 24
Finished Aug 07 06:22:34 PM PDT 24
Peak memory 233436 kb
Host smart-fe1ccbe9-43f7-4665-a9db-1d3a25d4293e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219383651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.2219383651
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.2696354611
Short name T878
Test name
Test status
Simulation time 41876479 ps
CPU time 0.73 seconds
Started Aug 07 06:20:07 PM PDT 24
Finished Aug 07 06:20:08 PM PDT 24
Peak memory 206248 kb
Host smart-887afe21-136e-4c59-9713-a11a83f7229c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696354611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.2
696354611
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.3965502430
Short name T49
Test name
Test status
Simulation time 538775497 ps
CPU time 4.33 seconds
Started Aug 07 06:20:01 PM PDT 24
Finished Aug 07 06:20:05 PM PDT 24
Peak memory 233432 kb
Host smart-36116a1b-5ced-4de2-83f5-237de2b1c588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965502430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.3965502430
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.53816719
Short name T323
Test name
Test status
Simulation time 34080148 ps
CPU time 0.81 seconds
Started Aug 07 06:20:03 PM PDT 24
Finished Aug 07 06:20:04 PM PDT 24
Peak memory 206952 kb
Host smart-435c95c8-1c53-4c86-b6e3-4aab62975cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53816719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.53816719
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.4004061930
Short name T945
Test name
Test status
Simulation time 31680793 ps
CPU time 0.79 seconds
Started Aug 07 06:20:02 PM PDT 24
Finished Aug 07 06:20:03 PM PDT 24
Peak memory 216460 kb
Host smart-6d4d1e94-b239-4879-841a-faabf8c40d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004061930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.4004061930
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.4180856910
Short name T702
Test name
Test status
Simulation time 49674183605 ps
CPU time 74.62 seconds
Started Aug 07 06:20:01 PM PDT 24
Finished Aug 07 06:21:15 PM PDT 24
Peak memory 239048 kb
Host smart-5d432709-7da6-4ca8-8210-28c4564bd11f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180856910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.4180856910
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.2031708905
Short name T844
Test name
Test status
Simulation time 3146889760 ps
CPU time 40.72 seconds
Started Aug 07 06:20:01 PM PDT 24
Finished Aug 07 06:20:42 PM PDT 24
Peak memory 249928 kb
Host smart-16701798-7ae3-441a-8741-61f8ce1e87b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031708905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.2031708905
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.3435603955
Short name T565
Test name
Test status
Simulation time 2260238919 ps
CPU time 24.16 seconds
Started Aug 07 06:20:04 PM PDT 24
Finished Aug 07 06:20:28 PM PDT 24
Peak memory 233540 kb
Host smart-d5192f95-37a9-4583-9491-f15575086a6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435603955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.3435603955
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.850339083
Short name T691
Test name
Test status
Simulation time 5883781811 ps
CPU time 52.17 seconds
Started Aug 07 06:20:01 PM PDT 24
Finished Aug 07 06:20:54 PM PDT 24
Peak memory 249924 kb
Host smart-68a35bf7-6e6e-48eb-971c-ef0ad22fed54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850339083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds.
850339083
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/5.spi_device_intercept.265563366
Short name T441
Test name
Test status
Simulation time 179134360 ps
CPU time 3.42 seconds
Started Aug 07 06:20:03 PM PDT 24
Finished Aug 07 06:20:07 PM PDT 24
Peak memory 225260 kb
Host smart-ccc3acec-ad18-4685-975d-1b0796d2ebd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265563366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.265563366
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.1776039349
Short name T754
Test name
Test status
Simulation time 16328152309 ps
CPU time 40.62 seconds
Started Aug 07 06:20:01 PM PDT 24
Finished Aug 07 06:20:42 PM PDT 24
Peak memory 225216 kb
Host smart-8b3cee67-1744-4a1f-b991-a83ef28b723b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776039349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.1776039349
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.2989788347
Short name T36
Test name
Test status
Simulation time 28568529 ps
CPU time 1.02 seconds
Started Aug 07 06:20:04 PM PDT 24
Finished Aug 07 06:20:05 PM PDT 24
Peak memory 218416 kb
Host smart-80cecb3e-7b71-4906-8912-da003eca532f
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989788347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.spi_device_mem_parity.2989788347
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.313305614
Short name T522
Test name
Test status
Simulation time 4001193521 ps
CPU time 5.54 seconds
Started Aug 07 06:20:02 PM PDT 24
Finished Aug 07 06:20:07 PM PDT 24
Peak memory 233408 kb
Host smart-a6b29b24-bbca-48cf-a666-cd3a24dc4cc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313305614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap.
313305614
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.479190441
Short name T773
Test name
Test status
Simulation time 150137973 ps
CPU time 2.74 seconds
Started Aug 07 06:20:02 PM PDT 24
Finished Aug 07 06:20:04 PM PDT 24
Peak memory 233384 kb
Host smart-af37a211-2560-46c8-a189-ffc032981ffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479190441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.479190441
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.645552854
Short name T140
Test name
Test status
Simulation time 1112524533 ps
CPU time 14.29 seconds
Started Aug 07 06:20:05 PM PDT 24
Finished Aug 07 06:20:20 PM PDT 24
Peak memory 220644 kb
Host smart-f9e954c6-d40a-41f9-a30e-40b6bb072a35
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=645552854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_direc
t.645552854
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.163680800
Short name T233
Test name
Test status
Simulation time 464682731344 ps
CPU time 800.96 seconds
Started Aug 07 06:20:06 PM PDT 24
Finished Aug 07 06:33:27 PM PDT 24
Peak memory 290472 kb
Host smart-e1ce0bd3-57b4-450d-94e3-98afd7aff20b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163680800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stress
_all.163680800
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.2081896109
Short name T480
Test name
Test status
Simulation time 2918835330 ps
CPU time 4.87 seconds
Started Aug 07 06:20:06 PM PDT 24
Finished Aug 07 06:20:11 PM PDT 24
Peak memory 217096 kb
Host smart-2b04eba8-bb51-4683-a784-4b6a70a9736a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081896109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.2081896109
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.2606625870
Short name T718
Test name
Test status
Simulation time 922778043 ps
CPU time 6.17 seconds
Started Aug 07 06:20:00 PM PDT 24
Finished Aug 07 06:20:06 PM PDT 24
Peak memory 217016 kb
Host smart-648a68e5-3160-47df-8a9b-055352ee8d9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606625870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.2606625870
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.2254910399
Short name T489
Test name
Test status
Simulation time 419222976 ps
CPU time 6.19 seconds
Started Aug 07 06:20:03 PM PDT 24
Finished Aug 07 06:20:10 PM PDT 24
Peak memory 217016 kb
Host smart-07e047fe-c56b-46d2-a231-421c91038557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254910399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.2254910399
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.3613724012
Short name T27
Test name
Test status
Simulation time 87459665 ps
CPU time 0.97 seconds
Started Aug 07 06:20:06 PM PDT 24
Finished Aug 07 06:20:07 PM PDT 24
Peak memory 207036 kb
Host smart-dbe5b374-1cc1-4eb0-9402-b105c6731b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613724012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.3613724012
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.1600273880
Short name T662
Test name
Test status
Simulation time 5978088733 ps
CPU time 22.19 seconds
Started Aug 07 06:20:00 PM PDT 24
Finished Aug 07 06:20:23 PM PDT 24
Peak memory 233928 kb
Host smart-d09c1048-29ae-40d8-bc81-3a50742444e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600273880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.1600273880
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.1640304368
Short name T339
Test name
Test status
Simulation time 11308574 ps
CPU time 0.72 seconds
Started Aug 07 06:20:27 PM PDT 24
Finished Aug 07 06:20:27 PM PDT 24
Peak memory 205848 kb
Host smart-f2e4c944-5550-4973-8f9e-ff65b75eba09
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640304368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.1
640304368
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.2668637555
Short name T126
Test name
Test status
Simulation time 1599236152 ps
CPU time 11.09 seconds
Started Aug 07 06:20:27 PM PDT 24
Finished Aug 07 06:20:39 PM PDT 24
Peak memory 225256 kb
Host smart-49d4a86f-9e81-4ce0-9821-17e1689fb018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668637555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.2668637555
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.3644103173
Short name T332
Test name
Test status
Simulation time 32150704 ps
CPU time 0.78 seconds
Started Aug 07 06:20:07 PM PDT 24
Finished Aug 07 06:20:08 PM PDT 24
Peak memory 207072 kb
Host smart-ab2d0783-fec9-4640-8c98-b8786f4fa41d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644103173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.3644103173
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.59198104
Short name T187
Test name
Test status
Simulation time 5742440172 ps
CPU time 78.73 seconds
Started Aug 07 06:20:07 PM PDT 24
Finished Aug 07 06:21:26 PM PDT 24
Peak memory 249908 kb
Host smart-6af64fea-fb8b-4cd2-9ebc-ce8ec2ebb411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59198104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.59198104
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.2745248028
Short name T153
Test name
Test status
Simulation time 31816827148 ps
CPU time 291.35 seconds
Started Aug 07 06:20:08 PM PDT 24
Finished Aug 07 06:24:59 PM PDT 24
Peak memory 257604 kb
Host smart-1011b6dd-cc9e-4f1d-927c-b091ab7dd404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745248028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.2745248028
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.276994387
Short name T319
Test name
Test status
Simulation time 11845364325 ps
CPU time 37.98 seconds
Started Aug 07 06:20:06 PM PDT 24
Finished Aug 07 06:20:44 PM PDT 24
Peak memory 233556 kb
Host smart-a4cbaad4-90bd-435b-b07f-8b9c6a63815f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276994387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle.
276994387
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.2185387336
Short name T862
Test name
Test status
Simulation time 1015391716 ps
CPU time 8.28 seconds
Started Aug 07 06:20:10 PM PDT 24
Finished Aug 07 06:20:19 PM PDT 24
Peak memory 225260 kb
Host smart-f75ba79a-5d5b-433f-bd3a-476bbcb2573e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185387336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.2185387336
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.3055368759
Short name T47
Test name
Test status
Simulation time 5005445877 ps
CPU time 48.53 seconds
Started Aug 07 06:20:07 PM PDT 24
Finished Aug 07 06:20:56 PM PDT 24
Peak memory 249776 kb
Host smart-eeef2aee-f054-4304-bda7-51c1b515c2b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055368759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds
.3055368759
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/6.spi_device_intercept.2131848309
Short name T648
Test name
Test status
Simulation time 3014821188 ps
CPU time 32.47 seconds
Started Aug 07 06:20:10 PM PDT 24
Finished Aug 07 06:20:43 PM PDT 24
Peak memory 233516 kb
Host smart-3f9a80fb-d04c-4caa-a393-1e912d6cbce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131848309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.2131848309
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.339674803
Short name T444
Test name
Test status
Simulation time 934786770 ps
CPU time 11.62 seconds
Started Aug 07 06:20:07 PM PDT 24
Finished Aug 07 06:20:19 PM PDT 24
Peak memory 233420 kb
Host smart-598e9b34-8f04-4fa5-9af4-df2b6374501a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339674803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.339674803
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.3445354353
Short name T822
Test name
Test status
Simulation time 33127568 ps
CPU time 1.14 seconds
Started Aug 07 06:20:08 PM PDT 24
Finished Aug 07 06:20:10 PM PDT 24
Peak memory 217220 kb
Host smart-310be721-6833-4be5-ad26-0b35a72e8073
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445354353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.spi_device_mem_parity.3445354353
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.513628306
Short name T478
Test name
Test status
Simulation time 17869450255 ps
CPU time 11.57 seconds
Started Aug 07 06:20:09 PM PDT 24
Finished Aug 07 06:20:21 PM PDT 24
Peak memory 233536 kb
Host smart-4fc40c0c-6d51-471c-9371-f142a7057a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513628306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap.
513628306
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.588040405
Short name T494
Test name
Test status
Simulation time 746825704 ps
CPU time 2.39 seconds
Started Aug 07 06:20:06 PM PDT 24
Finished Aug 07 06:20:08 PM PDT 24
Peak memory 225112 kb
Host smart-c5cd1b38-6226-42f1-81de-300fded27470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588040405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.588040405
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.2871745805
Short name T456
Test name
Test status
Simulation time 917433784 ps
CPU time 5.04 seconds
Started Aug 07 06:20:22 PM PDT 24
Finished Aug 07 06:20:27 PM PDT 24
Peak memory 223504 kb
Host smart-353ece81-5c80-4500-bcd1-690f90dfb6c1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2871745805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.2871745805
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.3047779646
Short name T933
Test name
Test status
Simulation time 216496451872 ps
CPU time 232.76 seconds
Started Aug 07 06:20:26 PM PDT 24
Finished Aug 07 06:24:19 PM PDT 24
Peak memory 266568 kb
Host smart-ae6acb72-651c-405f-b949-4b56f1c0e4b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047779646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.3047779646
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.1626485290
Short name T389
Test name
Test status
Simulation time 35257378971 ps
CPU time 29.55 seconds
Started Aug 07 06:20:10 PM PDT 24
Finished Aug 07 06:20:40 PM PDT 24
Peak memory 217088 kb
Host smart-cfaf0cfc-3ca5-4f03-ac70-d16578993794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626485290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.1626485290
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.642630267
Short name T772
Test name
Test status
Simulation time 7001933205 ps
CPU time 22.6 seconds
Started Aug 07 06:20:07 PM PDT 24
Finished Aug 07 06:20:29 PM PDT 24
Peak memory 216960 kb
Host smart-76409db9-2acb-44eb-aad3-1383398c030b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642630267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.642630267
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.2416538196
Short name T351
Test name
Test status
Simulation time 30244751 ps
CPU time 1.06 seconds
Started Aug 07 06:20:07 PM PDT 24
Finished Aug 07 06:20:09 PM PDT 24
Peak memory 207720 kb
Host smart-96353010-c0d6-4e07-8d8c-86ea701a27cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416538196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.2416538196
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.644875777
Short name T455
Test name
Test status
Simulation time 45554112 ps
CPU time 0.77 seconds
Started Aug 07 06:20:08 PM PDT 24
Finished Aug 07 06:20:09 PM PDT 24
Peak memory 206596 kb
Host smart-570651a1-6737-4ac6-bc8e-00eb52964e9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644875777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.644875777
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.3667012913
Short name T264
Test name
Test status
Simulation time 1718941984 ps
CPU time 7.37 seconds
Started Aug 07 06:20:06 PM PDT 24
Finished Aug 07 06:20:14 PM PDT 24
Peak memory 233460 kb
Host smart-9fbf13b8-4cce-433c-a3f1-b64224623b5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667012913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.3667012913
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.3051835264
Short name T398
Test name
Test status
Simulation time 40838117 ps
CPU time 0.7 seconds
Started Aug 07 06:20:22 PM PDT 24
Finished Aug 07 06:20:23 PM PDT 24
Peak memory 205256 kb
Host smart-1809ed38-d21b-4c84-b923-f119fda78ee1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051835264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.3
051835264
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.44878505
Short name T79
Test name
Test status
Simulation time 138671314 ps
CPU time 2.29 seconds
Started Aug 07 06:20:06 PM PDT 24
Finished Aug 07 06:20:09 PM PDT 24
Peak memory 225268 kb
Host smart-1f63f08a-261a-4033-8dc0-8e1ef9d1f698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44878505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.44878505
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.1035525048
Short name T557
Test name
Test status
Simulation time 14483181 ps
CPU time 0.77 seconds
Started Aug 07 06:20:09 PM PDT 24
Finished Aug 07 06:20:10 PM PDT 24
Peak memory 207020 kb
Host smart-b9b81a7b-d8cf-4e4f-8377-84087a7ae846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035525048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.1035525048
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.40679807
Short name T211
Test name
Test status
Simulation time 697086172714 ps
CPU time 290.27 seconds
Started Aug 07 06:20:07 PM PDT 24
Finished Aug 07 06:24:57 PM PDT 24
Peak memory 249928 kb
Host smart-b23bfbc8-2d51-4c48-996d-e906645cf7e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40679807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.40679807
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.1168351756
Short name T267
Test name
Test status
Simulation time 11507041495 ps
CPU time 161.81 seconds
Started Aug 07 06:20:08 PM PDT 24
Finished Aug 07 06:22:50 PM PDT 24
Peak memory 265520 kb
Host smart-bec947a7-2b3c-48e7-ae8a-fc2718d318a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168351756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.1168351756
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.3859794099
Short name T234
Test name
Test status
Simulation time 12134662620 ps
CPU time 127.45 seconds
Started Aug 07 06:20:07 PM PDT 24
Finished Aug 07 06:22:15 PM PDT 24
Peak memory 254152 kb
Host smart-9600bb31-fb32-44c0-bcb1-bdba2a30c297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859794099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.3859794099
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.2586116862
Short name T710
Test name
Test status
Simulation time 2361302745 ps
CPU time 32.51 seconds
Started Aug 07 06:20:06 PM PDT 24
Finished Aug 07 06:20:39 PM PDT 24
Peak memory 240216 kb
Host smart-1e1348fa-f691-4cb9-949e-118e97d4b7ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586116862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.2586116862
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.520816931
Short name T809
Test name
Test status
Simulation time 82620424703 ps
CPU time 139.16 seconds
Started Aug 07 06:20:05 PM PDT 24
Finished Aug 07 06:22:25 PM PDT 24
Peak memory 266800 kb
Host smart-1f81ab4f-7d4f-4e3d-93fa-f8b6112a67c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520816931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds.
520816931
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_intercept.3039852975
Short name T686
Test name
Test status
Simulation time 415467423 ps
CPU time 2.34 seconds
Started Aug 07 06:20:07 PM PDT 24
Finished Aug 07 06:20:10 PM PDT 24
Peak memory 225236 kb
Host smart-d4a3211d-9a2b-4c32-8bed-ee0a706d603d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039852975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.3039852975
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.3020435047
Short name T1004
Test name
Test status
Simulation time 102275759 ps
CPU time 2.24 seconds
Started Aug 07 06:20:08 PM PDT 24
Finished Aug 07 06:20:10 PM PDT 24
Peak memory 233120 kb
Host smart-5ec8287d-9bce-4fa8-a8b8-e2497aefc169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020435047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.3020435047
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.3710526014
Short name T462
Test name
Test status
Simulation time 217382519 ps
CPU time 1 seconds
Started Aug 07 06:20:25 PM PDT 24
Finished Aug 07 06:20:26 PM PDT 24
Peak memory 217192 kb
Host smart-5e8de70b-7835-4bb0-b5ba-d920b04fe138
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710526014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.spi_device_mem_parity.3710526014
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.122446458
Short name T615
Test name
Test status
Simulation time 2918595649 ps
CPU time 4.38 seconds
Started Aug 07 06:20:25 PM PDT 24
Finished Aug 07 06:20:35 PM PDT 24
Peak memory 229712 kb
Host smart-152d554a-7663-4b31-bfff-294a09e0cbdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122446458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap.
122446458
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.2926612576
Short name T664
Test name
Test status
Simulation time 15813154327 ps
CPU time 15.73 seconds
Started Aug 07 06:20:09 PM PDT 24
Finished Aug 07 06:20:24 PM PDT 24
Peak memory 233464 kb
Host smart-41824e64-db2c-4c78-a7b6-ee4617e179e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926612576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.2926612576
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.1988959178
Short name T537
Test name
Test status
Simulation time 1957505427 ps
CPU time 9.42 seconds
Started Aug 07 06:20:07 PM PDT 24
Finished Aug 07 06:20:17 PM PDT 24
Peak memory 219312 kb
Host smart-f5ecb550-7dbb-4921-90f2-d5bdc797d98d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1988959178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.1988959178
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.1478868752
Short name T703
Test name
Test status
Simulation time 3666956276 ps
CPU time 3.45 seconds
Started Aug 07 06:20:26 PM PDT 24
Finished Aug 07 06:20:30 PM PDT 24
Peak memory 225200 kb
Host smart-7b06056a-f169-4238-89a4-adcce2557076
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478868752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.1478868752
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.1867763865
Short name T1027
Test name
Test status
Simulation time 11939949 ps
CPU time 0.74 seconds
Started Aug 07 06:20:07 PM PDT 24
Finished Aug 07 06:20:08 PM PDT 24
Peak memory 206172 kb
Host smart-9393dacf-d07d-4f4a-947b-ab2626fd7622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867763865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.1867763865
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.199910749
Short name T600
Test name
Test status
Simulation time 10515868442 ps
CPU time 4.71 seconds
Started Aug 07 06:20:11 PM PDT 24
Finished Aug 07 06:20:15 PM PDT 24
Peak memory 217080 kb
Host smart-98c061cc-bec3-4ad9-a6e9-4ae1f1389386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199910749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.199910749
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.1638887068
Short name T45
Test name
Test status
Simulation time 204821323 ps
CPU time 3.93 seconds
Started Aug 07 06:20:08 PM PDT 24
Finished Aug 07 06:20:12 PM PDT 24
Peak memory 216908 kb
Host smart-4e27169a-4b58-4e14-9de7-3df5490c6e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638887068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.1638887068
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.4083312726
Short name T574
Test name
Test status
Simulation time 33338705 ps
CPU time 0.75 seconds
Started Aug 07 06:20:07 PM PDT 24
Finished Aug 07 06:20:08 PM PDT 24
Peak memory 206576 kb
Host smart-4a4cbe43-75d2-4f48-bd4c-ce0840935bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083312726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.4083312726
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.1337896387
Short name T528
Test name
Test status
Simulation time 43631927798 ps
CPU time 30.62 seconds
Started Aug 07 06:20:06 PM PDT 24
Finished Aug 07 06:20:37 PM PDT 24
Peak memory 233540 kb
Host smart-6c48f34d-3704-4920-99c0-babb1f46f6b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337896387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.1337896387
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.163507598
Short name T724
Test name
Test status
Simulation time 49293953 ps
CPU time 0.7 seconds
Started Aug 07 06:20:16 PM PDT 24
Finished Aug 07 06:20:17 PM PDT 24
Peak memory 205804 kb
Host smart-7e15fefd-27a5-44a1-85bb-4f10899e0ffa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163507598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.163507598
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.3791512187
Short name T818
Test name
Test status
Simulation time 190980628 ps
CPU time 2.61 seconds
Started Aug 07 06:20:13 PM PDT 24
Finished Aug 07 06:20:15 PM PDT 24
Peak memory 233404 kb
Host smart-8a923f49-9d52-4b4f-80c1-4653cc17ff38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791512187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.3791512187
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.475474564
Short name T932
Test name
Test status
Simulation time 13911165 ps
CPU time 0.77 seconds
Started Aug 07 06:20:06 PM PDT 24
Finished Aug 07 06:20:07 PM PDT 24
Peak memory 206048 kb
Host smart-ff811567-5bc6-49ab-9748-3a34930ca0b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475474564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.475474564
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.142474718
Short name T43
Test name
Test status
Simulation time 27771956139 ps
CPU time 179.71 seconds
Started Aug 07 06:20:14 PM PDT 24
Finished Aug 07 06:23:14 PM PDT 24
Peak memory 266072 kb
Host smart-1da357ea-5541-40d3-a4e6-aa70b6d16d80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142474718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.142474718
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.3038658779
Short name T172
Test name
Test status
Simulation time 1056983345908 ps
CPU time 915.36 seconds
Started Aug 07 06:20:13 PM PDT 24
Finished Aug 07 06:35:28 PM PDT 24
Peak memory 274548 kb
Host smart-05ce3999-a653-4458-b921-53f7beb8bfb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038658779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.3038658779
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.1831907801
Short name T387
Test name
Test status
Simulation time 12331881762 ps
CPU time 19.07 seconds
Started Aug 07 06:20:15 PM PDT 24
Finished Aug 07 06:20:35 PM PDT 24
Peak memory 225332 kb
Host smart-10d088fc-8600-4e29-b920-45425fee80c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831907801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.1831907801
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.230396678
Short name T539
Test name
Test status
Simulation time 1975221441 ps
CPU time 27.57 seconds
Started Aug 07 06:20:14 PM PDT 24
Finished Aug 07 06:20:42 PM PDT 24
Peak memory 234784 kb
Host smart-b6904848-ec3a-4957-9187-82b318c19ce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230396678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.230396678
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.3924338944
Short name T257
Test name
Test status
Simulation time 1064193752 ps
CPU time 25.45 seconds
Started Aug 07 06:20:12 PM PDT 24
Finished Aug 07 06:20:37 PM PDT 24
Peak memory 255184 kb
Host smart-f2abad18-c5b5-49a6-a27e-a0f83f5ea9a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924338944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds
.3924338944
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/8.spi_device_intercept.754455928
Short name T561
Test name
Test status
Simulation time 1338697778 ps
CPU time 6.28 seconds
Started Aug 07 06:20:12 PM PDT 24
Finished Aug 07 06:20:18 PM PDT 24
Peak memory 219492 kb
Host smart-db4c94d7-c4d1-4153-bc8a-a40d63c4133c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754455928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.754455928
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.1494748451
Short name T840
Test name
Test status
Simulation time 235174372 ps
CPU time 4.36 seconds
Started Aug 07 06:20:13 PM PDT 24
Finished Aug 07 06:20:18 PM PDT 24
Peak memory 233476 kb
Host smart-6319cd71-7e83-4c02-b09b-221df6cab7e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494748451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.1494748451
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.3966750446
Short name T956
Test name
Test status
Simulation time 17844836 ps
CPU time 1.05 seconds
Started Aug 07 06:20:26 PM PDT 24
Finished Aug 07 06:20:27 PM PDT 24
Peak memory 217192 kb
Host smart-24cd5d47-e3f6-4957-a108-c9c6c0bcd5ba
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966750446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.spi_device_mem_parity.3966750446
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.2779414971
Short name T1031
Test name
Test status
Simulation time 2358164060 ps
CPU time 8.91 seconds
Started Aug 07 06:20:13 PM PDT 24
Finished Aug 07 06:20:22 PM PDT 24
Peak memory 233516 kb
Host smart-468ac26a-c3c5-42d5-85af-048e980bb611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779414971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.2779414971
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.2169271860
Short name T159
Test name
Test status
Simulation time 978213074 ps
CPU time 2.97 seconds
Started Aug 07 06:20:16 PM PDT 24
Finished Aug 07 06:20:19 PM PDT 24
Peak memory 233456 kb
Host smart-f6a6f23c-e96e-46e7-8ce9-38bcf4fd7aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169271860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.2169271860
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.2545216260
Short name T392
Test name
Test status
Simulation time 2689417308 ps
CPU time 8.9 seconds
Started Aug 07 06:20:16 PM PDT 24
Finished Aug 07 06:20:25 PM PDT 24
Peak memory 223736 kb
Host smart-172525bc-46f5-481a-91ea-cd37c57497f1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2545216260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.2545216260
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.2703000524
Short name T782
Test name
Test status
Simulation time 16830154645 ps
CPU time 22.59 seconds
Started Aug 07 06:20:17 PM PDT 24
Finished Aug 07 06:20:39 PM PDT 24
Peak memory 217204 kb
Host smart-27aab892-adee-4fcc-a7a4-c83602d85e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703000524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.2703000524
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.3457187690
Short name T929
Test name
Test status
Simulation time 801685729 ps
CPU time 6.15 seconds
Started Aug 07 06:20:14 PM PDT 24
Finished Aug 07 06:20:21 PM PDT 24
Peak memory 216956 kb
Host smart-018ad4d6-40b9-4992-91f3-0c966cf2f240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457187690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.3457187690
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.2610940013
Short name T995
Test name
Test status
Simulation time 215965483 ps
CPU time 1.47 seconds
Started Aug 07 06:20:15 PM PDT 24
Finished Aug 07 06:20:17 PM PDT 24
Peak memory 216932 kb
Host smart-837aba8e-46b7-4fe8-be83-bd360195ea96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610940013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.2610940013
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.1977975955
Short name T627
Test name
Test status
Simulation time 138822828 ps
CPU time 0.77 seconds
Started Aug 07 06:20:15 PM PDT 24
Finished Aug 07 06:20:16 PM PDT 24
Peak memory 206548 kb
Host smart-10b450ee-8c37-49f1-9add-a5ec57c0c4fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977975955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.1977975955
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.2716014415
Short name T1015
Test name
Test status
Simulation time 62886788 ps
CPU time 2.22 seconds
Started Aug 07 06:20:14 PM PDT 24
Finished Aug 07 06:20:16 PM PDT 24
Peak memory 225236 kb
Host smart-4aa40744-4994-48af-8ba4-db4bebe28772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716014415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.2716014415
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.4293720225
Short name T763
Test name
Test status
Simulation time 12445251 ps
CPU time 0.79 seconds
Started Aug 07 06:20:25 PM PDT 24
Finished Aug 07 06:20:26 PM PDT 24
Peak memory 206212 kb
Host smart-4eae510a-5df9-4a7e-af43-090fc9a071ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293720225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.4
293720225
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.1061256685
Short name T354
Test name
Test status
Simulation time 117865021 ps
CPU time 2.03 seconds
Started Aug 07 06:20:14 PM PDT 24
Finished Aug 07 06:20:16 PM PDT 24
Peak memory 225256 kb
Host smart-8e8a9a09-2352-428e-bd36-bf1383acf3fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061256685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.1061256685
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.1310557662
Short name T372
Test name
Test status
Simulation time 37120226 ps
CPU time 0.75 seconds
Started Aug 07 06:20:26 PM PDT 24
Finished Aug 07 06:20:27 PM PDT 24
Peak memory 207100 kb
Host smart-26a609d7-b401-4151-ae46-97d02a3fe721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310557662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.1310557662
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.2567362683
Short name T436
Test name
Test status
Simulation time 2248891491 ps
CPU time 44.42 seconds
Started Aug 07 06:20:13 PM PDT 24
Finished Aug 07 06:20:58 PM PDT 24
Peak memory 255756 kb
Host smart-e6ee5495-cd28-4f05-a902-90cd600abb0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567362683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.2567362683
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.4061662837
Short name T694
Test name
Test status
Simulation time 14401332836 ps
CPU time 65.71 seconds
Started Aug 07 06:20:16 PM PDT 24
Finished Aug 07 06:21:21 PM PDT 24
Peak memory 236300 kb
Host smart-6acad904-1c21-4a6d-bf8b-57656394c8f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061662837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.4061662837
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.1060844133
Short name T521
Test name
Test status
Simulation time 23769018671 ps
CPU time 173.14 seconds
Started Aug 07 06:20:16 PM PDT 24
Finished Aug 07 06:23:09 PM PDT 24
Peak memory 252072 kb
Host smart-954c5343-ef1a-4fb9-bfc2-248648b80ba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060844133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.1060844133
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.1094733284
Short name T1011
Test name
Test status
Simulation time 37235287 ps
CPU time 2.93 seconds
Started Aug 07 06:20:12 PM PDT 24
Finished Aug 07 06:20:15 PM PDT 24
Peak memory 233432 kb
Host smart-15c9147f-1af6-4c80-858b-9057bfa7ba28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094733284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.1094733284
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.1298501999
Short name T239
Test name
Test status
Simulation time 17358990019 ps
CPU time 117.95 seconds
Started Aug 07 06:20:13 PM PDT 24
Finished Aug 07 06:22:11 PM PDT 24
Peak memory 266288 kb
Host smart-5ee4dee0-c7ee-40f5-a14d-f2d5e02631af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298501999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds
.1298501999
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/9.spi_device_intercept.1450205136
Short name T847
Test name
Test status
Simulation time 4274833081 ps
CPU time 11.49 seconds
Started Aug 07 06:20:14 PM PDT 24
Finished Aug 07 06:20:26 PM PDT 24
Peak memory 233468 kb
Host smart-1190cd77-cb58-4fa5-be11-b16a2b80738d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450205136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.1450205136
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.1528439804
Short name T285
Test name
Test status
Simulation time 2256165584 ps
CPU time 5.82 seconds
Started Aug 07 06:20:13 PM PDT 24
Finished Aug 07 06:20:19 PM PDT 24
Peak memory 233572 kb
Host smart-531c0b91-8388-4f2e-a278-82d2ddf27aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528439804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.1528439804
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.1915573264
Short name T636
Test name
Test status
Simulation time 29272602 ps
CPU time 1.02 seconds
Started Aug 07 06:20:13 PM PDT 24
Finished Aug 07 06:20:15 PM PDT 24
Peak memory 218428 kb
Host smart-fabee71b-e14f-44d8-9a37-a54fd80863db
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915573264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.spi_device_mem_parity.1915573264
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.4122312672
Short name T481
Test name
Test status
Simulation time 3677434143 ps
CPU time 4.15 seconds
Started Aug 07 06:20:14 PM PDT 24
Finished Aug 07 06:20:18 PM PDT 24
Peak memory 233536 kb
Host smart-33455974-6da6-49da-a16a-866086a118b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122312672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.4122312672
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.1304652616
Short name T723
Test name
Test status
Simulation time 332379125 ps
CPU time 5.52 seconds
Started Aug 07 06:20:14 PM PDT 24
Finished Aug 07 06:20:19 PM PDT 24
Peak memory 239268 kb
Host smart-7af67165-c944-42e8-b0c4-ed904a55af8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304652616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.1304652616
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.355541880
Short name T403
Test name
Test status
Simulation time 1891002652 ps
CPU time 13.67 seconds
Started Aug 07 06:20:14 PM PDT 24
Finished Aug 07 06:20:28 PM PDT 24
Peak memory 221552 kb
Host smart-7a93e1d5-7f61-4420-9aea-db8fcf9dc8ef
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=355541880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_direc
t.355541880
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.572548196
Short name T21
Test name
Test status
Simulation time 224172650 ps
CPU time 0.98 seconds
Started Aug 07 06:20:16 PM PDT 24
Finished Aug 07 06:20:17 PM PDT 24
Peak memory 208200 kb
Host smart-f2a9d9bd-0723-4576-8162-3f21fc0c614b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572548196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stress
_all.572548196
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.3940394111
Short name T316
Test name
Test status
Simulation time 454464495 ps
CPU time 4.09 seconds
Started Aug 07 06:20:17 PM PDT 24
Finished Aug 07 06:20:21 PM PDT 24
Peak memory 216980 kb
Host smart-548510d3-241d-4378-82e4-1eb5dc85ab08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940394111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.3940394111
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.3891318217
Short name T708
Test name
Test status
Simulation time 3439825113 ps
CPU time 5.27 seconds
Started Aug 07 06:20:17 PM PDT 24
Finished Aug 07 06:20:22 PM PDT 24
Peak memory 217048 kb
Host smart-6aa0b876-ba9c-422a-ae87-498bcc082a6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891318217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.3891318217
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.4284246762
Short name T714
Test name
Test status
Simulation time 234875241 ps
CPU time 6.4 seconds
Started Aug 07 06:20:15 PM PDT 24
Finished Aug 07 06:20:21 PM PDT 24
Peak memory 217012 kb
Host smart-8da3415a-b085-4923-a82c-b814cea9974c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284246762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.4284246762
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.98231519
Short name T515
Test name
Test status
Simulation time 81244257 ps
CPU time 0.93 seconds
Started Aug 07 06:20:14 PM PDT 24
Finished Aug 07 06:20:16 PM PDT 24
Peak memory 207588 kb
Host smart-f2906fef-01f4-4b05-b42d-b3f82fd7a43b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98231519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.98231519
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.2607143875
Short name T200
Test name
Test status
Simulation time 1213975873 ps
CPU time 3.63 seconds
Started Aug 07 06:20:11 PM PDT 24
Finished Aug 07 06:20:15 PM PDT 24
Peak memory 233480 kb
Host smart-864b3ab1-9ea9-4aea-a2fc-ba68407a580a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607143875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.2607143875
Directory /workspace/9.spi_device_upload/latest
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