Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2702058	1			T1	1		T3	437		T4	60849
all_values[1]	2702058	1			T1	1		T3	437		T4	60849
all_values[2]	2702058	1			T1	1		T3	437		T4	60849
all_values[3]	2702058	1			T1	1		T3	437		T4	60849
all_values[4]	2702058	1			T1	1		T3	437		T4	60849
all_values[5]	2702058	1			T1	1		T3	437		T4	60849
all_values[6]	2702058	1			T1	1		T3	437		T4	60849
all_values[7]	2702058	1			T1	1		T3	437		T4	60849

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21467664

1

T1

8

T3

3496

T4

486792

auto[1]

148800

1

T14

35

T17

45

T19

102

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21588501

1

T1

8

T3

3496

T4

486341

auto[1]

27963

1

T4

451

T9

6

T11

43

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2677983	1			T1	1		T3	437		T4	60607
all_values[0]	auto[0]	auto[1]	13145	1			T4	242		T9	3		T11	15
all_values[0]	auto[1]	auto[0]	10683	1			T17	2		T19	8		T20	1
all_values[0]	auto[1]	auto[1]	247	1			T14	2		T17	1		T19	3
all_values[1]	auto[0]	auto[0]	2674386	1			T1	1		T3	437		T4	60717
all_values[1]	auto[0]	auto[1]	8557	1			T4	132		T9	3		T11	15
all_values[1]	auto[1]	auto[0]	18721	1			T14	4		T17	2		T19	11
all_values[1]	auto[1]	auto[1]	394	1			T14	2		T17	3		T19	5
all_values[2]	auto[0]	auto[0]	2677072	1			T1	1		T3	437		T4	60772
all_values[2]	auto[0]	auto[1]	3434	1			T4	77		T11	13		T14	6
all_values[2]	auto[1]	auto[0]	21275	1			T14	6		T17	1		T19	10
all_values[2]	auto[1]	auto[1]	277	1			T14	2		T17	3		T19	7
all_values[3]	auto[0]	auto[0]	2685780	1			T1	1		T3	437		T4	60849
all_values[3]	auto[0]	auto[1]	216	1			T14	4		T17	3		T19	6
all_values[3]	auto[1]	auto[0]	15855	1			T14	1		T17	5		T19	8
all_values[3]	auto[1]	auto[1]	207	1			T14	1		T17	1		T19	3
all_values[4]	auto[0]	auto[0]	2685035	1			T1	1		T3	437		T4	60849
all_values[4]	auto[0]	auto[1]	150	1			T17	6		T19	9		T21	4
all_values[4]	auto[1]	auto[0]	16694	1			T14	2		T17	1		T19	6
all_values[4]	auto[1]	auto[1]	179	1			T14	2		T17	2		T19	3
all_values[5]	auto[0]	auto[0]	2690271	1			T1	1		T3	437		T4	60849
all_values[5]	auto[0]	auto[1]	190	1			T17	3		T19	7		T21	6
all_values[5]	auto[1]	auto[0]	11419	1			T14	4		T17	1		T19	8
all_values[5]	auto[1]	auto[1]	178	1			T14	4		T17	4		T19	5
all_values[6]	auto[0]	auto[0]	2678134	1			T1	1		T3	437		T4	60849
all_values[6]	auto[0]	auto[1]	198	1			T14	2		T17	1		T19	9
all_values[6]	auto[1]	auto[0]	23542	1			T17	6		T19	2		T20	2
all_values[6]	auto[1]	auto[1]	184	1			T14	3		T17	4		T19	6
all_values[7]	auto[0]	auto[0]	2672907	1			T1	1		T3	437		T4	60849
all_values[7]	auto[0]	auto[1]	206	1			T14	4		T17	2		T19	3
all_values[7]	auto[1]	auto[0]	28744	1			T14	1		T17	4		T19	11
all_values[7]	auto[1]	auto[1]	201	1			T14	1		T17	5		T19	6