Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	34265	1			T3	41		T4	175		T9	226
auto[SpiFlashAddrCfg]	7735	1			T1	2		T3	6		T4	40
auto[SpiFlashAddr3b]	9185	1			T3	2		T4	59		T9	56
auto[SpiFlashAddr4b]	7696	1			T1	2		T4	46		T7	2

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33181

1

T3

41

T4

179

T7

2

auto[1]

25700

1

T1

4

T3

8

T4

141

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31143

1

T1

4

T3

13

T4

183

auto[1]

27738

1

T3

36

T4

137

T9

163

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	39091	1			T1	2		T3	43		T4	210
values[1]	1210	1			T1	2		T4	11		T9	4
values[2]	1437	1			T3	2		T4	5		T9	4
values[3]	1455	1			T4	3		T9	9		T11	2
values[4]	1431	1			T4	15		T9	13		T11	6
values[5]	1459	1			T3	1		T4	13		T9	8
values[6]	1452	1			T3	1		T4	3		T9	12
values[7]	1382	1			T4	7		T7	1		T9	6
values[8]	9964	1			T3	2		T4	53		T7	1

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33030

1

T1

4

T3

49

T8

2

auto[1]

25851

1

T4

320

T7

2

T9

388

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

55419

1

T1

2

T3

47

T4

289

write

3462

1

T1

2

T3

2

T4

31

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

19326

1

T3

10

T4

122

T7

2

valids[0x1]

39555

1

T1

4

T3

39

T4

198

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1580	1			T3	1		T4	16		T9	17
internal_process_ops[0x5a]	1528	1			T4	13		T9	15		T11	5
internal_process_ops[0x05]	20259	1			T3	29		T4	51		T9	116
internal_process_ops[0x35]	1543	1			T3	2		T4	17		T9	11
internal_process_ops[0x15]	1635	1			T3	1		T4	12		T9	15
internal_process_ops[0x03]	1088	1			T4	3		T11	1		T14	3
internal_process_ops[0x0b]	1004	1			T1	2		T4	3		T9	4
internal_process_ops[0x3b]	1060	1			T4	5		T9	4		T11	2
internal_process_ops[0x6b]	1055	1			T4	5		T9	6		T11	3
internal_process_ops[0xbb]	1033	1			T3	1		T4	4		T7	1
internal_process_ops[0xeb]	1073	1			T3	1		T4	4		T7	1

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

57199

1

T1

2

T3

48

T4

312

auto[1]

1682

1

T1

2

T3

1

T4

8

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

56496

1

T1

4

T3

46

T4

302

auto[1]

2385

1

T3

3

T4

18

T9

14

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

11449

1

T3

37

T11

9

T14

24

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7206

1

T3

4

T11

3

T14

24

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2050

1

T3

1

T8

2

T11

2

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1886

1

T1

2

T3

3

T11

3

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2466

1

T3

2

T10

6

T11

11

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2242

1

T11

4

T14

15

T15

4

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2102

1

T11

4

T14

11

T28

4

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1889

1

T11

6

T14

6

T36

26

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

136

1

T10

2

T16

1

T17

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

96

1

T36

2

T16

3

T163

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

77

1

T16

2

T43

3

T82

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

104

1

T16

1

T43

1

T17

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

133

1

T36

2

T47

2

T100

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

118

1

T3

1

T14

1

T43

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

96

1

T3

1

T17

2

T102

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

107

1

T36

3

T16

1

T44

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

132

1

T36

2

T16

5

T100

4

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

106

1

T14

1

T16

1

T17

3

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

118

1

T36

2

T16

2

T18

3

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

108

1

T14

2

T42

2

T17

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

107

1

T36

2

T17

1

T18

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

87

1

T11

1

T36

3

T16

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

105

1

T11

1

T36

1

T43

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

110

1

T1

2

T36

1

T17

1

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

8700

1

T4

101

T9

99

T35

34

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6077

1

T4

66

T9

118

T35

20

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1421

1

T4

19

T9

26

T35

13

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1479

1

T4

13

T9

19

T35

15

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1807

1

T4

24

T9

36

T35

15

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1808

1

T4

26

T9

19

T35

10

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1422

1

T4

16

T7

2

T9

23

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1415

1

T4

24

T9

20

T35

10

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

109

1

T4

1

T9

3

T35

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

98

1

T4

3

T35

1

T16

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

95

1

T4

2

T9

3

T16

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

118

1

T4

2

T9

3

T35

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

97

1

T4

3

T9

2

T35

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

103

1

T9

3

T16

1

T79

4

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

127

1

T4

4

T35

2

T16

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

118

1

T4

1

T9

5

T16

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

101

1

T4

8

T35

1

T86

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

99

1

T35

1

T16

3

T18

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

101

1

T4

1

T9

1

T35

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

97

1

T16

4

T79

3

T164

4

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

137

1

T4

3

T9

1

T16

4

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

105

1

T4

1

T9

2

T79

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

109

1

T4

1

T35

4

T79

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

108

1

T4

1

T9

5

T35

1

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3979	1			T3	7		T11	8		T14	22
auto[0]	values[0]	valids[0x1]	17748	1			T1	2		T3	36		T10	2
auto[0]	values[1]	valids[0x1]	617	1			T1	2		T14	2		T28	2
auto[0]	values[2]	valids[0x0]	508	1			T3	1		T10	2		T14	2
auto[0]	values[2]	valids[0x1]	318	1			T3	1		T11	1		T14	6
auto[0]	values[3]	valids[0x0]	555	1			T11	2		T14	1		T36	2
auto[0]	values[3]	valids[0x1]	259	1			T14	3		T36	1		T43	4
auto[0]	values[4]	valids[0x0]	537	1			T11	2		T14	2		T36	8
auto[0]	values[4]	valids[0x1]	322	1			T11	4		T14	1		T36	3
auto[0]	values[5]	valids[0x0]	569	1			T3	1		T11	1		T14	2
auto[0]	values[5]	valids[0x1]	292	1			T42	2		T36	4		T16	2
auto[0]	values[6]	valids[0x0]	519	1			T3	1		T11	1		T14	3
auto[0]	values[6]	valids[0x1]	282	1			T14	1		T36	3		T16	1
auto[0]	values[7]	valids[0x0]	519	1			T14	4		T15	2		T36	5
auto[0]	values[7]	valids[0x1]	295	1			T14	4		T36	1		T16	3
auto[0]	values[8]	valids[0x0]	3632	1			T8	2		T10	4		T11	8
auto[0]	values[8]	valids[0x1]	2079	1			T3	2		T11	2		T14	13
auto[1]	values[0]	valids[0x0]	3824	1			T4	68		T9	61		T35	28
auto[1]	values[0]	valids[0x1]	13540	1			T4	142		T9	201		T35	51
auto[1]	values[1]	valids[0x1]	593	1			T4	11		T9	4		T16	6
auto[1]	values[2]	valids[0x0]	391	1			T4	2		T9	4		T35	7
auto[1]	values[2]	valids[0x1]	220	1			T4	3		T16	3		T79	2
auto[1]	values[3]	valids[0x0]	389	1			T4	3		T9	5		T35	2
auto[1]	values[3]	valids[0x1]	252	1			T9	4		T35	1		T16	6
auto[1]	values[4]	valids[0x0]	383	1			T4	10		T9	8		T35	5
auto[1]	values[4]	valids[0x1]	189	1			T4	5		T9	5		T16	2
auto[1]	values[5]	valids[0x0]	361	1			T4	8		T9	5		T35	2
auto[1]	values[5]	valids[0x1]	237	1			T4	5		T9	3		T35	2
auto[1]	values[6]	valids[0x0]	398	1			T4	3		T9	2		T35	4
auto[1]	values[6]	valids[0x1]	253	1			T9	10		T35	3		T16	1
auto[1]	values[7]	valids[0x0]	335	1			T4	2		T7	1		T9	3
auto[1]	values[7]	valids[0x1]	233	1			T4	5		T9	3		T35	4
auto[1]	values[8]	valids[0x0]	2427	1			T4	26		T7	1		T9	46
auto[1]	values[8]	valids[0x1]	1826	1			T4	27		T9	24		T35	10