Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3273347

1

T1

1

T3

2903

T4

16446

auto[1]

30646

1

T3

29

T4

40

T9

108

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

842167

1

T1

1

T3

11

T4

111

auto[1]

2461826

1

T3

2921

T4

16375

T9

11710

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	627053	1			T1	1		T3	129		T4	4388
auto[524288:1048575]	385544	1			T4	1048		T9	1314		T14	3512
auto[1048576:1572863]	351403	1			T4	3438		T9	261		T11	4
auto[1572864:2097151]	403152	1			T4	24		T7	22		T9	1549
auto[2097152:2621439]	378567	1			T4	1425		T7	3		T9	544
auto[2621440:3145727]	371961	1			T4	3369		T7	105		T9	3477
auto[3145728:3670015]	413291	1			T3	2796		T4	1144		T9	2180
auto[3670016:4194303]	373022	1			T3	7		T4	1650		T9	351

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2494856

1

T1

1

T3

2930

T4

16481

auto[1]

809137

1

T3

2

T4

5

T7

115

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2848337

1

T1

1

T3

2931

T4

11084

auto[1]

455656

1

T3

1

T4

5402

T9

1713

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	193766	1			T1	1		T3	1		T4	10
auto[0]	auto[0]	auto[0:524287]	auto[1]	355701	1			T3	128		T4	4368		T9	2112
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	100045	1			T9	11		T14	6		T87	4293
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	241950	1			T9	773		T14	3504		T36	2572
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	73722	1			T4	14		T9	1		T11	2
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	206460	1			T4	650		T9	256		T11	1
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	99344	1			T4	3		T7	22		T9	6
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	246856	1			T4	12		T9	512		T11	2558
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	94850	1			T4	4		T7	3		T9	6
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	214515	1			T4	1235		T9	518		T11	1
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	99680	1			T4	15		T7	105		T9	13
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	229073	1			T4	2574		T9	3280		T11	1
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	72957	1			T3	5		T4	8		T9	8
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	273876	1			T3	2766		T4	513		T9	2171
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	94061	1			T3	1		T4	9		T9	3
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	225307	1			T3	1		T4	1636		T9	326
auto[0]	auto[1]	auto[0:524287]	auto[0]	2168	1			T4	2		T16	6		T17	2
auto[0]	auto[1]	auto[0:524287]	auto[1]	70742	1			T16	1575		T17	2100		T102	129
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	955	1			T4	10		T9	1		T36	2
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	39796	1			T4	1033		T9	512		T36	2118
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	3413	1			T4	3		T9	4		T35	3
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	62333	1			T4	2766		T16	540		T17	1
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	825	1			T4	2		T9	5		T35	21
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	53271	1			T9	1025		T35	517		T18	384
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	664	1			T4	4		T9	2		T35	37
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	65165	1			T4	181		T35	2051		T16	2886
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	653	1			T4	2		T9	5		T35	41
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	39412	1			T4	769		T9	129		T35	1283
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	592	1			T3	1		T4	5		T35	11
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	61535	1			T4	616		T35	256		T16	2769
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	574	1			T4	2		T9	4		T14	2
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	49086	1			T9	2		T35	804		T16	280
auto[1]	auto[0]	auto[0:524287]	auto[0]	496	1			T4	2		T9	1		T14	3
auto[1]	auto[0]	auto[0:524287]	auto[1]	3803	1			T4	6		T9	4		T14	1
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	392	1			T9	2		T14	1		T16	5
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	1984	1			T9	15		T14	1		T16	50
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	400	1			T4	1		T11	1		T36	3
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	4682	1			T4	3		T36	50		T79	20
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	371	1			T4	2		T35	9		T36	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	2215	1			T4	5		T36	4		T16	3
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	317	1			T4	1		T9	2		T11	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	1870	1			T9	16		T36	7		T16	15
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	424	1			T4	4		T9	4		T11	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	2268	1			T4	4		T9	39		T36	22
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	453	1			T3	2		T4	1		T9	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	3030	1			T3	22		T4	1		T35	2
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	408	1			T3	1		T4	1		T16	3
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	3061	1			T3	4		T4	2		T16	27
auto[1]	auto[1]	auto[0:524287]	auto[0]	40	1			T16	1		T17	2		T102	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	337	1			T17	1		T102	27		T217	1
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	83	1			T4	4		T36	1		T16	2
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	339	1			T4	1		T36	11		T16	16
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	78	1			T4	1		T35	3		T17	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	315	1			T20	1		T209	6		T189	23
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	49	1			T9	1		T195	1		T199	2
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	221	1			T227	8		T218	1		T48	10
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	86	1			T35	7		T16	2		T79	2
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	1100	1			T16	2		T79	3		T214	3
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	77	1			T4	1		T9	1		T16	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	374	1			T9	6		T16	2		T43	16
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	101	1			T35	4		T16	1		T17	2
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	747	1			T16	2		T17	1		T79	6
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	123	1			T9	2		T35	18		T20	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	402	1			T9	14		T205	1		T195	6

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	2018559	1			T1	1		T3	2901		T4	11050
auto[0]	auto[0]	auto[1]	803604	1			T3	1		T4	1		T7	115
auto[0]	auto[1]	auto[0]	446249	1			T3	1		T4	5395		T9	1686
auto[0]	auto[1]	auto[1]	4935	1			T9	3		T36	1		T80	9
auto[1]	auto[0]	auto[0]	25651	1			T3	28		T4	29		T9	79
auto[1]	auto[0]	auto[1]	523	1			T3	1		T4	4		T9	5
auto[1]	auto[1]	auto[0]	4397	1			T4	7		T9	22		T35	29
auto[1]	auto[1]	auto[1]	75	1			T9	2		T35	3		T36	1