Summary for Variable cp_intr_pin
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for cp_intr_pin
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_pins[0] |
2702058 |
1 |
|
|
T1 |
1 |
|
T3 |
437 |
|
T4 |
60849 |
all_pins[1] |
2702058 |
1 |
|
|
T1 |
1 |
|
T3 |
437 |
|
T4 |
60849 |
all_pins[2] |
2702058 |
1 |
|
|
T1 |
1 |
|
T3 |
437 |
|
T4 |
60849 |
all_pins[3] |
2702058 |
1 |
|
|
T1 |
1 |
|
T3 |
437 |
|
T4 |
60849 |
all_pins[4] |
2702058 |
1 |
|
|
T1 |
1 |
|
T3 |
437 |
|
T4 |
60849 |
all_pins[5] |
2702058 |
1 |
|
|
T1 |
1 |
|
T3 |
437 |
|
T4 |
60849 |
all_pins[6] |
2702058 |
1 |
|
|
T1 |
1 |
|
T3 |
437 |
|
T4 |
60849 |
all_pins[7] |
2702058 |
1 |
|
|
T1 |
1 |
|
T3 |
437 |
|
T4 |
60849 |
Summary for Variable cp_intr_pin_value
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for cp_intr_pin_value
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x0] |
21591306 |
1 |
|
|
T1 |
8 |
|
T3 |
3496 |
|
T4 |
486792 |
values[0x1] |
25158 |
1 |
|
|
T14 |
17 |
|
T17 |
23 |
|
T19 |
38 |
transitions[0x0=>0x1] |
24576 |
1 |
|
|
T14 |
10 |
|
T17 |
17 |
|
T19 |
28 |
transitions[0x1=>0x0] |
24590 |
1 |
|
|
T14 |
10 |
|
T17 |
17 |
|
T19 |
28 |
Summary for Cross cp_intr_pins_all_values
Samples crossed: cp_intr_pin cp_intr_pin_value
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
32 |
0 |
32 |
100.00 |
|
Automatically Generated Cross Bins for cp_intr_pins_all_values
Bins
cp_intr_pin | cp_intr_pin_value | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_pins[0] |
values[0x0] |
2701804 |
1 |
|
|
T1 |
1 |
|
T3 |
437 |
|
T4 |
60849 |
all_pins[0] |
values[0x1] |
254 |
1 |
|
|
T14 |
2 |
|
T17 |
1 |
|
T19 |
3 |
all_pins[0] |
transitions[0x0=>0x1] |
195 |
1 |
|
|
T14 |
1 |
|
T17 |
1 |
|
T19 |
2 |
all_pins[0] |
transitions[0x1=>0x0] |
358 |
1 |
|
|
T14 |
1 |
|
T17 |
3 |
|
T19 |
4 |
all_pins[1] |
values[0x0] |
2701641 |
1 |
|
|
T1 |
1 |
|
T3 |
437 |
|
T4 |
60849 |
all_pins[1] |
values[0x1] |
417 |
1 |
|
|
T14 |
2 |
|
T17 |
3 |
|
T19 |
5 |
all_pins[1] |
transitions[0x0=>0x1] |
346 |
1 |
|
|
T14 |
2 |
|
T17 |
1 |
|
T19 |
4 |
all_pins[1] |
transitions[0x1=>0x0] |
214 |
1 |
|
|
T14 |
2 |
|
T17 |
1 |
|
T19 |
6 |
all_pins[2] |
values[0x0] |
2701773 |
1 |
|
|
T1 |
1 |
|
T3 |
437 |
|
T4 |
60849 |
all_pins[2] |
values[0x1] |
285 |
1 |
|
|
T14 |
2 |
|
T17 |
3 |
|
T19 |
7 |
all_pins[2] |
transitions[0x0=>0x1] |
228 |
1 |
|
|
T14 |
1 |
|
T17 |
3 |
|
T19 |
7 |
all_pins[2] |
transitions[0x1=>0x0] |
150 |
1 |
|
|
T17 |
1 |
|
T19 |
3 |
|
T21 |
3 |
all_pins[3] |
values[0x0] |
2701851 |
1 |
|
|
T1 |
1 |
|
T3 |
437 |
|
T4 |
60849 |
all_pins[3] |
values[0x1] |
207 |
1 |
|
|
T14 |
1 |
|
T17 |
1 |
|
T19 |
3 |
all_pins[3] |
transitions[0x0=>0x1] |
154 |
1 |
|
|
T17 |
1 |
|
T19 |
3 |
|
T21 |
3 |
all_pins[3] |
transitions[0x1=>0x0] |
126 |
1 |
|
|
T14 |
1 |
|
T17 |
2 |
|
T19 |
3 |
all_pins[4] |
values[0x0] |
2701879 |
1 |
|
|
T1 |
1 |
|
T3 |
437 |
|
T4 |
60849 |
all_pins[4] |
values[0x1] |
179 |
1 |
|
|
T14 |
2 |
|
T17 |
2 |
|
T19 |
3 |
all_pins[4] |
transitions[0x0=>0x1] |
138 |
1 |
|
|
T17 |
2 |
|
T19 |
1 |
|
T21 |
1 |
all_pins[4] |
transitions[0x1=>0x0] |
318 |
1 |
|
|
T14 |
2 |
|
T17 |
4 |
|
T19 |
3 |
all_pins[5] |
values[0x0] |
2701699 |
1 |
|
|
T1 |
1 |
|
T3 |
437 |
|
T4 |
60849 |
all_pins[5] |
values[0x1] |
359 |
1 |
|
|
T14 |
4 |
|
T17 |
4 |
|
T19 |
5 |
all_pins[5] |
transitions[0x0=>0x1] |
182 |
1 |
|
|
T14 |
3 |
|
T17 |
2 |
|
T19 |
3 |
all_pins[5] |
transitions[0x1=>0x0] |
23079 |
1 |
|
|
T14 |
2 |
|
T17 |
2 |
|
T19 |
4 |
all_pins[6] |
values[0x0] |
2678802 |
1 |
|
|
T1 |
1 |
|
T3 |
437 |
|
T4 |
60849 |
all_pins[6] |
values[0x1] |
23256 |
1 |
|
|
T14 |
3 |
|
T17 |
4 |
|
T19 |
6 |
all_pins[6] |
transitions[0x0=>0x1] |
23191 |
1 |
|
|
T14 |
2 |
|
T17 |
3 |
|
T19 |
3 |
all_pins[6] |
transitions[0x1=>0x0] |
136 |
1 |
|
|
T17 |
4 |
|
T19 |
3 |
|
T21 |
1 |
all_pins[7] |
values[0x0] |
2701857 |
1 |
|
|
T1 |
1 |
|
T3 |
437 |
|
T4 |
60849 |
all_pins[7] |
values[0x1] |
201 |
1 |
|
|
T14 |
1 |
|
T17 |
5 |
|
T19 |
6 |
all_pins[7] |
transitions[0x0=>0x1] |
142 |
1 |
|
|
T14 |
1 |
|
T17 |
4 |
|
T19 |
5 |
all_pins[7] |
transitions[0x1=>0x0] |
209 |
1 |
|
|
T14 |
2 |
|
T19 |
2 |
|
T21 |
4 |