Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18982

1

T3

41

T8

2

T10

8

auto[1]

14048

1

T1

4

T3

8

T11

17

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4058	1			T8	2		T10	8		T15	8
values[1]	3866	1			T37	14		T36	20		T43	124
values[2]	3999	1			T14	22		T136	16		T43	20
values[3]	3985	1			T14	41		T88	12		T16	27
values[4]	4474	1			T36	62		T16	20		T43	51
values[5]	3932	1			T1	4		T11	22		T14	20
values[6]	3913	1			T3	49		T87	14		T36	37
values[7]	4803	1			T11	22		T14	44		T42	6

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4342	1			T42	6		T98	4		T88	12
values[1]	4026	1			T1	4		T3	49		T14	21
values[2]	4742	1			T14	64		T16	60		T43	51
values[3]	3883	1			T36	77		T16	22		T17	20
values[4]	3652	1			T10	8		T11	22		T37	14
values[5]	4670	1			T8	2		T11	22		T15	8
values[6]	3598	1			T14	20		T28	24		T36	37
values[7]	4117	1			T14	22		T80	12		T18	28

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	313	1			T36	6		T229	42		T81	12
auto[0]	values[0]	values[1]	182	1			T36	12		T17	13		T38	10
auto[0]	values[0]	values[2]	365	1			T102	14		T214	12		T208	27
auto[0]	values[0]	values[3]	430	1			T36	9		T16	16		T102	37
auto[0]	values[0]	values[4]	212	1			T10	8		T102	13		T230	2
auto[0]	values[0]	values[5]	414	1			T8	2		T36	18		T231	12
auto[0]	values[0]	values[6]	217	1			T16	17		T17	13		T206	6
auto[0]	values[0]	values[7]	397	1			T18	12		T22	5		T195	14
auto[0]	values[1]	values[0]	267	1			T201	15		T217	15		T232	4
auto[0]	values[1]	values[1]	389	1			T36	15		T100	87		T17	19
auto[0]	values[1]	values[2]	320	1			T195	128		T233	2		T53	13
auto[0]	values[1]	values[3]	451	1			T234	2		T82	17		T22	14
auto[0]	values[1]	values[4]	239	1			T37	14		T18	11		T235	2
auto[0]	values[1]	values[5]	126	1			T18	14		T158	8		T51	10
auto[0]	values[1]	values[6]	223	1			T43	8		T18	12		T163	15
auto[0]	values[1]	values[7]	264	1			T236	10		T82	11		T205	53
auto[0]	values[2]	values[0]	214	1			T200	14		T214	12		T183	24
auto[0]	values[2]	values[1]	261	1			T17	13		T205	12		T199	10
auto[0]	values[2]	values[2]	189	1			T208	11		T195	38		T71	17
auto[0]	values[2]	values[3]	464	1			T17	14		T151	16		T71	14
auto[0]	values[2]	values[4]	221	1			T43	11		T200	9		T177	6
auto[0]	values[2]	values[5]	361	1			T178	4		T237	2		T176	21
auto[0]	values[2]	values[6]	261	1			T136	16		T17	12		T200	12
auto[0]	values[2]	values[7]	345	1			T14	15		T80	12		T195	15
auto[0]	values[3]	values[0]	211	1			T88	12		T17	13		T238	13
auto[0]	values[3]	values[1]	230	1			T14	8		T176	10		T189	35
auto[0]	values[3]	values[2]	482	1			T226	10		T71	19		T158	10
auto[0]	values[3]	values[3]	255	1			T18	44		T102	15		T217	12
auto[0]	values[3]	values[4]	181	1			T16	21		T17	10		T200	8
auto[0]	values[3]	values[5]	371	1			T43	15		T82	8		T71	11
auto[0]	values[3]	values[6]	293	1			T14	13		T102	16		T163	10
auto[0]	values[3]	values[7]	193	1			T205	8		T189	15		T192	13
auto[0]	values[4]	values[0]	484	1			T16	10		T17	12		T200	10
auto[0]	values[4]	values[1]	536	1			T82	10		T158	9		T189	21
auto[0]	values[4]	values[2]	284	1			T43	32		T200	12		T199	17
auto[0]	values[4]	values[3]	134	1			T195	13		T194	18		T51	11
auto[0]	values[4]	values[4]	368	1			T36	12		T193	43		T195	14
auto[0]	values[4]	values[5]	305	1			T199	10		T210	9		T192	11
auto[0]	values[4]	values[6]	166	1			T53	6		T239	12		T138	13
auto[0]	values[4]	values[7]	189	1			T205	39		T208	10		T180	10
auto[0]	values[5]	values[0]	188	1			T36	10		T16	11		T22	16
auto[0]	values[5]	values[1]	287	1			T189	12		T240	76		T180	34
auto[0]	values[5]	values[2]	174	1			T14	10		T53	15		T180	16
auto[0]	values[5]	values[3]	243	1			T36	15		T205	13		T29	13
auto[0]	values[5]	values[4]	475	1			T11	11		T200	11		T82	11
auto[0]	values[5]	values[5]	380	1			T163	10		T200	13		T211	9
auto[0]	values[5]	values[6]	154	1			T16	12		T18	11		T51	12
auto[0]	values[5]	values[7]	310	1			T209	10		T210	14		T192	11
auto[0]	values[6]	values[0]	227	1			T241	4		T195	20		T242	14
auto[0]	values[6]	values[1]	299	1			T3	41		T87	14		T16	10
auto[0]	values[6]	values[2]	335	1			T243	6		T208	13		T195	13
auto[0]	values[6]	values[3]	175	1			T244	8		T245	10		T202	12
auto[0]	values[6]	values[4]	198	1			T82	14		T187	8		T176	7
auto[0]	values[6]	values[5]	395	1			T47	81		T17	19		T18	18
auto[0]	values[6]	values[6]	391	1			T36	29		T246	14		T190	22
auto[0]	values[6]	values[7]	240	1			T247	4		T196	14		T192	12
auto[0]	values[7]	values[0]	581	1			T98	4		T16	16		T248	6
auto[0]	values[7]	values[1]	269	1			T36	10		T214	10		T216	8
auto[0]	values[7]	values[2]	379	1			T14	20		T16	13		T83	4
auto[0]	values[7]	values[3]	159	1			T200	14		T249	12		T203	15
auto[0]	values[7]	values[4]	219	1			T17	52		T200	9		T180	16
auto[0]	values[7]	values[5]	324	1			T11	16		T17	23		T200	8
auto[0]	values[7]	values[6]	302	1			T28	24		T16	9		T102	9
auto[0]	values[7]	values[7]	471	1			T224	4		T205	19		T209	21
auto[1]	values[0]	values[0]	235	1			T36	14		T188	49		T29	10
auto[1]	values[0]	values[1]	131	1			T36	31		T17	10		T38	10
auto[1]	values[0]	values[2]	222	1			T102	6		T214	26		T208	3
auto[1]	values[0]	values[3]	263	1			T36	11		T16	6		T102	11
auto[1]	values[0]	values[4]	208	1			T102	7		T211	76		T51	30
auto[1]	values[0]	values[5]	169	1			T15	8		T36	9		T188	14
auto[1]	values[0]	values[6]	135	1			T16	3		T17	10		T188	9
auto[1]	values[0]	values[7]	165	1			T18	16		T22	15		T195	6
auto[1]	values[1]	values[0]	144	1			T201	5		T217	5		T250	14
auto[1]	values[1]	values[1]	174	1			T36	5		T17	7		T251	4
auto[1]	values[1]	values[2]	365	1			T207	16		T195	144		T53	7
auto[1]	values[1]	values[3]	260	1			T82	3		T22	46		T189	20
auto[1]	values[1]	values[4]	146	1			T18	9		T211	24		T51	9
auto[1]	values[1]	values[5]	126	1			T18	6		T158	13		T51	21
auto[1]	values[1]	values[6]	227	1			T43	116		T18	8		T163	6
auto[1]	values[1]	values[7]	145	1			T82	9		T205	13		T225	10
auto[1]	values[2]	values[0]	251	1			T200	6		T214	8		T183	18
auto[1]	values[2]	values[1]	298	1			T17	15		T205	106		T252	16
auto[1]	values[2]	values[2]	107	1			T208	9		T195	22		T71	6
auto[1]	values[2]	values[3]	152	1			T17	6		T71	9		T176	7
auto[1]	values[2]	values[4]	184	1			T43	9		T200	11		T177	14
auto[1]	values[2]	values[5]	193	1			T176	19		T253	7		T211	3
auto[1]	values[2]	values[6]	141	1			T17	10		T200	8		T177	5
auto[1]	values[2]	values[7]	357	1			T14	7		T195	13		T188	5
auto[1]	values[3]	values[0]	144	1			T17	9		T238	7		T239	7
auto[1]	values[3]	values[1]	148	1			T14	13		T176	10		T189	11
auto[1]	values[3]	values[2]	308	1			T71	3		T158	10		T29	10
auto[1]	values[3]	values[3]	179	1			T18	9		T102	5		T217	11
auto[1]	values[3]	values[4]	117	1			T16	6		T17	29		T200	12
auto[1]	values[3]	values[5]	537	1			T43	5		T82	12		T71	30
auto[1]	values[3]	values[6]	213	1			T14	7		T102	4		T163	14
auto[1]	values[3]	values[7]	123	1			T205	51		T189	5		T192	7
auto[1]	values[4]	values[0]	355	1			T16	10		T17	8		T200	10
auto[1]	values[4]	values[1]	181	1			T82	10		T158	11		T189	9
auto[1]	values[4]	values[2]	177	1			T43	19		T200	8		T199	8
auto[1]	values[4]	values[3]	89	1			T195	7		T194	7		T51	11
auto[1]	values[4]	values[4]	316	1			T36	50		T195	6		T158	7
auto[1]	values[4]	values[5]	340	1			T199	10		T210	11		T192	9
auto[1]	values[4]	values[6]	237	1			T53	15		T239	8		T138	7
auto[1]	values[4]	values[7]	313	1			T205	9		T208	17		T180	11
auto[1]	values[5]	values[0]	203	1			T36	10		T16	9		T22	17
auto[1]	values[5]	values[1]	143	1			T1	4		T189	8		T180	13
auto[1]	values[5]	values[2]	152	1			T14	10		T53	7		T180	6
auto[1]	values[5]	values[3]	378	1			T36	42		T205	58		T29	7
auto[1]	values[5]	values[4]	241	1			T11	11		T200	9		T82	9
auto[1]	values[5]	values[5]	282	1			T163	10		T200	7		T211	11
auto[1]	values[5]	values[6]	128	1			T16	8		T18	26		T51	10
auto[1]	values[5]	values[7]	194	1			T209	10		T210	11		T192	9
auto[1]	values[6]	values[0]	239	1			T195	3		T254	24		T50	12
auto[1]	values[6]	values[1]	262	1			T3	8		T16	10		T44	16
auto[1]	values[6]	values[2]	376	1			T208	7		T195	14		T189	14
auto[1]	values[6]	values[3]	128	1			T189	32		T255	14		T253	10
auto[1]	values[6]	values[4]	223	1			T82	6		T176	13		T29	15
auto[1]	values[6]	values[5]	130	1			T17	5		T18	10		T201	5
auto[1]	values[6]	values[6]	220	1			T36	8		T195	8		T71	9
auto[1]	values[6]	values[7]	75	1			T192	8		T256	14		T212	6
auto[1]	values[7]	values[0]	286	1			T42	6		T16	5		T48	41
auto[1]	values[7]	values[1]	236	1			T36	34		T214	14		T208	11
auto[1]	values[7]	values[2]	507	1			T14	24		T16	47		T177	6
auto[1]	values[7]	values[3]	123	1			T200	6		T203	5		T257	13
auto[1]	values[7]	values[4]	104	1			T17	8		T200	11		T180	4
auto[1]	values[7]	values[5]	217	1			T11	6		T17	24		T258	8
auto[1]	values[7]	values[6]	290	1			T16	26		T102	13		T189	12
auto[1]	values[7]	values[7]	336	1			T259	22		T205	14		T68	6