Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	431	1			T11	2		T36	4		T136	6
auto[ReadAddrCrossIntoMailbox]	277	1			T11	1		T36	4		T16	2
auto[ReadAddrCrossOutOfMailbox]	309	1			T36	3		T17	4		T18	3
auto[ReadAddrCrossAllMailbox]	229	1			T16	1		T17	2		T18	3
auto[ReadAddrOutsideMailbox]	3422	1			T1	2		T3	2		T8	2

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2274

1

T1

1

T3

1

T8

1

auto[1]

2394

1

T1

1

T3

1

T8

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	825	1			T11	1		T14	3		T28	2
read_ops[0x0b]	735	1			T1	2		T11	4		T14	3
read_ops[0x3b]	764	1			T11	2		T14	2		T36	7
read_ops[0x6b]	787	1			T11	3		T14	6		T37	2
read_ops[0xbb]	763	1			T3	1		T8	2		T11	1
read_ops[0xeb]	794	1			T3	1		T11	1		T14	3

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	33	1			T36	1		T163	1		T214	2
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	36	1			T200	1		T208	2		T177	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	18	1			T36	1		T102	1		T48	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	30	1			T200	1		T208	1		T188	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	22	1			T18	1		T200	1		T210	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	30	1			T36	1		T208	1		T188	2
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	19	1			T29	1		T53	1		T50	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	17	1			T17	1		T18	2		T177	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	291	1			T14	2		T28	1		T36	5
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	329	1			T11	1		T14	1		T28	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	31	1			T200	1		T209	1		T48	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	38	1			T11	1		T36	1		T163	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	30	1			T17	1		T177	1		T176	2
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	24	1			T11	1		T36	1		T17	2
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	29	1			T195	1		T188	1		T199	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	32	1			T201	1		T200	1		T82	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	30	1			T18	1		T163	1		T200	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	20	1			T200	1		T208	1		T158	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	268	1			T1	1		T14	1		T28	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	233	1			T1	1		T11	2		T14	2
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	37	1			T36	1		T136	1		T200	3
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	39	1			T11	1		T136	1		T244	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	24	1			T43	1		T208	1		T195	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	21	1			T36	1		T18	1		T214	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	27	1			T208	1		T195	1		T199	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	30	1			T18	1		T201	1		T208	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T71	1		T180	3		T260	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	14	1			T82	1		T189	1		T159	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	279	1			T11	1		T14	1		T36	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	276	1			T14	1		T36	4		T16	3
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	28	1			T36	1		T136	2		T43	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	37	1			T136	2		T201	1		T196	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	15	1			T36	1		T208	1		T48	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	28	1			T16	1		T188	1		T199	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	18	1			T17	3		T29	1		T261	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	26	1			T17	1		T163	2		T214	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	12	1			T176	1		T210	1		T262	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	18	1			T16	1		T22	2		T209	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	300	1			T14	6		T37	1		T36	5
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	305	1			T11	3		T37	1		T36	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	31	1			T243	1		T244	1		T177	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	35	1			T17	2		T163	1		T243	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	24	1			T17	1		T201	1		T200	2
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	14	1			T176	1		T210	1		T50	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	23	1			T36	1		T241	1		T214	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	32	1			T241	1		T200	2		T214	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	13	1			T241	1		T201	1		T211	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	23	1			T241	1		T176	1		T51	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	258	1			T3	1		T8	1		T11	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	310	1			T8	1		T14	3		T37	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	42	1			T200	1		T208	1		T196	3
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	44	1			T200	1		T214	2		T22	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	24	1			T16	1		T200	1		T176	2
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	25	1			T17	1		T102	1		T214	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	19	1			T36	1		T18	1		T71	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	21	1			T205	1		T176	1		T189	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	22	1			T17	1		T209	1		T199	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	24	1			T205	1		T188	1		T176	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	290	1			T14	2		T36	2		T16	2
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	283	1			T3	1		T11	1		T14	1