Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3516	1			T14	41		T98	4		T43	20
values[1]	4100	1			T14	22		T36	40		T17	68
values[2]	4584	1			T8	2		T14	44		T42	6
values[3]	4638	1			T1	4		T11	22		T14	20
values[4]	3637	1			T28	24		T87	14		T36	90
values[5]	4243	1			T11	22		T88	12		T100	87
values[6]	3897	1			T36	57		T16	45		T47	81
values[7]	4415	1			T3	49		T10	8		T15	8

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3692	1			T11	22		T16	67		T100	87
values[1]	3957	1			T10	8		T14	22		T37	14
values[2]	3232	1			T14	21		T36	37		T16	20
values[3]	4957	1			T8	2		T28	24		T87	14
values[4]	4159	1			T1	4		T3	49		T98	4
values[5]	4451	1			T14	20		T15	8		T88	12
values[6]	3996	1			T11	22		T14	23		T42	6
values[7]	4586	1			T14	41		T36	91		T43	20

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32194

1

T1

2

T3

48

T8

2

auto[1]

836

1

T1

2

T3

1

T11

1

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	456	1			T17	48		T18	18		T214	38
auto[0]	values[0]	values[1]	489	1			T241	4		T195	18		T177	23
auto[0]	values[0]	values[2]	404	1			T14	21		T151	16		T263	4
auto[0]	values[0]	values[3]	534	1			T200	17		T231	12		T195	26
auto[0]	values[0]	values[4]	274	1			T98	4		T200	19		T205	63
auto[0]	values[0]	values[5]	303	1			T180	53		T183	21		T191	28
auto[0]	values[0]	values[6]	369	1			T22	59		T71	39		T189	45
auto[0]	values[0]	values[7]	589	1			T14	20		T43	19		T200	20
auto[0]	values[1]	values[0]	411	1			T200	19		T248	6		T53	20
auto[0]	values[1]	values[1]	325	1			T14	21		T17	20		T22	20
auto[0]	values[1]	values[2]	544	1			T194	25		T192	47		T203	100
auto[0]	values[1]	values[3]	703	1			T36	18		T17	27		T208	20
auto[0]	values[1]	values[4]	449	1			T18	28		T214	38		T195	46
auto[0]	values[1]	values[5]	349	1			T188	70		T264	4		T180	23
auto[0]	values[1]	values[6]	718	1			T17	16		T102	20		T163	20
auto[0]	values[1]	values[7]	509	1			T36	18		T246	14		T205	116
auto[0]	values[2]	values[0]	451	1			T16	45		T200	19		T195	20
auto[0]	values[2]	values[1]	758	1			T153	6		T200	20		T217	22
auto[0]	values[2]	values[2]	364	1			T80	12		T195	19		T245	10
auto[0]	values[2]	values[3]	582	1			T8	2		T43	20		T18	20
auto[0]	values[2]	values[4]	468	1			T44	14		T82	18		T158	20
auto[0]	values[2]	values[5]	788	1			T102	20		T236	10		T188	19
auto[0]	values[2]	values[6]	435	1			T14	21		T42	4		T82	20
auto[0]	values[2]	values[7]	624	1			T14	20		T17	21		T102	22
auto[0]	values[3]	values[0]	704	1			T11	21		T82	19		T177	20
auto[0]	values[3]	values[1]	454	1			T37	14		T16	22		T158	60
auto[0]	values[3]	values[2]	303	1			T36	37		T16	20		T243	6
auto[0]	values[3]	values[3]	433	1			T226	10		T204	8		T205	46
auto[0]	values[3]	values[4]	863	1			T1	2		T43	30		T176	19
auto[0]	values[3]	values[5]	656	1			T14	20		T190	22		T200	18
auto[0]	values[3]	values[6]	447	1			T188	19		T180	20		T51	40
auto[0]	values[3]	values[7]	682	1			T17	22		T250	14		T192	59
auto[0]	values[4]	values[0]	247	1			T16	20		T197	20		T29	20
auto[0]	values[4]	values[1]	426	1			T36	20		T16	20		T43	20
auto[0]	values[4]	values[2]	446	1			T17	58		T200	18		T82	19
auto[0]	values[4]	values[3]	485	1			T28	24		T87	14		T36	42
auto[0]	values[4]	values[4]	530	1			T50	28		T239	20		T213	20
auto[0]	values[4]	values[5]	440	1			T81	12		T188	18		T199	19
auto[0]	values[4]	values[6]	710	1			T16	34		T229	42		T179	10
auto[0]	values[4]	values[7]	242	1			T36	26		T265	8		T261	16
auto[0]	values[5]	values[0]	483	1			T100	87		T189	20		T266	21
auto[0]	values[5]	values[1]	293	1			T206	6		T209	20		T50	20
auto[0]	values[5]	values[2]	407	1			T22	28		T223	4		T189	40
auto[0]	values[5]	values[3]	796	1			T18	28		T102	20		T208	25
auto[0]	values[5]	values[4]	489	1			T17	65		T102	48		T200	15
auto[0]	values[5]	values[5]	471	1			T88	12		T17	21		T210	20
auto[0]	values[5]	values[6]	546	1			T11	22		T188	58		T189	29
auto[0]	values[5]	values[7]	662	1			T18	53		T82	17		T237	2
auto[0]	values[6]	values[0]	395	1			T17	21		T201	18		T188	20
auto[0]	values[6]	values[1]	607	1			T16	25		T195	20		T209	22
auto[0]	values[6]	values[2]	401	1			T136	16		T163	21		T224	4
auto[0]	values[6]	values[3]	439	1			T176	31		T48	55		T267	8
auto[0]	values[6]	values[4]	274	1			T16	18		T222	6		T71	23
auto[0]	values[6]	values[5]	631	1			T36	54		T47	81		T18	37
auto[0]	values[6]	values[6]	384	1			T200	18		T29	20		T230	2
auto[0]	values[6]	values[7]	635	1			T38	20		T259	20		T193	43
auto[0]	values[7]	values[0]	437	1			T201	20		T234	2		T176	15
auto[0]	values[7]	values[1]	507	1			T10	8		T18	18		T82	20
auto[0]	values[7]	values[2]	265	1			T180	20		T261	29		T268	6
auto[0]	values[7]	values[3]	848	1			T36	62		T43	124		T17	19
auto[0]	values[7]	values[4]	713	1			T3	48		T163	19		T214	20
auto[0]	values[7]	values[5]	703	1			T15	8		T16	53		T258	8
auto[0]	values[7]	values[6]	286	1			T36	20		T102	20		T188	20
auto[0]	values[7]	values[7]	558	1			T36	44		T178	4		T200	20
auto[1]	values[0]	values[0]	18	1			T17	2		T18	2		T214	3
auto[1]	values[0]	values[1]	13	1			T195	2		T256	1		T239	1
auto[1]	values[0]	values[2]	7	1			T269	1		T213	2		T270	3
auto[1]	values[0]	values[3]	15	1			T200	3		T195	2		T176	1
auto[1]	values[0]	values[4]	10	1			T200	1		T205	3		T173	1
auto[1]	values[0]	values[5]	11	1			T180	3		T183	1		T191	1
auto[1]	values[0]	values[6]	15	1			T22	1		T71	2		T189	1
auto[1]	values[0]	values[7]	9	1			T43	1		T199	1		T192	2
auto[1]	values[1]	values[0]	20	1			T200	1		T180	1		T51	2
auto[1]	values[1]	values[1]	10	1			T14	1		T173	2		T138	3
auto[1]	values[1]	values[2]	4	1			T192	1		T271	1		T272	2
auto[1]	values[1]	values[3]	14	1			T36	2		T17	1		T50	1
auto[1]	values[1]	values[4]	11	1			T195	1		T182	3		T273	2
auto[1]	values[1]	values[5]	7	1			T188	3		T180	3		T271	1
auto[1]	values[1]	values[6]	21	1			T17	4		T195	2		T199	1
auto[1]	values[1]	values[7]	5	1			T36	2		T205	2		T274	1
auto[1]	values[2]	values[0]	10	1			T16	2		T200	1		T71	1
auto[1]	values[2]	values[1]	14	1			T217	1		T192	1		T261	3
auto[1]	values[2]	values[2]	18	1			T195	2		T209	2		T180	3
auto[1]	values[2]	values[3]	21	1			T205	1		T266	3		T53	1
auto[1]	values[2]	values[4]	10	1			T44	2		T82	2		T29	1
auto[1]	values[2]	values[5]	15	1			T188	1		T189	1		T180	1
auto[1]	values[2]	values[6]	19	1			T14	2		T42	2		T195	4
auto[1]	values[2]	values[7]	7	1			T14	1		T17	2		T199	1
auto[1]	values[3]	values[0]	14	1			T11	1		T82	1		T183	2
auto[1]	values[3]	values[1]	10	1			T158	3		T192	1		T275	1
auto[1]	values[3]	values[2]	5	1			T199	1		T239	1		T184	3
auto[1]	values[3]	values[3]	10	1			T205	2		T173	1		T276	2
auto[1]	values[3]	values[4]	25	1			T1	2		T43	1		T176	1
auto[1]	values[3]	values[5]	15	1			T200	2		T177	3		T48	1
auto[1]	values[3]	values[6]	11	1			T188	1		T182	3		T277	1
auto[1]	values[3]	values[7]	6	1			T184	3		T271	1		T278	2
auto[1]	values[4]	values[0]	11	1			T269	1		T274	2		T31	1
auto[1]	values[4]	values[1]	8	1			T211	1		T279	2		T280	1
auto[1]	values[4]	values[2]	19	1			T17	2		T200	2		T82	1
auto[1]	values[4]	values[3]	15	1			T36	1		T188	2		T211	1
auto[1]	values[4]	values[4]	6	1			T198	2		T281	1		T282	1
auto[1]	values[4]	values[5]	14	1			T188	2		T199	1		T50	1
auto[1]	values[4]	values[6]	20	1			T16	1		T203	5		T173	2
auto[1]	values[4]	values[7]	18	1			T36	1		T265	6		T261	4
auto[1]	values[5]	values[0]	6	1			T266	1		T48	1		T194	1
auto[1]	values[5]	values[1]	7	1			T273	6		T276	1		-	-
auto[1]	values[5]	values[2]	15	1			T22	5		T189	1		T51	1
auto[1]	values[5]	values[3]	23	1			T208	2		T195	1		T192	5
auto[1]	values[5]	values[4]	14	1			T17	1		T200	5		T188	2
auto[1]	values[5]	values[5]	9	1			T17	2		T273	1		T283	1
auto[1]	values[5]	values[6]	7	1			T53	1		T192	1		T180	1
auto[1]	values[5]	values[7]	15	1			T82	3		T211	1		T51	5
auto[1]	values[6]	values[0]	16	1			T17	1		T201	2		T209	2
auto[1]	values[6]	values[1]	24	1			T284	8		T50	4		T51	2
auto[1]	values[6]	values[2]	18	1			T163	3		T195	3		T71	1
auto[1]	values[6]	values[3]	36	1			T176	9		T254	10		T211	1
auto[1]	values[6]	values[4]	6	1			T16	2		T285	1		T286	1
auto[1]	values[6]	values[5]	18	1			T36	3		T208	1		T48	3
auto[1]	values[6]	values[6]	4	1			T200	2		T287	1		T288	1
auto[1]	values[6]	values[7]	9	1			T259	2		T176	1		T269	2
auto[1]	values[7]	values[0]	13	1			T176	5		T289	3		T290	3
auto[1]	values[7]	values[1]	12	1			T18	2		T192	1		T291	3
auto[1]	values[7]	values[2]	12	1			T180	1		T261	2		T183	2
auto[1]	values[7]	values[3]	3	1			T17	1		T198	1		T277	1
auto[1]	values[7]	values[4]	17	1			T3	1		T163	2		T195	2
auto[1]	values[7]	values[5]	21	1			T16	3		T58	4		T194	2
auto[1]	values[7]	values[6]	4	1			T292	1		T269	1		T138	2
auto[1]	values[7]	values[7]	16	1			T29	4		T194	1		T203	4