Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	798	1			T14	7		T17	10		T19	24
all_values[1]	798	1			T14	7		T17	10		T19	24
all_values[2]	798	1			T14	7		T17	10		T19	24
all_values[3]	798	1			T14	7		T17	10		T19	24
all_values[4]	798	1			T14	7		T17	10		T19	24
all_values[5]	798	1			T14	7		T17	10		T19	24
all_values[6]	798	1			T14	7		T17	10		T19	24
all_values[7]	798	1			T14	7		T17	10		T19	24

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3318

1

T14

31

T17

32

T19

99

auto[1]

3066

1

T14

25

T17

48

T19

93

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2548

1

T14

19

T17

31

T19

78

auto[1]

3836

1

T14

37

T17

49

T19

114

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3641

1

T14

32

T17

49

T19

109

auto[1]

2743

1

T14

24

T17

31

T19

83

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	175	1			T14	3		T17	4		T19	5
all_values[0]	auto[0]	auto[0]	auto[1]	70	1			T14	1		T17	1		T19	4
all_values[0]	auto[0]	auto[1]	auto[0]	158	1			T17	3		T19	7		T20	1
all_values[0]	auto[0]	auto[1]	auto[1]	80	1			T21	3		T158	2		T48	1
all_values[0]	auto[1]	auto[0]	auto[1]	161	1			T14	1		T17	1		T19	4
all_values[0]	auto[1]	auto[1]	auto[1]	154	1			T14	2		T17	1		T19	4
all_values[1]	auto[0]	auto[0]	auto[0]	164	1			T14	2		T17	2		T19	3
all_values[1]	auto[0]	auto[0]	auto[1]	77	1			T17	1		T19	2		T21	1
all_values[1]	auto[0]	auto[1]	auto[0]	137	1			T14	1		T17	3		T19	5
all_values[1]	auto[0]	auto[1]	auto[1]	84	1			T14	2		T17	1		T19	2
all_values[1]	auto[1]	auto[0]	auto[1]	171	1			T14	1		T17	1		T19	4
all_values[1]	auto[1]	auto[1]	auto[1]	165	1			T14	1		T17	2		T19	8
all_values[2]	auto[0]	auto[0]	auto[0]	139	1			T14	2		T17	4		T19	6
all_values[2]	auto[0]	auto[0]	auto[1]	68	1			T22	2		T162	1		T158	1
all_values[2]	auto[0]	auto[1]	auto[0]	141	1			T14	1		T17	2		T19	6
all_values[2]	auto[0]	auto[1]	auto[1]	92	1			T19	4		T20	2		T21	2
all_values[2]	auto[1]	auto[0]	auto[1]	191	1			T14	1		T17	1		T19	4
all_values[2]	auto[1]	auto[1]	auto[1]	167	1			T14	3		T17	3		T19	4
all_values[3]	auto[0]	auto[0]	auto[0]	146	1			T14	1		T19	6		T20	4
all_values[3]	auto[0]	auto[0]	auto[1]	86	1			T14	2		T17	1		T19	1
all_values[3]	auto[0]	auto[1]	auto[0]	125	1			T17	5		T19	5		T21	4
all_values[3]	auto[0]	auto[1]	auto[1]	84	1			T14	1		T17	1		T19	1
all_values[3]	auto[1]	auto[0]	auto[1]	176	1			T14	2		T17	2		T19	8
all_values[3]	auto[1]	auto[1]	auto[1]	181	1			T14	1		T17	1		T19	3
all_values[4]	auto[0]	auto[0]	auto[0]	194	1			T14	2		T17	1		T19	3
all_values[4]	auto[0]	auto[0]	auto[1]	59	1			T17	4		T19	3		T21	2
all_values[4]	auto[0]	auto[1]	auto[0]	151	1			T14	1		T19	4		T20	1
all_values[4]	auto[0]	auto[1]	auto[1]	73	1			T14	1		T17	2		T19	3
all_values[4]	auto[1]	auto[0]	auto[1]	159	1			T14	1		T17	1		T19	5
all_values[4]	auto[1]	auto[1]	auto[1]	162	1			T14	2		T17	2		T19	6
all_values[5]	auto[0]	auto[0]	auto[0]	225	1			T14	1		T17	2		T19	5
all_values[5]	auto[0]	auto[1]	auto[0]	205	1			T14	2		T17	1		T19	7
all_values[5]	auto[1]	auto[0]	auto[1]	215	1			T14	1		T17	2		T19	7
all_values[5]	auto[1]	auto[1]	auto[1]	153	1			T14	3		T17	5		T19	5
all_values[6]	auto[0]	auto[0]	auto[0]	170	1			T14	1		T19	6		T20	1
all_values[6]	auto[0]	auto[0]	auto[1]	91	1			T14	3		T19	6		T21	2
all_values[6]	auto[0]	auto[1]	auto[0]	138	1			T17	2		T20	2		T162	1
all_values[6]	auto[0]	auto[1]	auto[1]	61	1			T14	1		T17	1		T19	2
all_values[6]	auto[1]	auto[0]	auto[1]	165	1			T14	1		T17	1		T19	5
all_values[6]	auto[1]	auto[1]	auto[1]	173	1			T14	1		T17	6		T19	5
all_values[7]	auto[0]	auto[0]	auto[0]	141	1			T19	4		T20	1		T21	2
all_values[7]	auto[0]	auto[0]	auto[1]	91	1			T14	2		T17	3		T19	2
all_values[7]	auto[0]	auto[1]	auto[0]	139	1			T14	2		T17	2		T19	6
all_values[7]	auto[0]	auto[1]	auto[1]	77	1			T17	3		T19	1		T21	1
all_values[7]	auto[1]	auto[0]	auto[1]	184	1			T14	3		T19	6		T21	5
all_values[7]	auto[1]	auto[1]	auto[1]	166	1			T17	2		T19	5		T20	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal