Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1954

1

T4

7

T9

4

T11

6

auto[1]

2000

1

T4

4

T9

4

T11

9

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2109

1

T4

6

T9

8

T11

15

auto[1]

1845

1

T4

5

T12

22

T13

3

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3102

1

T4

6

T9

4

T11

12

auto[1]

852

1

T4

5

T9

4

T11

3

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	804	1			T4	3		T9	1		T11	4
valid[1]	779	1			T4	2		T9	1		T11	3
valid[2]	788	1			T4	2		T9	1		T11	2
valid[3]	768	1			T4	2		T9	4		T11	4
valid[4]	815	1			T4	2		T9	1		T11	2

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	120	1			T4	1		T9	1		T11	2
auto[0]	auto[0]	valid[0]	auto[1]	187	1			T12	4		T27	5		T16	1
auto[0]	auto[0]	valid[1]	auto[0]	116	1			T11	1		T24	1		T79	1
auto[0]	auto[0]	valid[1]	auto[1]	195	1			T12	4		T13	1		T25	2
auto[0]	auto[0]	valid[2]	auto[0]	125	1			T9	1		T11	1		T14	1
auto[0]	auto[0]	valid[2]	auto[1]	154	1			T4	1		T12	3		T27	3
auto[0]	auto[0]	valid[3]	auto[0]	121	1			T11	2		T14	1		T16	2
auto[0]	auto[0]	valid[3]	auto[1]	183	1			T12	2		T27	1		T19	2
auto[0]	auto[0]	valid[4]	auto[0]	120	1			T14	1		T79	4		T164	1
auto[0]	auto[0]	valid[4]	auto[1]	206	1			T4	1		T24	1		T27	3
auto[0]	auto[1]	valid[0]	auto[0]	141	1			T11	2		T14	1		T24	1
auto[0]	auto[1]	valid[0]	auto[1]	189	1			T4	1		T12	1		T27	3
auto[0]	auto[1]	valid[1]	auto[0]	116	1			T9	1		T11	2		T14	1
auto[0]	auto[1]	valid[1]	auto[1]	173	1			T12	2		T24	1		T27	2
auto[0]	auto[1]	valid[2]	auto[0]	121	1			T11	1		T14	1		T24	2
auto[0]	auto[1]	valid[2]	auto[1]	192	1			T12	1		T24	1		T27	5
auto[0]	auto[1]	valid[3]	auto[0]	141	1			T14	1		T24	2		T26	1
auto[0]	auto[1]	valid[3]	auto[1]	175	1			T4	2		T12	1		T13	1
auto[0]	auto[1]	valid[4]	auto[0]	136	1			T9	1		T11	1		T14	3
auto[0]	auto[1]	valid[4]	auto[1]	191	1			T12	4		T13	1		T14	1
auto[1]	auto[0]	valid[0]	auto[0]	80	1			T4	1		T46	1		T17	1
auto[1]	auto[0]	valid[1]	auto[0]	96	1			T4	1		T14	1		T24	1
auto[1]	auto[0]	valid[2]	auto[0]	101	1			T4	1		T14	1		T24	1
auto[1]	auto[0]	valid[3]	auto[0]	76	1			T9	2		T14	1		T24	1
auto[1]	auto[0]	valid[4]	auto[0]	74	1			T4	1		T14	2		T79	1
auto[1]	auto[1]	valid[0]	auto[0]	87	1			T14	1		T24	1		T26	1
auto[1]	auto[1]	valid[1]	auto[0]	83	1			T4	1		T24	1		T16	1
auto[1]	auto[1]	valid[2]	auto[0]	95	1			T14	1		T24	2		T79	1
auto[1]	auto[1]	valid[3]	auto[0]	72	1			T9	2		T11	2		T14	1
auto[1]	auto[1]	valid[4]	auto[0]	88	1			T11	1		T14	2		T79	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal