Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

55001

1

T4

263

T9

187

T11

440

auto[1]

19806

1

T4

60

T12

310

T13

58

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

54288

1

T4

190

T9

129

T11

299

auto[1]

20519

1

T4

133

T9

58

T11

141

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	38455	1			T4	167		T9	94		T11	232
others[1]	6278	1			T4	26		T9	27		T11	36
others[2]	6338	1			T4	26		T9	21		T11	27
others[3]	7046	1			T4	30		T9	15		T11	44
interest[1]	4272	1			T4	22		T9	9		T11	25
interest[4]	25115	1			T4	113		T9	57		T11	149
interest[64]	12418	1			T4	52		T9	21		T11	76

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	17572	1			T4	66		T9	58		T11	160
auto[0]	auto[0]	others[1]	2904	1			T4	8		T9	13		T11	24
auto[0]	auto[0]	others[2]	2946	1			T4	10		T9	20		T11	22
auto[0]	auto[0]	others[3]	3255	1			T4	19		T9	11		T11	30
auto[0]	auto[0]	interest[1]	2042	1			T4	6		T9	7		T11	17
auto[0]	auto[0]	interest[4]	11532	1			T4	43		T9	35		T11	113
auto[0]	auto[0]	interest[64]	5763	1			T4	21		T9	20		T11	46
auto[0]	auto[1]	others[0]	10509	1			T4	33		T12	158		T13	32
auto[0]	auto[1]	others[1]	1638	1			T4	6		T12	30		T13	2
auto[0]	auto[1]	others[2]	1597	1			T4	6		T12	26		T13	4
auto[0]	auto[1]	others[3]	1847	1			T4	3		T12	29		T13	3
auto[0]	auto[1]	interest[1]	1021	1			T4	5		T12	17		T13	6
auto[0]	auto[1]	interest[4]	6893	1			T4	26		T12	102		T13	21
auto[0]	auto[1]	interest[64]	3194	1			T4	7		T12	50		T13	11
auto[1]	auto[0]	others[0]	10374	1			T4	68		T9	36		T11	72
auto[1]	auto[0]	others[1]	1736	1			T4	12		T9	14		T11	12
auto[1]	auto[0]	others[2]	1795	1			T4	10		T9	1		T11	5
auto[1]	auto[0]	others[3]	1944	1			T4	8		T9	4		T11	14
auto[1]	auto[0]	interest[1]	1209	1			T4	11		T9	2		T11	8
auto[1]	auto[0]	interest[4]	6690	1			T4	44		T9	22		T11	36
auto[1]	auto[0]	interest[64]	3461	1			T4	24		T9	1		T11	30

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal