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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.07 98.44 94.08 98.62 89.36 97.28 95.43 99.26


Total test records in report: 1150
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T1037 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.2598790475 Aug 08 06:08:40 PM PDT 24 Aug 08 06:08:41 PM PDT 24 19600660 ps
T114 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.884852698 Aug 08 06:08:34 PM PDT 24 Aug 08 06:08:38 PM PDT 24 514918648 ps
T112 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.746936698 Aug 08 06:08:36 PM PDT 24 Aug 08 06:08:39 PM PDT 24 301883876 ps
T125 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.2815715661 Aug 08 06:08:24 PM PDT 24 Aug 08 06:08:25 PM PDT 24 21025566 ps
T1038 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.1853052282 Aug 08 06:08:44 PM PDT 24 Aug 08 06:08:45 PM PDT 24 42002128 ps
T96 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.3994008325 Aug 08 06:08:19 PM PDT 24 Aug 08 06:08:33 PM PDT 24 211766263 ps
T118 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2165659263 Aug 08 06:08:43 PM PDT 24 Aug 08 06:08:46 PM PDT 24 381044251 ps
T104 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.1348273237 Aug 08 06:08:34 PM PDT 24 Aug 08 06:08:38 PM PDT 24 140024737 ps
T1039 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2977715384 Aug 08 06:08:45 PM PDT 24 Aug 08 06:08:46 PM PDT 24 76060689 ps
T126 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.4294001990 Aug 08 06:08:20 PM PDT 24 Aug 08 06:08:22 PM PDT 24 35535206 ps
T154 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.3623865488 Aug 08 06:08:35 PM PDT 24 Aug 08 06:08:37 PM PDT 24 62874181 ps
T1040 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.3774545202 Aug 08 06:08:44 PM PDT 24 Aug 08 06:08:45 PM PDT 24 16736299 ps
T1041 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.2392406743 Aug 08 06:08:36 PM PDT 24 Aug 08 06:08:37 PM PDT 24 36736142 ps
T1042 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.2690048767 Aug 08 06:08:33 PM PDT 24 Aug 08 06:08:33 PM PDT 24 11839907 ps
T127 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.1542287327 Aug 08 06:08:43 PM PDT 24 Aug 08 06:08:46 PM PDT 24 111199444 ps
T155 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1827898267 Aug 08 06:08:34 PM PDT 24 Aug 08 06:08:36 PM PDT 24 143727001 ps
T1043 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.4138120184 Aug 08 06:08:53 PM PDT 24 Aug 08 06:08:54 PM PDT 24 23083296 ps
T1044 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2584987186 Aug 08 06:08:36 PM PDT 24 Aug 08 06:08:39 PM PDT 24 420900708 ps
T1045 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.2496281621 Aug 08 06:08:38 PM PDT 24 Aug 08 06:08:39 PM PDT 24 22736623 ps
T1046 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2399900956 Aug 08 06:08:42 PM PDT 24 Aug 08 06:08:43 PM PDT 24 11124882 ps
T108 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.2065377998 Aug 08 06:08:36 PM PDT 24 Aug 08 06:08:40 PM PDT 24 175027145 ps
T166 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.898260293 Aug 08 06:08:38 PM PDT 24 Aug 08 06:08:50 PM PDT 24 783381422 ps
T115 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.3662467212 Aug 08 06:08:47 PM PDT 24 Aug 08 06:08:50 PM PDT 24 41443107 ps
T1047 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.3411194084 Aug 08 06:08:45 PM PDT 24 Aug 08 06:08:46 PM PDT 24 42007336 ps
T105 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.3919523502 Aug 08 06:08:40 PM PDT 24 Aug 08 06:08:44 PM PDT 24 2903803342 ps
T128 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.1776381155 Aug 08 06:08:38 PM PDT 24 Aug 08 06:08:45 PM PDT 24 422656384 ps
T1048 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.2583730790 Aug 08 06:08:35 PM PDT 24 Aug 08 06:08:36 PM PDT 24 12233955 ps
T1049 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.50627131 Aug 08 06:08:36 PM PDT 24 Aug 08 06:08:39 PM PDT 24 45231984 ps
T111 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.2243242940 Aug 08 06:08:42 PM PDT 24 Aug 08 06:08:57 PM PDT 24 1432920465 ps
T129 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.4253871870 Aug 08 06:08:39 PM PDT 24 Aug 08 06:08:54 PM PDT 24 1160461581 ps
T77 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.548890512 Aug 08 06:08:28 PM PDT 24 Aug 08 06:08:30 PM PDT 24 39097223 ps
T130 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.2218279413 Aug 08 06:08:35 PM PDT 24 Aug 08 06:08:38 PM PDT 24 336511890 ps
T106 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.3650644049 Aug 08 06:08:23 PM PDT 24 Aug 08 06:08:27 PM PDT 24 247561650 ps
T1050 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3856810936 Aug 08 06:08:23 PM PDT 24 Aug 08 06:08:26 PM PDT 24 427948656 ps
T1051 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.2766200011 Aug 08 06:08:39 PM PDT 24 Aug 08 06:08:40 PM PDT 24 12510337 ps
T1052 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.56710379 Aug 08 06:08:42 PM PDT 24 Aug 08 06:08:45 PM PDT 24 44582764 ps
T156 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.1084386797 Aug 08 06:08:46 PM PDT 24 Aug 08 06:08:50 PM PDT 24 145051103 ps
T1053 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2471073378 Aug 08 06:08:28 PM PDT 24 Aug 08 06:08:30 PM PDT 24 59186089 ps
T157 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.3575728646 Aug 08 06:08:34 PM PDT 24 Aug 08 06:08:42 PM PDT 24 638619505 ps
T1054 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.1627789367 Aug 08 06:08:34 PM PDT 24 Aug 08 06:08:35 PM PDT 24 91475944 ps
T1055 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.2691203941 Aug 08 06:08:26 PM PDT 24 Aug 08 06:08:27 PM PDT 24 157717148 ps
T1056 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1537228287 Aug 08 06:08:27 PM PDT 24 Aug 08 06:08:42 PM PDT 24 2242404102 ps
T107 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.3062642206 Aug 08 06:08:34 PM PDT 24 Aug 08 06:08:38 PM PDT 24 418010155 ps
T1057 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.2081141539 Aug 08 06:08:46 PM PDT 24 Aug 08 06:08:46 PM PDT 24 38325648 ps
T1058 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.2283056492 Aug 08 06:08:47 PM PDT 24 Aug 08 06:08:49 PM PDT 24 237256605 ps
T1059 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.164368837 Aug 08 06:08:35 PM PDT 24 Aug 08 06:08:37 PM PDT 24 130861104 ps
T131 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.583573678 Aug 08 06:08:42 PM PDT 24 Aug 08 06:08:45 PM PDT 24 119820017 ps
T1060 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.2018907158 Aug 08 06:08:43 PM PDT 24 Aug 08 06:08:45 PM PDT 24 239272655 ps
T1061 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.720693231 Aug 08 06:08:26 PM PDT 24 Aug 08 06:08:29 PM PDT 24 564103795 ps
T113 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.352493477 Aug 08 06:08:43 PM PDT 24 Aug 08 06:08:45 PM PDT 24 164773933 ps
T1062 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.3751040414 Aug 08 06:08:50 PM PDT 24 Aug 08 06:08:51 PM PDT 24 48968377 ps
T1063 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.2465645622 Aug 08 06:08:50 PM PDT 24 Aug 08 06:08:51 PM PDT 24 55248904 ps
T1064 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.2136527716 Aug 08 06:08:40 PM PDT 24 Aug 08 06:08:42 PM PDT 24 132427446 ps
T109 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.447572101 Aug 08 06:08:29 PM PDT 24 Aug 08 06:08:33 PM PDT 24 222569300 ps
T1065 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.2919335343 Aug 08 06:08:47 PM PDT 24 Aug 08 06:08:48 PM PDT 24 25180151 ps
T1066 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.2269041139 Aug 08 06:08:32 PM PDT 24 Aug 08 06:08:32 PM PDT 24 49612147 ps
T1067 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.704797517 Aug 08 06:08:34 PM PDT 24 Aug 08 06:08:47 PM PDT 24 4004281102 ps
T1068 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.3644084183 Aug 08 06:08:34 PM PDT 24 Aug 08 06:08:47 PM PDT 24 2328142737 ps
T1069 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.3071576341 Aug 08 06:08:34 PM PDT 24 Aug 08 06:08:37 PM PDT 24 127494231 ps
T167 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1293345552 Aug 08 06:08:34 PM PDT 24 Aug 08 06:08:54 PM PDT 24 560498365 ps
T1070 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3079497532 Aug 08 06:08:23 PM PDT 24 Aug 08 06:08:24 PM PDT 24 79735021 ps
T116 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.3718628359 Aug 08 06:08:24 PM PDT 24 Aug 08 06:08:26 PM PDT 24 106609558 ps
T1071 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.2369796647 Aug 08 06:08:41 PM PDT 24 Aug 08 06:08:42 PM PDT 24 14135608 ps
T1072 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.2604535926 Aug 08 06:08:42 PM PDT 24 Aug 08 06:08:43 PM PDT 24 113471552 ps
T132 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.849325557 Aug 08 06:08:39 PM PDT 24 Aug 08 06:08:42 PM PDT 24 38552778 ps
T1073 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.2950720895 Aug 08 06:08:42 PM PDT 24 Aug 08 06:08:43 PM PDT 24 36964992 ps
T1074 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.1569347153 Aug 08 06:08:39 PM PDT 24 Aug 08 06:08:40 PM PDT 24 14448311 ps
T1075 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.1377361517 Aug 08 06:08:29 PM PDT 24 Aug 08 06:08:51 PM PDT 24 1406758259 ps
T1076 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2674653005 Aug 08 06:08:51 PM PDT 24 Aug 08 06:08:52 PM PDT 24 34395054 ps
T1077 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.3856769061 Aug 08 06:08:27 PM PDT 24 Aug 08 06:08:34 PM PDT 24 1094233324 ps
T1078 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3382086492 Aug 08 06:08:41 PM PDT 24 Aug 08 06:08:45 PM PDT 24 69882830 ps
T1079 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2350830952 Aug 08 06:08:41 PM PDT 24 Aug 08 06:08:44 PM PDT 24 558098724 ps
T1080 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.490032719 Aug 08 06:08:35 PM PDT 24 Aug 08 06:08:38 PM PDT 24 124429408 ps
T110 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.73599637 Aug 08 06:08:37 PM PDT 24 Aug 08 06:08:42 PM PDT 24 734991584 ps
T1081 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.262060779 Aug 08 06:08:23 PM PDT 24 Aug 08 06:08:24 PM PDT 24 195800927 ps
T1082 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.4179470625 Aug 08 06:08:53 PM PDT 24 Aug 08 06:08:54 PM PDT 24 17778743 ps
T1083 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.1171533702 Aug 08 06:08:45 PM PDT 24 Aug 08 06:08:47 PM PDT 24 81893759 ps
T1084 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.1944487891 Aug 08 06:08:51 PM PDT 24 Aug 08 06:08:52 PM PDT 24 24648151 ps
T1085 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.2485863281 Aug 08 06:08:38 PM PDT 24 Aug 08 06:08:39 PM PDT 24 20484514 ps
T1086 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3196816404 Aug 08 06:08:28 PM PDT 24 Aug 08 06:08:29 PM PDT 24 23436016 ps
T1087 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3212082964 Aug 08 06:08:39 PM PDT 24 Aug 08 06:08:43 PM PDT 24 45966180 ps
T1088 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3748546613 Aug 08 06:08:35 PM PDT 24 Aug 08 06:08:39 PM PDT 24 157302101 ps
T1089 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1737282419 Aug 08 06:08:16 PM PDT 24 Aug 08 06:08:39 PM PDT 24 354422071 ps
T1090 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.4130022586 Aug 08 06:08:33 PM PDT 24 Aug 08 06:08:50 PM PDT 24 2806691364 ps
T1091 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.1628116573 Aug 08 06:08:28 PM PDT 24 Aug 08 06:08:30 PM PDT 24 1161091375 ps
T1092 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2355571350 Aug 08 06:08:51 PM PDT 24 Aug 08 06:08:52 PM PDT 24 31988025 ps
T1093 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.100413890 Aug 08 06:08:27 PM PDT 24 Aug 08 06:08:30 PM PDT 24 108762759 ps
T1094 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.1260033835 Aug 08 06:08:34 PM PDT 24 Aug 08 06:08:37 PM PDT 24 47958325 ps
T1095 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.316348362 Aug 08 06:08:34 PM PDT 24 Aug 08 06:08:36 PM PDT 24 94417281 ps
T1096 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.2286770581 Aug 08 06:08:24 PM PDT 24 Aug 08 06:08:30 PM PDT 24 1938978373 ps
T1097 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.2344924044 Aug 08 06:08:51 PM PDT 24 Aug 08 06:08:52 PM PDT 24 13612499 ps
T1098 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.3518723349 Aug 08 06:08:46 PM PDT 24 Aug 08 06:08:47 PM PDT 24 62730986 ps
T1099 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.528833239 Aug 08 06:08:38 PM PDT 24 Aug 08 06:08:55 PM PDT 24 3321210644 ps
T1100 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.2282417016 Aug 08 06:08:42 PM PDT 24 Aug 08 06:08:43 PM PDT 24 56747235 ps
T1101 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.2719936508 Aug 08 06:08:26 PM PDT 24 Aug 08 06:08:29 PM PDT 24 62338253 ps
T1102 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.4075514952 Aug 08 06:08:47 PM PDT 24 Aug 08 06:08:51 PM PDT 24 644203865 ps
T1103 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.2936642649 Aug 08 06:08:39 PM PDT 24 Aug 08 06:08:43 PM PDT 24 81780585 ps
T1104 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.1899096271 Aug 08 06:08:35 PM PDT 24 Aug 08 06:08:37 PM PDT 24 105778677 ps
T1105 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.1208858355 Aug 08 06:08:50 PM PDT 24 Aug 08 06:08:51 PM PDT 24 18828408 ps
T1106 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.4280624123 Aug 08 06:08:49 PM PDT 24 Aug 08 06:09:01 PM PDT 24 756360281 ps
T1107 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.621918559 Aug 08 06:08:47 PM PDT 24 Aug 08 06:08:51 PM PDT 24 412582841 ps
T1108 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1083002161 Aug 08 06:08:34 PM PDT 24 Aug 08 06:08:36 PM PDT 24 28179389 ps
T1109 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.2261296813 Aug 08 06:08:19 PM PDT 24 Aug 08 06:08:20 PM PDT 24 29967983 ps
T1110 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1364680212 Aug 08 06:08:33 PM PDT 24 Aug 08 06:08:37 PM PDT 24 59169384 ps
T168 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.2632746009 Aug 08 06:08:37 PM PDT 24 Aug 08 06:08:50 PM PDT 24 9710731982 ps
T1111 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1696114281 Aug 08 06:08:42 PM PDT 24 Aug 08 06:09:01 PM PDT 24 1240971773 ps
T1112 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.4132986773 Aug 08 06:08:27 PM PDT 24 Aug 08 06:08:29 PM PDT 24 229467347 ps
T165 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.2907355668 Aug 08 06:08:48 PM PDT 24 Aug 08 06:08:52 PM PDT 24 128633068 ps
T1113 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.1512785100 Aug 08 06:08:31 PM PDT 24 Aug 08 06:08:33 PM PDT 24 73803146 ps
T1114 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.844399293 Aug 08 06:08:43 PM PDT 24 Aug 08 06:08:47 PM PDT 24 509139193 ps
T1115 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.3341033669 Aug 08 06:08:16 PM PDT 24 Aug 08 06:08:31 PM PDT 24 732563321 ps
T1116 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.2717055628 Aug 08 06:08:45 PM PDT 24 Aug 08 06:08:45 PM PDT 24 12815355 ps
T1117 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.3730787669 Aug 08 06:08:35 PM PDT 24 Aug 08 06:08:37 PM PDT 24 152482301 ps
T1118 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.2808140319 Aug 08 06:08:39 PM PDT 24 Aug 08 06:09:15 PM PDT 24 1850876463 ps
T1119 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.706336206 Aug 08 06:08:42 PM PDT 24 Aug 08 06:08:43 PM PDT 24 115111723 ps
T169 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3626097308 Aug 08 06:08:20 PM PDT 24 Aug 08 06:08:41 PM PDT 24 809576852 ps
T170 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.64786951 Aug 08 06:08:43 PM PDT 24 Aug 08 06:08:57 PM PDT 24 542023491 ps
T1120 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.3444428750 Aug 08 06:08:40 PM PDT 24 Aug 08 06:08:46 PM PDT 24 932535685 ps
T1121 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.537425553 Aug 08 06:08:31 PM PDT 24 Aug 08 06:08:35 PM PDT 24 467223912 ps
T1122 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.1380666970 Aug 08 06:08:43 PM PDT 24 Aug 08 06:08:43 PM PDT 24 13427976 ps
T1123 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1932440806 Aug 08 06:08:27 PM PDT 24 Aug 08 06:08:27 PM PDT 24 15576792 ps
T1124 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.1163397823 Aug 08 06:08:24 PM PDT 24 Aug 08 06:08:26 PM PDT 24 145797599 ps
T1125 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.3458319114 Aug 08 06:08:47 PM PDT 24 Aug 08 06:08:50 PM PDT 24 419856208 ps
T1126 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.261328898 Aug 08 06:08:48 PM PDT 24 Aug 08 06:08:49 PM PDT 24 11108498 ps
T171 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.4241441398 Aug 08 06:08:34 PM PDT 24 Aug 08 06:08:46 PM PDT 24 792455810 ps
T1127 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.1121583076 Aug 08 06:08:47 PM PDT 24 Aug 08 06:08:48 PM PDT 24 12041308 ps
T1128 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.633961470 Aug 08 06:08:49 PM PDT 24 Aug 08 06:08:50 PM PDT 24 13571590 ps
T1129 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3370589842 Aug 08 06:08:37 PM PDT 24 Aug 08 06:08:40 PM PDT 24 198100455 ps
T1130 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.1053544090 Aug 08 06:08:34 PM PDT 24 Aug 08 06:08:39 PM PDT 24 610960516 ps
T1131 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.1897612347 Aug 08 06:08:47 PM PDT 24 Aug 08 06:08:51 PM PDT 24 122362953 ps
T1132 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.2972436516 Aug 08 06:08:35 PM PDT 24 Aug 08 06:08:37 PM PDT 24 262765626 ps
T1133 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.3663099822 Aug 08 06:08:26 PM PDT 24 Aug 08 06:09:05 PM PDT 24 2790628446 ps
T1134 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.3594130799 Aug 08 06:08:28 PM PDT 24 Aug 08 06:08:40 PM PDT 24 781831125 ps
T1135 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.2048311509 Aug 08 06:08:45 PM PDT 24 Aug 08 06:08:48 PM PDT 24 82662722 ps
T1136 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.3186490646 Aug 08 06:08:29 PM PDT 24 Aug 08 06:08:29 PM PDT 24 19328768 ps
T1137 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.53113380 Aug 08 06:08:40 PM PDT 24 Aug 08 06:08:48 PM PDT 24 340674308 ps
T1138 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.3308524740 Aug 08 06:08:29 PM PDT 24 Aug 08 06:08:30 PM PDT 24 128650612 ps
T1139 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.995798285 Aug 08 06:08:41 PM PDT 24 Aug 08 06:08:42 PM PDT 24 68997785 ps
T1140 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.2550762086 Aug 08 06:08:49 PM PDT 24 Aug 08 06:08:50 PM PDT 24 31076042 ps
T1141 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.1667666401 Aug 08 06:08:44 PM PDT 24 Aug 08 06:08:45 PM PDT 24 17331708 ps
T1142 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.3606055998 Aug 08 06:08:34 PM PDT 24 Aug 08 06:08:36 PM PDT 24 100657379 ps
T1143 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.2356372903 Aug 08 06:08:34 PM PDT 24 Aug 08 06:08:35 PM PDT 24 59640034 ps
T1144 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.2143432852 Aug 08 06:08:39 PM PDT 24 Aug 08 06:08:47 PM PDT 24 2088394230 ps
T1145 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.381109812 Aug 08 06:08:37 PM PDT 24 Aug 08 06:08:40 PM PDT 24 37014807 ps
T1146 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.3856806710 Aug 08 06:08:36 PM PDT 24 Aug 08 06:08:37 PM PDT 24 56099381 ps
T1147 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.3561407279 Aug 08 06:08:45 PM PDT 24 Aug 08 06:08:47 PM PDT 24 28939859 ps
T1148 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.2632653894 Aug 08 06:08:22 PM PDT 24 Aug 08 06:08:24 PM PDT 24 481391315 ps
T1149 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.2372026745 Aug 08 06:08:28 PM PDT 24 Aug 08 06:08:30 PM PDT 24 501259785 ps
T78 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.4198742308 Aug 08 06:08:17 PM PDT 24 Aug 08 06:08:18 PM PDT 24 461335645 ps
T1150 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.2829698405 Aug 08 06:08:43 PM PDT 24 Aug 08 06:08:44 PM PDT 24 18608911 ps

Test location /workspace/coverage/default/46.spi_device_stress_all.2884703277
Short name T4
Test name
Test status
Simulation time 55714184717 ps
CPU time 524.44 seconds
Started Aug 08 06:12:56 PM PDT 24
Finished Aug 08 06:21:41 PM PDT 24
Peak memory 258124 kb
Host smart-32f76d37-5c7b-442f-8421-ea5c362eee68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884703277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.2884703277
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.1487404989
Short name T14
Test name
Test status
Simulation time 27425549988 ps
CPU time 276.68 seconds
Started Aug 08 06:10:30 PM PDT 24
Finished Aug 08 06:15:07 PM PDT 24
Peak memory 256216 kb
Host smart-afeff243-d024-4e54-b1d1-d06791f5109b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487404989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.1487404989
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.2548285164
Short name T1
Test name
Test status
Simulation time 1057916596 ps
CPU time 2.96 seconds
Started Aug 08 06:11:23 PM PDT 24
Finished Aug 08 06:11:26 PM PDT 24
Peak memory 233452 kb
Host smart-324aa812-fdf1-46c0-a0a7-f5743a8becf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548285164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.2548285164
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.2039042530
Short name T95
Test name
Test status
Simulation time 1169501536 ps
CPU time 21.68 seconds
Started Aug 08 06:08:47 PM PDT 24
Finished Aug 08 06:09:09 PM PDT 24
Peak memory 215616 kb
Host smart-b8b78208-1489-4375-869c-21cb8d750f0e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039042530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.2039042530
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.2079822574
Short name T11
Test name
Test status
Simulation time 30723843910 ps
CPU time 86.39 seconds
Started Aug 08 06:12:37 PM PDT 24
Finished Aug 08 06:14:03 PM PDT 24
Peak memory 233564 kb
Host smart-f5711630-8b2e-45ae-8d40-ea48a661a397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079822574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.2079822574
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.4162897835
Short name T17
Test name
Test status
Simulation time 61151387723 ps
CPU time 556.2 seconds
Started Aug 08 06:12:16 PM PDT 24
Finished Aug 08 06:21:32 PM PDT 24
Peak memory 274488 kb
Host smart-214082d3-8921-4247-8db6-c595ea302924
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162897835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.4162897835
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.2301717388
Short name T48
Test name
Test status
Simulation time 109458344403 ps
CPU time 268.29 seconds
Started Aug 08 06:10:09 PM PDT 24
Finished Aug 08 06:14:37 PM PDT 24
Peak memory 273976 kb
Host smart-b2aecae1-fbdd-4d67-a4f5-0b6e7f318bb5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301717388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.2301717388
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.3260839590
Short name T63
Test name
Test status
Simulation time 15117742 ps
CPU time 0.74 seconds
Started Aug 08 06:10:08 PM PDT 24
Finished Aug 08 06:10:09 PM PDT 24
Peak memory 216700 kb
Host smart-62f8dc45-9ed7-4d1a-bf42-5bee952053bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260839590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.3260839590
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.126583623
Short name T51
Test name
Test status
Simulation time 699946523615 ps
CPU time 759.71 seconds
Started Aug 08 06:11:58 PM PDT 24
Finished Aug 08 06:24:38 PM PDT 24
Peak memory 282404 kb
Host smart-04ce9676-deca-458a-b3e8-72f83eae2039
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126583623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stres
s_all.126583623
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.2497269631
Short name T16
Test name
Test status
Simulation time 72997299012 ps
CPU time 610.89 seconds
Started Aug 08 06:11:36 PM PDT 24
Finished Aug 08 06:21:47 PM PDT 24
Peak memory 274488 kb
Host smart-a8678a4f-114a-409f-bb00-3cc0bf80004e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497269631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.2497269631
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.1465129055
Short name T180
Test name
Test status
Simulation time 69807907618 ps
CPU time 403.82 seconds
Started Aug 08 06:12:13 PM PDT 24
Finished Aug 08 06:18:57 PM PDT 24
Peak memory 270740 kb
Host smart-a53d6c50-a0fe-4354-a685-53dcdf7634aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465129055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.1465129055
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.4075146196
Short name T141
Test name
Test status
Simulation time 610258751 ps
CPU time 14.8 seconds
Started Aug 08 06:10:39 PM PDT 24
Finished Aug 08 06:10:54 PM PDT 24
Peak memory 233492 kb
Host smart-74c22556-5c25-4a54-be70-7d0141769de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075146196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.4075146196
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.2956116285
Short name T200
Test name
Test status
Simulation time 303704302698 ps
CPU time 487.64 seconds
Started Aug 08 06:10:06 PM PDT 24
Finished Aug 08 06:18:14 PM PDT 24
Peak memory 263984 kb
Host smart-992f3d6a-da54-4de1-bbdc-80072d3b33ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956116285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds
.2956116285
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.1017410405
Short name T149
Test name
Test status
Simulation time 23624242 ps
CPU time 0.74 seconds
Started Aug 08 06:11:14 PM PDT 24
Finished Aug 08 06:11:15 PM PDT 24
Peak memory 205848 kb
Host smart-f840361c-c6df-4cad-8702-28f408aaa94b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017410405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
1017410405
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2344352964
Short name T97
Test name
Test status
Simulation time 441584919 ps
CPU time 3.34 seconds
Started Aug 08 06:08:43 PM PDT 24
Finished Aug 08 06:08:46 PM PDT 24
Peak memory 215864 kb
Host smart-a321d1aa-ffb1-44ba-b3e6-2578dbf23d81
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344352964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.2
344352964
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.867686283
Short name T192
Test name
Test status
Simulation time 5782648404 ps
CPU time 104.89 seconds
Started Aug 08 06:10:37 PM PDT 24
Finished Aug 08 06:12:22 PM PDT 24
Peak memory 257344 kb
Host smart-c5397ce7-6426-42fe-af26-e8750462b58c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867686283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.867686283
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.2419268150
Short name T188
Test name
Test status
Simulation time 47301368186 ps
CPU time 332.29 seconds
Started Aug 08 06:13:03 PM PDT 24
Finished Aug 08 06:18:35 PM PDT 24
Peak memory 258080 kb
Host smart-b86b5d04-9bc8-4694-b4d9-9f53307719af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419268150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.2419268150
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.4294001990
Short name T126
Test name
Test status
Simulation time 35535206 ps
CPU time 2.27 seconds
Started Aug 08 06:08:20 PM PDT 24
Finished Aug 08 06:08:22 PM PDT 24
Peak memory 215556 kb
Host smart-a94697c1-6446-47c0-bb10-d54de0ed7a2a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294001990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.4
294001990
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.864435954
Short name T195
Test name
Test status
Simulation time 50547129219 ps
CPU time 366.26 seconds
Started Aug 08 06:11:24 PM PDT 24
Finished Aug 08 06:17:31 PM PDT 24
Peak memory 267388 kb
Host smart-b64e22f8-102b-47b9-99ee-b9eb8cab8d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864435954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.864435954
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.2094379228
Short name T289
Test name
Test status
Simulation time 229689251274 ps
CPU time 508.37 seconds
Started Aug 08 06:12:43 PM PDT 24
Finished Aug 08 06:21:11 PM PDT 24
Peak memory 266312 kb
Host smart-e41102cd-8b1e-4129-bdcb-84de9dde951c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094379228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmd
s.2094379228
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.3352659876
Short name T228
Test name
Test status
Simulation time 10212874088 ps
CPU time 87.16 seconds
Started Aug 08 06:12:24 PM PDT 24
Finished Aug 08 06:13:51 PM PDT 24
Peak memory 249884 kb
Host smart-ce3fce53-c28a-485f-9741-7a8e41633910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352659876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.3352659876
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.38699744
Short name T453
Test name
Test status
Simulation time 45390330 ps
CPU time 1.03 seconds
Started Aug 08 06:10:42 PM PDT 24
Finished Aug 08 06:10:43 PM PDT 24
Peak memory 217216 kb
Host smart-60313d7f-f4ad-4c24-89c9-9e6207aa5564
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38699744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TES
T_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.spi_device_mem_parity.38699744
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.1329620960
Short name T163
Test name
Test status
Simulation time 24826554869 ps
CPU time 206.86 seconds
Started Aug 08 06:11:35 PM PDT 24
Finished Aug 08 06:15:02 PM PDT 24
Peak memory 241560 kb
Host smart-825ed753-6791-44d8-a58d-f2b76b264a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329620960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.1329620960
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.2628586493
Short name T44
Test name
Test status
Simulation time 2826948567 ps
CPU time 9.06 seconds
Started Aug 08 06:11:56 PM PDT 24
Finished Aug 08 06:12:05 PM PDT 24
Peak memory 233492 kb
Host smart-b388968f-7505-41d5-bcec-7f4452dfd284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628586493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.2628586493
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.1031574878
Short name T66
Test name
Test status
Simulation time 87538974 ps
CPU time 1.14 seconds
Started Aug 08 06:10:09 PM PDT 24
Finished Aug 08 06:10:10 PM PDT 24
Peak memory 236604 kb
Host smart-fd24f8bf-d732-46d7-afa4-7786bbff8567
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031574878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.1031574878
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.3062642206
Short name T107
Test name
Test status
Simulation time 418010155 ps
CPU time 4.74 seconds
Started Aug 08 06:08:34 PM PDT 24
Finished Aug 08 06:08:38 PM PDT 24
Peak memory 215800 kb
Host smart-0be46408-42b0-418b-9c6d-170fa3c6896f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062642206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.3
062642206
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.156145617
Short name T277
Test name
Test status
Simulation time 55499827316 ps
CPU time 164.41 seconds
Started Aug 08 06:10:47 PM PDT 24
Finished Aug 08 06:13:31 PM PDT 24
Peak memory 287748 kb
Host smart-e3df4a96-b916-4f64-b676-356f22a91728
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156145617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stres
s_all.156145617
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.805377312
Short name T269
Test name
Test status
Simulation time 28257153837 ps
CPU time 230.34 seconds
Started Aug 08 06:10:29 PM PDT 24
Finished Aug 08 06:14:20 PM PDT 24
Peak memory 270552 kb
Host smart-da52a258-2fa2-446c-9b8c-28acd8a5647e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805377312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.805377312
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.4155860132
Short name T36
Test name
Test status
Simulation time 27918105825 ps
CPU time 221.08 seconds
Started Aug 08 06:11:59 PM PDT 24
Finished Aug 08 06:15:40 PM PDT 24
Peak memory 257564 kb
Host smart-2c289da7-538c-4dd0-9b47-2ba8bdb64b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155860132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.4155860132
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.3188694735
Short name T53
Test name
Test status
Simulation time 405495909214 ps
CPU time 925.67 seconds
Started Aug 08 06:10:38 PM PDT 24
Finished Aug 08 06:26:04 PM PDT 24
Peak memory 273656 kb
Host smart-a63d2f6c-0d03-41c1-b5bc-d5f5a73bb80a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188694735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.3188694735
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.521082381
Short name T276
Test name
Test status
Simulation time 41433251723 ps
CPU time 271.8 seconds
Started Aug 08 06:11:13 PM PDT 24
Finished Aug 08 06:15:45 PM PDT 24
Peak memory 267732 kb
Host smart-9701fe14-4463-44dd-b6d8-df662dfb4412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521082381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.521082381
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.3474948666
Short name T29
Test name
Test status
Simulation time 56499681529 ps
CPU time 486.38 seconds
Started Aug 08 06:11:07 PM PDT 24
Finished Aug 08 06:19:14 PM PDT 24
Peak memory 250940 kb
Host smart-a2c392a7-2902-44ad-8d47-c48f5819c86b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474948666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.3474948666
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.4241441398
Short name T171
Test name
Test status
Simulation time 792455810 ps
CPU time 12.33 seconds
Started Aug 08 06:08:34 PM PDT 24
Finished Aug 08 06:08:46 PM PDT 24
Peak memory 215572 kb
Host smart-15026c98-67a2-474d-a4ac-ff0c5bc6323e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241441398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.4241441398
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.2103315890
Short name T954
Test name
Test status
Simulation time 13702126820 ps
CPU time 223.49 seconds
Started Aug 08 06:11:47 PM PDT 24
Finished Aug 08 06:15:30 PM PDT 24
Peak memory 257556 kb
Host smart-e4ac63a8-01e0-46f8-81b9-a880f8ebdada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103315890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.2103315890
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.1499829044
Short name T184
Test name
Test status
Simulation time 70096176042 ps
CPU time 621.86 seconds
Started Aug 08 06:12:36 PM PDT 24
Finished Aug 08 06:22:58 PM PDT 24
Peak memory 266340 kb
Host smart-22519253-b406-4e3b-96f1-7243d5e24cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499829044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.1499829044
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.1193261462
Short name T211
Test name
Test status
Simulation time 66530246144 ps
CPU time 153.28 seconds
Started Aug 08 06:10:15 PM PDT 24
Finished Aug 08 06:12:48 PM PDT 24
Peak memory 249868 kb
Host smart-7167c479-b298-4756-a424-b7331250be3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193261462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.1193261462
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.1919953602
Short name T295
Test name
Test status
Simulation time 702119206 ps
CPU time 15.22 seconds
Started Aug 08 06:11:55 PM PDT 24
Finished Aug 08 06:12:11 PM PDT 24
Peak memory 237132 kb
Host smart-07ac2aa3-ce03-4496-8f0f-813a28445bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919953602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.1919953602
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.3759314391
Short name T300
Test name
Test status
Simulation time 597522678 ps
CPU time 11.6 seconds
Started Aug 08 06:10:19 PM PDT 24
Finished Aug 08 06:10:30 PM PDT 24
Peak memory 233488 kb
Host smart-c7ee4b8c-0833-4ea3-b67e-6a69560c228e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759314391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.3759314391
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.2733787202
Short name T210
Test name
Test status
Simulation time 36675169461 ps
CPU time 149.29 seconds
Started Aug 08 06:12:42 PM PDT 24
Finished Aug 08 06:15:12 PM PDT 24
Peak memory 263908 kb
Host smart-605580c3-1082-4726-8d44-b7035887e8eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733787202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.2733787202
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.2347989772
Short name T397
Test name
Test status
Simulation time 317781530 ps
CPU time 2.65 seconds
Started Aug 08 06:12:22 PM PDT 24
Finished Aug 08 06:12:25 PM PDT 24
Peak memory 233436 kb
Host smart-c364f70b-0a0c-41d8-a6bd-6c418b918b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347989772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.2347989772
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.1053544090
Short name T1130
Test name
Test status
Simulation time 610960516 ps
CPU time 4.19 seconds
Started Aug 08 06:08:34 PM PDT 24
Finished Aug 08 06:08:39 PM PDT 24
Peak memory 215704 kb
Host smart-79bab70b-5d15-4e59-bc02-034b9a186b81
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053544090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.1
053544090
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.1758011217
Short name T103
Test name
Test status
Simulation time 43929553668 ps
CPU time 60.29 seconds
Started Aug 08 06:11:11 PM PDT 24
Finished Aug 08 06:12:11 PM PDT 24
Peak memory 225404 kb
Host smart-927e40d7-4057-4f96-9432-a49bea7eaeda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758011217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.1758011217
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.898260293
Short name T166
Test name
Test status
Simulation time 783381422 ps
CPU time 12.16 seconds
Started Aug 08 06:08:38 PM PDT 24
Finished Aug 08 06:08:50 PM PDT 24
Peak memory 216188 kb
Host smart-17319984-bcb0-42b8-8302-e00264a0b261
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898260293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device
_tl_intg_err.898260293
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.1814731213
Short name T302
Test name
Test status
Simulation time 140552904 ps
CPU time 4.52 seconds
Started Aug 08 06:10:09 PM PDT 24
Finished Aug 08 06:10:14 PM PDT 24
Peak memory 233436 kb
Host smart-94d06350-388a-4469-aea4-9dd8e800068d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814731213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.1814731213
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.1047577877
Short name T87
Test name
Test status
Simulation time 4635817499 ps
CPU time 41.17 seconds
Started Aug 08 06:10:14 PM PDT 24
Finished Aug 08 06:10:55 PM PDT 24
Peak memory 235752 kb
Host smart-3516adcf-ae03-4bf0-9d5c-851c4de3cc4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047577877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.1047577877
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.4198742308
Short name T78
Test name
Test status
Simulation time 461335645 ps
CPU time 1.46 seconds
Started Aug 08 06:08:17 PM PDT 24
Finished Aug 08 06:08:18 PM PDT 24
Peak memory 207356 kb
Host smart-6372311d-bd38-4bd7-90b5-36f08f78d7f9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198742308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.4198742308
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.3341033669
Short name T1115
Test name
Test status
Simulation time 732563321 ps
CPU time 14.81 seconds
Started Aug 08 06:08:16 PM PDT 24
Finished Aug 08 06:08:31 PM PDT 24
Peak memory 207392 kb
Host smart-2e641869-c3a1-440c-9373-7f72cc08a290
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341033669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.3341033669
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1737282419
Short name T1089
Test name
Test status
Simulation time 354422071 ps
CPU time 22.46 seconds
Started Aug 08 06:08:16 PM PDT 24
Finished Aug 08 06:08:39 PM PDT 24
Peak memory 207380 kb
Host smart-1704cf71-ed72-4c54-a752-fdfde38a6307
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737282419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.1737282419
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.746936698
Short name T112
Test name
Test status
Simulation time 301883876 ps
CPU time 2.65 seconds
Started Aug 08 06:08:36 PM PDT 24
Finished Aug 08 06:08:39 PM PDT 24
Peak memory 217676 kb
Host smart-6af117e9-b037-4efb-bf9e-7ddf25097527
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746936698 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.746936698
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.689138235
Short name T1030
Test name
Test status
Simulation time 16469161 ps
CPU time 0.78 seconds
Started Aug 08 06:08:17 PM PDT 24
Finished Aug 08 06:08:18 PM PDT 24
Peak memory 204056 kb
Host smart-65c27bba-d7a3-4974-88e5-e2a744a47143
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689138235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.689138235
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.2632653894
Short name T1148
Test name
Test status
Simulation time 481391315 ps
CPU time 2.23 seconds
Started Aug 08 06:08:22 PM PDT 24
Finished Aug 08 06:08:24 PM PDT 24
Peak memory 215648 kb
Host smart-a97d485d-f171-4425-b71f-508efae79812
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632653894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.2632653894
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.2261296813
Short name T1109
Test name
Test status
Simulation time 29967983 ps
CPU time 0.66 seconds
Started Aug 08 06:08:19 PM PDT 24
Finished Aug 08 06:08:20 PM PDT 24
Peak memory 204284 kb
Host smart-511d5af0-dd6c-4184-9058-a7dc7064294c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261296813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.2261296813
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3856810936
Short name T1050
Test name
Test status
Simulation time 427948656 ps
CPU time 3.02 seconds
Started Aug 08 06:08:23 PM PDT 24
Finished Aug 08 06:08:26 PM PDT 24
Peak memory 215576 kb
Host smart-7f48eeac-0742-485b-9b67-553660c7fe52
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856810936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.3856810936
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.3650644049
Short name T106
Test name
Test status
Simulation time 247561650 ps
CPU time 3.64 seconds
Started Aug 08 06:08:23 PM PDT 24
Finished Aug 08 06:08:27 PM PDT 24
Peak memory 215856 kb
Host smart-ac3e69a2-092e-4bd4-b156-53d94284122d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650644049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.3
650644049
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3626097308
Short name T169
Test name
Test status
Simulation time 809576852 ps
CPU time 21.15 seconds
Started Aug 08 06:08:20 PM PDT 24
Finished Aug 08 06:08:41 PM PDT 24
Peak memory 215796 kb
Host smart-2f6232b4-1050-4610-8e6e-47848affeca2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626097308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.3626097308
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1537228287
Short name T1056
Test name
Test status
Simulation time 2242404102 ps
CPU time 15.05 seconds
Started Aug 08 06:08:27 PM PDT 24
Finished Aug 08 06:08:42 PM PDT 24
Peak memory 207528 kb
Host smart-fec88cf9-c867-4c93-901a-cc67e983c03a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537228287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.1537228287
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.1377361517
Short name T1075
Test name
Test status
Simulation time 1406758259 ps
CPU time 22.49 seconds
Started Aug 08 06:08:29 PM PDT 24
Finished Aug 08 06:08:51 PM PDT 24
Peak memory 207332 kb
Host smart-1cd4a2d0-963b-495a-9c44-7fbf056cccd3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377361517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.1377361517
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3079497532
Short name T1070
Test name
Test status
Simulation time 79735021 ps
CPU time 0.93 seconds
Started Aug 08 06:08:23 PM PDT 24
Finished Aug 08 06:08:24 PM PDT 24
Peak memory 207144 kb
Host smart-ca653cb0-9c1d-42cc-9ca9-f95386f0c3ec
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079497532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.3079497532
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.1628116573
Short name T1091
Test name
Test status
Simulation time 1161091375 ps
CPU time 2.59 seconds
Started Aug 08 06:08:28 PM PDT 24
Finished Aug 08 06:08:30 PM PDT 24
Peak memory 216620 kb
Host smart-5311dba7-0baa-4698-a8c9-e4a1a82f9021
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628116573 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.1628116573
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.1163397823
Short name T1124
Test name
Test status
Simulation time 145797599 ps
CPU time 2.46 seconds
Started Aug 08 06:08:24 PM PDT 24
Finished Aug 08 06:08:26 PM PDT 24
Peak memory 215580 kb
Host smart-4b45b690-fdec-4b46-bc77-ebf84251f664
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163397823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.1
163397823
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.262060779
Short name T1081
Test name
Test status
Simulation time 195800927 ps
CPU time 0.72 seconds
Started Aug 08 06:08:23 PM PDT 24
Finished Aug 08 06:08:24 PM PDT 24
Peak memory 204324 kb
Host smart-49ded274-8489-461c-aa6f-dad0540da7d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262060779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.262060779
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.4132986773
Short name T1112
Test name
Test status
Simulation time 229467347 ps
CPU time 2.08 seconds
Started Aug 08 06:08:27 PM PDT 24
Finished Aug 08 06:08:29 PM PDT 24
Peak memory 215616 kb
Host smart-1cf8c4fd-7baa-4263-8f12-2296276842a3
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132986773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.4132986773
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.2691203941
Short name T1055
Test name
Test status
Simulation time 157717148 ps
CPU time 0.68 seconds
Started Aug 08 06:08:26 PM PDT 24
Finished Aug 08 06:08:27 PM PDT 24
Peak memory 204220 kb
Host smart-10e43deb-e71d-4d68-8c0e-abf4a72ed6a7
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691203941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.2691203941
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2471073378
Short name T1053
Test name
Test status
Simulation time 59186089 ps
CPU time 1.9 seconds
Started Aug 08 06:08:28 PM PDT 24
Finished Aug 08 06:08:30 PM PDT 24
Peak memory 215560 kb
Host smart-c699cd24-3950-4ba2-88a4-4430d5eb7bf9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471073378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.2471073378
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.447572101
Short name T109
Test name
Test status
Simulation time 222569300 ps
CPU time 3.69 seconds
Started Aug 08 06:08:29 PM PDT 24
Finished Aug 08 06:08:33 PM PDT 24
Peak memory 215820 kb
Host smart-77c2c30e-d8cd-4185-90d9-c4e240c7797f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447572101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.447572101
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.3994008325
Short name T96
Test name
Test status
Simulation time 211766263 ps
CPU time 13.27 seconds
Started Aug 08 06:08:19 PM PDT 24
Finished Aug 08 06:08:33 PM PDT 24
Peak memory 215508 kb
Host smart-a3cedade-6557-4b23-a180-7505e77e2f1d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994008325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.3994008325
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3212082964
Short name T1087
Test name
Test status
Simulation time 45966180 ps
CPU time 2.99 seconds
Started Aug 08 06:08:39 PM PDT 24
Finished Aug 08 06:08:43 PM PDT 24
Peak memory 218448 kb
Host smart-c26ca592-6a71-4c5c-b8bd-a8d82a997984
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212082964 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.3212082964
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.2218279413
Short name T130
Test name
Test status
Simulation time 336511890 ps
CPU time 2.83 seconds
Started Aug 08 06:08:35 PM PDT 24
Finished Aug 08 06:08:38 PM PDT 24
Peak memory 207380 kb
Host smart-eeebb269-730d-4b48-8eb5-77874e46d94e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218279413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
2218279413
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.2583730790
Short name T1048
Test name
Test status
Simulation time 12233955 ps
CPU time 0.69 seconds
Started Aug 08 06:08:35 PM PDT 24
Finished Aug 08 06:08:36 PM PDT 24
Peak memory 204396 kb
Host smart-f93de6cc-37a2-4388-8a2a-25ca19149984
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583730790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
2583730790
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1827898267
Short name T155
Test name
Test status
Simulation time 143727001 ps
CPU time 1.79 seconds
Started Aug 08 06:08:34 PM PDT 24
Finished Aug 08 06:08:36 PM PDT 24
Peak memory 215520 kb
Host smart-54afa2ca-bc8b-4cf6-9256-4f36264dd88b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827898267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.1827898267
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.1348273237
Short name T104
Test name
Test status
Simulation time 140024737 ps
CPU time 3.59 seconds
Started Aug 08 06:08:34 PM PDT 24
Finished Aug 08 06:08:38 PM PDT 24
Peak memory 215740 kb
Host smart-79d711a7-3f06-48a9-9ebb-3737b76b05fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348273237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
1348273237
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.4117328874
Short name T93
Test name
Test status
Simulation time 276192355 ps
CPU time 7.6 seconds
Started Aug 08 06:08:34 PM PDT 24
Finished Aug 08 06:08:41 PM PDT 24
Peak memory 215548 kb
Host smart-4b1548e3-4903-4902-bbed-7d68fd653f83
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117328874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.4117328874
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3748546613
Short name T1088
Test name
Test status
Simulation time 157302101 ps
CPU time 3.12 seconds
Started Aug 08 06:08:35 PM PDT 24
Finished Aug 08 06:08:39 PM PDT 24
Peak memory 217768 kb
Host smart-2bc2303f-db59-49b6-bf9d-f710f3d0dac1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748546613 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.3748546613
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.3071576341
Short name T1069
Test name
Test status
Simulation time 127494231 ps
CPU time 2.87 seconds
Started Aug 08 06:08:34 PM PDT 24
Finished Aug 08 06:08:37 PM PDT 24
Peak memory 207352 kb
Host smart-da0a5ad7-2c53-45ce-bfb5-775ba1cb3a92
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071576341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
3071576341
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.2269041139
Short name T1066
Test name
Test status
Simulation time 49612147 ps
CPU time 0.71 seconds
Started Aug 08 06:08:32 PM PDT 24
Finished Aug 08 06:08:32 PM PDT 24
Peak memory 204024 kb
Host smart-88baeffc-3d3d-4d4a-b3a2-ef1745856f5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269041139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
2269041139
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.1260033835
Short name T1094
Test name
Test status
Simulation time 47958325 ps
CPU time 2.8 seconds
Started Aug 08 06:08:34 PM PDT 24
Finished Aug 08 06:08:37 PM PDT 24
Peak memory 215548 kb
Host smart-0f60303b-e0ce-4a80-85b2-52599e6d3203
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260033835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.1260033835
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.2065377998
Short name T108
Test name
Test status
Simulation time 175027145 ps
CPU time 3.85 seconds
Started Aug 08 06:08:36 PM PDT 24
Finished Aug 08 06:08:40 PM PDT 24
Peak memory 215836 kb
Host smart-fc1853d8-56ec-48a2-a78c-cebd9df35506
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065377998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
2065377998
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.2143432852
Short name T1144
Test name
Test status
Simulation time 2088394230 ps
CPU time 7.12 seconds
Started Aug 08 06:08:39 PM PDT 24
Finished Aug 08 06:08:47 PM PDT 24
Peak memory 215564 kb
Host smart-e718b0c0-b3b8-4e11-ae3b-efa09462ee68
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143432852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.2143432852
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.1899096271
Short name T1104
Test name
Test status
Simulation time 105778677 ps
CPU time 1.74 seconds
Started Aug 08 06:08:35 PM PDT 24
Finished Aug 08 06:08:37 PM PDT 24
Peak memory 215800 kb
Host smart-7a92e327-32ca-4575-aef5-16f4cf93a6b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899096271 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.1899096271
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.3730787669
Short name T1117
Test name
Test status
Simulation time 152482301 ps
CPU time 2.34 seconds
Started Aug 08 06:08:35 PM PDT 24
Finished Aug 08 06:08:37 PM PDT 24
Peak memory 215516 kb
Host smart-c1cac00b-9bb9-427a-aab3-01ad1d5c0ee4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730787669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
3730787669
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.2392406743
Short name T1041
Test name
Test status
Simulation time 36736142 ps
CPU time 0.7 seconds
Started Aug 08 06:08:36 PM PDT 24
Finished Aug 08 06:08:37 PM PDT 24
Peak memory 203984 kb
Host smart-9e3e1ee9-a2fc-493e-80f6-6d961abae5e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392406743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
2392406743
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.56710379
Short name T1052
Test name
Test status
Simulation time 44582764 ps
CPU time 2.83 seconds
Started Aug 08 06:08:42 PM PDT 24
Finished Aug 08 06:08:45 PM PDT 24
Peak memory 215428 kb
Host smart-7807a66e-7641-493f-8682-035cbef09592
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56710379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sp
i_device_same_csr_outstanding.56710379
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.352493477
Short name T113
Test name
Test status
Simulation time 164773933 ps
CPU time 2.26 seconds
Started Aug 08 06:08:43 PM PDT 24
Finished Aug 08 06:08:45 PM PDT 24
Peak memory 215728 kb
Host smart-7fd10c83-d42b-466c-8544-e276ccdfbff6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352493477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.352493477
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.704797517
Short name T1067
Test name
Test status
Simulation time 4004281102 ps
CPU time 13 seconds
Started Aug 08 06:08:34 PM PDT 24
Finished Aug 08 06:08:47 PM PDT 24
Peak memory 215936 kb
Host smart-6516b758-3da9-409b-8bf2-35e6a250d7a1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704797517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device
_tl_intg_err.704797517
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.3561570205
Short name T90
Test name
Test status
Simulation time 98484051 ps
CPU time 2.81 seconds
Started Aug 08 06:08:35 PM PDT 24
Finished Aug 08 06:08:38 PM PDT 24
Peak memory 216720 kb
Host smart-d6cc8e32-2bcf-4e14-8a01-4fb43bd890d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561570205 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.3561570205
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.3605288131
Short name T122
Test name
Test status
Simulation time 35629316 ps
CPU time 1.24 seconds
Started Aug 08 06:08:38 PM PDT 24
Finished Aug 08 06:08:40 PM PDT 24
Peak memory 215632 kb
Host smart-ee82e9c4-b7e8-45a7-a872-0faef3618c96
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605288131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
3605288131
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.2766200011
Short name T1051
Test name
Test status
Simulation time 12510337 ps
CPU time 0.69 seconds
Started Aug 08 06:08:39 PM PDT 24
Finished Aug 08 06:08:40 PM PDT 24
Peak memory 204056 kb
Host smart-664f2694-bf0d-4a2c-9a2c-2617ebbe04ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766200011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
2766200011
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.50627131
Short name T1049
Test name
Test status
Simulation time 45231984 ps
CPU time 2.63 seconds
Started Aug 08 06:08:36 PM PDT 24
Finished Aug 08 06:08:39 PM PDT 24
Peak memory 215488 kb
Host smart-1653dd4f-e7cd-45e8-b610-600acb23f86b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50627131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sp
i_device_same_csr_outstanding.50627131
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.73599637
Short name T110
Test name
Test status
Simulation time 734991584 ps
CPU time 5.09 seconds
Started Aug 08 06:08:37 PM PDT 24
Finished Aug 08 06:08:42 PM PDT 24
Peak memory 215732 kb
Host smart-34cf4990-a091-44d1-8b3e-ca36c8094797
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73599637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.73599637
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3370589842
Short name T1129
Test name
Test status
Simulation time 198100455 ps
CPU time 2.62 seconds
Started Aug 08 06:08:37 PM PDT 24
Finished Aug 08 06:08:40 PM PDT 24
Peak memory 216824 kb
Host smart-66877d9a-9806-4ca1-8b20-1be3b21d8d94
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370589842 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.3370589842
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.2136527716
Short name T1064
Test name
Test status
Simulation time 132427446 ps
CPU time 1.8 seconds
Started Aug 08 06:08:40 PM PDT 24
Finished Aug 08 06:08:42 PM PDT 24
Peak memory 207272 kb
Host smart-f46066f4-0bd4-44c3-a3e0-22ab346482f2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136527716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
2136527716
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.995798285
Short name T1139
Test name
Test status
Simulation time 68997785 ps
CPU time 0.78 seconds
Started Aug 08 06:08:41 PM PDT 24
Finished Aug 08 06:08:42 PM PDT 24
Peak memory 203896 kb
Host smart-b2ff6d93-bbdd-42b7-84b5-1a39b498d581
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995798285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.995798285
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2350830952
Short name T1079
Test name
Test status
Simulation time 558098724 ps
CPU time 3.05 seconds
Started Aug 08 06:08:41 PM PDT 24
Finished Aug 08 06:08:44 PM PDT 24
Peak memory 215488 kb
Host smart-214d3110-89fb-4229-8b1e-bae32567c695
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350830952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.2350830952
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.2244615043
Short name T89
Test name
Test status
Simulation time 441911461 ps
CPU time 2.58 seconds
Started Aug 08 06:08:47 PM PDT 24
Finished Aug 08 06:08:50 PM PDT 24
Peak memory 215828 kb
Host smart-43ee1c6d-4046-45e2-9382-1482b66031be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244615043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
2244615043
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.3575728646
Short name T157
Test name
Test status
Simulation time 638619505 ps
CPU time 7.29 seconds
Started Aug 08 06:08:34 PM PDT 24
Finished Aug 08 06:08:42 PM PDT 24
Peak memory 215564 kb
Host smart-30d2f3c0-a9dd-4a13-8daa-6a72c064a749
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575728646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.3575728646
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.3606055998
Short name T1142
Test name
Test status
Simulation time 100657379 ps
CPU time 2.65 seconds
Started Aug 08 06:08:34 PM PDT 24
Finished Aug 08 06:08:36 PM PDT 24
Peak memory 217292 kb
Host smart-8db8d5bc-456f-4b9b-bebc-cb59648ad88e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606055998 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.3606055998
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.1542287327
Short name T127
Test name
Test status
Simulation time 111199444 ps
CPU time 2.74 seconds
Started Aug 08 06:08:43 PM PDT 24
Finished Aug 08 06:08:46 PM PDT 24
Peak memory 215592 kb
Host smart-4e52cefd-0506-4f94-b801-ce0dbd08bcb7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542287327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
1542287327
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.2170460719
Short name T1033
Test name
Test status
Simulation time 13276110 ps
CPU time 0.74 seconds
Started Aug 08 06:08:35 PM PDT 24
Finished Aug 08 06:08:36 PM PDT 24
Peak memory 204080 kb
Host smart-a40a8741-aded-4eca-a3a7-9e825fd31250
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170460719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
2170460719
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.316348362
Short name T1095
Test name
Test status
Simulation time 94417281 ps
CPU time 1.62 seconds
Started Aug 08 06:08:34 PM PDT 24
Finished Aug 08 06:08:36 PM PDT 24
Peak memory 207212 kb
Host smart-c56888d1-947b-452c-b52f-904cf19e9967
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316348362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.s
pi_device_same_csr_outstanding.316348362
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.3444428750
Short name T1120
Test name
Test status
Simulation time 932535685 ps
CPU time 5.73 seconds
Started Aug 08 06:08:40 PM PDT 24
Finished Aug 08 06:08:46 PM PDT 24
Peak memory 216860 kb
Host smart-d0ee2625-6cf0-4c75-899f-4cfa28b48ce1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444428750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
3444428750
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.2243242940
Short name T111
Test name
Test status
Simulation time 1432920465 ps
CPU time 14.46 seconds
Started Aug 08 06:08:42 PM PDT 24
Finished Aug 08 06:08:57 PM PDT 24
Peak memory 216112 kb
Host smart-05e2aacf-4709-4edb-a1d0-305072548f69
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243242940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.2243242940
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.2283056492
Short name T1058
Test name
Test status
Simulation time 237256605 ps
CPU time 1.81 seconds
Started Aug 08 06:08:47 PM PDT 24
Finished Aug 08 06:08:49 PM PDT 24
Peak memory 216528 kb
Host smart-5211b14c-14c8-41f8-a02d-8ea48345151d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283056492 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.2283056492
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.1171533702
Short name T1083
Test name
Test status
Simulation time 81893759 ps
CPU time 2.08 seconds
Started Aug 08 06:08:45 PM PDT 24
Finished Aug 08 06:08:47 PM PDT 24
Peak memory 207416 kb
Host smart-e340e843-a4d3-4501-bf42-f9753a5f0711
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171533702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
1171533702
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.2286109473
Short name T1029
Test name
Test status
Simulation time 44680032 ps
CPU time 0.8 seconds
Started Aug 08 06:08:43 PM PDT 24
Finished Aug 08 06:08:44 PM PDT 24
Peak memory 204284 kb
Host smart-c8c9a63b-f91c-42b0-a94f-386ee225e19b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286109473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
2286109473
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.621918559
Short name T1107
Test name
Test status
Simulation time 412582841 ps
CPU time 3.74 seconds
Started Aug 08 06:08:47 PM PDT 24
Finished Aug 08 06:08:51 PM PDT 24
Peak memory 215584 kb
Host smart-2ff37045-c7a2-4502-aa8d-91ea19112fad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621918559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.s
pi_device_same_csr_outstanding.621918559
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.3919523502
Short name T105
Test name
Test status
Simulation time 2903803342 ps
CPU time 4.39 seconds
Started Aug 08 06:08:40 PM PDT 24
Finished Aug 08 06:08:44 PM PDT 24
Peak memory 216028 kb
Host smart-d950a293-20ad-460a-8fda-826a3c9eafc8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919523502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
3919523502
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1696114281
Short name T1111
Test name
Test status
Simulation time 1240971773 ps
CPU time 19.42 seconds
Started Aug 08 06:08:42 PM PDT 24
Finished Aug 08 06:09:01 PM PDT 24
Peak memory 215568 kb
Host smart-277c3dd8-e6b4-4b78-9f19-1fda7931c12f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696114281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.1696114281
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.3662467212
Short name T115
Test name
Test status
Simulation time 41443107 ps
CPU time 3.09 seconds
Started Aug 08 06:08:47 PM PDT 24
Finished Aug 08 06:08:50 PM PDT 24
Peak memory 217920 kb
Host smart-26cdcce5-2c3c-4c97-a95c-e9090f32fc6e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662467212 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.3662467212
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.2018907158
Short name T1060
Test name
Test status
Simulation time 239272655 ps
CPU time 1.95 seconds
Started Aug 08 06:08:43 PM PDT 24
Finished Aug 08 06:08:45 PM PDT 24
Peak memory 207412 kb
Host smart-290d5172-f2d5-4c59-b543-3ff51e90e076
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018907158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
2018907158
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.2919335343
Short name T1065
Test name
Test status
Simulation time 25180151 ps
CPU time 0.73 seconds
Started Aug 08 06:08:47 PM PDT 24
Finished Aug 08 06:08:48 PM PDT 24
Peak memory 204048 kb
Host smart-882652c2-4b72-45ff-9ef7-74bed56f2d48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919335343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
2919335343
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.3458319114
Short name T1125
Test name
Test status
Simulation time 419856208 ps
CPU time 3.18 seconds
Started Aug 08 06:08:47 PM PDT 24
Finished Aug 08 06:08:50 PM PDT 24
Peak memory 215596 kb
Host smart-34e25cbd-59da-48d8-9a7c-e132e9f22ee4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458319114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.3458319114
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.2907355668
Short name T165
Test name
Test status
Simulation time 128633068 ps
CPU time 3.76 seconds
Started Aug 08 06:08:48 PM PDT 24
Finished Aug 08 06:08:52 PM PDT 24
Peak memory 215884 kb
Host smart-54651ad1-8a39-4c02-b854-4e92395b53d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907355668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
2907355668
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.4280624123
Short name T1106
Test name
Test status
Simulation time 756360281 ps
CPU time 12.45 seconds
Started Aug 08 06:08:49 PM PDT 24
Finished Aug 08 06:09:01 PM PDT 24
Peak memory 215564 kb
Host smart-acee68ab-d88e-4fe0-abad-a01bbbabaa32
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280624123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.4280624123
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.1116327145
Short name T117
Test name
Test status
Simulation time 86820775 ps
CPU time 2.4 seconds
Started Aug 08 06:08:42 PM PDT 24
Finished Aug 08 06:08:44 PM PDT 24
Peak memory 216736 kb
Host smart-09419ada-2527-4f96-a51d-12e113b8d937
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116327145 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.1116327145
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.2048311509
Short name T1135
Test name
Test status
Simulation time 82662722 ps
CPU time 2.26 seconds
Started Aug 08 06:08:45 PM PDT 24
Finished Aug 08 06:08:48 PM PDT 24
Peak memory 207432 kb
Host smart-15f9f1cc-f5df-4a0f-afe4-42fab88ace0e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048311509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
2048311509
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.1380666970
Short name T1122
Test name
Test status
Simulation time 13427976 ps
CPU time 0.7 seconds
Started Aug 08 06:08:43 PM PDT 24
Finished Aug 08 06:08:43 PM PDT 24
Peak memory 204384 kb
Host smart-d4e1e3ee-c44a-49ed-a73f-5b9573175b9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380666970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
1380666970
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.1084386797
Short name T156
Test name
Test status
Simulation time 145051103 ps
CPU time 3.18 seconds
Started Aug 08 06:08:46 PM PDT 24
Finished Aug 08 06:08:50 PM PDT 24
Peak memory 215512 kb
Host smart-b9c8c33d-1983-4fa3-8d13-5fb17b36c59d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084386797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.1084386797
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.844399293
Short name T1114
Test name
Test status
Simulation time 509139193 ps
CPU time 3.86 seconds
Started Aug 08 06:08:43 PM PDT 24
Finished Aug 08 06:08:47 PM PDT 24
Peak memory 215720 kb
Host smart-f37daa32-ca53-4bac-b48b-ea4807015051
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844399293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.844399293
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.64786951
Short name T170
Test name
Test status
Simulation time 542023491 ps
CPU time 13.88 seconds
Started Aug 08 06:08:43 PM PDT 24
Finished Aug 08 06:08:57 PM PDT 24
Peak memory 216316 kb
Host smart-5b9aed03-5098-4255-8bbe-a07f28cd5800
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64786951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_
tl_intg_err.64786951
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2165659263
Short name T118
Test name
Test status
Simulation time 381044251 ps
CPU time 2.54 seconds
Started Aug 08 06:08:43 PM PDT 24
Finished Aug 08 06:08:46 PM PDT 24
Peak memory 217360 kb
Host smart-487e773c-4926-41d8-a14d-663bf6f9a717
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165659263 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.2165659263
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.3561407279
Short name T1147
Test name
Test status
Simulation time 28939859 ps
CPU time 1.82 seconds
Started Aug 08 06:08:45 PM PDT 24
Finished Aug 08 06:08:47 PM PDT 24
Peak memory 215528 kb
Host smart-4edc1f9d-f1c6-4a65-a295-6979d3c834f2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561407279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
3561407279
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.1667666401
Short name T1141
Test name
Test status
Simulation time 17331708 ps
CPU time 0.81 seconds
Started Aug 08 06:08:44 PM PDT 24
Finished Aug 08 06:08:45 PM PDT 24
Peak memory 204352 kb
Host smart-6bb81da0-69ed-4564-bdf6-e1f1ad70f500
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667666401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
1667666401
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.4075514952
Short name T1102
Test name
Test status
Simulation time 644203865 ps
CPU time 4.12 seconds
Started Aug 08 06:08:47 PM PDT 24
Finished Aug 08 06:08:51 PM PDT 24
Peak memory 215280 kb
Host smart-8df9e925-eefb-4953-a721-2013c672f9ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075514952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.4075514952
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.1897612347
Short name T1131
Test name
Test status
Simulation time 122362953 ps
CPU time 3.61 seconds
Started Aug 08 06:08:47 PM PDT 24
Finished Aug 08 06:08:51 PM PDT 24
Peak memory 215788 kb
Host smart-5bc92004-9b4a-41f7-99e5-c50ad684e74b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897612347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
1897612347
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.1776381155
Short name T128
Test name
Test status
Simulation time 422656384 ps
CPU time 7.61 seconds
Started Aug 08 06:08:38 PM PDT 24
Finished Aug 08 06:08:45 PM PDT 24
Peak memory 207360 kb
Host smart-87a760cb-1493-4db7-ac87-299fb1f5c242
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776381155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.1776381155
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.3663099822
Short name T1133
Test name
Test status
Simulation time 2790628446 ps
CPU time 38.26 seconds
Started Aug 08 06:08:26 PM PDT 24
Finished Aug 08 06:09:05 PM PDT 24
Peak memory 207532 kb
Host smart-3524da88-f711-45c4-93a5-780bb44148e0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663099822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.3663099822
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.548890512
Short name T77
Test name
Test status
Simulation time 39097223 ps
CPU time 1.4 seconds
Started Aug 08 06:08:28 PM PDT 24
Finished Aug 08 06:08:30 PM PDT 24
Peak memory 216508 kb
Host smart-5e13a276-4e9b-49f0-b17d-855e9ba32aeb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548890512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_hw_reset.548890512
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.537425553
Short name T1121
Test name
Test status
Simulation time 467223912 ps
CPU time 3.62 seconds
Started Aug 08 06:08:31 PM PDT 24
Finished Aug 08 06:08:35 PM PDT 24
Peak memory 218156 kb
Host smart-87953434-f767-4cf6-a18f-f1bd0f5366a9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537425553 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.537425553
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.767863228
Short name T121
Test name
Test status
Simulation time 84897304 ps
CPU time 1.73 seconds
Started Aug 08 06:08:30 PM PDT 24
Finished Aug 08 06:08:32 PM PDT 24
Peak memory 215624 kb
Host smart-364c6d26-fb43-4cec-9d77-e934f4f0d4ec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767863228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.767863228
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.1672473730
Short name T1034
Test name
Test status
Simulation time 55031459 ps
CPU time 0.75 seconds
Started Aug 08 06:08:26 PM PDT 24
Finished Aug 08 06:08:26 PM PDT 24
Peak memory 204360 kb
Host smart-efa23e55-de7d-426b-93a3-86e372cedc65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672473730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.1
672473730
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2509637948
Short name T120
Test name
Test status
Simulation time 67675518 ps
CPU time 2.2 seconds
Started Aug 08 06:08:31 PM PDT 24
Finished Aug 08 06:08:33 PM PDT 24
Peak memory 215556 kb
Host smart-d0863990-8e13-45fb-8046-8eb9ae6a56a9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509637948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.2509637948
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.2496281621
Short name T1045
Test name
Test status
Simulation time 22736623 ps
CPU time 0.68 seconds
Started Aug 08 06:08:38 PM PDT 24
Finished Aug 08 06:08:39 PM PDT 24
Peak memory 203944 kb
Host smart-f5e92f5f-f346-4473-910e-287cf8c6a8e8
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496281621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.2496281621
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1364680212
Short name T1110
Test name
Test status
Simulation time 59169384 ps
CPU time 3.73 seconds
Started Aug 08 06:08:33 PM PDT 24
Finished Aug 08 06:08:37 PM PDT 24
Peak memory 215620 kb
Host smart-9e342713-1b60-4424-a782-3f84c9287c26
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364680212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.1364680212
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.2719936508
Short name T1101
Test name
Test status
Simulation time 62338253 ps
CPU time 3.67 seconds
Started Aug 08 06:08:26 PM PDT 24
Finished Aug 08 06:08:29 PM PDT 24
Peak memory 215808 kb
Host smart-104474db-c0f4-4ff1-b29c-7df620f902d6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719936508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.2
719936508
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.53113380
Short name T1137
Test name
Test status
Simulation time 340674308 ps
CPU time 7.59 seconds
Started Aug 08 06:08:40 PM PDT 24
Finished Aug 08 06:08:48 PM PDT 24
Peak memory 216156 kb
Host smart-5d6218d2-f981-41f9-afb7-b85cee3f8fc5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53113380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_t
l_intg_err.53113380
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.2950720895
Short name T1073
Test name
Test status
Simulation time 36964992 ps
CPU time 0.75 seconds
Started Aug 08 06:08:42 PM PDT 24
Finished Aug 08 06:08:43 PM PDT 24
Peak memory 204324 kb
Host smart-871fb369-5182-4492-985e-cf6eb3ff7baf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950720895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
2950720895
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.1121583076
Short name T1127
Test name
Test status
Simulation time 12041308 ps
CPU time 0.67 seconds
Started Aug 08 06:08:47 PM PDT 24
Finished Aug 08 06:08:48 PM PDT 24
Peak memory 204032 kb
Host smart-9f5b2135-7b0d-45dc-9d06-4e91542f3145
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121583076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
1121583076
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.2604535926
Short name T1072
Test name
Test status
Simulation time 113471552 ps
CPU time 0.72 seconds
Started Aug 08 06:08:42 PM PDT 24
Finished Aug 08 06:08:43 PM PDT 24
Peak memory 203964 kb
Host smart-ec382795-270a-4b78-8622-559d03ec8804
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604535926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
2604535926
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2674653005
Short name T1076
Test name
Test status
Simulation time 34395054 ps
CPU time 0.7 seconds
Started Aug 08 06:08:51 PM PDT 24
Finished Aug 08 06:08:52 PM PDT 24
Peak memory 204364 kb
Host smart-4aee3672-f9bc-47c6-99c2-d963b3d61582
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674653005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
2674653005
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.706336206
Short name T1119
Test name
Test status
Simulation time 115111723 ps
CPU time 0.74 seconds
Started Aug 08 06:08:42 PM PDT 24
Finished Aug 08 06:08:43 PM PDT 24
Peak memory 204344 kb
Host smart-6126d0d6-19ee-44a9-be43-570333ad0f62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706336206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.706336206
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.3774545202
Short name T1040
Test name
Test status
Simulation time 16736299 ps
CPU time 0.72 seconds
Started Aug 08 06:08:44 PM PDT 24
Finished Aug 08 06:08:45 PM PDT 24
Peak memory 204004 kb
Host smart-e7a2353b-5092-4669-8de5-0d2ed8b409a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774545202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
3774545202
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2355571350
Short name T1092
Test name
Test status
Simulation time 31988025 ps
CPU time 0.72 seconds
Started Aug 08 06:08:51 PM PDT 24
Finished Aug 08 06:08:52 PM PDT 24
Peak memory 204360 kb
Host smart-329811d2-85ab-4a77-b015-1fa32d068b5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355571350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
2355571350
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.2276610937
Short name T1036
Test name
Test status
Simulation time 42351178 ps
CPU time 0.71 seconds
Started Aug 08 06:08:43 PM PDT 24
Finished Aug 08 06:08:44 PM PDT 24
Peak memory 204384 kb
Host smart-e39bdf4d-826d-4fda-bf04-338238a4311d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276610937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
2276610937
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.2344924044
Short name T1097
Test name
Test status
Simulation time 13612499 ps
CPU time 0.72 seconds
Started Aug 08 06:08:51 PM PDT 24
Finished Aug 08 06:08:52 PM PDT 24
Peak memory 204308 kb
Host smart-823ebdee-0343-4a25-8bb6-2cb65f42c4d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344924044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
2344924044
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2977715384
Short name T1039
Test name
Test status
Simulation time 76060689 ps
CPU time 0.75 seconds
Started Aug 08 06:08:45 PM PDT 24
Finished Aug 08 06:08:46 PM PDT 24
Peak memory 204360 kb
Host smart-d312a799-caf9-4108-88b6-d6b251089549
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977715384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
2977715384
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.528833239
Short name T1099
Test name
Test status
Simulation time 3321210644 ps
CPU time 17.41 seconds
Started Aug 08 06:08:38 PM PDT 24
Finished Aug 08 06:08:55 PM PDT 24
Peak memory 215532 kb
Host smart-7ef48cd4-c550-45a5-acca-f9fc73d29c09
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528833239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_aliasing.528833239
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.2808140319
Short name T1118
Test name
Test status
Simulation time 1850876463 ps
CPU time 35.66 seconds
Started Aug 08 06:08:39 PM PDT 24
Finished Aug 08 06:09:15 PM PDT 24
Peak memory 207276 kb
Host smart-a241f05b-61ec-403f-a627-a119e2f66e95
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808140319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.2808140319
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.2734896910
Short name T76
Test name
Test status
Simulation time 90888864 ps
CPU time 0.95 seconds
Started Aug 08 06:08:37 PM PDT 24
Finished Aug 08 06:08:38 PM PDT 24
Peak memory 207044 kb
Host smart-f3d025b0-c0e8-4cc9-a156-3946f821ed99
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734896910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.2734896910
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.720693231
Short name T1061
Test name
Test status
Simulation time 564103795 ps
CPU time 3.5 seconds
Started Aug 08 06:08:26 PM PDT 24
Finished Aug 08 06:08:29 PM PDT 24
Peak memory 217320 kb
Host smart-c38f1f71-9149-43d8-bc2e-cd3a4cab1ea4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720693231 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.720693231
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.3308524740
Short name T1138
Test name
Test status
Simulation time 128650612 ps
CPU time 1.26 seconds
Started Aug 08 06:08:29 PM PDT 24
Finished Aug 08 06:08:30 PM PDT 24
Peak memory 215604 kb
Host smart-b0a11ff8-032f-40fb-9013-e6fc40c069b1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308524740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.3
308524740
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.1627789367
Short name T1054
Test name
Test status
Simulation time 91475944 ps
CPU time 0.76 seconds
Started Aug 08 06:08:34 PM PDT 24
Finished Aug 08 06:08:35 PM PDT 24
Peak memory 204020 kb
Host smart-8916107b-1fc8-45ad-a230-647788a557dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627789367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.1
627789367
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.3698267709
Short name T123
Test name
Test status
Simulation time 72421615 ps
CPU time 1.67 seconds
Started Aug 08 06:08:32 PM PDT 24
Finished Aug 08 06:08:34 PM PDT 24
Peak memory 215608 kb
Host smart-b3340cd8-5476-415e-9e42-c522df3142ca
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698267709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.3698267709
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.2485863281
Short name T1085
Test name
Test status
Simulation time 20484514 ps
CPU time 0.64 seconds
Started Aug 08 06:08:38 PM PDT 24
Finished Aug 08 06:08:39 PM PDT 24
Peak memory 203896 kb
Host smart-4d8828b4-9678-4f5f-92a8-6da4458f4946
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485863281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.2485863281
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.3818905714
Short name T140
Test name
Test status
Simulation time 45526557 ps
CPU time 1.63 seconds
Started Aug 08 06:08:28 PM PDT 24
Finished Aug 08 06:08:30 PM PDT 24
Peak memory 215480 kb
Host smart-cdd59cdb-4908-400d-82df-58ea9d28a5f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818905714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.3818905714
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.3718628359
Short name T116
Test name
Test status
Simulation time 106609558 ps
CPU time 1.97 seconds
Started Aug 08 06:08:24 PM PDT 24
Finished Aug 08 06:08:26 PM PDT 24
Peak memory 215832 kb
Host smart-381c00f1-eb60-4785-b3f0-eb512b6f1ca1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718628359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.3
718628359
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.3856769061
Short name T1077
Test name
Test status
Simulation time 1094233324 ps
CPU time 7.41 seconds
Started Aug 08 06:08:27 PM PDT 24
Finished Aug 08 06:08:34 PM PDT 24
Peak memory 222292 kb
Host smart-339a8a1a-d67c-4653-9f2c-c906c3b1b331
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856769061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.3856769061
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.2717055628
Short name T1116
Test name
Test status
Simulation time 12815355 ps
CPU time 0.68 seconds
Started Aug 08 06:08:45 PM PDT 24
Finished Aug 08 06:08:45 PM PDT 24
Peak memory 204000 kb
Host smart-31f84e76-5bf0-4eb1-aaa8-fb0a329d7c97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717055628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
2717055628
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.1853052282
Short name T1038
Test name
Test status
Simulation time 42002128 ps
CPU time 0.72 seconds
Started Aug 08 06:08:44 PM PDT 24
Finished Aug 08 06:08:45 PM PDT 24
Peak memory 204016 kb
Host smart-3c13f291-8b32-480b-b487-b1b95428add4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853052282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
1853052282
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.3518723349
Short name T1098
Test name
Test status
Simulation time 62730986 ps
CPU time 0.73 seconds
Started Aug 08 06:08:46 PM PDT 24
Finished Aug 08 06:08:47 PM PDT 24
Peak memory 203972 kb
Host smart-ad7ac088-4c2f-4b60-8a1e-e3227d6d58d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518723349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
3518723349
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.3411194084
Short name T1047
Test name
Test status
Simulation time 42007336 ps
CPU time 0.67 seconds
Started Aug 08 06:08:45 PM PDT 24
Finished Aug 08 06:08:46 PM PDT 24
Peak memory 203988 kb
Host smart-9f648db9-6d79-453d-8789-2c06dba8eb7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411194084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
3411194084
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.2829698405
Short name T1150
Test name
Test status
Simulation time 18608911 ps
CPU time 0.74 seconds
Started Aug 08 06:08:43 PM PDT 24
Finished Aug 08 06:08:44 PM PDT 24
Peak memory 204080 kb
Host smart-a321ab2f-a68e-4e0a-868a-e398d1d32a1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829698405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
2829698405
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.4138120184
Short name T1043
Test name
Test status
Simulation time 23083296 ps
CPU time 0.7 seconds
Started Aug 08 06:08:53 PM PDT 24
Finished Aug 08 06:08:54 PM PDT 24
Peak memory 203964 kb
Host smart-0f899b68-ab31-45cd-ba3c-7b21370d9ee6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138120184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
4138120184
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.2081141539
Short name T1057
Test name
Test status
Simulation time 38325648 ps
CPU time 0.77 seconds
Started Aug 08 06:08:46 PM PDT 24
Finished Aug 08 06:08:46 PM PDT 24
Peak memory 204048 kb
Host smart-a2d7ad5f-15f6-42db-b5ad-73d3b7be424e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081141539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
2081141539
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.261328898
Short name T1126
Test name
Test status
Simulation time 11108498 ps
CPU time 0.72 seconds
Started Aug 08 06:08:48 PM PDT 24
Finished Aug 08 06:08:49 PM PDT 24
Peak memory 204052 kb
Host smart-36b3d9e6-8695-422b-9439-474ba7c6cda2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261328898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.261328898
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.2748745140
Short name T1031
Test name
Test status
Simulation time 33175611 ps
CPU time 0.75 seconds
Started Aug 08 06:08:47 PM PDT 24
Finished Aug 08 06:08:48 PM PDT 24
Peak memory 204036 kb
Host smart-27b52dc6-669d-49dc-aa68-0ca5d68f4716
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748745140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
2748745140
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.2369796647
Short name T1071
Test name
Test status
Simulation time 14135608 ps
CPU time 0.73 seconds
Started Aug 08 06:08:41 PM PDT 24
Finished Aug 08 06:08:42 PM PDT 24
Peak memory 204348 kb
Host smart-45d2e63a-4558-44e6-a2ec-dee90537932c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369796647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
2369796647
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.4253871870
Short name T129
Test name
Test status
Simulation time 1160461581 ps
CPU time 15.64 seconds
Started Aug 08 06:08:39 PM PDT 24
Finished Aug 08 06:08:54 PM PDT 24
Peak memory 215472 kb
Host smart-34a8299b-4a64-4b3e-91e2-803111f938f6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253871870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.4253871870
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.2441070431
Short name T124
Test name
Test status
Simulation time 13855825205 ps
CPU time 25.38 seconds
Started Aug 08 06:08:39 PM PDT 24
Finished Aug 08 06:09:05 PM PDT 24
Peak memory 207280 kb
Host smart-ffcfc979-1d77-44c9-afc7-9b440c41b07d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441070431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.2441070431
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3196816404
Short name T1086
Test name
Test status
Simulation time 23436016 ps
CPU time 0.98 seconds
Started Aug 08 06:08:28 PM PDT 24
Finished Aug 08 06:08:29 PM PDT 24
Peak memory 207112 kb
Host smart-384b37b7-b2f5-4a36-94bc-04271f9f3a5c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196816404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.3196816404
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.2936642649
Short name T1103
Test name
Test status
Simulation time 81780585 ps
CPU time 3.77 seconds
Started Aug 08 06:08:39 PM PDT 24
Finished Aug 08 06:08:43 PM PDT 24
Peak memory 216652 kb
Host smart-3d352bb1-babd-4a80-a20e-4d1eae510519
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936642649 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.2936642649
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.849325557
Short name T132
Test name
Test status
Simulation time 38552778 ps
CPU time 2.52 seconds
Started Aug 08 06:08:39 PM PDT 24
Finished Aug 08 06:08:42 PM PDT 24
Peak memory 220508 kb
Host smart-83a121af-2068-4f9f-a39c-eef61b745826
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849325557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.849325557
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.2598790475
Short name T1037
Test name
Test status
Simulation time 19600660 ps
CPU time 0.76 seconds
Started Aug 08 06:08:40 PM PDT 24
Finished Aug 08 06:08:41 PM PDT 24
Peak memory 203920 kb
Host smart-9ef8adf5-1453-4fcc-a0ae-0a72163d9fbd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598790475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.2
598790475
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.2815715661
Short name T125
Test name
Test status
Simulation time 21025566 ps
CPU time 1.54 seconds
Started Aug 08 06:08:24 PM PDT 24
Finished Aug 08 06:08:25 PM PDT 24
Peak memory 215536 kb
Host smart-82ef5eb9-c68e-4b89-a2bf-58b2da792cfb
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815715661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.2815715661
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1932440806
Short name T1123
Test name
Test status
Simulation time 15576792 ps
CPU time 0.66 seconds
Started Aug 08 06:08:27 PM PDT 24
Finished Aug 08 06:08:27 PM PDT 24
Peak memory 204256 kb
Host smart-c6bbc014-47ec-4644-b03e-8489778c8f34
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932440806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.1932440806
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.100413890
Short name T1093
Test name
Test status
Simulation time 108762759 ps
CPU time 3.04 seconds
Started Aug 08 06:08:27 PM PDT 24
Finished Aug 08 06:08:30 PM PDT 24
Peak memory 215516 kb
Host smart-4402c3fd-d3f4-4670-b8ce-bc42030a58a8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100413890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sp
i_device_same_csr_outstanding.100413890
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.1512785100
Short name T1113
Test name
Test status
Simulation time 73803146 ps
CPU time 1.59 seconds
Started Aug 08 06:08:31 PM PDT 24
Finished Aug 08 06:08:33 PM PDT 24
Peak memory 215760 kb
Host smart-4f1814fb-eb8a-4628-9441-b6c6b76f4400
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512785100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.1
512785100
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.3594130799
Short name T1134
Test name
Test status
Simulation time 781831125 ps
CPU time 11.46 seconds
Started Aug 08 06:08:28 PM PDT 24
Finished Aug 08 06:08:40 PM PDT 24
Peak memory 215664 kb
Host smart-05f99052-8b7f-4a89-bf2a-76b493b03036
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594130799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.3594130799
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2399900956
Short name T1046
Test name
Test status
Simulation time 11124882 ps
CPU time 0.69 seconds
Started Aug 08 06:08:42 PM PDT 24
Finished Aug 08 06:08:43 PM PDT 24
Peak memory 203996 kb
Host smart-107a75a4-fc2e-4a04-8ad6-6c2940df9926
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399900956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
2399900956
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.1983521355
Short name T1035
Test name
Test status
Simulation time 25035155 ps
CPU time 0.74 seconds
Started Aug 08 06:08:47 PM PDT 24
Finished Aug 08 06:08:48 PM PDT 24
Peak memory 204020 kb
Host smart-83cf7727-1c03-462f-b233-df1b11b470dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983521355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
1983521355
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.2282417016
Short name T1100
Test name
Test status
Simulation time 56747235 ps
CPU time 0.78 seconds
Started Aug 08 06:08:42 PM PDT 24
Finished Aug 08 06:08:43 PM PDT 24
Peak memory 204256 kb
Host smart-a9e52970-79dc-4076-897d-6efec0376990
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282417016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
2282417016
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.1944487891
Short name T1084
Test name
Test status
Simulation time 24648151 ps
CPU time 0.72 seconds
Started Aug 08 06:08:51 PM PDT 24
Finished Aug 08 06:08:52 PM PDT 24
Peak memory 204024 kb
Host smart-16e24569-0da8-4a91-967d-0c936c91654d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944487891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
1944487891
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.3751040414
Short name T1062
Test name
Test status
Simulation time 48968377 ps
CPU time 0.71 seconds
Started Aug 08 06:08:50 PM PDT 24
Finished Aug 08 06:08:51 PM PDT 24
Peak memory 204316 kb
Host smart-b204b6e9-834c-4085-96a4-a8a90efb95ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751040414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
3751040414
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.4179470625
Short name T1082
Test name
Test status
Simulation time 17778743 ps
CPU time 0.79 seconds
Started Aug 08 06:08:53 PM PDT 24
Finished Aug 08 06:08:54 PM PDT 24
Peak memory 204048 kb
Host smart-2f3e70f4-f0d7-415e-abe5-5278c7c3220a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179470625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
4179470625
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.633961470
Short name T1128
Test name
Test status
Simulation time 13571590 ps
CPU time 0.71 seconds
Started Aug 08 06:08:49 PM PDT 24
Finished Aug 08 06:08:50 PM PDT 24
Peak memory 204040 kb
Host smart-a3b1a899-7893-4e1f-a195-3a9685c70fa2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633961470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.633961470
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.2550762086
Short name T1140
Test name
Test status
Simulation time 31076042 ps
CPU time 0.73 seconds
Started Aug 08 06:08:49 PM PDT 24
Finished Aug 08 06:08:50 PM PDT 24
Peak memory 204404 kb
Host smart-3483157d-7dca-48ef-a7a4-0e99d747eb83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550762086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
2550762086
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.1208858355
Short name T1105
Test name
Test status
Simulation time 18828408 ps
CPU time 0.75 seconds
Started Aug 08 06:08:50 PM PDT 24
Finished Aug 08 06:08:51 PM PDT 24
Peak memory 203956 kb
Host smart-d2ba9fd0-6e60-4b1e-95a8-b2aad8b07213
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208858355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
1208858355
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.2465645622
Short name T1063
Test name
Test status
Simulation time 55248904 ps
CPU time 0.7 seconds
Started Aug 08 06:08:50 PM PDT 24
Finished Aug 08 06:08:51 PM PDT 24
Peak memory 204360 kb
Host smart-e2233224-4b3e-49cd-a2dd-4c34b7fcb8ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465645622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
2465645622
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.3623865488
Short name T154
Test name
Test status
Simulation time 62874181 ps
CPU time 1.77 seconds
Started Aug 08 06:08:35 PM PDT 24
Finished Aug 08 06:08:37 PM PDT 24
Peak memory 216688 kb
Host smart-8d1e9b12-e8a4-4717-ab13-eca280b8fc4e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623865488 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.3623865488
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.2372026745
Short name T1149
Test name
Test status
Simulation time 501259785 ps
CPU time 1.36 seconds
Started Aug 08 06:08:28 PM PDT 24
Finished Aug 08 06:08:30 PM PDT 24
Peak memory 207412 kb
Host smart-e064d315-d278-435c-9efe-30d8a70a736e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372026745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.2
372026745
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.3186490646
Short name T1136
Test name
Test status
Simulation time 19328768 ps
CPU time 0.73 seconds
Started Aug 08 06:08:29 PM PDT 24
Finished Aug 08 06:08:29 PM PDT 24
Peak memory 204040 kb
Host smart-f5bbe639-ecbe-49f3-9aeb-87c20e1e6038
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186490646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.3
186490646
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2584987186
Short name T1044
Test name
Test status
Simulation time 420900708 ps
CPU time 2.96 seconds
Started Aug 08 06:08:36 PM PDT 24
Finished Aug 08 06:08:39 PM PDT 24
Peak memory 215512 kb
Host smart-95666b69-786f-45c9-847e-84a0a93241e7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584987186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.2584987186
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.2286770581
Short name T1096
Test name
Test status
Simulation time 1938978373 ps
CPU time 5.45 seconds
Started Aug 08 06:08:24 PM PDT 24
Finished Aug 08 06:08:30 PM PDT 24
Peak memory 215788 kb
Host smart-358ada5d-0db4-46f9-8f39-aa216da903da
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286770581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.2
286770581
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1293345552
Short name T167
Test name
Test status
Simulation time 560498365 ps
CPU time 19.98 seconds
Started Aug 08 06:08:34 PM PDT 24
Finished Aug 08 06:08:54 PM PDT 24
Peak memory 215868 kb
Host smart-32049f3a-9286-42cb-a8cc-ce9c4622ec59
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293345552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.1293345552
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.884852698
Short name T114
Test name
Test status
Simulation time 514918648 ps
CPU time 3.87 seconds
Started Aug 08 06:08:34 PM PDT 24
Finished Aug 08 06:08:38 PM PDT 24
Peak memory 218276 kb
Host smart-020b2f1d-8f0d-4ba8-b832-130ef19462b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884852698 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.884852698
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.583573678
Short name T131
Test name
Test status
Simulation time 119820017 ps
CPU time 2.87 seconds
Started Aug 08 06:08:42 PM PDT 24
Finished Aug 08 06:08:45 PM PDT 24
Peak memory 215616 kb
Host smart-06c6785b-2918-4f84-a6e2-b3d2e3131604
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583573678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.583573678
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.2356372903
Short name T1143
Test name
Test status
Simulation time 59640034 ps
CPU time 0.74 seconds
Started Aug 08 06:08:34 PM PDT 24
Finished Aug 08 06:08:35 PM PDT 24
Peak memory 203960 kb
Host smart-92ae1a16-5360-4ec4-ad8c-0250afd8f117
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356372903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.2
356372903
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.2972436516
Short name T1132
Test name
Test status
Simulation time 262765626 ps
CPU time 1.91 seconds
Started Aug 08 06:08:35 PM PDT 24
Finished Aug 08 06:08:37 PM PDT 24
Peak memory 207328 kb
Host smart-7f340868-f245-420f-8f87-95f020d205db
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972436516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.2972436516
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.3644084183
Short name T1068
Test name
Test status
Simulation time 2328142737 ps
CPU time 13.22 seconds
Started Aug 08 06:08:34 PM PDT 24
Finished Aug 08 06:08:47 PM PDT 24
Peak memory 216132 kb
Host smart-48a9127e-c662-43e5-ba7c-5a9d9953298f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644084183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.3644084183
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3912296055
Short name T92
Test name
Test status
Simulation time 89985568 ps
CPU time 1.78 seconds
Started Aug 08 06:08:39 PM PDT 24
Finished Aug 08 06:08:41 PM PDT 24
Peak memory 215576 kb
Host smart-32329057-f2c9-4904-8cd9-ef9c3a2e0f35
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912296055 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.3912296055
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1083002161
Short name T1108
Test name
Test status
Simulation time 28179389 ps
CPU time 1.86 seconds
Started Aug 08 06:08:34 PM PDT 24
Finished Aug 08 06:08:36 PM PDT 24
Peak memory 207508 kb
Host smart-b0b51b61-d7e8-4401-b160-1c9dea39e495
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083002161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.1
083002161
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.2644463015
Short name T1032
Test name
Test status
Simulation time 58983603 ps
CPU time 0.71 seconds
Started Aug 08 06:08:39 PM PDT 24
Finished Aug 08 06:08:40 PM PDT 24
Peak memory 204012 kb
Host smart-c9f504d0-5e42-4ecb-bb7b-69e13a10b917
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644463015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.2
644463015
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.631085449
Short name T139
Test name
Test status
Simulation time 89493352 ps
CPU time 1.98 seconds
Started Aug 08 06:08:35 PM PDT 24
Finished Aug 08 06:08:37 PM PDT 24
Peak memory 215472 kb
Host smart-a645cbef-d112-4ff4-82d1-0d2c8d1d61d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631085449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sp
i_device_same_csr_outstanding.631085449
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.3856806710
Short name T1146
Test name
Test status
Simulation time 56099381 ps
CPU time 1.59 seconds
Started Aug 08 06:08:36 PM PDT 24
Finished Aug 08 06:08:37 PM PDT 24
Peak memory 215884 kb
Host smart-7225fa89-1210-40ce-86d4-2dbff1e3b50b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856806710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.3
856806710
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.1273352425
Short name T91
Test name
Test status
Simulation time 29023498 ps
CPU time 1.65 seconds
Started Aug 08 06:08:34 PM PDT 24
Finished Aug 08 06:08:36 PM PDT 24
Peak memory 216680 kb
Host smart-446ad038-c1e1-4fb1-824c-14d86396edea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273352425 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.1273352425
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.490032719
Short name T1080
Test name
Test status
Simulation time 124429408 ps
CPU time 3.02 seconds
Started Aug 08 06:08:35 PM PDT 24
Finished Aug 08 06:08:38 PM PDT 24
Peak memory 215520 kb
Host smart-9d5169cf-7941-4ec1-a5a5-13d3c12484d6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490032719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.490032719
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.2690048767
Short name T1042
Test name
Test status
Simulation time 11839907 ps
CPU time 0.75 seconds
Started Aug 08 06:08:33 PM PDT 24
Finished Aug 08 06:08:33 PM PDT 24
Peak memory 204052 kb
Host smart-97f551ce-0ccb-48dc-80f6-b77138c7b138
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690048767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.2
690048767
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.164368837
Short name T1059
Test name
Test status
Simulation time 130861104 ps
CPU time 2.67 seconds
Started Aug 08 06:08:35 PM PDT 24
Finished Aug 08 06:08:37 PM PDT 24
Peak memory 215528 kb
Host smart-58128c52-1e6e-490b-935b-1540cb7d0e9a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164368837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sp
i_device_same_csr_outstanding.164368837
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.4130022586
Short name T1090
Test name
Test status
Simulation time 2806691364 ps
CPU time 16.27 seconds
Started Aug 08 06:08:33 PM PDT 24
Finished Aug 08 06:08:50 PM PDT 24
Peak memory 215692 kb
Host smart-9c7e4590-ac0a-4290-9b96-48682dab8a80
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130022586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.4130022586
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.724176674
Short name T94
Test name
Test status
Simulation time 139141956 ps
CPU time 3.54 seconds
Started Aug 08 06:08:37 PM PDT 24
Finished Aug 08 06:08:40 PM PDT 24
Peak memory 218304 kb
Host smart-3154aca3-f9a3-4101-a74c-abfcd07659a2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724176674 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.724176674
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.381109812
Short name T1145
Test name
Test status
Simulation time 37014807 ps
CPU time 2.25 seconds
Started Aug 08 06:08:37 PM PDT 24
Finished Aug 08 06:08:40 PM PDT 24
Peak memory 215620 kb
Host smart-af59677d-fbe8-4189-9621-0431e07d7694
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381109812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.381109812
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.1569347153
Short name T1074
Test name
Test status
Simulation time 14448311 ps
CPU time 0.73 seconds
Started Aug 08 06:08:39 PM PDT 24
Finished Aug 08 06:08:40 PM PDT 24
Peak memory 204064 kb
Host smart-537e82df-cc37-4d38-ae19-aafd5cfcaf69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569347153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.1
569347153
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3382086492
Short name T1078
Test name
Test status
Simulation time 69882830 ps
CPU time 3.88 seconds
Started Aug 08 06:08:41 PM PDT 24
Finished Aug 08 06:08:45 PM PDT 24
Peak memory 215500 kb
Host smart-7b0c270b-c5b6-4e73-a7f9-36abf89c2dd2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382086492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.3382086492
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.2632746009
Short name T168
Test name
Test status
Simulation time 9710731982 ps
CPU time 13.49 seconds
Started Aug 08 06:08:37 PM PDT 24
Finished Aug 08 06:08:50 PM PDT 24
Peak memory 216136 kb
Host smart-bc47c15a-1c31-4957-8075-1ce51f7b3828
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632746009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.2632746009
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.3717564139
Short name T572
Test name
Test status
Simulation time 16694113 ps
CPU time 0.76 seconds
Started Aug 08 06:10:09 PM PDT 24
Finished Aug 08 06:10:10 PM PDT 24
Peak memory 205268 kb
Host smart-155c4fdf-3cf3-4207-bcbb-86b63ac5b42c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717564139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.3
717564139
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.2624120670
Short name T548
Test name
Test status
Simulation time 56558933 ps
CPU time 3.01 seconds
Started Aug 08 06:10:04 PM PDT 24
Finished Aug 08 06:10:07 PM PDT 24
Peak memory 233428 kb
Host smart-354e6224-c661-483c-b828-a6d2433c40e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624120670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.2624120670
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.679102100
Short name T356
Test name
Test status
Simulation time 22967775 ps
CPU time 0.83 seconds
Started Aug 08 06:10:05 PM PDT 24
Finished Aug 08 06:10:06 PM PDT 24
Peak memory 207352 kb
Host smart-969f00a5-c1ad-4aa7-bade-657b9416782a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679102100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.679102100
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.139673873
Short name T826
Test name
Test status
Simulation time 9378685032 ps
CPU time 31.91 seconds
Started Aug 08 06:10:09 PM PDT 24
Finished Aug 08 06:10:41 PM PDT 24
Peak memory 252096 kb
Host smart-896289fc-5349-4921-aeeb-7052e6a96542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139673873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.139673873
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.372775175
Short name T828
Test name
Test status
Simulation time 11256169299 ps
CPU time 111.14 seconds
Started Aug 08 06:10:06 PM PDT 24
Finished Aug 08 06:11:57 PM PDT 24
Peak memory 240460 kb
Host smart-23af8b97-56d8-4f73-9b52-9d76928fdc4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372775175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.372775175
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.3886928625
Short name T282
Test name
Test status
Simulation time 32066649454 ps
CPU time 187.45 seconds
Started Aug 08 06:10:06 PM PDT 24
Finished Aug 08 06:13:14 PM PDT 24
Peak memory 254056 kb
Host smart-7fe6633e-15a5-435d-b407-d7207aea6863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886928625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.3886928625
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_intercept.843024837
Short name T216
Test name
Test status
Simulation time 19561372097 ps
CPU time 14.29 seconds
Started Aug 08 06:10:05 PM PDT 24
Finished Aug 08 06:10:20 PM PDT 24
Peak memory 225236 kb
Host smart-b13f96e2-fe28-44ce-be8f-51da656ca1a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843024837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.843024837
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.3824469057
Short name T865
Test name
Test status
Simulation time 1468771402 ps
CPU time 6.84 seconds
Started Aug 08 06:10:07 PM PDT 24
Finished Aug 08 06:10:14 PM PDT 24
Peak memory 233448 kb
Host smart-cfec7975-235d-4cc9-a6a0-92042965624e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824469057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.3824469057
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.3488780480
Short name T812
Test name
Test status
Simulation time 166327735 ps
CPU time 1.06 seconds
Started Aug 08 06:10:07 PM PDT 24
Finished Aug 08 06:10:08 PM PDT 24
Peak memory 217244 kb
Host smart-84e611e7-e2e5-4806-9499-cc09c669ba4d
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488780480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.spi_device_mem_parity.3488780480
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.545923472
Short name T893
Test name
Test status
Simulation time 6590350420 ps
CPU time 11.09 seconds
Started Aug 08 06:10:04 PM PDT 24
Finished Aug 08 06:10:15 PM PDT 24
Peak memory 241188 kb
Host smart-75ca479c-ec22-494d-8218-df896f648203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545923472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap.
545923472
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.2876879055
Short name T224
Test name
Test status
Simulation time 77244252 ps
CPU time 2.95 seconds
Started Aug 08 06:10:09 PM PDT 24
Finished Aug 08 06:10:12 PM PDT 24
Peak memory 233324 kb
Host smart-e7161c93-97ce-4198-a42c-7290dd0b330c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876879055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.2876879055
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.3899047392
Short name T551
Test name
Test status
Simulation time 1799502854 ps
CPU time 10.82 seconds
Started Aug 08 06:10:04 PM PDT 24
Finished Aug 08 06:10:15 PM PDT 24
Peak memory 223104 kb
Host smart-4d2fa76c-4182-431b-826f-00bb490a52ea
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3899047392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.3899047392
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.3478259441
Short name T708
Test name
Test status
Simulation time 8069429980 ps
CPU time 24.03 seconds
Started Aug 08 06:10:09 PM PDT 24
Finished Aug 08 06:10:34 PM PDT 24
Peak memory 217248 kb
Host smart-03bc3615-b240-47d2-b59a-d9c03b802d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478259441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.3478259441
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.296636716
Short name T701
Test name
Test status
Simulation time 12605060 ps
CPU time 0.75 seconds
Started Aug 08 06:10:09 PM PDT 24
Finished Aug 08 06:10:10 PM PDT 24
Peak memory 206180 kb
Host smart-8211ba37-74d2-4d1b-827b-f96576d9cc00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296636716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.296636716
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.3543842680
Short name T404
Test name
Test status
Simulation time 58819299 ps
CPU time 1.16 seconds
Started Aug 08 06:10:10 PM PDT 24
Finished Aug 08 06:10:11 PM PDT 24
Peak memory 208580 kb
Host smart-f8e085e6-0bb0-4f4d-88d2-886589feafac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543842680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.3543842680
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.811327986
Short name T817
Test name
Test status
Simulation time 420681218 ps
CPU time 0.93 seconds
Started Aug 08 06:10:07 PM PDT 24
Finished Aug 08 06:10:08 PM PDT 24
Peak memory 207620 kb
Host smart-28eb47a8-0539-45db-83c2-28ee4a521042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811327986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.811327986
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.3200905210
Short name T510
Test name
Test status
Simulation time 3253907002 ps
CPU time 8.62 seconds
Started Aug 08 06:10:06 PM PDT 24
Finished Aug 08 06:10:14 PM PDT 24
Peak memory 241596 kb
Host smart-af1d909d-56b8-4bf6-961f-1fa56db78318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200905210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.3200905210
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.1500434485
Short name T932
Test name
Test status
Simulation time 10984215 ps
CPU time 0.7 seconds
Started Aug 08 06:10:15 PM PDT 24
Finished Aug 08 06:10:16 PM PDT 24
Peak memory 205876 kb
Host smart-549a88fc-1db0-4b5d-9a2e-b21b9761e731
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500434485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.1
500434485
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.3437399138
Short name T566
Test name
Test status
Simulation time 990124949 ps
CPU time 2.71 seconds
Started Aug 08 06:10:12 PM PDT 24
Finished Aug 08 06:10:15 PM PDT 24
Peak memory 225196 kb
Host smart-05d613f8-1d95-43b6-b537-b1b5aa9f883e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437399138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.3437399138
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.4170443592
Short name T342
Test name
Test status
Simulation time 17139683 ps
CPU time 0.79 seconds
Started Aug 08 06:10:07 PM PDT 24
Finished Aug 08 06:10:08 PM PDT 24
Peak memory 207052 kb
Host smart-dbaaff76-18f7-4a43-8ada-5ed56d0f0cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170443592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.4170443592
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.2328901038
Short name T541
Test name
Test status
Simulation time 4795578672 ps
CPU time 101.34 seconds
Started Aug 08 06:10:14 PM PDT 24
Finished Aug 08 06:11:55 PM PDT 24
Peak memory 251240 kb
Host smart-ab4b65ae-14cf-4f16-83dd-fe918c844456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328901038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.2328901038
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.1645270095
Short name T270
Test name
Test status
Simulation time 6651110788 ps
CPU time 142.18 seconds
Started Aug 08 06:10:15 PM PDT 24
Finished Aug 08 06:12:38 PM PDT 24
Peak memory 267792 kb
Host smart-5dec2bea-f055-4e47-83a9-9f1ba4e9e54a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645270095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.1645270095
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.3845032871
Short name T394
Test name
Test status
Simulation time 4537511338 ps
CPU time 43.62 seconds
Started Aug 08 06:10:11 PM PDT 24
Finished Aug 08 06:10:55 PM PDT 24
Peak memory 233568 kb
Host smart-99b5dcc9-a9d3-49eb-94ed-505e8ee0af65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845032871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.3845032871
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.3750116273
Short name T348
Test name
Test status
Simulation time 15808398484 ps
CPU time 12.16 seconds
Started Aug 08 06:10:11 PM PDT 24
Finished Aug 08 06:10:24 PM PDT 24
Peak memory 225336 kb
Host smart-8e3d29ea-a9e5-41af-928b-36efc895135a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750116273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds
.3750116273
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/1.spi_device_intercept.2000564139
Short name T707
Test name
Test status
Simulation time 310840845 ps
CPU time 2.73 seconds
Started Aug 08 06:10:11 PM PDT 24
Finished Aug 08 06:10:14 PM PDT 24
Peak memory 225276 kb
Host smart-3610af8b-d71a-4744-99e8-0b0f7d075469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000564139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.2000564139
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.3826889696
Short name T626
Test name
Test status
Simulation time 1306702982 ps
CPU time 12.51 seconds
Started Aug 08 06:10:13 PM PDT 24
Finished Aug 08 06:10:26 PM PDT 24
Peak memory 225216 kb
Host smart-6a861962-be74-43e0-8632-f32aca2be520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826889696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.3826889696
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.1120966813
Short name T584
Test name
Test status
Simulation time 128120026 ps
CPU time 1.09 seconds
Started Aug 08 06:10:09 PM PDT 24
Finished Aug 08 06:10:11 PM PDT 24
Peak memory 217236 kb
Host smart-22fe4adf-836c-4775-b134-7ddf9f83bb9f
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120966813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.spi_device_mem_parity.1120966813
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.839528931
Short name T68
Test name
Test status
Simulation time 769847077 ps
CPU time 6.73 seconds
Started Aug 08 06:10:12 PM PDT 24
Finished Aug 08 06:10:19 PM PDT 24
Peak memory 233492 kb
Host smart-0ba0f740-a2bf-4aea-ba6c-0c8504a70933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839528931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap.
839528931
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.1807478716
Short name T627
Test name
Test status
Simulation time 3996852336 ps
CPU time 15.38 seconds
Started Aug 08 06:10:10 PM PDT 24
Finished Aug 08 06:10:25 PM PDT 24
Peak memory 233472 kb
Host smart-2fa6f6bf-9199-40a3-a5a9-bb292ec7e0d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807478716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.1807478716
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.2178715411
Short name T423
Test name
Test status
Simulation time 153843250 ps
CPU time 3.63 seconds
Started Aug 08 06:10:14 PM PDT 24
Finished Aug 08 06:10:18 PM PDT 24
Peak memory 223204 kb
Host smart-dc88fdb2-6541-44be-8ba6-5f79457e8827
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2178715411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.2178715411
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.3490130007
Short name T67
Test name
Test status
Simulation time 73468514 ps
CPU time 0.95 seconds
Started Aug 08 06:10:15 PM PDT 24
Finished Aug 08 06:10:16 PM PDT 24
Peak memory 235532 kb
Host smart-3f6e9730-849c-4b6a-a21e-2c9257c3b767
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490130007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.3490130007
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.2851002358
Short name T547
Test name
Test status
Simulation time 24019226984 ps
CPU time 49.88 seconds
Started Aug 08 06:10:10 PM PDT 24
Finished Aug 08 06:11:00 PM PDT 24
Peak memory 250024 kb
Host smart-74fe7296-4f4a-4c00-b1b3-432b03a0fb5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851002358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.2851002358
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.1318361597
Short name T527
Test name
Test status
Simulation time 5548508197 ps
CPU time 28.98 seconds
Started Aug 08 06:10:13 PM PDT 24
Finished Aug 08 06:10:42 PM PDT 24
Peak memory 217032 kb
Host smart-0ee80a36-d8a3-4489-a45d-cb95d99bbaf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318361597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.1318361597
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.442686164
Short name T441
Test name
Test status
Simulation time 4172913575 ps
CPU time 16.76 seconds
Started Aug 08 06:10:06 PM PDT 24
Finished Aug 08 06:10:23 PM PDT 24
Peak memory 217036 kb
Host smart-a1506f6f-73f6-4904-a9ac-e28efeb8804e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442686164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.442686164
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.3546190321
Short name T1008
Test name
Test status
Simulation time 67388917 ps
CPU time 0.93 seconds
Started Aug 08 06:10:15 PM PDT 24
Finished Aug 08 06:10:16 PM PDT 24
Peak memory 207024 kb
Host smart-d3c14d61-9643-4ea1-b3c3-446acb039491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546190321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.3546190321
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.52934992
Short name T641
Test name
Test status
Simulation time 101947018 ps
CPU time 0.91 seconds
Started Aug 08 06:10:14 PM PDT 24
Finished Aug 08 06:10:15 PM PDT 24
Peak memory 207596 kb
Host smart-f5648a02-cc63-49bc-8203-3e6130bdb9b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52934992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.52934992
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.3035693450
Short name T683
Test name
Test status
Simulation time 2449987187 ps
CPU time 7.49 seconds
Started Aug 08 06:10:11 PM PDT 24
Finished Aug 08 06:10:19 PM PDT 24
Peak memory 238504 kb
Host smart-f37ce4ff-337d-4a9d-b8f9-ce2a342d3f14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035693450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.3035693450
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.818573737
Short name T727
Test name
Test status
Simulation time 43953357 ps
CPU time 0.71 seconds
Started Aug 08 06:10:56 PM PDT 24
Finished Aug 08 06:10:57 PM PDT 24
Peak memory 205288 kb
Host smart-ab5c8f8d-07b4-435e-9ab8-ccad55ff7624
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818573737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.818573737
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.3492688742
Short name T608
Test name
Test status
Simulation time 275733899 ps
CPU time 3.71 seconds
Started Aug 08 06:10:46 PM PDT 24
Finished Aug 08 06:10:50 PM PDT 24
Peak memory 225200 kb
Host smart-bf6a9a41-32ff-41b4-a453-e6af196999b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492688742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.3492688742
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.2255480615
Short name T786
Test name
Test status
Simulation time 243013563 ps
CPU time 0.78 seconds
Started Aug 08 06:10:40 PM PDT 24
Finished Aug 08 06:10:41 PM PDT 24
Peak memory 207020 kb
Host smart-74723687-9661-46ad-814a-8b9ed4c49005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255480615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.2255480615
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.1089323796
Short name T191
Test name
Test status
Simulation time 46858423268 ps
CPU time 352.53 seconds
Started Aug 08 06:10:45 PM PDT 24
Finished Aug 08 06:16:38 PM PDT 24
Peak memory 268640 kb
Host smart-6506f5dd-f5c0-4498-839e-5ca3039e8a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089323796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.1089323796
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.1885818253
Short name T197
Test name
Test status
Simulation time 528676080 ps
CPU time 13.49 seconds
Started Aug 08 06:10:48 PM PDT 24
Finished Aug 08 06:11:01 PM PDT 24
Peak memory 222540 kb
Host smart-ec86f158-8b4f-4cf5-805b-8b76c7ac204a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885818253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.1885818253
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.3881248926
Short name T811
Test name
Test status
Simulation time 21708093933 ps
CPU time 65.64 seconds
Started Aug 08 06:10:46 PM PDT 24
Finished Aug 08 06:11:52 PM PDT 24
Peak memory 233556 kb
Host smart-0f32ba45-d1e9-404b-b01e-5f9672f73c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881248926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.3881248926
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.2532093775
Short name T971
Test name
Test status
Simulation time 210491648 ps
CPU time 3.74 seconds
Started Aug 08 06:10:49 PM PDT 24
Finished Aug 08 06:10:52 PM PDT 24
Peak memory 233460 kb
Host smart-76d90eb3-c78b-4957-828c-56ef2b72a62c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532093775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.2532093775
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.256590615
Short name T782
Test name
Test status
Simulation time 173201695831 ps
CPU time 303.38 seconds
Started Aug 08 06:10:47 PM PDT 24
Finished Aug 08 06:15:50 PM PDT 24
Peak memory 262708 kb
Host smart-b8274bcf-fddb-46b4-bc7f-60575718f41a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256590615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmds
.256590615
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/10.spi_device_intercept.600494242
Short name T802
Test name
Test status
Simulation time 2744779737 ps
CPU time 17.55 seconds
Started Aug 08 06:10:45 PM PDT 24
Finished Aug 08 06:11:02 PM PDT 24
Peak memory 233536 kb
Host smart-1e5988c4-5b29-45ea-bb23-a049714d2022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600494242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.600494242
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.3033892937
Short name T609
Test name
Test status
Simulation time 34167185 ps
CPU time 2.29 seconds
Started Aug 08 06:10:46 PM PDT 24
Finished Aug 08 06:10:48 PM PDT 24
Peak memory 233072 kb
Host smart-b4f9ff9c-0fda-4030-811c-825f6c487e19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033892937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.3033892937
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.971189829
Short name T742
Test name
Test status
Simulation time 188671045 ps
CPU time 4.52 seconds
Started Aug 08 06:10:47 PM PDT 24
Finished Aug 08 06:10:52 PM PDT 24
Peak memory 241424 kb
Host smart-ecd15760-acc3-489f-9ce3-a0cbd4be58a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971189829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swap
.971189829
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.39892527
Short name T486
Test name
Test status
Simulation time 2727544315 ps
CPU time 3.06 seconds
Started Aug 08 06:10:46 PM PDT 24
Finished Aug 08 06:10:49 PM PDT 24
Peak memory 233488 kb
Host smart-2f20e568-b5c3-4c77-9bda-1a14872d186a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39892527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.39892527
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.3448589566
Short name T491
Test name
Test status
Simulation time 1363621498 ps
CPU time 7.01 seconds
Started Aug 08 06:10:46 PM PDT 24
Finished Aug 08 06:10:53 PM PDT 24
Peak memory 223668 kb
Host smart-d19cc0ef-85cd-489c-80e0-e635d45b2fad
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3448589566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.3448589566
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.2691798302
Short name T31
Test name
Test status
Simulation time 22416545723 ps
CPU time 237.73 seconds
Started Aug 08 06:10:57 PM PDT 24
Finished Aug 08 06:14:55 PM PDT 24
Peak memory 273540 kb
Host smart-813095f4-8970-466e-9eb8-110baa6d133c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691798302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.2691798302
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.4001286842
Short name T956
Test name
Test status
Simulation time 1846006600 ps
CPU time 4.26 seconds
Started Aug 08 06:10:46 PM PDT 24
Finished Aug 08 06:10:50 PM PDT 24
Peak memory 216960 kb
Host smart-57c4986b-2d76-40cc-ab94-93ab8e2733e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001286842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.4001286842
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.1176150983
Short name T333
Test name
Test status
Simulation time 2107626802 ps
CPU time 8.52 seconds
Started Aug 08 06:10:40 PM PDT 24
Finished Aug 08 06:10:48 PM PDT 24
Peak memory 216952 kb
Host smart-e5309f65-ae01-476f-bb71-77f369363eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176150983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.1176150983
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.967716351
Short name T979
Test name
Test status
Simulation time 70967670 ps
CPU time 1.29 seconds
Started Aug 08 06:10:56 PM PDT 24
Finished Aug 08 06:10:57 PM PDT 24
Peak memory 216984 kb
Host smart-978d2c29-3ff0-4022-8cae-d0bb77415459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967716351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.967716351
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.338588919
Short name T795
Test name
Test status
Simulation time 21677649 ps
CPU time 0.72 seconds
Started Aug 08 06:10:46 PM PDT 24
Finished Aug 08 06:10:47 PM PDT 24
Peak memory 206528 kb
Host smart-8831b7fc-958c-4435-8e2c-9cf90f2623cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338588919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.338588919
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.4066682581
Short name T558
Test name
Test status
Simulation time 3176751799 ps
CPU time 9.16 seconds
Started Aug 08 06:10:46 PM PDT 24
Finished Aug 08 06:10:55 PM PDT 24
Peak memory 238412 kb
Host smart-54ceaca9-6a5c-477e-9621-102cf0b820e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066682581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.4066682581
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.961361894
Short name T460
Test name
Test status
Simulation time 14995323 ps
CPU time 0.71 seconds
Started Aug 08 06:10:47 PM PDT 24
Finished Aug 08 06:10:48 PM PDT 24
Peak memory 205320 kb
Host smart-ce45fdf7-3d17-460c-b7aa-f75114ed7478
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961361894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.961361894
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.3236777597
Short name T80
Test name
Test status
Simulation time 856882686 ps
CPU time 3.53 seconds
Started Aug 08 06:10:45 PM PDT 24
Finished Aug 08 06:10:48 PM PDT 24
Peak memory 225212 kb
Host smart-02bd8be0-a496-48c4-a5b1-a6753b401b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236777597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.3236777597
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.1923226078
Short name T822
Test name
Test status
Simulation time 37402440 ps
CPU time 0.79 seconds
Started Aug 08 06:10:46 PM PDT 24
Finished Aug 08 06:10:46 PM PDT 24
Peak memory 207104 kb
Host smart-36e0136e-940b-416f-8f28-d8f44e599278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923226078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.1923226078
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.893419102
Short name T603
Test name
Test status
Simulation time 105075578735 ps
CPU time 189.91 seconds
Started Aug 08 06:10:48 PM PDT 24
Finished Aug 08 06:13:58 PM PDT 24
Peak memory 258120 kb
Host smart-f7308c3c-a971-4d0d-8c95-214981b6dfd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893419102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.893419102
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.4037195268
Short name T407
Test name
Test status
Simulation time 78640608547 ps
CPU time 212.26 seconds
Started Aug 08 06:10:45 PM PDT 24
Finished Aug 08 06:14:17 PM PDT 24
Peak memory 258148 kb
Host smart-06175cae-8f62-4715-911d-7c73df779839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037195268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.4037195268
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.651581962
Short name T640
Test name
Test status
Simulation time 27585924434 ps
CPU time 224.16 seconds
Started Aug 08 06:10:50 PM PDT 24
Finished Aug 08 06:14:34 PM PDT 24
Peak memory 249992 kb
Host smart-f4551626-b491-440d-a011-9bd5a312b425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651581962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idle
.651581962
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.1622140624
Short name T119
Test name
Test status
Simulation time 235945851 ps
CPU time 3.1 seconds
Started Aug 08 06:10:44 PM PDT 24
Finished Aug 08 06:10:47 PM PDT 24
Peak memory 233404 kb
Host smart-1df18dc0-5ccb-4e36-8dea-222ac5dfa119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622140624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.1622140624
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.2073869363
Short name T706
Test name
Test status
Simulation time 4698838646 ps
CPU time 65.4 seconds
Started Aug 08 06:10:47 PM PDT 24
Finished Aug 08 06:11:52 PM PDT 24
Peak memory 254244 kb
Host smart-65e26861-1411-47a5-82ea-4efd044ea176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073869363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmd
s.2073869363
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_intercept.1761567440
Short name T206
Test name
Test status
Simulation time 974135377 ps
CPU time 4.37 seconds
Started Aug 08 06:10:56 PM PDT 24
Finished Aug 08 06:11:01 PM PDT 24
Peak memory 225272 kb
Host smart-436b5768-020f-4c34-97ce-2fe8f8f4d83b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761567440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.1761567440
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.1943717704
Short name T969
Test name
Test status
Simulation time 2133531449 ps
CPU time 8.37 seconds
Started Aug 08 06:10:47 PM PDT 24
Finished Aug 08 06:10:55 PM PDT 24
Peak memory 225184 kb
Host smart-26e489a7-37c3-4df2-bbdb-9a9e6e42c6b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943717704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.1943717704
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.633132809
Short name T493
Test name
Test status
Simulation time 43262949 ps
CPU time 0.95 seconds
Started Aug 08 06:10:55 PM PDT 24
Finished Aug 08 06:10:56 PM PDT 24
Peak memory 218440 kb
Host smart-9f87604e-1d6e-4ee6-bf14-2ed9e5d1f23b
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633132809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.spi_device_mem_parity.633132809
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.1573114287
Short name T870
Test name
Test status
Simulation time 5858636665 ps
CPU time 9.01 seconds
Started Aug 08 06:10:45 PM PDT 24
Finished Aug 08 06:10:54 PM PDT 24
Peak memory 241228 kb
Host smart-b39d1650-6eba-4ea9-9c5a-33c29e207d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573114287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.1573114287
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.781003829
Short name T502
Test name
Test status
Simulation time 497873003 ps
CPU time 8.28 seconds
Started Aug 08 06:10:49 PM PDT 24
Finished Aug 08 06:10:57 PM PDT 24
Peak memory 233488 kb
Host smart-c3ab41bd-3cc8-4d36-8c33-d8e9d61c69af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781003829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.781003829
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.1408150179
Short name T349
Test name
Test status
Simulation time 538121470 ps
CPU time 8.48 seconds
Started Aug 08 06:10:48 PM PDT 24
Finished Aug 08 06:10:56 PM PDT 24
Peak memory 223204 kb
Host smart-078d9f79-988a-4a88-8591-900ebf917abb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1408150179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.1408150179
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.320439842
Short name T1003
Test name
Test status
Simulation time 43983912421 ps
CPU time 52.43 seconds
Started Aug 08 06:10:49 PM PDT 24
Finished Aug 08 06:11:41 PM PDT 24
Peak memory 217124 kb
Host smart-45bb2b41-2642-4b50-aaac-25296162ebba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320439842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.320439842
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.136976351
Short name T785
Test name
Test status
Simulation time 11840387777 ps
CPU time 4.27 seconds
Started Aug 08 06:10:45 PM PDT 24
Finished Aug 08 06:10:50 PM PDT 24
Peak memory 217084 kb
Host smart-ca7f300d-1780-401a-af6e-b0189f3d861a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136976351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.136976351
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.1843081617
Short name T366
Test name
Test status
Simulation time 1478943352 ps
CPU time 1.51 seconds
Started Aug 08 06:10:48 PM PDT 24
Finished Aug 08 06:10:50 PM PDT 24
Peak memory 216988 kb
Host smart-0a20271b-ae12-483f-9744-2f7fd5a1a46d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843081617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.1843081617
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.2417995047
Short name T376
Test name
Test status
Simulation time 138849140 ps
CPU time 0.95 seconds
Started Aug 08 06:10:48 PM PDT 24
Finished Aug 08 06:10:49 PM PDT 24
Peak memory 206596 kb
Host smart-0110ece2-a183-4fdf-84d7-931cbb9d0dbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417995047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.2417995047
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.1690664508
Short name T340
Test name
Test status
Simulation time 912967218 ps
CPU time 6.81 seconds
Started Aug 08 06:10:49 PM PDT 24
Finished Aug 08 06:10:55 PM PDT 24
Peak memory 241620 kb
Host smart-62ae7254-a7aa-4799-860d-e4f7b36e9855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690664508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.1690664508
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.2909506130
Short name T429
Test name
Test status
Simulation time 39006735 ps
CPU time 0.71 seconds
Started Aug 08 06:10:54 PM PDT 24
Finished Aug 08 06:10:55 PM PDT 24
Peak memory 205284 kb
Host smart-fe9f14e6-3f7f-4792-b7ea-99142b0fbbe1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909506130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
2909506130
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.2336924866
Short name T488
Test name
Test status
Simulation time 1658290938 ps
CPU time 15.59 seconds
Started Aug 08 06:10:54 PM PDT 24
Finished Aug 08 06:11:10 PM PDT 24
Peak memory 233404 kb
Host smart-11650ebb-c9b6-4b80-8eb7-1ebfbd884872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336924866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.2336924866
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.2796842763
Short name T628
Test name
Test status
Simulation time 78237376 ps
CPU time 0.76 seconds
Started Aug 08 06:10:46 PM PDT 24
Finished Aug 08 06:10:47 PM PDT 24
Peak memory 206044 kb
Host smart-ce5eacc2-a44f-4c60-ade1-408615660596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796842763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.2796842763
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.1151244232
Short name T137
Test name
Test status
Simulation time 102814423 ps
CPU time 0.78 seconds
Started Aug 08 06:10:55 PM PDT 24
Finished Aug 08 06:10:56 PM PDT 24
Peak memory 216472 kb
Host smart-9b3ed1c6-8d54-4ed3-bb75-f2f30ec1f173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151244232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.1151244232
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.2309085505
Short name T567
Test name
Test status
Simulation time 7080641750 ps
CPU time 90.02 seconds
Started Aug 08 06:10:57 PM PDT 24
Finished Aug 08 06:12:27 PM PDT 24
Peak memory 255896 kb
Host smart-c32cd5a5-56a7-443a-95c8-94e5b338ba88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309085505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.2309085505
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.1147923768
Short name T793
Test name
Test status
Simulation time 64524990309 ps
CPU time 271.09 seconds
Started Aug 08 06:10:55 PM PDT 24
Finished Aug 08 06:15:26 PM PDT 24
Peak memory 258072 kb
Host smart-e4168326-506a-4002-89df-05118a1b7617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147923768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.1147923768
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.800891098
Short name T712
Test name
Test status
Simulation time 1823549163 ps
CPU time 8.18 seconds
Started Aug 08 06:10:53 PM PDT 24
Finished Aug 08 06:11:01 PM PDT 24
Peak memory 241640 kb
Host smart-d0327f49-f7f0-4cbb-9fa6-2eedd9baa404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800891098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.800891098
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.1955517924
Short name T855
Test name
Test status
Simulation time 14154383396 ps
CPU time 77.54 seconds
Started Aug 08 06:10:55 PM PDT 24
Finished Aug 08 06:12:13 PM PDT 24
Peak memory 258136 kb
Host smart-9b94a3fc-fd65-40a3-95d3-d5d277977127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955517924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmd
s.1955517924
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_intercept.2098230972
Short name T483
Test name
Test status
Simulation time 1012651076 ps
CPU time 5.13 seconds
Started Aug 08 06:10:47 PM PDT 24
Finished Aug 08 06:10:52 PM PDT 24
Peak memory 230112 kb
Host smart-b08392f3-7013-4f07-b086-007e5d3f748f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098230972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.2098230972
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.4087001507
Short name T642
Test name
Test status
Simulation time 22606500510 ps
CPU time 74.25 seconds
Started Aug 08 06:10:57 PM PDT 24
Finished Aug 08 06:12:11 PM PDT 24
Peak memory 241516 kb
Host smart-a5ae4aff-5dcd-40e8-87fc-de322c037149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087001507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.4087001507
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.3842281158
Short name T466
Test name
Test status
Simulation time 124503663 ps
CPU time 1.08 seconds
Started Aug 08 06:10:47 PM PDT 24
Finished Aug 08 06:10:48 PM PDT 24
Peak memory 217212 kb
Host smart-587054d1-83c7-497a-8d06-528863d4514a
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842281158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.spi_device_mem_parity.3842281158
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.1533797211
Short name T252
Test name
Test status
Simulation time 248055715 ps
CPU time 5.28 seconds
Started Aug 08 06:11:01 PM PDT 24
Finished Aug 08 06:11:06 PM PDT 24
Peak memory 233456 kb
Host smart-8ff0f934-ea0d-4d9a-8d74-35a731e4102b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533797211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.1533797211
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.568161969
Short name T190
Test name
Test status
Simulation time 120731193918 ps
CPU time 23.02 seconds
Started Aug 08 06:10:47 PM PDT 24
Finished Aug 08 06:11:10 PM PDT 24
Peak memory 225320 kb
Host smart-6ee002e8-af54-4787-9df6-997b0956e616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568161969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.568161969
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.3885772897
Short name T143
Test name
Test status
Simulation time 437094107 ps
CPU time 3.99 seconds
Started Aug 08 06:10:57 PM PDT 24
Finished Aug 08 06:11:01 PM PDT 24
Peak memory 223492 kb
Host smart-f4827556-7622-4d36-bfac-10136cecc69c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3885772897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.3885772897
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.4186728142
Short name T911
Test name
Test status
Simulation time 98660576 ps
CPU time 1.13 seconds
Started Aug 08 06:10:56 PM PDT 24
Finished Aug 08 06:10:57 PM PDT 24
Peak memory 208260 kb
Host smart-ffdf5dfc-06ab-4b11-ba72-aeda9ee7b24d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186728142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.4186728142
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.276006903
Short name T620
Test name
Test status
Simulation time 7875310914 ps
CPU time 40.85 seconds
Started Aug 08 06:10:47 PM PDT 24
Finished Aug 08 06:11:28 PM PDT 24
Peak memory 220876 kb
Host smart-555c1bf1-ebc1-4bc1-91f9-9d02e91cc8e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276006903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.276006903
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.3842676651
Short name T580
Test name
Test status
Simulation time 10067741753 ps
CPU time 13.45 seconds
Started Aug 08 06:10:45 PM PDT 24
Finished Aug 08 06:10:59 PM PDT 24
Peak memory 217108 kb
Host smart-48b8b77d-7bb6-4386-81cb-6fb42dd5ac7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842676651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.3842676651
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.1827238698
Short name T46
Test name
Test status
Simulation time 339518503 ps
CPU time 1.5 seconds
Started Aug 08 06:10:56 PM PDT 24
Finished Aug 08 06:10:58 PM PDT 24
Peak memory 216976 kb
Host smart-a8fff0d6-8ab4-435b-8919-df3bb1c30141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827238698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.1827238698
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.3647080658
Short name T747
Test name
Test status
Simulation time 112948460 ps
CPU time 0.89 seconds
Started Aug 08 06:10:45 PM PDT 24
Finished Aug 08 06:10:46 PM PDT 24
Peak memory 207572 kb
Host smart-989c029a-a1df-4daf-b355-577e6f72ac23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647080658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.3647080658
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.3972987275
Short name T964
Test name
Test status
Simulation time 267409697 ps
CPU time 2.3 seconds
Started Aug 08 06:10:57 PM PDT 24
Finished Aug 08 06:10:59 PM PDT 24
Peak memory 224784 kb
Host smart-57478705-0963-45ba-9e81-2a3192af379e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972987275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.3972987275
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.471026875
Short name T513
Test name
Test status
Simulation time 33688905 ps
CPU time 0.71 seconds
Started Aug 08 06:10:56 PM PDT 24
Finished Aug 08 06:10:57 PM PDT 24
Peak memory 206120 kb
Host smart-367b8092-b868-4839-a007-5d831ec76647
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471026875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.471026875
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.3448854063
Short name T179
Test name
Test status
Simulation time 1454258494 ps
CPU time 10.6 seconds
Started Aug 08 06:10:54 PM PDT 24
Finished Aug 08 06:11:05 PM PDT 24
Peak memory 233492 kb
Host smart-a81ac1a8-c107-49b7-9d5e-9596172b41b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448854063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.3448854063
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.2458308863
Short name T682
Test name
Test status
Simulation time 114367195 ps
CPU time 0.8 seconds
Started Aug 08 06:11:01 PM PDT 24
Finished Aug 08 06:11:02 PM PDT 24
Peak memory 205972 kb
Host smart-a295e4cf-e859-45ed-8c50-cb8eacd7955e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458308863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.2458308863
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.112282126
Short name T177
Test name
Test status
Simulation time 84974757952 ps
CPU time 153.5 seconds
Started Aug 08 06:10:57 PM PDT 24
Finished Aug 08 06:13:30 PM PDT 24
Peak memory 249900 kb
Host smart-6951e95c-739c-464f-8550-bb0c8bbffdd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112282126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.112282126
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.564929848
Short name T427
Test name
Test status
Simulation time 5750581727 ps
CPU time 15.6 seconds
Started Aug 08 06:10:55 PM PDT 24
Finished Aug 08 06:11:11 PM PDT 24
Peak memory 225328 kb
Host smart-341a427f-4d59-4c7e-98f1-0fcfd2fe4001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564929848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.564929848
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.496090409
Short name T880
Test name
Test status
Simulation time 13223488907 ps
CPU time 139.98 seconds
Started Aug 08 06:10:55 PM PDT 24
Finished Aug 08 06:13:15 PM PDT 24
Peak memory 240972 kb
Host smart-87baf260-a6af-4b0d-890d-f51ccfe5ef9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496090409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idle
.496090409
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.3272229582
Short name T39
Test name
Test status
Simulation time 10582930098 ps
CPU time 49.41 seconds
Started Aug 08 06:10:54 PM PDT 24
Finished Aug 08 06:11:44 PM PDT 24
Peak memory 249944 kb
Host smart-72311d98-4914-4f3b-a3cc-aec4bd033320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272229582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.3272229582
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.812142208
Short name T279
Test name
Test status
Simulation time 113378316125 ps
CPU time 208.91 seconds
Started Aug 08 06:10:57 PM PDT 24
Finished Aug 08 06:14:26 PM PDT 24
Peak memory 265308 kb
Host smart-493b57c4-5e9b-4e4d-b930-c2f39e2d3f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812142208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmds
.812142208
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/13.spi_device_intercept.2398719525
Short name T997
Test name
Test status
Simulation time 452017471 ps
CPU time 3.06 seconds
Started Aug 08 06:10:57 PM PDT 24
Finished Aug 08 06:11:00 PM PDT 24
Peak memory 225192 kb
Host smart-b9b9b332-1b1b-48b4-819d-d87355bb62f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398719525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.2398719525
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.3497247485
Short name T452
Test name
Test status
Simulation time 91162113560 ps
CPU time 30.93 seconds
Started Aug 08 06:10:55 PM PDT 24
Finished Aug 08 06:11:26 PM PDT 24
Peak memory 225200 kb
Host smart-5c4733bf-9f71-4c56-b1c5-3ccbfb9e6f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497247485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.3497247485
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.665273715
Short name T32
Test name
Test status
Simulation time 32878496 ps
CPU time 1.11 seconds
Started Aug 08 06:10:59 PM PDT 24
Finished Aug 08 06:11:00 PM PDT 24
Peak memory 217172 kb
Host smart-d9f3911b-12c9-47c1-b9a1-a2102622a18b
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665273715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.spi_device_mem_parity.665273715
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.2502408853
Short name T15
Test name
Test status
Simulation time 5522482401 ps
CPU time 17.35 seconds
Started Aug 08 06:10:59 PM PDT 24
Finished Aug 08 06:11:17 PM PDT 24
Peak memory 233448 kb
Host smart-e858f582-9509-4bba-b8c1-44da011672e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502408853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.2502408853
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.3499307290
Short name T989
Test name
Test status
Simulation time 3392472586 ps
CPU time 7.23 seconds
Started Aug 08 06:10:58 PM PDT 24
Finished Aug 08 06:11:05 PM PDT 24
Peak memory 233544 kb
Host smart-0917fa15-4959-42d9-acc5-c46de246e47c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499307290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.3499307290
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.1045914938
Short name T917
Test name
Test status
Simulation time 130812479 ps
CPU time 3.32 seconds
Started Aug 08 06:10:55 PM PDT 24
Finished Aug 08 06:10:58 PM PDT 24
Peak memory 223704 kb
Host smart-27574518-6fd1-4a15-afdc-b17ad66c7bb3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1045914938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.1045914938
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.1211552274
Short name T158
Test name
Test status
Simulation time 230082873538 ps
CPU time 489.16 seconds
Started Aug 08 06:11:15 PM PDT 24
Finished Aug 08 06:19:24 PM PDT 24
Peak memory 274528 kb
Host smart-40448488-a1a0-4e0f-b94e-8e73f38ce3df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211552274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.1211552274
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.3672339009
Short name T314
Test name
Test status
Simulation time 19757412913 ps
CPU time 27.1 seconds
Started Aug 08 06:11:15 PM PDT 24
Finished Aug 08 06:11:42 PM PDT 24
Peak memory 217000 kb
Host smart-703119e8-8ebd-4548-9028-5c8babf02b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672339009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.3672339009
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.2505321656
Short name T379
Test name
Test status
Simulation time 10265893178 ps
CPU time 10.9 seconds
Started Aug 08 06:10:55 PM PDT 24
Finished Aug 08 06:11:06 PM PDT 24
Peak memory 216936 kb
Host smart-77d17de6-e261-41f3-8506-78611c824dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505321656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.2505321656
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.37235297
Short name T816
Test name
Test status
Simulation time 545487527 ps
CPU time 6.94 seconds
Started Aug 08 06:10:55 PM PDT 24
Finished Aug 08 06:11:02 PM PDT 24
Peak memory 217000 kb
Host smart-dc38e7b4-79ec-4d08-8dba-19f97a40f5f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37235297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.37235297
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.1983504290
Short name T437
Test name
Test status
Simulation time 198625021 ps
CPU time 0.83 seconds
Started Aug 08 06:10:58 PM PDT 24
Finished Aug 08 06:10:59 PM PDT 24
Peak memory 206524 kb
Host smart-be13cc56-2a19-4223-bd88-faf4c5074303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983504290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.1983504290
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.2680797055
Short name T1011
Test name
Test status
Simulation time 385229709 ps
CPU time 3.11 seconds
Started Aug 08 06:10:54 PM PDT 24
Finished Aug 08 06:10:57 PM PDT 24
Peak memory 233472 kb
Host smart-77d7128e-b4c5-41b3-a0a7-909694b6eef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680797055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.2680797055
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.1377651095
Short name T696
Test name
Test status
Simulation time 38999068 ps
CPU time 0.69 seconds
Started Aug 08 06:10:58 PM PDT 24
Finished Aug 08 06:10:59 PM PDT 24
Peak memory 205820 kb
Host smart-ecd44582-b5c0-43bc-9dd9-c70e08c656df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377651095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
1377651095
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.720772193
Short name T537
Test name
Test status
Simulation time 1186648790 ps
CPU time 8.04 seconds
Started Aug 08 06:11:06 PM PDT 24
Finished Aug 08 06:11:14 PM PDT 24
Peak memory 225240 kb
Host smart-4bc03d1e-84c4-4cea-b3ab-80b23b732420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720772193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.720772193
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.1490794606
Short name T325
Test name
Test status
Simulation time 31875729 ps
CPU time 0.77 seconds
Started Aug 08 06:10:56 PM PDT 24
Finished Aug 08 06:10:57 PM PDT 24
Peak memory 207012 kb
Host smart-7a450191-8876-4352-9eb1-51f7b40425a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490794606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.1490794606
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.3794604157
Short name T43
Test name
Test status
Simulation time 26010846497 ps
CPU time 106.33 seconds
Started Aug 08 06:10:55 PM PDT 24
Finished Aug 08 06:12:42 PM PDT 24
Peak memory 249156 kb
Host smart-a53a8517-ebf2-4065-9a2e-2b6093bf0dd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794604157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.3794604157
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.3024907045
Short name T700
Test name
Test status
Simulation time 9702383407 ps
CPU time 89.17 seconds
Started Aug 08 06:11:09 PM PDT 24
Finished Aug 08 06:12:38 PM PDT 24
Peak memory 250028 kb
Host smart-ddc403a9-87d1-4572-abce-e77256b561cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024907045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.3024907045
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.3741918264
Short name T1022
Test name
Test status
Simulation time 21108631419 ps
CPU time 127.63 seconds
Started Aug 08 06:11:06 PM PDT 24
Finished Aug 08 06:13:14 PM PDT 24
Peak memory 270728 kb
Host smart-a72174bd-cbf3-4797-b068-9b6ba73f84bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741918264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.3741918264
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.1941498062
Short name T623
Test name
Test status
Simulation time 588052384 ps
CPU time 5.23 seconds
Started Aug 08 06:10:56 PM PDT 24
Finished Aug 08 06:11:02 PM PDT 24
Peak memory 233436 kb
Host smart-611115cd-4df5-4c50-b8ab-be79ec786a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941498062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.1941498062
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.3609160710
Short name T201
Test name
Test status
Simulation time 6702413522 ps
CPU time 50.72 seconds
Started Aug 08 06:10:58 PM PDT 24
Finished Aug 08 06:11:49 PM PDT 24
Peak memory 241696 kb
Host smart-5401fba7-5a60-489b-85c7-6b4d354a07d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609160710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmd
s.3609160710
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/14.spi_device_intercept.4103210938
Short name T268
Test name
Test status
Simulation time 801340027 ps
CPU time 4.22 seconds
Started Aug 08 06:10:52 PM PDT 24
Finished Aug 08 06:10:57 PM PDT 24
Peak memory 233644 kb
Host smart-5b3888d7-ccdb-44eb-8fdc-db8de5f6a81d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103210938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.4103210938
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.2838994362
Short name T968
Test name
Test status
Simulation time 237521014 ps
CPU time 4.95 seconds
Started Aug 08 06:11:02 PM PDT 24
Finished Aug 08 06:11:07 PM PDT 24
Peak memory 233476 kb
Host smart-644257c7-e56d-4b07-9eab-911339b73af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838994362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.2838994362
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.4254857381
Short name T868
Test name
Test status
Simulation time 163675907 ps
CPU time 1.04 seconds
Started Aug 08 06:10:55 PM PDT 24
Finished Aug 08 06:10:56 PM PDT 24
Peak memory 218432 kb
Host smart-2dd5cf0d-a186-4a0f-b2ed-88a0dfe9007a
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254857381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.spi_device_mem_parity.4254857381
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.179683349
Short name T265
Test name
Test status
Simulation time 1272014657 ps
CPU time 8.53 seconds
Started Aug 08 06:11:08 PM PDT 24
Finished Aug 08 06:11:16 PM PDT 24
Peak memory 225164 kb
Host smart-5d353099-b84c-4395-82bd-d7854e2a1fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179683349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swap
.179683349
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.939308653
Short name T583
Test name
Test status
Simulation time 4540654036 ps
CPU time 18.85 seconds
Started Aug 08 06:10:56 PM PDT 24
Finished Aug 08 06:11:15 PM PDT 24
Peak memory 241700 kb
Host smart-e490c9e3-e939-4520-b756-29f9b3ef0a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939308653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.939308653
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.4260111026
Short name T413
Test name
Test status
Simulation time 1316506572 ps
CPU time 9.32 seconds
Started Aug 08 06:10:55 PM PDT 24
Finished Aug 08 06:11:04 PM PDT 24
Peak memory 224328 kb
Host smart-8beb73a1-7018-4b95-bd74-9a69b38ac310
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4260111026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.4260111026
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.3984506076
Short name T22
Test name
Test status
Simulation time 20310163416 ps
CPU time 241.16 seconds
Started Aug 08 06:10:58 PM PDT 24
Finished Aug 08 06:14:59 PM PDT 24
Peak memory 274380 kb
Host smart-8d18fd65-c26e-48de-9b02-68ccf9a8400b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984506076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.3984506076
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.1763108078
Short name T981
Test name
Test status
Simulation time 8078418941 ps
CPU time 21.39 seconds
Started Aug 08 06:11:01 PM PDT 24
Finished Aug 08 06:11:23 PM PDT 24
Peak memory 217336 kb
Host smart-5f9c8c2d-5ca1-4246-a919-4814866f9283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763108078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.1763108078
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.1103497983
Short name T363
Test name
Test status
Simulation time 601788044 ps
CPU time 1.84 seconds
Started Aug 08 06:10:57 PM PDT 24
Finished Aug 08 06:10:59 PM PDT 24
Peak memory 216712 kb
Host smart-ba3f4f95-1c82-4f3a-8a1b-6fb7b87ab9c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103497983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.1103497983
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.585888641
Short name T771
Test name
Test status
Simulation time 14931613 ps
CPU time 0.73 seconds
Started Aug 08 06:10:54 PM PDT 24
Finished Aug 08 06:10:55 PM PDT 24
Peak memory 206588 kb
Host smart-fe0a2365-8787-4bcb-b23c-47c851a36e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585888641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.585888641
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.2064941535
Short name T875
Test name
Test status
Simulation time 72885564 ps
CPU time 0.8 seconds
Started Aug 08 06:10:55 PM PDT 24
Finished Aug 08 06:10:56 PM PDT 24
Peak memory 206584 kb
Host smart-5f774271-53c7-4010-a90f-7d340e3033dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064941535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.2064941535
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.435921185
Short name T229
Test name
Test status
Simulation time 1226820906 ps
CPU time 6.05 seconds
Started Aug 08 06:10:56 PM PDT 24
Finished Aug 08 06:11:03 PM PDT 24
Peak memory 225284 kb
Host smart-5184e97c-fdfa-42c3-8007-862e25d5c4c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435921185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.435921185
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.3630658297
Short name T374
Test name
Test status
Simulation time 10901216 ps
CPU time 0.71 seconds
Started Aug 08 06:11:06 PM PDT 24
Finished Aug 08 06:11:07 PM PDT 24
Peak memory 205900 kb
Host smart-df565017-dfaf-4551-8c37-29735d5f7b28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630658297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
3630658297
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.403697384
Short name T511
Test name
Test status
Simulation time 3427572595 ps
CPU time 9.59 seconds
Started Aug 08 06:10:59 PM PDT 24
Finished Aug 08 06:11:09 PM PDT 24
Peak memory 233528 kb
Host smart-57e2aceb-296a-49c3-9764-806b4e1db67d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403697384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.403697384
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.1963396280
Short name T524
Test name
Test status
Simulation time 46345028 ps
CPU time 0.73 seconds
Started Aug 08 06:11:02 PM PDT 24
Finished Aug 08 06:11:03 PM PDT 24
Peak memory 206016 kb
Host smart-1d1e3657-f49e-442d-856e-7d603d47bf4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963396280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.1963396280
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.983713914
Short name T675
Test name
Test status
Simulation time 39495256611 ps
CPU time 73.43 seconds
Started Aug 08 06:11:17 PM PDT 24
Finished Aug 08 06:12:31 PM PDT 24
Peak memory 253908 kb
Host smart-c1e40f69-80fa-4390-9824-da3c072a45b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983713914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.983713914
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.1332348934
Short name T458
Test name
Test status
Simulation time 24810060203 ps
CPU time 155.4 seconds
Started Aug 08 06:11:13 PM PDT 24
Finished Aug 08 06:13:49 PM PDT 24
Peak memory 251012 kb
Host smart-306867ca-6820-4331-8d5e-526495380a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332348934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.1332348934
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.4029029340
Short name T717
Test name
Test status
Simulation time 1402996394 ps
CPU time 23.25 seconds
Started Aug 08 06:11:12 PM PDT 24
Finished Aug 08 06:11:36 PM PDT 24
Peak memory 225232 kb
Host smart-796ecdd9-992b-4344-a30a-9a5a669d210c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029029340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.4029029340
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.2449322291
Short name T765
Test name
Test status
Simulation time 5311423425 ps
CPU time 33.61 seconds
Started Aug 08 06:11:03 PM PDT 24
Finished Aug 08 06:11:37 PM PDT 24
Peak memory 237976 kb
Host smart-5e3a6450-dc30-47ec-a97a-141430c45775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449322291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmd
s.2449322291
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/15.spi_device_intercept.429385400
Short name T226
Test name
Test status
Simulation time 1607991580 ps
CPU time 12.39 seconds
Started Aug 08 06:10:55 PM PDT 24
Finished Aug 08 06:11:08 PM PDT 24
Peak memory 232288 kb
Host smart-0ebfb53c-fa8f-4ad0-8f2d-11ed267fe847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429385400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.429385400
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.3162467255
Short name T475
Test name
Test status
Simulation time 13424316929 ps
CPU time 29.35 seconds
Started Aug 08 06:11:12 PM PDT 24
Finished Aug 08 06:11:42 PM PDT 24
Peak memory 225316 kb
Host smart-0f6b59c7-79ad-4b23-b23a-0df0fb37bac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162467255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.3162467255
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.775766350
Short name T830
Test name
Test status
Simulation time 62280334 ps
CPU time 1.02 seconds
Started Aug 08 06:10:56 PM PDT 24
Finished Aug 08 06:10:57 PM PDT 24
Peak memory 217244 kb
Host smart-99e08500-d68e-4068-b7c4-92b226344fea
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775766350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.spi_device_mem_parity.775766350
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.65334734
Short name T736
Test name
Test status
Simulation time 71449509 ps
CPU time 2.96 seconds
Started Aug 08 06:11:15 PM PDT 24
Finished Aug 08 06:11:18 PM PDT 24
Peak memory 233388 kb
Host smart-96a8088e-50d3-478f-aaa3-30dd73d1450d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65334734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swap.65334734
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.1861140075
Short name T237
Test name
Test status
Simulation time 314418558 ps
CPU time 2.1 seconds
Started Aug 08 06:10:56 PM PDT 24
Finished Aug 08 06:10:58 PM PDT 24
Peak memory 225248 kb
Host smart-d5558153-dba3-4244-8976-5686048ff12a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861140075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.1861140075
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.1728894906
Short name T467
Test name
Test status
Simulation time 149027839 ps
CPU time 4.01 seconds
Started Aug 08 06:11:12 PM PDT 24
Finished Aug 08 06:11:17 PM PDT 24
Peak memory 220912 kb
Host smart-9177020f-e61e-415b-8f36-d482107830de
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1728894906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.1728894906
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.2311723375
Short name T315
Test name
Test status
Simulation time 8772389548 ps
CPU time 38.53 seconds
Started Aug 08 06:11:04 PM PDT 24
Finished Aug 08 06:11:42 PM PDT 24
Peak memory 225356 kb
Host smart-69f81486-a0f1-49e2-8645-d3e49c469925
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311723375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.2311723375
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.1797343870
Short name T803
Test name
Test status
Simulation time 25151789066 ps
CPU time 25.72 seconds
Started Aug 08 06:10:56 PM PDT 24
Finished Aug 08 06:11:22 PM PDT 24
Peak memory 217024 kb
Host smart-60ad9f88-6b7f-442e-bf77-fa2ad3772179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797343870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.1797343870
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.1522986209
Short name T403
Test name
Test status
Simulation time 1812548492 ps
CPU time 8.1 seconds
Started Aug 08 06:11:15 PM PDT 24
Finished Aug 08 06:11:23 PM PDT 24
Peak memory 216900 kb
Host smart-92d368b7-85d2-4268-8b50-d8ccc9ac449a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522986209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.1522986209
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.1663889326
Short name T367
Test name
Test status
Simulation time 44652604 ps
CPU time 1.03 seconds
Started Aug 08 06:10:57 PM PDT 24
Finished Aug 08 06:10:58 PM PDT 24
Peak memory 208572 kb
Host smart-1365617a-59aa-435b-92b1-fa25a0b7cbdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663889326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.1663889326
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.3400881955
Short name T763
Test name
Test status
Simulation time 206379297 ps
CPU time 0.98 seconds
Started Aug 08 06:10:58 PM PDT 24
Finished Aug 08 06:10:59 PM PDT 24
Peak memory 206532 kb
Host smart-4ce58aea-fc07-4b9f-a684-47492bf39de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400881955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.3400881955
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.1746810064
Short name T220
Test name
Test status
Simulation time 11668713932 ps
CPU time 13.52 seconds
Started Aug 08 06:11:12 PM PDT 24
Finished Aug 08 06:11:26 PM PDT 24
Peak memory 241456 kb
Host smart-13f4a82b-c05f-4a71-aed8-aeab261cecfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746810064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.1746810064
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.2849320133
Short name T463
Test name
Test status
Simulation time 69100420 ps
CPU time 0.7 seconds
Started Aug 08 06:11:04 PM PDT 24
Finished Aug 08 06:11:04 PM PDT 24
Peak memory 205848 kb
Host smart-c3385d14-2f2f-44cd-90e8-5062e7aa4999
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849320133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
2849320133
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.441732534
Short name T84
Test name
Test status
Simulation time 1568726186 ps
CPU time 11.71 seconds
Started Aug 08 06:11:10 PM PDT 24
Finished Aug 08 06:11:22 PM PDT 24
Peak memory 225172 kb
Host smart-fbf14f88-5e93-4ea5-8a8b-dacea0afd69f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441732534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.441732534
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.1410058034
Short name T784
Test name
Test status
Simulation time 127047390 ps
CPU time 0.74 seconds
Started Aug 08 06:11:11 PM PDT 24
Finished Aug 08 06:11:12 PM PDT 24
Peak memory 206368 kb
Host smart-05efaf7a-b60b-47af-af0f-083853b8c21c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410058034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.1410058034
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.438881749
Short name T287
Test name
Test status
Simulation time 86182072597 ps
CPU time 108.2 seconds
Started Aug 08 06:11:06 PM PDT 24
Finished Aug 08 06:12:54 PM PDT 24
Peak memory 236184 kb
Host smart-22a4b3fb-8f84-4a9d-8f6f-570b13c15e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438881749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.438881749
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.3747712583
Short name T215
Test name
Test status
Simulation time 207990046403 ps
CPU time 214.43 seconds
Started Aug 08 06:11:12 PM PDT 24
Finished Aug 08 06:14:46 PM PDT 24
Peak memory 258124 kb
Host smart-d94dc6a1-5b67-4843-8367-2700bf6a8d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747712583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.3747712583
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.297488312
Short name T221
Test name
Test status
Simulation time 16778227578 ps
CPU time 91.42 seconds
Started Aug 08 06:11:04 PM PDT 24
Finished Aug 08 06:12:36 PM PDT 24
Peak memory 240676 kb
Host smart-e46860a2-8745-4aff-bffe-6158b1d70f11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297488312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idle
.297488312
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.416651430
Short name T294
Test name
Test status
Simulation time 2238215582 ps
CPU time 33.01 seconds
Started Aug 08 06:11:10 PM PDT 24
Finished Aug 08 06:11:43 PM PDT 24
Peak memory 236436 kb
Host smart-49bf778f-5fe1-4661-860b-24f3e7a92754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416651430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.416651430
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.1934861528
Short name T290
Test name
Test status
Simulation time 25569877182 ps
CPU time 216.4 seconds
Started Aug 08 06:11:15 PM PDT 24
Finished Aug 08 06:14:52 PM PDT 24
Peak memory 255188 kb
Host smart-39dc0f41-fe58-4f97-b468-eae7b6800798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934861528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmd
s.1934861528
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/16.spi_device_intercept.2491989892
Short name T136
Test name
Test status
Simulation time 2300787313 ps
CPU time 7.22 seconds
Started Aug 08 06:11:07 PM PDT 24
Finished Aug 08 06:11:14 PM PDT 24
Peak memory 233548 kb
Host smart-552a285f-423b-4089-a0a8-b2a74accdd88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491989892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.2491989892
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.1171945548
Short name T563
Test name
Test status
Simulation time 26444306902 ps
CPU time 63.32 seconds
Started Aug 08 06:11:07 PM PDT 24
Finished Aug 08 06:12:10 PM PDT 24
Peak memory 233552 kb
Host smart-4ab3ce44-3b55-47f8-a366-83ba662a3741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171945548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.1171945548
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.738361068
Short name T678
Test name
Test status
Simulation time 16450744 ps
CPU time 1.03 seconds
Started Aug 08 06:11:12 PM PDT 24
Finished Aug 08 06:11:14 PM PDT 24
Peak memory 217160 kb
Host smart-b05a42f9-3865-4528-95ec-d8767e2beaea
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738361068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.spi_device_mem_parity.738361068
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.1708924163
Short name T722
Test name
Test status
Simulation time 32514189 ps
CPU time 2.59 seconds
Started Aug 08 06:11:04 PM PDT 24
Finished Aug 08 06:11:07 PM PDT 24
Peak memory 233424 kb
Host smart-0c4c65b4-97a7-4f05-9b0e-85cd483c03bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708924163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.1708924163
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.1031064072
Short name T574
Test name
Test status
Simulation time 5476178173 ps
CPU time 11.8 seconds
Started Aug 08 06:11:10 PM PDT 24
Finished Aug 08 06:11:21 PM PDT 24
Peak memory 241596 kb
Host smart-6f6e83e2-022f-41c9-a00f-b74c43cd6ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031064072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.1031064072
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.2676153079
Short name T615
Test name
Test status
Simulation time 585276724 ps
CPU time 8.24 seconds
Started Aug 08 06:11:04 PM PDT 24
Finished Aug 08 06:11:12 PM PDT 24
Peak memory 222296 kb
Host smart-53ceb0a8-af87-4caa-8433-2a791858f541
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2676153079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.2676153079
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.810869861
Short name T710
Test name
Test status
Simulation time 177019609 ps
CPU time 1 seconds
Started Aug 08 06:11:14 PM PDT 24
Finished Aug 08 06:11:15 PM PDT 24
Peak memory 208020 kb
Host smart-90f88e0b-118e-4bb9-a9e3-a973f9910fae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810869861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stres
s_all.810869861
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.339833314
Short name T24
Test name
Test status
Simulation time 24925845616 ps
CPU time 32.02 seconds
Started Aug 08 06:11:10 PM PDT 24
Finished Aug 08 06:11:43 PM PDT 24
Peak memory 217088 kb
Host smart-91aaf1bb-1d4c-485a-a285-287a352bdba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339833314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.339833314
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.81929173
Short name T351
Test name
Test status
Simulation time 13193559152 ps
CPU time 22.14 seconds
Started Aug 08 06:11:06 PM PDT 24
Finished Aug 08 06:11:29 PM PDT 24
Peak memory 217064 kb
Host smart-eb6e09f5-3224-47aa-a3d1-e4d8a8e6ed9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81929173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.81929173
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.1127421067
Short name T805
Test name
Test status
Simulation time 55868477 ps
CPU time 1.16 seconds
Started Aug 08 06:11:13 PM PDT 24
Finished Aug 08 06:11:14 PM PDT 24
Peak memory 207816 kb
Host smart-a733df78-f19c-439d-8b2e-828f7009a318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127421067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.1127421067
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.1626850021
Short name T534
Test name
Test status
Simulation time 324123058 ps
CPU time 0.99 seconds
Started Aug 08 06:11:01 PM PDT 24
Finished Aug 08 06:11:02 PM PDT 24
Peak memory 207788 kb
Host smart-190c7e49-0839-483a-b666-34772c45adbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626850021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.1626850021
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.2780346003
Short name T998
Test name
Test status
Simulation time 25594305904 ps
CPU time 13.42 seconds
Started Aug 08 06:11:03 PM PDT 24
Finished Aug 08 06:11:16 PM PDT 24
Peak memory 233552 kb
Host smart-aa24b6e1-c288-4346-871b-5cc5e00f7093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780346003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.2780346003
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.4184316903
Short name T838
Test name
Test status
Simulation time 85282075 ps
CPU time 0.73 seconds
Started Aug 08 06:11:12 PM PDT 24
Finished Aug 08 06:11:13 PM PDT 24
Peak memory 205912 kb
Host smart-89afd1c9-4ef5-4bd7-abc4-0bc15fee4af4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184316903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
4184316903
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.606289586
Short name T433
Test name
Test status
Simulation time 191637343 ps
CPU time 3.43 seconds
Started Aug 08 06:11:03 PM PDT 24
Finished Aug 08 06:11:07 PM PDT 24
Peak memory 233448 kb
Host smart-d2a5f02f-30f5-4cf5-9d0b-887aee88c545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606289586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.606289586
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.496752791
Short name T422
Test name
Test status
Simulation time 20182280 ps
CPU time 0.82 seconds
Started Aug 08 06:11:11 PM PDT 24
Finished Aug 08 06:11:12 PM PDT 24
Peak memory 207088 kb
Host smart-11b6d9d5-3aa7-4cec-83de-e0c2f9126379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496752791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.496752791
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.1211950147
Short name T993
Test name
Test status
Simulation time 20039794698 ps
CPU time 87.72 seconds
Started Aug 08 06:11:04 PM PDT 24
Finished Aug 08 06:12:32 PM PDT 24
Peak memory 255472 kb
Host smart-6a23dd10-373e-4efa-b3f5-49d8ea91e5f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211950147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.1211950147
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.4139260084
Short name T756
Test name
Test status
Simulation time 9142675939 ps
CPU time 76.95 seconds
Started Aug 08 06:11:07 PM PDT 24
Finished Aug 08 06:12:24 PM PDT 24
Peak memory 265336 kb
Host smart-00c0736c-bab5-472a-b0c5-1f04e78d7e20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139260084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.4139260084
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.3220050502
Short name T631
Test name
Test status
Simulation time 25202260131 ps
CPU time 64.8 seconds
Started Aug 08 06:11:05 PM PDT 24
Finished Aug 08 06:12:10 PM PDT 24
Peak memory 253244 kb
Host smart-9a45c3ef-f8c4-498b-9e18-2f10e65ed4c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220050502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.3220050502
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.1471362257
Short name T699
Test name
Test status
Simulation time 1718702667 ps
CPU time 30.3 seconds
Started Aug 08 06:11:06 PM PDT 24
Finished Aug 08 06:11:36 PM PDT 24
Peak memory 251744 kb
Host smart-294d72a8-e0ab-4b6c-aaf5-99e9aca8b668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471362257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmd
s.1471362257
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/17.spi_device_intercept.3791273215
Short name T402
Test name
Test status
Simulation time 105619641 ps
CPU time 2.61 seconds
Started Aug 08 06:11:06 PM PDT 24
Finished Aug 08 06:11:09 PM PDT 24
Peak memory 233420 kb
Host smart-02e3285c-59be-4431-b174-64dcededc054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791273215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.3791273215
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.3676794416
Short name T779
Test name
Test status
Simulation time 1156847198 ps
CPU time 6.5 seconds
Started Aug 08 06:11:10 PM PDT 24
Finished Aug 08 06:11:16 PM PDT 24
Peak memory 225288 kb
Host smart-f3defa11-bf2e-43d8-8bf2-ea5d6f87bae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676794416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.3676794416
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.329320281
Short name T616
Test name
Test status
Simulation time 171573082 ps
CPU time 1.13 seconds
Started Aug 08 06:11:15 PM PDT 24
Finished Aug 08 06:11:16 PM PDT 24
Peak memory 217204 kb
Host smart-21679297-1892-4820-adae-3a42bf0bfd0c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329320281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.spi_device_mem_parity.329320281
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.2397223118
Short name T445
Test name
Test status
Simulation time 30131000177 ps
CPU time 20.92 seconds
Started Aug 08 06:11:15 PM PDT 24
Finished Aug 08 06:11:36 PM PDT 24
Peak memory 233484 kb
Host smart-4cb01857-f59c-45b5-82ee-edaf5b845b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397223118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.2397223118
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.3573038361
Short name T532
Test name
Test status
Simulation time 4765873050 ps
CPU time 11.77 seconds
Started Aug 08 06:11:11 PM PDT 24
Finished Aug 08 06:11:23 PM PDT 24
Peak memory 225204 kb
Host smart-f4290617-48aa-4b69-bca5-147cf1e1dba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573038361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.3573038361
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.2956476030
Short name T504
Test name
Test status
Simulation time 881143140 ps
CPU time 9.63 seconds
Started Aug 08 06:11:08 PM PDT 24
Finished Aug 08 06:11:18 PM PDT 24
Peak memory 222800 kb
Host smart-8c901253-7441-4b0a-8587-2843c6b86979
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2956476030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.2956476030
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.1524746717
Short name T288
Test name
Test status
Simulation time 5867395445 ps
CPU time 134.95 seconds
Started Aug 08 06:11:06 PM PDT 24
Finished Aug 08 06:13:21 PM PDT 24
Peak memory 256748 kb
Host smart-0f26ad4d-ed24-4297-b745-87df3b018298
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524746717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.1524746717
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.3426072403
Short name T861
Test name
Test status
Simulation time 8270274879 ps
CPU time 44.01 seconds
Started Aug 08 06:11:10 PM PDT 24
Finished Aug 08 06:11:54 PM PDT 24
Peak memory 217180 kb
Host smart-41cdf3fd-0fd7-41e3-8c13-7e523b4ea845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426072403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.3426072403
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.4025115981
Short name T412
Test name
Test status
Simulation time 2521837065 ps
CPU time 5.84 seconds
Started Aug 08 06:11:11 PM PDT 24
Finished Aug 08 06:11:17 PM PDT 24
Peak memory 217084 kb
Host smart-dcfc5a31-d1d8-4c23-980d-02ff24ad2503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025115981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.4025115981
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.3115197022
Short name T368
Test name
Test status
Simulation time 200717965 ps
CPU time 10 seconds
Started Aug 08 06:11:07 PM PDT 24
Finished Aug 08 06:11:17 PM PDT 24
Peak memory 216980 kb
Host smart-ae2f3e3e-e43a-4325-9204-3d67064e6e4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115197022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.3115197022
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.348024094
Short name T810
Test name
Test status
Simulation time 137860449 ps
CPU time 0.92 seconds
Started Aug 08 06:11:08 PM PDT 24
Finished Aug 08 06:11:09 PM PDT 24
Peak memory 206932 kb
Host smart-4c2fa873-f1cb-409c-b0e6-61cf75a634ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348024094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.348024094
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.2387762439
Short name T47
Test name
Test status
Simulation time 500284489 ps
CPU time 5.28 seconds
Started Aug 08 06:11:07 PM PDT 24
Finished Aug 08 06:11:13 PM PDT 24
Peak memory 241528 kb
Host smart-0ef8c787-57f6-452c-a3c6-a58e2e976a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387762439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.2387762439
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.1508768753
Short name T401
Test name
Test status
Simulation time 35301593 ps
CPU time 0.69 seconds
Started Aug 08 06:11:10 PM PDT 24
Finished Aug 08 06:11:11 PM PDT 24
Peak memory 205872 kb
Host smart-67f83dea-31a7-4575-b05f-e33858896244
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508768753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
1508768753
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.4118459193
Short name T916
Test name
Test status
Simulation time 1328288826 ps
CPU time 11.68 seconds
Started Aug 08 06:11:12 PM PDT 24
Finished Aug 08 06:11:24 PM PDT 24
Peak memory 233384 kb
Host smart-5e96e183-d826-49e2-a004-4dcf1b00a8b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118459193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.4118459193
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.3829872781
Short name T594
Test name
Test status
Simulation time 27251402 ps
CPU time 0.78 seconds
Started Aug 08 06:11:08 PM PDT 24
Finished Aug 08 06:11:09 PM PDT 24
Peak memory 207024 kb
Host smart-6199c8c8-bf30-42a6-91db-a53c7911ff2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829872781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.3829872781
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.90833035
Short name T182
Test name
Test status
Simulation time 7826923867 ps
CPU time 92.65 seconds
Started Aug 08 06:11:13 PM PDT 24
Finished Aug 08 06:12:46 PM PDT 24
Peak memory 257484 kb
Host smart-93c07fe6-8c0e-4ad3-8786-e2d58abcd172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90833035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.90833035
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.833908758
Short name T992
Test name
Test status
Simulation time 38850974214 ps
CPU time 170.1 seconds
Started Aug 08 06:11:07 PM PDT 24
Finished Aug 08 06:13:58 PM PDT 24
Peak memory 249908 kb
Host smart-75eb5a08-fa38-4e78-aff5-100a542d1cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833908758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.833908758
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.3341392036
Short name T260
Test name
Test status
Simulation time 83404304582 ps
CPU time 75.35 seconds
Started Aug 08 06:11:12 PM PDT 24
Finished Aug 08 06:12:27 PM PDT 24
Peak memory 241232 kb
Host smart-0b19f97d-d417-4cb9-810d-19624e23cc4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341392036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.3341392036
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.1579876116
Short name T297
Test name
Test status
Simulation time 3876047214 ps
CPU time 10.02 seconds
Started Aug 08 06:11:14 PM PDT 24
Finished Aug 08 06:11:24 PM PDT 24
Peak memory 235504 kb
Host smart-86445658-9b70-4d7e-bf59-07d999a79a96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579876116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.1579876116
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.4128899312
Short name T82
Test name
Test status
Simulation time 28039795435 ps
CPU time 200.46 seconds
Started Aug 08 06:11:11 PM PDT 24
Finished Aug 08 06:14:31 PM PDT 24
Peak memory 233464 kb
Host smart-461bd967-0620-4c94-8f5f-980a4674d85b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128899312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmd
s.4128899312
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/18.spi_device_intercept.1897545561
Short name T848
Test name
Test status
Simulation time 57771914 ps
CPU time 2.58 seconds
Started Aug 08 06:11:05 PM PDT 24
Finished Aug 08 06:11:08 PM PDT 24
Peak memory 225260 kb
Host smart-ab33e6e4-44b3-45fc-a3ae-117488fbdade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897545561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.1897545561
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.4085314289
Short name T570
Test name
Test status
Simulation time 7738429211 ps
CPU time 62.84 seconds
Started Aug 08 06:11:05 PM PDT 24
Finished Aug 08 06:12:08 PM PDT 24
Peak memory 238284 kb
Host smart-a8a6a3bc-40e2-472b-b8ff-9c29f2b04c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085314289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.4085314289
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.3753700678
Short name T851
Test name
Test status
Simulation time 16669486 ps
CPU time 1.02 seconds
Started Aug 08 06:11:07 PM PDT 24
Finished Aug 08 06:11:08 PM PDT 24
Peak memory 217120 kb
Host smart-2cf17b61-5530-4677-843a-7dd8004a93e4
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753700678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.spi_device_mem_parity.3753700678
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.2724815904
Short name T392
Test name
Test status
Simulation time 15318796992 ps
CPU time 13.06 seconds
Started Aug 08 06:11:06 PM PDT 24
Finished Aug 08 06:11:20 PM PDT 24
Peak memory 233524 kb
Host smart-54b8ab3e-d0d3-43cb-8ea4-88e3329888c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724815904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.2724815904
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.2906723545
Short name T664
Test name
Test status
Simulation time 830188571 ps
CPU time 4.63 seconds
Started Aug 08 06:11:06 PM PDT 24
Finished Aug 08 06:11:11 PM PDT 24
Peak memory 225204 kb
Host smart-525f2fba-8450-4102-aff6-186e4f08f53a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906723545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.2906723545
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.1475532028
Short name T973
Test name
Test status
Simulation time 1537306819 ps
CPU time 12.21 seconds
Started Aug 08 06:11:07 PM PDT 24
Finished Aug 08 06:11:19 PM PDT 24
Peak memory 223372 kb
Host smart-1ace68a2-6746-4a1c-9fbb-1222fab3e8d3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1475532028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.1475532028
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.1768679658
Short name T257
Test name
Test status
Simulation time 12404624129 ps
CPU time 67.13 seconds
Started Aug 08 06:11:07 PM PDT 24
Finished Aug 08 06:12:14 PM PDT 24
Peak memory 249912 kb
Host smart-d2dce9dc-7f23-4e5a-ac64-c6e25dc29ecc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768679658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.1768679658
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.3471122657
Short name T818
Test name
Test status
Simulation time 8332365066 ps
CPU time 38.75 seconds
Started Aug 08 06:11:09 PM PDT 24
Finished Aug 08 06:11:48 PM PDT 24
Peak memory 215848 kb
Host smart-a8f406b4-a1bf-4e5f-9221-07a2203ad275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471122657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.3471122657
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.1983738529
Short name T813
Test name
Test status
Simulation time 6647651773 ps
CPU time 9.17 seconds
Started Aug 08 06:11:15 PM PDT 24
Finished Aug 08 06:11:25 PM PDT 24
Peak memory 217000 kb
Host smart-3cfb84a6-e011-45c8-a6e3-89709d2e9f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983738529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.1983738529
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.426977342
Short name T975
Test name
Test status
Simulation time 513687553 ps
CPU time 5.22 seconds
Started Aug 08 06:11:07 PM PDT 24
Finished Aug 08 06:11:13 PM PDT 24
Peak memory 216972 kb
Host smart-c4a86993-c3a2-4a56-8f6e-42fde876ef43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426977342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.426977342
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.1376686165
Short name T605
Test name
Test status
Simulation time 117381046 ps
CPU time 1.06 seconds
Started Aug 08 06:11:07 PM PDT 24
Finished Aug 08 06:11:08 PM PDT 24
Peak memory 207600 kb
Host smart-65979d69-6602-4120-8e0a-e7964940baa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376686165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.1376686165
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.1882880291
Short name T734
Test name
Test status
Simulation time 20218455012 ps
CPU time 37.48 seconds
Started Aug 08 06:11:13 PM PDT 24
Finished Aug 08 06:11:50 PM PDT 24
Peak memory 241744 kb
Host smart-e4441e8c-1e8c-4a2b-903c-36c86482be49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882880291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.1882880291
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.3050576936
Short name T556
Test name
Test status
Simulation time 1616279134 ps
CPU time 17.88 seconds
Started Aug 08 06:11:13 PM PDT 24
Finished Aug 08 06:11:31 PM PDT 24
Peak memory 225228 kb
Host smart-2575f6c5-72ca-4e22-a2b1-dcb993b1b322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050576936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.3050576936
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.689852795
Short name T744
Test name
Test status
Simulation time 23732015 ps
CPU time 0.8 seconds
Started Aug 08 06:11:10 PM PDT 24
Finished Aug 08 06:11:10 PM PDT 24
Peak memory 207092 kb
Host smart-65e3d893-2b2e-4bc3-8f44-936c4de70bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689852795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.689852795
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.269187515
Short name T946
Test name
Test status
Simulation time 10683602791 ps
CPU time 91.5 seconds
Started Aug 08 06:11:13 PM PDT 24
Finished Aug 08 06:12:45 PM PDT 24
Peak memory 253020 kb
Host smart-e83bc80b-130a-4aee-86e9-7016dee0354f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269187515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.269187515
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.380443801
Short name T967
Test name
Test status
Simulation time 104230904546 ps
CPU time 155.19 seconds
Started Aug 08 06:11:11 PM PDT 24
Finished Aug 08 06:13:47 PM PDT 24
Peak memory 249916 kb
Host smart-232b7101-0ea9-4f51-a7bf-4a3be90c0be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380443801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idle
.380443801
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.3862963077
Short name T644
Test name
Test status
Simulation time 457999074 ps
CPU time 3.97 seconds
Started Aug 08 06:11:17 PM PDT 24
Finished Aug 08 06:11:21 PM PDT 24
Peak memory 225236 kb
Host smart-f4f96702-8a1c-4284-a5e3-a634a326b5a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862963077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.3862963077
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.3975446537
Short name T595
Test name
Test status
Simulation time 23677029209 ps
CPU time 163.67 seconds
Started Aug 08 06:11:13 PM PDT 24
Finished Aug 08 06:13:56 PM PDT 24
Peak memory 251756 kb
Host smart-c1f74dd8-fe21-4d2a-b551-832d2e1e7206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975446537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmd
s.3975446537
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/19.spi_device_intercept.1269135564
Short name T846
Test name
Test status
Simulation time 2363421379 ps
CPU time 13.71 seconds
Started Aug 08 06:11:15 PM PDT 24
Finished Aug 08 06:11:29 PM PDT 24
Peak memory 233460 kb
Host smart-a8a85fd4-c7ef-421f-a4e4-e821e136e59f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269135564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.1269135564
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.2905961561
Short name T960
Test name
Test status
Simulation time 402300255 ps
CPU time 7.49 seconds
Started Aug 08 06:11:12 PM PDT 24
Finished Aug 08 06:11:20 PM PDT 24
Peak memory 233456 kb
Host smart-36ad7747-fff6-4a2e-8c48-97b8b46ad484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905961561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.2905961561
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.782787784
Short name T738
Test name
Test status
Simulation time 83455682 ps
CPU time 1.06 seconds
Started Aug 08 06:11:10 PM PDT 24
Finished Aug 08 06:11:11 PM PDT 24
Peak memory 217232 kb
Host smart-b701e9d8-c91c-41a7-8629-09535477c4c1
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782787784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.spi_device_mem_parity.782787784
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.237764838
Short name T251
Test name
Test status
Simulation time 4930304348 ps
CPU time 4.32 seconds
Started Aug 08 06:11:14 PM PDT 24
Finished Aug 08 06:11:18 PM PDT 24
Peak memory 233468 kb
Host smart-41bd23e6-86a5-448f-a9c7-6404cdfb4872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237764838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swap
.237764838
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.3378053790
Short name T187
Test name
Test status
Simulation time 12438801136 ps
CPU time 17.52 seconds
Started Aug 08 06:11:13 PM PDT 24
Finished Aug 08 06:11:31 PM PDT 24
Peak memory 233408 kb
Host smart-c5f81a24-d440-4142-bdcb-1725c834b99c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378053790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.3378053790
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.2892350906
Short name T70
Test name
Test status
Simulation time 94870308 ps
CPU time 3.45 seconds
Started Aug 08 06:11:12 PM PDT 24
Finished Aug 08 06:11:15 PM PDT 24
Peak memory 223232 kb
Host smart-0511175e-572a-4e4c-bf32-fe0d39f1097d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2892350906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.2892350906
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.286275873
Short name T18
Test name
Test status
Simulation time 21256195546 ps
CPU time 221.17 seconds
Started Aug 08 06:11:18 PM PDT 24
Finished Aug 08 06:15:00 PM PDT 24
Peak memory 256868 kb
Host smart-e1eed0ca-59fb-4870-9c3f-d9a93542b179
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286275873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stres
s_all.286275873
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.2637288259
Short name T306
Test name
Test status
Simulation time 2615632440 ps
CPU time 25.99 seconds
Started Aug 08 06:11:13 PM PDT 24
Finished Aug 08 06:11:39 PM PDT 24
Peak memory 220760 kb
Host smart-c798e2ef-3b38-4d71-b030-68303afe576c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637288259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.2637288259
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.4204276163
Short name T977
Test name
Test status
Simulation time 1089338606 ps
CPU time 7.51 seconds
Started Aug 08 06:11:10 PM PDT 24
Finished Aug 08 06:11:17 PM PDT 24
Peak memory 216976 kb
Host smart-341df587-898b-4423-b94b-6e63db399158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204276163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.4204276163
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.2916255298
Short name T405
Test name
Test status
Simulation time 39247252 ps
CPU time 0.82 seconds
Started Aug 08 06:11:12 PM PDT 24
Finished Aug 08 06:11:13 PM PDT 24
Peak memory 206608 kb
Host smart-cc009c52-f723-4d9e-b4cb-2c5110a3375c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916255298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.2916255298
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.2403521436
Short name T25
Test name
Test status
Simulation time 55191417 ps
CPU time 0.75 seconds
Started Aug 08 06:11:13 PM PDT 24
Finished Aug 08 06:11:14 PM PDT 24
Peak memory 206480 kb
Host smart-17c21bd0-5298-4d04-bb22-5aff7bd23fe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403521436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.2403521436
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.1794705233
Short name T37
Test name
Test status
Simulation time 1409674530 ps
CPU time 7.27 seconds
Started Aug 08 06:11:14 PM PDT 24
Finished Aug 08 06:11:22 PM PDT 24
Peak memory 233452 kb
Host smart-d96ef7b7-eeff-46cf-bee2-b6a6ce45b229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794705233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.1794705233
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.2111499057
Short name T894
Test name
Test status
Simulation time 15484143 ps
CPU time 0.76 seconds
Started Aug 08 06:10:22 PM PDT 24
Finished Aug 08 06:10:23 PM PDT 24
Peak memory 205264 kb
Host smart-c62c1cdf-3289-4823-87c8-9ae16f4236ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111499057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.2
111499057
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.532147647
Short name T388
Test name
Test status
Simulation time 114129663 ps
CPU time 2.34 seconds
Started Aug 08 06:10:13 PM PDT 24
Finished Aug 08 06:10:15 PM PDT 24
Peak memory 225188 kb
Host smart-027528e6-ab11-44ec-b693-38a9a7df7c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532147647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.532147647
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.767805569
Short name T815
Test name
Test status
Simulation time 20605258 ps
CPU time 0.79 seconds
Started Aug 08 06:10:15 PM PDT 24
Finished Aug 08 06:10:16 PM PDT 24
Peak memory 207056 kb
Host smart-5a8932ab-f7b2-4ea4-bbd5-d4972851ecf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767805569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.767805569
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.656764693
Short name T227
Test name
Test status
Simulation time 220564407273 ps
CPU time 160.94 seconds
Started Aug 08 06:10:11 PM PDT 24
Finished Aug 08 06:12:52 PM PDT 24
Peak memory 249884 kb
Host smart-fc99c32c-250d-4f3d-b217-a995c14e7041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656764693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.656764693
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.2697009971
Short name T464
Test name
Test status
Simulation time 19612071567 ps
CPU time 110.97 seconds
Started Aug 08 06:10:15 PM PDT 24
Finished Aug 08 06:12:06 PM PDT 24
Peak memory 253024 kb
Host smart-c3704f26-3147-4ff5-8de8-daa6e1f410c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697009971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.2697009971
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.4206993805
Short name T1025
Test name
Test status
Simulation time 254657754325 ps
CPU time 562.93 seconds
Started Aug 08 06:10:14 PM PDT 24
Finished Aug 08 06:19:37 PM PDT 24
Peak memory 258128 kb
Host smart-49f94041-1fca-4329-a6f0-be7945202d22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206993805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.4206993805
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.3939469207
Short name T1004
Test name
Test status
Simulation time 117860014 ps
CPU time 4.61 seconds
Started Aug 08 06:10:11 PM PDT 24
Finished Aug 08 06:10:16 PM PDT 24
Peak memory 233456 kb
Host smart-948d5529-924d-42ae-bff1-6b786a965010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939469207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.3939469207
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.2438738807
Short name T238
Test name
Test status
Simulation time 789322044 ps
CPU time 10.86 seconds
Started Aug 08 06:10:13 PM PDT 24
Finished Aug 08 06:10:24 PM PDT 24
Peak memory 235444 kb
Host smart-6323f759-1f20-4e8c-a537-4649d73963c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438738807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds
.2438738807
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_intercept.1324661252
Short name T497
Test name
Test status
Simulation time 128882640 ps
CPU time 3.84 seconds
Started Aug 08 06:10:13 PM PDT 24
Finished Aug 08 06:10:17 PM PDT 24
Peak memory 225268 kb
Host smart-b28e7b3a-d6d9-43ad-9a90-8e5c21c9c0d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324661252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.1324661252
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.2865603325
Short name T34
Test name
Test status
Simulation time 160014297 ps
CPU time 1.03 seconds
Started Aug 08 06:10:12 PM PDT 24
Finished Aug 08 06:10:13 PM PDT 24
Peak memory 217276 kb
Host smart-730ccc51-5148-44c0-be41-9b8bbd1297d5
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865603325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.spi_device_mem_parity.2865603325
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.1997920176
Short name T928
Test name
Test status
Simulation time 5313416767 ps
CPU time 8.01 seconds
Started Aug 08 06:10:11 PM PDT 24
Finished Aug 08 06:10:20 PM PDT 24
Peak memory 225296 kb
Host smart-69f15a66-4e49-48e5-8c47-826dd659f4c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997920176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.1997920176
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.478523298
Short name T382
Test name
Test status
Simulation time 128144596 ps
CPU time 2.55 seconds
Started Aug 08 06:10:12 PM PDT 24
Finished Aug 08 06:10:15 PM PDT 24
Peak memory 233028 kb
Host smart-664c803c-377a-4ada-bc81-4f517d1ab4d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478523298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.478523298
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.808753065
Short name T961
Test name
Test status
Simulation time 1791520073 ps
CPU time 20.46 seconds
Started Aug 08 06:10:14 PM PDT 24
Finished Aug 08 06:10:35 PM PDT 24
Peak memory 223096 kb
Host smart-1a93cee8-f2ce-474a-94b7-a1ca7b383b6a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=808753065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_direc
t.808753065
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.3321191428
Short name T23
Test name
Test status
Simulation time 77510044 ps
CPU time 1.09 seconds
Started Aug 08 06:10:15 PM PDT 24
Finished Aug 08 06:10:16 PM PDT 24
Peak memory 235572 kb
Host smart-155c9f5a-def6-4783-b8cc-bbbd571bbf62
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321191428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.3321191428
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.2967525054
Short name T162
Test name
Test status
Simulation time 3638163418 ps
CPU time 19.48 seconds
Started Aug 08 06:10:15 PM PDT 24
Finished Aug 08 06:10:35 PM PDT 24
Peak memory 223752 kb
Host smart-a907ceb2-4c98-4723-ac9c-efec18177ee8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967525054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.2967525054
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.231558368
Short name T305
Test name
Test status
Simulation time 1464575511 ps
CPU time 24.16 seconds
Started Aug 08 06:10:10 PM PDT 24
Finished Aug 08 06:10:34 PM PDT 24
Peak memory 216964 kb
Host smart-fce3a626-8d04-4f7f-818c-ee7256226356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231558368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.231558368
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.2316376662
Short name T726
Test name
Test status
Simulation time 2815716383 ps
CPU time 3.61 seconds
Started Aug 08 06:10:15 PM PDT 24
Finished Aug 08 06:10:19 PM PDT 24
Peak memory 217040 kb
Host smart-3297cb94-fe60-4cfb-b445-a868b2d0ca73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316376662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.2316376662
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.1162104354
Short name T74
Test name
Test status
Simulation time 97516576 ps
CPU time 0.88 seconds
Started Aug 08 06:10:14 PM PDT 24
Finished Aug 08 06:10:15 PM PDT 24
Peak memory 207864 kb
Host smart-93e122c3-9c63-4656-ae3f-9e87a9e5e97d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162104354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.1162104354
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.392689811
Short name T530
Test name
Test status
Simulation time 81604840 ps
CPU time 0.95 seconds
Started Aug 08 06:10:14 PM PDT 24
Finished Aug 08 06:10:15 PM PDT 24
Peak memory 207024 kb
Host smart-8b3ea610-c23b-4053-aabe-392c7c0e220f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392689811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.392689811
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.753486147
Short name T100
Test name
Test status
Simulation time 247494380 ps
CPU time 4.02 seconds
Started Aug 08 06:10:15 PM PDT 24
Finished Aug 08 06:10:19 PM PDT 24
Peak memory 233496 kb
Host smart-70439394-1dc5-4ba7-9626-480fceee29e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753486147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.753486147
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.3463913518
Short name T761
Test name
Test status
Simulation time 24216333 ps
CPU time 0.71 seconds
Started Aug 08 06:11:20 PM PDT 24
Finished Aug 08 06:11:21 PM PDT 24
Peak memory 206228 kb
Host smart-dd148a32-78f8-4530-b3f0-1a0f2c151f59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463913518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
3463913518
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.1959784284
Short name T323
Test name
Test status
Simulation time 458425751 ps
CPU time 8.89 seconds
Started Aug 08 06:11:13 PM PDT 24
Finished Aug 08 06:11:22 PM PDT 24
Peak memory 225272 kb
Host smart-3ac0c7ba-7105-47a7-b6b0-fee7099135d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959784284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.1959784284
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.1927219648
Short name T416
Test name
Test status
Simulation time 44785960 ps
CPU time 0.74 seconds
Started Aug 08 06:11:16 PM PDT 24
Finished Aug 08 06:11:17 PM PDT 24
Peak memory 206388 kb
Host smart-7744b0b6-06ba-4e8c-901f-81d1d5212c1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927219648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.1927219648
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.581164397
Short name T183
Test name
Test status
Simulation time 44534989142 ps
CPU time 147.59 seconds
Started Aug 08 06:11:14 PM PDT 24
Finished Aug 08 06:13:42 PM PDT 24
Peak memory 261744 kb
Host smart-7ed8effb-502c-43a1-ad44-7ef88d690ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581164397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.581164397
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.989508608
Short name T915
Test name
Test status
Simulation time 1995977914 ps
CPU time 12.06 seconds
Started Aug 08 06:11:14 PM PDT 24
Finished Aug 08 06:11:26 PM PDT 24
Peak memory 225180 kb
Host smart-515c8aa5-8446-4ded-8d76-4ab522aecefa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989508608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.989508608
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.347849349
Short name T693
Test name
Test status
Simulation time 22843425662 ps
CPU time 52.78 seconds
Started Aug 08 06:11:15 PM PDT 24
Finished Aug 08 06:12:08 PM PDT 24
Peak memory 249968 kb
Host smart-fdc2feed-9f26-471f-9f6c-7dc1a12e1e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347849349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idle
.347849349
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.1340424644
Short name T823
Test name
Test status
Simulation time 4378387187 ps
CPU time 13.58 seconds
Started Aug 08 06:11:16 PM PDT 24
Finished Aug 08 06:11:30 PM PDT 24
Peak memory 225240 kb
Host smart-ed4ef57b-5892-44ae-b517-c9736c40b2b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340424644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.1340424644
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.118110639
Short name T328
Test name
Test status
Simulation time 40371917 ps
CPU time 0.79 seconds
Started Aug 08 06:11:15 PM PDT 24
Finished Aug 08 06:11:16 PM PDT 24
Peak memory 216644 kb
Host smart-e07f95b6-ae6c-448e-ae5b-fafd69c70ebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118110639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmds
.118110639
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/20.spi_device_intercept.2439258670
Short name T866
Test name
Test status
Simulation time 402280244 ps
CPU time 3.65 seconds
Started Aug 08 06:11:13 PM PDT 24
Finished Aug 08 06:11:17 PM PDT 24
Peak memory 225188 kb
Host smart-11b850b7-8641-4b26-8db9-839a4e720974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439258670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.2439258670
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.2187752454
Short name T223
Test name
Test status
Simulation time 4414881434 ps
CPU time 14.95 seconds
Started Aug 08 06:11:13 PM PDT 24
Finished Aug 08 06:11:28 PM PDT 24
Peak memory 249840 kb
Host smart-418ccdb1-65b2-4621-9658-0b4a3225bab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187752454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.2187752454
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.200257848
Short name T259
Test name
Test status
Simulation time 17991752115 ps
CPU time 33.88 seconds
Started Aug 08 06:11:13 PM PDT 24
Finished Aug 08 06:11:47 PM PDT 24
Peak memory 225248 kb
Host smart-e96da452-3eef-4326-bccb-9a6ba41e1302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200257848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swap
.200257848
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.602612819
Short name T247
Test name
Test status
Simulation time 996262214 ps
CPU time 5.13 seconds
Started Aug 08 06:11:14 PM PDT 24
Finished Aug 08 06:11:19 PM PDT 24
Peak memory 233440 kb
Host smart-6b5d0e0f-6f88-424e-9da2-a5e80ed0fb47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602612819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.602612819
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.1686919676
Short name T974
Test name
Test status
Simulation time 109481995 ps
CPU time 3.63 seconds
Started Aug 08 06:11:11 PM PDT 24
Finished Aug 08 06:11:14 PM PDT 24
Peak memory 220968 kb
Host smart-52b7e5cf-7394-42ab-8269-c729014f77ab
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1686919676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.1686919676
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.1769867070
Short name T1000
Test name
Test status
Simulation time 7399268008 ps
CPU time 35.84 seconds
Started Aug 08 06:11:14 PM PDT 24
Finished Aug 08 06:11:50 PM PDT 24
Peak memory 236288 kb
Host smart-2dd683d3-61cd-4875-bc1d-067cf06d3519
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769867070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.1769867070
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.2700985326
Short name T312
Test name
Test status
Simulation time 4590039770 ps
CPU time 17.89 seconds
Started Aug 08 06:11:14 PM PDT 24
Finished Aug 08 06:11:32 PM PDT 24
Peak memory 217232 kb
Host smart-d4aa1c95-8845-4629-84d0-9e190cd8c409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700985326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.2700985326
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.948081167
Short name T525
Test name
Test status
Simulation time 10759711958 ps
CPU time 25.44 seconds
Started Aug 08 06:11:19 PM PDT 24
Finished Aug 08 06:11:45 PM PDT 24
Peak memory 217020 kb
Host smart-c33f831c-2c84-47ef-965e-7441f6ff1a39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948081167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.948081167
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.3692210545
Short name T829
Test name
Test status
Simulation time 32609356 ps
CPU time 1.25 seconds
Started Aug 08 06:11:14 PM PDT 24
Finished Aug 08 06:11:15 PM PDT 24
Peak memory 208512 kb
Host smart-fb2afd5f-cfce-4bc8-bb50-3c15b27186b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692210545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.3692210545
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.4273038431
Short name T335
Test name
Test status
Simulation time 203960933 ps
CPU time 0.75 seconds
Started Aug 08 06:11:16 PM PDT 24
Finished Aug 08 06:11:17 PM PDT 24
Peak memory 206600 kb
Host smart-3ad15da9-7a5e-49e9-af90-66452ccf5017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273038431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.4273038431
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.1095811333
Short name T508
Test name
Test status
Simulation time 725491832 ps
CPU time 4.34 seconds
Started Aug 08 06:11:14 PM PDT 24
Finished Aug 08 06:11:19 PM PDT 24
Peak memory 233340 kb
Host smart-c6b9f102-162e-4713-b693-780bfc8dfb18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095811333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.1095811333
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.4117149126
Short name T319
Test name
Test status
Simulation time 15777177 ps
CPU time 0.68 seconds
Started Aug 08 06:11:12 PM PDT 24
Finished Aug 08 06:11:13 PM PDT 24
Peak memory 206208 kb
Host smart-c650f48d-5420-4c65-92e3-000a45a24550
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117149126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
4117149126
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.564964692
Short name T550
Test name
Test status
Simulation time 262140866 ps
CPU time 2.61 seconds
Started Aug 08 06:11:19 PM PDT 24
Finished Aug 08 06:11:22 PM PDT 24
Peak memory 225212 kb
Host smart-6a7fe0ae-c69f-4266-9903-08fd587982bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564964692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.564964692
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.387507790
Short name T377
Test name
Test status
Simulation time 56043950 ps
CPU time 0.78 seconds
Started Aug 08 06:11:16 PM PDT 24
Finished Aug 08 06:11:17 PM PDT 24
Peak memory 207388 kb
Host smart-aef82d88-c457-4b27-8be6-bde26db6f05c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387507790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.387507790
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.2657357736
Short name T364
Test name
Test status
Simulation time 21219420888 ps
CPU time 42.94 seconds
Started Aug 08 06:11:14 PM PDT 24
Finished Aug 08 06:11:57 PM PDT 24
Peak memory 236404 kb
Host smart-02dfea9d-3d59-4db2-be8f-a1fb97d3a344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657357736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.2657357736
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.1924918399
Short name T522
Test name
Test status
Simulation time 13865245541 ps
CPU time 137.62 seconds
Started Aug 08 06:11:16 PM PDT 24
Finished Aug 08 06:13:33 PM PDT 24
Peak memory 240476 kb
Host smart-51dcf555-de0b-494a-a8e8-75f4082427da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924918399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.1924918399
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.3155340698
Short name T194
Test name
Test status
Simulation time 75183207000 ps
CPU time 80.01 seconds
Started Aug 08 06:11:15 PM PDT 24
Finished Aug 08 06:12:35 PM PDT 24
Peak memory 253336 kb
Host smart-cdbdcf68-e175-4d30-9130-88e8b5873966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155340698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.3155340698
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.2457018002
Short name T142
Test name
Test status
Simulation time 73934345 ps
CPU time 4.52 seconds
Started Aug 08 06:11:12 PM PDT 24
Finished Aug 08 06:11:17 PM PDT 24
Peak memory 225168 kb
Host smart-997bbcb7-c90d-4bac-9a3d-de318c6ca382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457018002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.2457018002
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.1452859246
Short name T176
Test name
Test status
Simulation time 13655242262 ps
CPU time 97.27 seconds
Started Aug 08 06:11:12 PM PDT 24
Finished Aug 08 06:12:50 PM PDT 24
Peak memory 254624 kb
Host smart-8aa5fb2d-ea1d-49ad-b940-85593d750e83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452859246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmd
s.1452859246
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_intercept.2761281514
Short name T859
Test name
Test status
Simulation time 971561948 ps
CPU time 9.19 seconds
Started Aug 08 06:11:13 PM PDT 24
Finished Aug 08 06:11:23 PM PDT 24
Peak memory 225184 kb
Host smart-00a2b07c-572a-48f7-9767-4baa1cec8065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761281514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.2761281514
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.570640762
Short name T883
Test name
Test status
Simulation time 687668836 ps
CPU time 10 seconds
Started Aug 08 06:11:16 PM PDT 24
Finished Aug 08 06:11:26 PM PDT 24
Peak memory 239800 kb
Host smart-d5c7a30f-86a6-4d87-aca2-a90bf22c4859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570640762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.570640762
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.1118146503
Short name T890
Test name
Test status
Simulation time 53752712737 ps
CPU time 22.15 seconds
Started Aug 08 06:11:14 PM PDT 24
Finished Aug 08 06:11:36 PM PDT 24
Peak memory 225252 kb
Host smart-ff24b682-ee86-4524-a10d-72f2b3e32b92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118146503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.1118146503
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.1621569666
Short name T233
Test name
Test status
Simulation time 55799891 ps
CPU time 2.86 seconds
Started Aug 08 06:11:15 PM PDT 24
Finished Aug 08 06:11:18 PM PDT 24
Peak memory 233412 kb
Host smart-3b60c6b4-2148-4657-a0d0-10888944c4ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621569666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.1621569666
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.3373034289
Short name T638
Test name
Test status
Simulation time 219374438 ps
CPU time 5.13 seconds
Started Aug 08 06:11:13 PM PDT 24
Finished Aug 08 06:11:18 PM PDT 24
Peak memory 223124 kb
Host smart-40d2b756-d125-4b44-8cca-fab5e59fee7a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3373034289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.3373034289
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.3481339115
Short name T877
Test name
Test status
Simulation time 22964980791 ps
CPU time 136.24 seconds
Started Aug 08 06:11:14 PM PDT 24
Finished Aug 08 06:13:30 PM PDT 24
Peak memory 241604 kb
Host smart-5ccd3534-6565-49b5-af5f-c347f7437702
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481339115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.3481339115
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.3151616276
Short name T311
Test name
Test status
Simulation time 7847358469 ps
CPU time 41.35 seconds
Started Aug 08 06:11:12 PM PDT 24
Finished Aug 08 06:11:53 PM PDT 24
Peak memory 217088 kb
Host smart-544f1e5c-e35f-4b0b-8bb1-ec95a9c3f67d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151616276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.3151616276
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.1444117872
Short name T526
Test name
Test status
Simulation time 619668015 ps
CPU time 4.31 seconds
Started Aug 08 06:11:12 PM PDT 24
Finished Aug 08 06:11:17 PM PDT 24
Peak memory 216936 kb
Host smart-902c4c92-c7d7-4f18-9dc2-24af8a498752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444117872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.1444117872
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.942442717
Short name T535
Test name
Test status
Simulation time 16396128 ps
CPU time 1 seconds
Started Aug 08 06:11:12 PM PDT 24
Finished Aug 08 06:11:13 PM PDT 24
Peak memory 208420 kb
Host smart-d97f3e92-7eda-4b8b-b0eb-f4a39e95dd17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942442717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.942442717
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.2726564710
Short name T844
Test name
Test status
Simulation time 78155262 ps
CPU time 0.85 seconds
Started Aug 08 06:11:17 PM PDT 24
Finished Aug 08 06:11:18 PM PDT 24
Peak memory 206532 kb
Host smart-80f31988-3852-4168-87de-937605fdf1e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726564710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.2726564710
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.1326249801
Short name T10
Test name
Test status
Simulation time 1960294420 ps
CPU time 12.3 seconds
Started Aug 08 06:11:13 PM PDT 24
Finished Aug 08 06:11:26 PM PDT 24
Peak memory 241648 kb
Host smart-0f6d1cc4-c3b0-4404-a26a-05c92edcc089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326249801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.1326249801
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.1296211979
Short name T150
Test name
Test status
Simulation time 27618918 ps
CPU time 0.72 seconds
Started Aug 08 06:11:23 PM PDT 24
Finished Aug 08 06:11:24 PM PDT 24
Peak memory 205304 kb
Host smart-fa346926-267b-425f-80a0-da13c68c7bb6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296211979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
1296211979
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.3522372014
Short name T636
Test name
Test status
Simulation time 57234100 ps
CPU time 2.13 seconds
Started Aug 08 06:11:24 PM PDT 24
Finished Aug 08 06:11:26 PM PDT 24
Peak memory 233060 kb
Host smart-ff664a9b-04a5-4400-b292-a8120b5e6817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522372014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.3522372014
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.3689749949
Short name T561
Test name
Test status
Simulation time 16679017 ps
CPU time 0.76 seconds
Started Aug 08 06:11:13 PM PDT 24
Finished Aug 08 06:11:14 PM PDT 24
Peak memory 207008 kb
Host smart-ed4108ff-8a7a-4c7d-a418-34077ce037ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689749949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.3689749949
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.2901999613
Short name T597
Test name
Test status
Simulation time 4741948625 ps
CPU time 64.9 seconds
Started Aug 08 06:11:25 PM PDT 24
Finished Aug 08 06:12:30 PM PDT 24
Peak memory 257132 kb
Host smart-147176e9-7683-4976-b572-94c2a37ac38f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901999613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.2901999613
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.3487654404
Short name T776
Test name
Test status
Simulation time 35230649787 ps
CPU time 290.11 seconds
Started Aug 08 06:11:23 PM PDT 24
Finished Aug 08 06:16:14 PM PDT 24
Peak memory 250828 kb
Host smart-c913b8ea-f69f-44c5-ada5-c7b699befbfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487654404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.3487654404
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.1391712133
Short name T285
Test name
Test status
Simulation time 60948212325 ps
CPU time 463.77 seconds
Started Aug 08 06:11:25 PM PDT 24
Finished Aug 08 06:19:08 PM PDT 24
Peak memory 266340 kb
Host smart-13100eb5-89c5-4ea0-a8c5-617aa44e0211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391712133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.1391712133
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.3503750360
Short name T1002
Test name
Test status
Simulation time 1086151408 ps
CPU time 17.38 seconds
Started Aug 08 06:11:24 PM PDT 24
Finished Aug 08 06:11:42 PM PDT 24
Peak memory 225176 kb
Host smart-63ddffef-70f6-43b1-a925-6d958522861b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503750360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmd
s.3503750360
Directory /workspace/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/22.spi_device_intercept.1294821528
Short name T908
Test name
Test status
Simulation time 1811891555 ps
CPU time 10.91 seconds
Started Aug 08 06:11:24 PM PDT 24
Finished Aug 08 06:11:35 PM PDT 24
Peak memory 233384 kb
Host smart-2397333b-262f-4f19-ba99-d63ea6068ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294821528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.1294821528
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.3830602140
Short name T568
Test name
Test status
Simulation time 1219853111 ps
CPU time 21.08 seconds
Started Aug 08 06:11:23 PM PDT 24
Finished Aug 08 06:11:44 PM PDT 24
Peak memory 251088 kb
Host smart-0f97a89f-faa0-49eb-9c3f-7bc8d1e5a21c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830602140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.3830602140
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.75612950
Short name T751
Test name
Test status
Simulation time 1614184540 ps
CPU time 4.7 seconds
Started Aug 08 06:11:24 PM PDT 24
Finished Aug 08 06:11:29 PM PDT 24
Peak memory 233468 kb
Host smart-61272c7d-b22b-4317-a3d5-57d130685b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75612950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swap.75612950
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.491517668
Short name T249
Test name
Test status
Simulation time 8435912260 ps
CPU time 8.02 seconds
Started Aug 08 06:11:24 PM PDT 24
Finished Aug 08 06:11:32 PM PDT 24
Peak memory 219476 kb
Host smart-cb6311f8-bb37-40c0-9b41-5fb9b5a43ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491517668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.491517668
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.500060234
Short name T982
Test name
Test status
Simulation time 1091676780 ps
CPU time 12.06 seconds
Started Aug 08 06:11:25 PM PDT 24
Finished Aug 08 06:11:38 PM PDT 24
Peak memory 219884 kb
Host smart-41ff3372-e159-4c22-939a-74437b7aba12
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=500060234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dire
ct.500060234
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.4083104961
Short name T274
Test name
Test status
Simulation time 387110631838 ps
CPU time 944.72 seconds
Started Aug 08 06:11:23 PM PDT 24
Finished Aug 08 06:27:08 PM PDT 24
Peak memory 289524 kb
Host smart-5b4f766a-ee57-4462-acb3-e46642bcb4e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083104961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.4083104961
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.3875789689
Short name T559
Test name
Test status
Simulation time 132461012 ps
CPU time 0.67 seconds
Started Aug 08 06:11:16 PM PDT 24
Finished Aug 08 06:11:17 PM PDT 24
Peak memory 206156 kb
Host smart-2d054705-ee45-4e85-9848-dfb6ffdcc73b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875789689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.3875789689
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.1870396130
Short name T562
Test name
Test status
Simulation time 468957072 ps
CPU time 1.16 seconds
Started Aug 08 06:11:15 PM PDT 24
Finished Aug 08 06:11:16 PM PDT 24
Peak memory 207656 kb
Host smart-11fb35f1-382d-4948-abd1-c26b259f7729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870396130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.1870396130
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.570047038
Short name T990
Test name
Test status
Simulation time 225202596 ps
CPU time 2.86 seconds
Started Aug 08 06:11:14 PM PDT 24
Finished Aug 08 06:11:17 PM PDT 24
Peak memory 217008 kb
Host smart-c07075e3-4bc0-402e-b675-bd0073c0e232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570047038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.570047038
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.3933378643
Short name T867
Test name
Test status
Simulation time 243609154 ps
CPU time 0.85 seconds
Started Aug 08 06:11:13 PM PDT 24
Finished Aug 08 06:11:14 PM PDT 24
Peak memory 206612 kb
Host smart-5b8450da-b8df-4b85-9c2f-14b223b2f661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933378643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.3933378643
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.2339230248
Short name T505
Test name
Test status
Simulation time 162022814 ps
CPU time 3.41 seconds
Started Aug 08 06:11:23 PM PDT 24
Finished Aug 08 06:11:26 PM PDT 24
Peak memory 233472 kb
Host smart-f2c98e74-031f-4581-8f75-fe9625a43ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339230248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.2339230248
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.4097095335
Short name T59
Test name
Test status
Simulation time 17827047 ps
CPU time 0.76 seconds
Started Aug 08 06:11:23 PM PDT 24
Finished Aug 08 06:11:24 PM PDT 24
Peak memory 206036 kb
Host smart-34e4d6a0-7d1e-4b4b-9a63-0bd8ba425a63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097095335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
4097095335
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.1613881179
Short name T503
Test name
Test status
Simulation time 33480454 ps
CPU time 2.22 seconds
Started Aug 08 06:11:30 PM PDT 24
Finished Aug 08 06:11:32 PM PDT 24
Peak memory 225184 kb
Host smart-44c220dc-9614-4978-b5d4-9d54c4f7c48f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613881179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.1613881179
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.2162803276
Short name T778
Test name
Test status
Simulation time 38124226 ps
CPU time 0.84 seconds
Started Aug 08 06:11:24 PM PDT 24
Finished Aug 08 06:11:25 PM PDT 24
Peak memory 206980 kb
Host smart-8a2db221-ccc8-4f0f-97e0-1548ecf7cd83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162803276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.2162803276
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.4131016758
Short name T214
Test name
Test status
Simulation time 6951857895 ps
CPU time 71.55 seconds
Started Aug 08 06:11:25 PM PDT 24
Finished Aug 08 06:12:37 PM PDT 24
Peak memory 253828 kb
Host smart-ea8a9d39-6d25-491d-81ac-ee97d74924ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131016758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.4131016758
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.2586631000
Short name T213
Test name
Test status
Simulation time 3947133279 ps
CPU time 72.3 seconds
Started Aug 08 06:11:21 PM PDT 24
Finished Aug 08 06:12:34 PM PDT 24
Peak memory 252692 kb
Host smart-9a883489-7fcf-407c-9de6-d73569d2f9f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586631000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.2586631000
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.2113340377
Short name T296
Test name
Test status
Simulation time 2307702264 ps
CPU time 11.89 seconds
Started Aug 08 06:11:25 PM PDT 24
Finished Aug 08 06:11:37 PM PDT 24
Peak memory 232456 kb
Host smart-979cd700-1ac0-4955-9d39-750d4a100f95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113340377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.2113340377
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.1953288267
Short name T554
Test name
Test status
Simulation time 198671313 ps
CPU time 4.61 seconds
Started Aug 08 06:11:26 PM PDT 24
Finished Aug 08 06:11:31 PM PDT 24
Peak memory 241632 kb
Host smart-5f716c6f-57d0-4166-b97a-a859b9e2e015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953288267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmd
s.1953288267
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/23.spi_device_intercept.1193603574
Short name T766
Test name
Test status
Simulation time 2567107451 ps
CPU time 3.88 seconds
Started Aug 08 06:11:23 PM PDT 24
Finished Aug 08 06:11:27 PM PDT 24
Peak memory 225292 kb
Host smart-f58f75ca-bfcd-45df-ac4b-d75b071c3272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193603574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.1193603574
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.4015784589
Short name T904
Test name
Test status
Simulation time 55108289818 ps
CPU time 73.91 seconds
Started Aug 08 06:11:23 PM PDT 24
Finished Aug 08 06:12:37 PM PDT 24
Peak memory 233472 kb
Host smart-58069b1b-b5b0-4545-9f53-63612aa81916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015784589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.4015784589
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.2174242834
Short name T643
Test name
Test status
Simulation time 36627273825 ps
CPU time 29.14 seconds
Started Aug 08 06:11:25 PM PDT 24
Finished Aug 08 06:11:55 PM PDT 24
Peak memory 241648 kb
Host smart-9ad16931-cb7a-4763-a345-10fa0a9d8ba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174242834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.2174242834
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.2404811607
Short name T669
Test name
Test status
Simulation time 6453701299 ps
CPU time 19.8 seconds
Started Aug 08 06:11:28 PM PDT 24
Finished Aug 08 06:11:48 PM PDT 24
Peak memory 233492 kb
Host smart-75c362b1-85b2-41d0-8d32-29339f7bc2da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404811607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.2404811607
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.566029849
Short name T457
Test name
Test status
Simulation time 140819444 ps
CPU time 4.37 seconds
Started Aug 08 06:11:23 PM PDT 24
Finished Aug 08 06:11:28 PM PDT 24
Peak memory 220348 kb
Host smart-4a39aecb-a30d-440f-adae-d25346c655dc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=566029849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dire
ct.566029849
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.3294960637
Short name T159
Test name
Test status
Simulation time 5618605714 ps
CPU time 44.66 seconds
Started Aug 08 06:11:24 PM PDT 24
Finished Aug 08 06:12:09 PM PDT 24
Peak memory 257868 kb
Host smart-1113c743-848f-4ce4-9ae8-3bbcea21d2f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294960637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.3294960637
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.3831187433
Short name T450
Test name
Test status
Simulation time 868094368 ps
CPU time 9.33 seconds
Started Aug 08 06:11:22 PM PDT 24
Finished Aug 08 06:11:32 PM PDT 24
Peak memory 217012 kb
Host smart-a4198068-3836-48c7-bcc6-9dc002dc6c2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831187433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.3831187433
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.1433822619
Short name T509
Test name
Test status
Simulation time 4257810197 ps
CPU time 4.91 seconds
Started Aug 08 06:11:25 PM PDT 24
Finished Aug 08 06:11:30 PM PDT 24
Peak memory 217088 kb
Host smart-2216299a-ebe9-47d4-8c30-15397f626888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433822619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.1433822619
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.1045789243
Short name T336
Test name
Test status
Simulation time 78455747 ps
CPU time 1.69 seconds
Started Aug 08 06:11:25 PM PDT 24
Finished Aug 08 06:11:27 PM PDT 24
Peak memory 216980 kb
Host smart-4b1eb8a6-4d94-4c1c-8571-6dce557539c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045789243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.1045789243
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.809151145
Short name T884
Test name
Test status
Simulation time 64098688 ps
CPU time 0.78 seconds
Started Aug 08 06:11:23 PM PDT 24
Finished Aug 08 06:11:24 PM PDT 24
Peak memory 206576 kb
Host smart-b1ffbad4-4469-4d38-900b-5c70835b6e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809151145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.809151145
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.3596640058
Short name T836
Test name
Test status
Simulation time 2582131207 ps
CPU time 10.35 seconds
Started Aug 08 06:11:23 PM PDT 24
Finished Aug 08 06:11:34 PM PDT 24
Peak memory 225356 kb
Host smart-9b882e73-1e32-4181-be34-67b3f7f1f339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596640058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.3596640058
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.3401990633
Short name T768
Test name
Test status
Simulation time 44806120 ps
CPU time 0.75 seconds
Started Aug 08 06:11:43 PM PDT 24
Finished Aug 08 06:11:44 PM PDT 24
Peak memory 205884 kb
Host smart-f225f67e-0670-459b-9319-a28c22f1328d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401990633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
3401990633
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.3808616163
Short name T428
Test name
Test status
Simulation time 51415113 ps
CPU time 2.88 seconds
Started Aug 08 06:11:28 PM PDT 24
Finished Aug 08 06:11:31 PM PDT 24
Peak memory 233388 kb
Host smart-36ff510d-d158-4210-98a7-ba5ade0509b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808616163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.3808616163
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.881062799
Short name T760
Test name
Test status
Simulation time 25693439 ps
CPU time 0.77 seconds
Started Aug 08 06:11:24 PM PDT 24
Finished Aug 08 06:11:25 PM PDT 24
Peak memory 207424 kb
Host smart-c0844138-0181-4412-ad3b-6fec81eaed72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881062799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.881062799
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.1601958952
Short name T792
Test name
Test status
Simulation time 97747208732 ps
CPU time 160.47 seconds
Started Aug 08 06:11:36 PM PDT 24
Finished Aug 08 06:14:16 PM PDT 24
Peak memory 249892 kb
Host smart-99466830-eed5-4df5-8414-b84f8a51e4ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601958952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.1601958952
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.263852903
Short name T218
Test name
Test status
Simulation time 17240362840 ps
CPU time 172.93 seconds
Started Aug 08 06:11:35 PM PDT 24
Finished Aug 08 06:14:28 PM PDT 24
Peak memory 257972 kb
Host smart-c2aa064b-2a59-47cd-8293-7558ec8c1f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263852903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.263852903
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.1437323478
Short name T411
Test name
Test status
Simulation time 1068070494 ps
CPU time 11.16 seconds
Started Aug 08 06:11:38 PM PDT 24
Finished Aug 08 06:11:50 PM PDT 24
Peak memory 233412 kb
Host smart-2715cf91-fcda-4888-87c5-2557d497afe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437323478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.1437323478
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.1894539997
Short name T650
Test name
Test status
Simulation time 7461974775 ps
CPU time 38.8 seconds
Started Aug 08 06:11:36 PM PDT 24
Finished Aug 08 06:12:15 PM PDT 24
Peak memory 249888 kb
Host smart-8231b16c-46c4-487a-836e-a28d0f350feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894539997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmd
s.1894539997
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/24.spi_device_intercept.1540929848
Short name T196
Test name
Test status
Simulation time 1283352872 ps
CPU time 12.62 seconds
Started Aug 08 06:11:26 PM PDT 24
Finished Aug 08 06:11:39 PM PDT 24
Peak memory 233468 kb
Host smart-7ac517d2-ab42-45aa-9839-52c18fd7ab58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540929848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.1540929848
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.1713344344
Short name T646
Test name
Test status
Simulation time 105144101 ps
CPU time 2.35 seconds
Started Aug 08 06:11:26 PM PDT 24
Finished Aug 08 06:11:28 PM PDT 24
Peak memory 224452 kb
Host smart-3cebc793-2a8c-4658-8e54-d7ae962694d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713344344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.1713344344
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.3068793720
Short name T438
Test name
Test status
Simulation time 8432792852 ps
CPU time 5.38 seconds
Started Aug 08 06:11:23 PM PDT 24
Finished Aug 08 06:11:28 PM PDT 24
Peak memory 225240 kb
Host smart-211994de-6a98-4de6-b285-12eab27ab3c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068793720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.3068793720
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.1345273611
Short name T770
Test name
Test status
Simulation time 2841271188 ps
CPU time 8.94 seconds
Started Aug 08 06:11:35 PM PDT 24
Finished Aug 08 06:11:44 PM PDT 24
Peak memory 219456 kb
Host smart-cc3137bb-00bd-486c-84b2-a031d514a450
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1345273611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.1345273611
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.345859288
Short name T54
Test name
Test status
Simulation time 147564527 ps
CPU time 0.97 seconds
Started Aug 08 06:11:34 PM PDT 24
Finished Aug 08 06:11:35 PM PDT 24
Peak memory 207340 kb
Host smart-fcd79906-7ba8-4eb5-9404-df3cb6e7f6a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345859288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stres
s_all.345859288
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.3411254299
Short name T687
Test name
Test status
Simulation time 2209950476 ps
CPU time 11.35 seconds
Started Aug 08 06:11:26 PM PDT 24
Finished Aug 08 06:11:37 PM PDT 24
Peak memory 219668 kb
Host smart-2736cfab-9693-4836-9f06-9499401ee706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411254299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.3411254299
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.2731221124
Short name T754
Test name
Test status
Simulation time 975570209 ps
CPU time 2.59 seconds
Started Aug 08 06:11:24 PM PDT 24
Finished Aug 08 06:11:26 PM PDT 24
Peak memory 217000 kb
Host smart-223d2ad2-b50c-46c5-baca-1bcaddf95efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731221124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.2731221124
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.4186380378
Short name T45
Test name
Test status
Simulation time 73521532 ps
CPU time 0.96 seconds
Started Aug 08 06:11:29 PM PDT 24
Finished Aug 08 06:11:30 PM PDT 24
Peak memory 207540 kb
Host smart-16b23a60-d700-4637-bade-4e734cbd76ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186380378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.4186380378
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.2427953176
Short name T925
Test name
Test status
Simulation time 44098035 ps
CPU time 0.84 seconds
Started Aug 08 06:11:26 PM PDT 24
Finished Aug 08 06:11:27 PM PDT 24
Peak memory 206600 kb
Host smart-a035d3b7-c529-4b81-8ee2-e1629a957d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427953176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.2427953176
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.3051232678
Short name T948
Test name
Test status
Simulation time 91568517 ps
CPU time 2.28 seconds
Started Aug 08 06:11:27 PM PDT 24
Finished Aug 08 06:11:29 PM PDT 24
Peak memory 233072 kb
Host smart-f2a383cc-7006-45ec-9f1d-451fb2e8e013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051232678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.3051232678
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.690415644
Short name T801
Test name
Test status
Simulation time 43556867 ps
CPU time 0.7 seconds
Started Aug 08 06:11:36 PM PDT 24
Finished Aug 08 06:11:37 PM PDT 24
Peak memory 205288 kb
Host smart-5a9f5227-1966-41a3-aab1-401fe1dd8346
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690415644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.690415644
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.1477778641
Short name T1010
Test name
Test status
Simulation time 3451616433 ps
CPU time 8.07 seconds
Started Aug 08 06:11:40 PM PDT 24
Finished Aug 08 06:11:48 PM PDT 24
Peak memory 233504 kb
Host smart-641155d2-4c5c-4616-80dd-edb21c1f8a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477778641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.1477778641
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.3121377723
Short name T6
Test name
Test status
Simulation time 13626467 ps
CPU time 0.77 seconds
Started Aug 08 06:11:33 PM PDT 24
Finished Aug 08 06:11:33 PM PDT 24
Peak memory 207072 kb
Host smart-50ae9eb8-d2a3-4594-a8bc-077b33381d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121377723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.3121377723
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.41628704
Short name T337
Test name
Test status
Simulation time 19064964389 ps
CPU time 126.83 seconds
Started Aug 08 06:11:35 PM PDT 24
Finished Aug 08 06:13:42 PM PDT 24
Peak memory 241728 kb
Host smart-9082dbbe-d4f7-4945-96b2-48da763a3e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41628704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.41628704
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.3619936814
Short name T942
Test name
Test status
Simulation time 4489608413 ps
CPU time 61.87 seconds
Started Aug 08 06:11:34 PM PDT 24
Finished Aug 08 06:12:36 PM PDT 24
Peak memory 250036 kb
Host smart-278f8f4c-ad61-4639-bcb6-8a7c62b371ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619936814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.3619936814
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.649486203
Short name T209
Test name
Test status
Simulation time 7746145369 ps
CPU time 117.35 seconds
Started Aug 08 06:11:38 PM PDT 24
Finished Aug 08 06:13:35 PM PDT 24
Peak memory 250996 kb
Host smart-db742c44-dff2-4747-836d-185c97316fcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649486203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idle
.649486203
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.71901938
Short name T658
Test name
Test status
Simulation time 365237717 ps
CPU time 4.24 seconds
Started Aug 08 06:11:38 PM PDT 24
Finished Aug 08 06:11:42 PM PDT 24
Peak memory 225452 kb
Host smart-81bd735e-6f02-448a-b9c4-075293e1d013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71901938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.71901938
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.3661840069
Short name T35
Test name
Test status
Simulation time 14463168705 ps
CPU time 52.02 seconds
Started Aug 08 06:11:34 PM PDT 24
Finished Aug 08 06:12:26 PM PDT 24
Peak memory 251964 kb
Host smart-1d98b498-5f81-499a-bca0-c373f5639c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661840069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmd
s.3661840069
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/25.spi_device_intercept.821028680
Short name T944
Test name
Test status
Simulation time 499564863 ps
CPU time 4.62 seconds
Started Aug 08 06:11:33 PM PDT 24
Finished Aug 08 06:11:37 PM PDT 24
Peak memory 225252 kb
Host smart-f9157596-6cbe-4709-8d12-c69403c6fe62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821028680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.821028680
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.1456187089
Short name T153
Test name
Test status
Simulation time 820305129 ps
CPU time 20.07 seconds
Started Aug 08 06:11:41 PM PDT 24
Finished Aug 08 06:12:01 PM PDT 24
Peak memory 233392 kb
Host smart-9236b7ac-b54e-42ec-a02d-02bc070c35c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456187089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.1456187089
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.3574174254
Short name T800
Test name
Test status
Simulation time 852953878 ps
CPU time 2.71 seconds
Started Aug 08 06:11:34 PM PDT 24
Finished Aug 08 06:11:37 PM PDT 24
Peak memory 225208 kb
Host smart-02bbc822-262e-4904-ae55-df7b0e2c15d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574174254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.3574174254
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.91710344
Short name T611
Test name
Test status
Simulation time 82962042 ps
CPU time 2.44 seconds
Started Aug 08 06:11:37 PM PDT 24
Finished Aug 08 06:11:39 PM PDT 24
Peak memory 225248 kb
Host smart-1663b28f-1ab0-44fa-bed5-fd00d019f976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91710344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.91710344
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.2262081566
Short name T470
Test name
Test status
Simulation time 527184906 ps
CPU time 6.23 seconds
Started Aug 08 06:11:38 PM PDT 24
Finished Aug 08 06:11:44 PM PDT 24
Peak memory 223052 kb
Host smart-ff9b03da-4bc1-49f8-906e-46be1c7b89f6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2262081566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.2262081566
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.249612136
Short name T308
Test name
Test status
Simulation time 1462204220 ps
CPU time 21.74 seconds
Started Aug 08 06:11:35 PM PDT 24
Finished Aug 08 06:11:57 PM PDT 24
Peak memory 216980 kb
Host smart-925cf2b9-9f20-4a28-a724-9c5ba608713d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249612136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.249612136
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.3749475095
Short name T415
Test name
Test status
Simulation time 493646905 ps
CPU time 3.99 seconds
Started Aug 08 06:11:42 PM PDT 24
Finished Aug 08 06:11:46 PM PDT 24
Peak memory 216924 kb
Host smart-ffabc657-ccf1-4fa4-a714-2efebf0106d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749475095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.3749475095
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.2767918708
Short name T408
Test name
Test status
Simulation time 79557490 ps
CPU time 1.58 seconds
Started Aug 08 06:11:36 PM PDT 24
Finished Aug 08 06:11:38 PM PDT 24
Peak memory 216984 kb
Host smart-bf7f520f-5337-4ad2-bc4f-6e3c25e3a821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767918708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.2767918708
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.772168070
Short name T857
Test name
Test status
Simulation time 91035219 ps
CPU time 0.89 seconds
Started Aug 08 06:11:37 PM PDT 24
Finished Aug 08 06:11:38 PM PDT 24
Peak memory 206760 kb
Host smart-47911ee4-9262-4b7c-96d3-2e6bb2db47d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772168070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.772168070
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.2190095395
Short name T539
Test name
Test status
Simulation time 14664752019 ps
CPU time 16.14 seconds
Started Aug 08 06:11:39 PM PDT 24
Finished Aug 08 06:11:55 PM PDT 24
Peak memory 238504 kb
Host smart-4961a9bd-b40d-488f-b421-a98723b004d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190095395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.2190095395
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.2043515841
Short name T62
Test name
Test status
Simulation time 11979466 ps
CPU time 0.7 seconds
Started Aug 08 06:11:36 PM PDT 24
Finished Aug 08 06:11:37 PM PDT 24
Peak memory 206260 kb
Host smart-4e476309-59f9-49bd-9e8d-9b30506dd5a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043515841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
2043515841
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.3061194741
Short name T680
Test name
Test status
Simulation time 140697727 ps
CPU time 2.84 seconds
Started Aug 08 06:11:37 PM PDT 24
Finished Aug 08 06:11:40 PM PDT 24
Peak memory 225152 kb
Host smart-976a6948-4e27-40eb-be51-21a08f4bfed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061194741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.3061194741
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.2215714371
Short name T430
Test name
Test status
Simulation time 32058368 ps
CPU time 0.77 seconds
Started Aug 08 06:11:37 PM PDT 24
Finished Aug 08 06:11:38 PM PDT 24
Peak memory 207392 kb
Host smart-004266d5-31ce-4fb8-90f7-7826d5b1ea60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215714371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.2215714371
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.415848555
Short name T995
Test name
Test status
Simulation time 8985973794 ps
CPU time 24.2 seconds
Started Aug 08 06:11:33 PM PDT 24
Finished Aug 08 06:11:57 PM PDT 24
Peak memory 249824 kb
Host smart-23c01890-d23a-4c51-a731-8569f5e1cd4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415848555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.415848555
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.3920350586
Short name T777
Test name
Test status
Simulation time 104542889180 ps
CPU time 325.08 seconds
Started Aug 08 06:11:34 PM PDT 24
Finished Aug 08 06:16:59 PM PDT 24
Peak memory 273948 kb
Host smart-e060abea-f050-4e9f-9182-606b6cfdb9ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920350586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.3920350586
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.3161996661
Short name T490
Test name
Test status
Simulation time 146195706099 ps
CPU time 371.87 seconds
Started Aug 08 06:11:37 PM PDT 24
Finished Aug 08 06:17:49 PM PDT 24
Peak memory 256176 kb
Host smart-841b4ce8-6506-4a25-a31e-016ad730d62e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161996661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.3161996661
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.2429788515
Short name T978
Test name
Test status
Simulation time 556563078 ps
CPU time 3.61 seconds
Started Aug 08 06:11:36 PM PDT 24
Finished Aug 08 06:11:40 PM PDT 24
Peak memory 225304 kb
Host smart-7ffd3dff-fcd0-4a87-8d00-710f8631f542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429788515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.2429788515
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.2404067584
Short name T329
Test name
Test status
Simulation time 19973584 ps
CPU time 0.77 seconds
Started Aug 08 06:11:41 PM PDT 24
Finished Aug 08 06:11:42 PM PDT 24
Peak memory 216444 kb
Host smart-553b7208-26eb-4134-a8bb-00e272cb5f3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404067584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmd
s.2404067584
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_intercept.2818960887
Short name T242
Test name
Test status
Simulation time 2258311790 ps
CPU time 18.7 seconds
Started Aug 08 06:11:43 PM PDT 24
Finished Aug 08 06:12:01 PM PDT 24
Peak memory 233552 kb
Host smart-82bd54fe-f735-498f-8682-b93ecf7ffc2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818960887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.2818960887
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.101156578
Short name T88
Test name
Test status
Simulation time 386411371 ps
CPU time 7.46 seconds
Started Aug 08 06:11:33 PM PDT 24
Finished Aug 08 06:11:41 PM PDT 24
Peak memory 233400 kb
Host smart-85a864a2-3741-44bc-a68b-cd9a17228ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101156578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.101156578
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.956473288
Short name T935
Test name
Test status
Simulation time 288176027 ps
CPU time 3.81 seconds
Started Aug 08 06:11:34 PM PDT 24
Finished Aug 08 06:11:38 PM PDT 24
Peak memory 225236 kb
Host smart-41656eec-4b4f-4ed0-9fae-0f05468eb31a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956473288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swap
.956473288
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.3250165030
Short name T1018
Test name
Test status
Simulation time 10761801682 ps
CPU time 14.01 seconds
Started Aug 08 06:11:34 PM PDT 24
Finished Aug 08 06:11:48 PM PDT 24
Peak memory 233520 kb
Host smart-14292c20-bb16-4d44-b64c-c75afbbe1ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250165030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.3250165030
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.1962008947
Short name T639
Test name
Test status
Simulation time 1497331139 ps
CPU time 3.28 seconds
Started Aug 08 06:11:36 PM PDT 24
Finished Aug 08 06:11:39 PM PDT 24
Peak memory 220328 kb
Host smart-93a66af1-afad-45cc-80b6-21a64ba32b00
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1962008947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.1962008947
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.1948693196
Short name T266
Test name
Test status
Simulation time 11815913261 ps
CPU time 120.73 seconds
Started Aug 08 06:11:37 PM PDT 24
Finished Aug 08 06:13:38 PM PDT 24
Peak memory 253596 kb
Host smart-65a95c3c-4d9e-4201-92f9-f92e76f02df3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948693196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.1948693196
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.3000030645
Short name T769
Test name
Test status
Simulation time 4156191604 ps
CPU time 23.1 seconds
Started Aug 08 06:11:34 PM PDT 24
Finished Aug 08 06:11:57 PM PDT 24
Peak memory 217096 kb
Host smart-f93d81bd-d817-41e3-837e-24247d5ff3f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000030645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.3000030645
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.687391215
Short name T659
Test name
Test status
Simulation time 7250481703 ps
CPU time 7.82 seconds
Started Aug 08 06:11:34 PM PDT 24
Finished Aug 08 06:11:42 PM PDT 24
Peak memory 217324 kb
Host smart-884807fa-b419-4e99-b0f6-2e63b58911bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687391215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.687391215
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.1351560993
Short name T924
Test name
Test status
Simulation time 21233224 ps
CPU time 1.41 seconds
Started Aug 08 06:11:34 PM PDT 24
Finished Aug 08 06:11:36 PM PDT 24
Peak memory 216964 kb
Host smart-95d4e8d9-86ae-42c5-b8ca-39f4898de300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351560993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.1351560993
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.150325961
Short name T819
Test name
Test status
Simulation time 11392921 ps
CPU time 0.69 seconds
Started Aug 08 06:11:35 PM PDT 24
Finished Aug 08 06:11:36 PM PDT 24
Peak memory 206132 kb
Host smart-85995af0-ba37-4477-9399-c90e2462b3f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150325961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.150325961
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.1406621069
Short name T360
Test name
Test status
Simulation time 1756094862 ps
CPU time 4.51 seconds
Started Aug 08 06:11:36 PM PDT 24
Finished Aug 08 06:11:40 PM PDT 24
Peak memory 225268 kb
Host smart-6c514b2c-2240-4185-a37a-fa8f02190218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406621069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.1406621069
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.8579398
Short name T724
Test name
Test status
Simulation time 51064790 ps
CPU time 0.75 seconds
Started Aug 08 06:11:48 PM PDT 24
Finished Aug 08 06:11:49 PM PDT 24
Peak memory 205868 kb
Host smart-beff1c31-ab1d-49c1-9aa6-a020a2f9942f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8579398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.8579398
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.1108973169
Short name T871
Test name
Test status
Simulation time 382090605 ps
CPU time 2.91 seconds
Started Aug 08 06:11:45 PM PDT 24
Finished Aug 08 06:11:49 PM PDT 24
Peak memory 225204 kb
Host smart-3f479f61-36bd-4481-b7f7-511fac7e4397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108973169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.1108973169
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.2969020611
Short name T980
Test name
Test status
Simulation time 17113531 ps
CPU time 0.76 seconds
Started Aug 08 06:11:39 PM PDT 24
Finished Aug 08 06:11:40 PM PDT 24
Peak memory 207400 kb
Host smart-73d3aee0-1501-4e98-bf24-7945080823b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969020611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.2969020611
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.55538680
Short name T205
Test name
Test status
Simulation time 43126282635 ps
CPU time 91.84 seconds
Started Aug 08 06:11:53 PM PDT 24
Finished Aug 08 06:13:25 PM PDT 24
Peak memory 255024 kb
Host smart-f1ad98c4-3140-4db2-9758-abdf37566e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55538680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.55538680
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.976201383
Short name T459
Test name
Test status
Simulation time 24797352062 ps
CPU time 236 seconds
Started Aug 08 06:11:47 PM PDT 24
Finished Aug 08 06:15:44 PM PDT 24
Peak memory 257288 kb
Host smart-f074f19e-18a1-41d0-b269-7d599478a05b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976201383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.976201383
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.910376675
Short name T739
Test name
Test status
Simulation time 183227503 ps
CPU time 2.75 seconds
Started Aug 08 06:11:47 PM PDT 24
Finished Aug 08 06:11:50 PM PDT 24
Peak memory 233404 kb
Host smart-a3c5b6a7-158e-480d-b794-0fe23c20e77a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910376675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.910376675
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.396017559
Short name T175
Test name
Test status
Simulation time 44392107033 ps
CPU time 44.01 seconds
Started Aug 08 06:11:48 PM PDT 24
Finished Aug 08 06:12:32 PM PDT 24
Peak memory 235680 kb
Host smart-61bde7e6-223b-4efb-b8e5-e13d49100c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396017559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmds
.396017559
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/27.spi_device_intercept.2615088255
Short name T613
Test name
Test status
Simulation time 15782867165 ps
CPU time 18.86 seconds
Started Aug 08 06:11:45 PM PDT 24
Finished Aug 08 06:12:04 PM PDT 24
Peak memory 225276 kb
Host smart-8e920d9c-42dc-42c9-a0ce-a09422e2cdf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615088255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.2615088255
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.2386830741
Short name T689
Test name
Test status
Simulation time 12317235665 ps
CPU time 39.24 seconds
Started Aug 08 06:11:48 PM PDT 24
Finished Aug 08 06:12:27 PM PDT 24
Peak memory 233480 kb
Host smart-5f6ba389-c086-4128-981d-46be4bdc64f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386830741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.2386830741
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.1192006051
Short name T390
Test name
Test status
Simulation time 427534454 ps
CPU time 2.26 seconds
Started Aug 08 06:11:36 PM PDT 24
Finished Aug 08 06:11:38 PM PDT 24
Peak memory 224488 kb
Host smart-4ece9ff1-360a-403d-91a3-7a2645ff31fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192006051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.1192006051
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.4175713390
Short name T432
Test name
Test status
Simulation time 6774837740 ps
CPU time 13.82 seconds
Started Aug 08 06:11:39 PM PDT 24
Finished Aug 08 06:11:53 PM PDT 24
Peak memory 233440 kb
Host smart-d6a42aab-e5e5-4dbf-a5cd-4ae3cb35b99f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175713390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.4175713390
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.3551690415
Short name T662
Test name
Test status
Simulation time 7205762088 ps
CPU time 7.1 seconds
Started Aug 08 06:11:43 PM PDT 24
Finished Aug 08 06:11:50 PM PDT 24
Peak memory 223700 kb
Host smart-e039b04b-7135-4407-9aed-89df35d2764c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3551690415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.3551690415
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.1894812964
Short name T418
Test name
Test status
Simulation time 248863116 ps
CPU time 1.24 seconds
Started Aug 08 06:11:44 PM PDT 24
Finished Aug 08 06:11:46 PM PDT 24
Peak memory 207456 kb
Host smart-0857ebb1-1554-4eb7-bd4d-8e2051d4d378
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894812964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.1894812964
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.1962919107
Short name T555
Test name
Test status
Simulation time 15007953099 ps
CPU time 14.81 seconds
Started Aug 08 06:11:37 PM PDT 24
Finished Aug 08 06:11:52 PM PDT 24
Peak memory 217180 kb
Host smart-26557c74-0e7b-4ef7-87d7-942e24ee3278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962919107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.1962919107
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.985636860
Short name T557
Test name
Test status
Simulation time 39700780 ps
CPU time 0.75 seconds
Started Aug 08 06:11:38 PM PDT 24
Finished Aug 08 06:11:39 PM PDT 24
Peak memory 206364 kb
Host smart-ed27376a-bf84-4fc5-855a-c2bded68918d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985636860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.985636860
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.82296144
Short name T1027
Test name
Test status
Simulation time 543255708 ps
CPU time 2.72 seconds
Started Aug 08 06:11:37 PM PDT 24
Finished Aug 08 06:11:40 PM PDT 24
Peak memory 208744 kb
Host smart-037bd0d6-4ebd-43bb-b528-a83857c219e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82296144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.82296144
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.4099910886
Short name T679
Test name
Test status
Simulation time 92261438 ps
CPU time 0.98 seconds
Started Aug 08 06:11:35 PM PDT 24
Finished Aug 08 06:11:36 PM PDT 24
Peak memory 207624 kb
Host smart-e232ebd2-359a-42cb-823e-f28561c1e29b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099910886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.4099910886
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.63022851
Short name T821
Test name
Test status
Simulation time 176669060 ps
CPU time 2.82 seconds
Started Aug 08 06:11:52 PM PDT 24
Finished Aug 08 06:11:55 PM PDT 24
Peak memory 225284 kb
Host smart-90cfbf75-301f-4477-a487-b7b369cfa601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63022851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.63022851
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.3751125283
Short name T506
Test name
Test status
Simulation time 14529451 ps
CPU time 0.69 seconds
Started Aug 08 06:11:47 PM PDT 24
Finished Aug 08 06:11:47 PM PDT 24
Peak memory 205836 kb
Host smart-2567fb3f-64b4-40b4-b882-372396bd2f1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751125283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
3751125283
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.235444541
Short name T343
Test name
Test status
Simulation time 30315459 ps
CPU time 2.63 seconds
Started Aug 08 06:11:48 PM PDT 24
Finished Aug 08 06:11:51 PM PDT 24
Peak memory 233032 kb
Host smart-8d4a42be-e32d-4a4e-90d9-9cca2524b2fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235444541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.235444541
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.2189965199
Short name T101
Test name
Test status
Simulation time 21190520 ps
CPU time 0.77 seconds
Started Aug 08 06:11:44 PM PDT 24
Finished Aug 08 06:11:45 PM PDT 24
Peak memory 207424 kb
Host smart-6a70ac09-1b1d-45b7-8745-23153a3a5b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189965199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.2189965199
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.3726184239
Short name T102
Test name
Test status
Simulation time 16265878017 ps
CPU time 57.07 seconds
Started Aug 08 06:11:46 PM PDT 24
Finished Aug 08 06:12:43 PM PDT 24
Peak memory 241744 kb
Host smart-cf844670-b917-41ec-a8d2-a23176be83a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726184239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.3726184239
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.2485631564
Short name T729
Test name
Test status
Simulation time 28036881195 ps
CPU time 246.05 seconds
Started Aug 08 06:11:45 PM PDT 24
Finished Aug 08 06:15:51 PM PDT 24
Peak memory 250992 kb
Host smart-329e6d81-71d5-4d58-84f7-153fc9d6c16e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485631564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.2485631564
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.2659357653
Short name T79
Test name
Test status
Simulation time 3274578198 ps
CPU time 78.54 seconds
Started Aug 08 06:11:46 PM PDT 24
Finished Aug 08 06:13:05 PM PDT 24
Peak memory 257548 kb
Host smart-19b7e05a-35e8-4d85-9620-6f0e0ab4b26e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659357653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.2659357653
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.1764427406
Short name T831
Test name
Test status
Simulation time 2300313631 ps
CPU time 8.14 seconds
Started Aug 08 06:11:45 PM PDT 24
Finished Aug 08 06:11:53 PM PDT 24
Peak memory 233436 kb
Host smart-a86e7996-1845-4f8c-acfe-069e96eaf37f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764427406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.1764427406
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.3038944931
Short name T625
Test name
Test status
Simulation time 75425266750 ps
CPU time 212.46 seconds
Started Aug 08 06:11:44 PM PDT 24
Finished Aug 08 06:15:17 PM PDT 24
Peak memory 255544 kb
Host smart-a2acbe54-b3c5-4053-8cf6-89e823a125f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038944931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmd
s.3038944931
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/28.spi_device_intercept.3204366468
Short name T863
Test name
Test status
Simulation time 2457315628 ps
CPU time 6.2 seconds
Started Aug 08 06:11:44 PM PDT 24
Finished Aug 08 06:11:51 PM PDT 24
Peak memory 225252 kb
Host smart-9fe0d301-a445-4fb1-8e44-2ac43f5d8a0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204366468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.3204366468
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.3548781039
Short name T241
Test name
Test status
Simulation time 5924711047 ps
CPU time 43.65 seconds
Started Aug 08 06:11:52 PM PDT 24
Finished Aug 08 06:12:36 PM PDT 24
Peak memory 225304 kb
Host smart-cc92bfa9-4ee1-4054-9d61-03bbe2885f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548781039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.3548781039
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.1303605157
Short name T895
Test name
Test status
Simulation time 5002905112 ps
CPU time 13.34 seconds
Started Aug 08 06:11:46 PM PDT 24
Finished Aug 08 06:11:59 PM PDT 24
Peak memory 233428 kb
Host smart-5efab831-82c5-4171-81e3-b9a4e2389d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303605157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.1303605157
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.596787075
Short name T602
Test name
Test status
Simulation time 2467060260 ps
CPU time 3.48 seconds
Started Aug 08 06:11:45 PM PDT 24
Finished Aug 08 06:11:49 PM PDT 24
Peak memory 233492 kb
Host smart-4b0e21dd-b275-4fc8-866b-4a93774ead31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596787075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.596787075
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.4216325778
Short name T546
Test name
Test status
Simulation time 465986923 ps
CPU time 4.08 seconds
Started Aug 08 06:11:43 PM PDT 24
Finished Aug 08 06:11:47 PM PDT 24
Peak memory 223748 kb
Host smart-f32b9d23-175b-4ec7-b335-56c60c8084cd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4216325778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.4216325778
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.3098608528
Short name T991
Test name
Test status
Simulation time 10951790351 ps
CPU time 150.24 seconds
Started Aug 08 06:11:46 PM PDT 24
Finished Aug 08 06:14:16 PM PDT 24
Peak memory 258208 kb
Host smart-7053f08f-e2ac-4812-9fdb-899ec861101d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098608528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.3098608528
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.3590991878
Short name T385
Test name
Test status
Simulation time 19385855015 ps
CPU time 51.16 seconds
Started Aug 08 06:11:44 PM PDT 24
Finished Aug 08 06:12:36 PM PDT 24
Peak memory 217076 kb
Host smart-faa16668-3bb1-433a-af8d-cdfe94208883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590991878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.3590991878
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.4071275148
Short name T409
Test name
Test status
Simulation time 28304300686 ps
CPU time 19.17 seconds
Started Aug 08 06:11:47 PM PDT 24
Finished Aug 08 06:12:06 PM PDT 24
Peak memory 218192 kb
Host smart-6e38a939-1d49-4245-836f-35b90693277a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071275148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.4071275148
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.855927992
Short name T384
Test name
Test status
Simulation time 84564093 ps
CPU time 1.59 seconds
Started Aug 08 06:11:46 PM PDT 24
Finished Aug 08 06:11:48 PM PDT 24
Peak memory 217008 kb
Host smart-81e05fd7-5d7c-4c84-8611-e41853bb42dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855927992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.855927992
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.1041088403
Short name T1020
Test name
Test status
Simulation time 32105136 ps
CPU time 0.75 seconds
Started Aug 08 06:11:44 PM PDT 24
Finished Aug 08 06:11:45 PM PDT 24
Peak memory 206584 kb
Host smart-db57e95d-a345-4b73-874e-5c736ff5aab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041088403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.1041088403
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.3139442578
Short name T939
Test name
Test status
Simulation time 5448090406 ps
CPU time 6.36 seconds
Started Aug 08 06:11:46 PM PDT 24
Finished Aug 08 06:11:53 PM PDT 24
Peak memory 233508 kb
Host smart-7ebabf23-ae70-4d2f-b0ac-aeb0240a3b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139442578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.3139442578
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.2004835968
Short name T940
Test name
Test status
Simulation time 113459300 ps
CPU time 0.82 seconds
Started Aug 08 06:11:51 PM PDT 24
Finished Aug 08 06:11:52 PM PDT 24
Peak memory 205852 kb
Host smart-bf872abf-c9a4-42ad-a5f8-2e6913458eaf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004835968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
2004835968
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.2494311844
Short name T231
Test name
Test status
Simulation time 149044368 ps
CPU time 2.45 seconds
Started Aug 08 06:11:52 PM PDT 24
Finished Aug 08 06:11:55 PM PDT 24
Peak memory 225196 kb
Host smart-0be01c54-4910-4228-8e90-a9d04373f413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494311844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.2494311844
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.3786059341
Short name T758
Test name
Test status
Simulation time 18212105 ps
CPU time 0.75 seconds
Started Aug 08 06:11:47 PM PDT 24
Finished Aug 08 06:11:48 PM PDT 24
Peak memory 206320 kb
Host smart-47452099-ea1f-45f7-8e98-b86aeccceb53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786059341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.3786059341
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.452199756
Short name T1007
Test name
Test status
Simulation time 1907464524 ps
CPU time 36.86 seconds
Started Aug 08 06:11:52 PM PDT 24
Finished Aug 08 06:12:29 PM PDT 24
Peak memory 249868 kb
Host smart-d1304f0c-e303-4b1a-a652-2542caa37907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452199756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.452199756
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.1289102951
Short name T313
Test name
Test status
Simulation time 4406637304 ps
CPU time 18.44 seconds
Started Aug 08 06:11:53 PM PDT 24
Finished Aug 08 06:12:11 PM PDT 24
Peak memory 218288 kb
Host smart-09cb1d23-6223-4956-bc87-ffd30f757a17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289102951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.1289102951
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.2150061899
Short name T219
Test name
Test status
Simulation time 13655535554 ps
CPU time 163.92 seconds
Started Aug 08 06:11:46 PM PDT 24
Finished Aug 08 06:14:30 PM PDT 24
Peak memory 266540 kb
Host smart-0a41d235-71ea-4674-8c11-182b2035a941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150061899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.2150061899
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.4047245030
Short name T473
Test name
Test status
Simulation time 149528437 ps
CPU time 3.55 seconds
Started Aug 08 06:11:44 PM PDT 24
Finished Aug 08 06:11:48 PM PDT 24
Peak memory 225248 kb
Host smart-1be86563-516e-4bad-9727-b79b4b5ab31d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047245030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.4047245030
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.3115556445
Short name T601
Test name
Test status
Simulation time 14904320 ps
CPU time 0.78 seconds
Started Aug 08 06:11:46 PM PDT 24
Finished Aug 08 06:11:47 PM PDT 24
Peak memory 216460 kb
Host smart-226d3e06-9b9f-4091-b187-bdf276c0307c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115556445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmd
s.3115556445
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/29.spi_device_intercept.877944248
Short name T841
Test name
Test status
Simulation time 284590979 ps
CPU time 3.09 seconds
Started Aug 08 06:11:51 PM PDT 24
Finished Aug 08 06:11:54 PM PDT 24
Peak memory 233480 kb
Host smart-b4086c43-6b0a-4df9-85cb-984f2449d3e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877944248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.877944248
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.713122224
Short name T573
Test name
Test status
Simulation time 337490659 ps
CPU time 5.36 seconds
Started Aug 08 06:11:47 PM PDT 24
Finished Aug 08 06:11:53 PM PDT 24
Peak memory 225148 kb
Host smart-1cfdbfff-7fd0-4437-a47e-45f5798a0265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713122224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.713122224
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.850974887
Short name T361
Test name
Test status
Simulation time 136301557 ps
CPU time 2.5 seconds
Started Aug 08 06:11:46 PM PDT 24
Finished Aug 08 06:11:48 PM PDT 24
Peak memory 233428 kb
Host smart-850c0830-30ed-492b-a92a-78d82b0d40ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850974887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swap
.850974887
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.3940083986
Short name T655
Test name
Test status
Simulation time 29321152 ps
CPU time 2.08 seconds
Started Aug 08 06:11:45 PM PDT 24
Finished Aug 08 06:11:48 PM PDT 24
Peak memory 224488 kb
Host smart-b02a5dae-fdc7-4168-9583-e34323e19133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940083986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.3940083986
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.1463057912
Short name T741
Test name
Test status
Simulation time 2285969486 ps
CPU time 8.14 seconds
Started Aug 08 06:11:46 PM PDT 24
Finished Aug 08 06:11:54 PM PDT 24
Peak memory 223072 kb
Host smart-99f9d7f9-5413-4919-b8f3-7d62201cd0b5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1463057912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.1463057912
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.4240771943
Short name T856
Test name
Test status
Simulation time 9424212464 ps
CPU time 143.19 seconds
Started Aug 08 06:11:45 PM PDT 24
Finished Aug 08 06:14:09 PM PDT 24
Peak memory 266012 kb
Host smart-41f2d51f-0474-4410-82a6-a236aa27e667
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240771943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.4240771943
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.339076556
Short name T598
Test name
Test status
Simulation time 4677332274 ps
CPU time 30.43 seconds
Started Aug 08 06:11:51 PM PDT 24
Finished Aug 08 06:12:21 PM PDT 24
Peak memory 217052 kb
Host smart-0ac81e1d-b3c9-4bc0-882a-1cdfd12740e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339076556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.339076556
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.3753472077
Short name T435
Test name
Test status
Simulation time 1697169856 ps
CPU time 5.15 seconds
Started Aug 08 06:11:52 PM PDT 24
Finished Aug 08 06:11:57 PM PDT 24
Peak memory 216892 kb
Host smart-6cf74682-91c3-4376-84ce-4e095e3705af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753472077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.3753472077
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.1983772153
Short name T767
Test name
Test status
Simulation time 17703671 ps
CPU time 0.9 seconds
Started Aug 08 06:11:47 PM PDT 24
Finished Aug 08 06:11:48 PM PDT 24
Peak memory 206752 kb
Host smart-66d91a7c-0360-4e99-b59f-946b6b860a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983772153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.1983772153
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.2378196456
Short name T545
Test name
Test status
Simulation time 44989525 ps
CPU time 0.69 seconds
Started Aug 08 06:11:45 PM PDT 24
Finished Aug 08 06:11:46 PM PDT 24
Peak memory 206044 kb
Host smart-f5453a4d-265f-461c-9d53-dc06dab8f8d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378196456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.2378196456
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.2434950041
Short name T864
Test name
Test status
Simulation time 3735476800 ps
CPU time 13.91 seconds
Started Aug 08 06:11:47 PM PDT 24
Finished Aug 08 06:12:01 PM PDT 24
Peak memory 238924 kb
Host smart-a4175e70-1983-4638-b115-c307e34e0e87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434950041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.2434950041
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.4184709665
Short name T794
Test name
Test status
Simulation time 12701849 ps
CPU time 0.72 seconds
Started Aug 08 06:10:20 PM PDT 24
Finished Aug 08 06:10:21 PM PDT 24
Peak memory 205888 kb
Host smart-c141ea43-d881-4be2-9c54-8dcade4ce6fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184709665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.4
184709665
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.1751139079
Short name T780
Test name
Test status
Simulation time 30822877 ps
CPU time 2.03 seconds
Started Aug 08 06:10:20 PM PDT 24
Finished Aug 08 06:10:23 PM PDT 24
Peak memory 225192 kb
Host smart-c354396b-a915-44e6-9921-e479dcb74ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751139079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.1751139079
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.4230031596
Short name T456
Test name
Test status
Simulation time 70482301 ps
CPU time 0.77 seconds
Started Aug 08 06:10:18 PM PDT 24
Finished Aug 08 06:10:19 PM PDT 24
Peak memory 206984 kb
Host smart-8819d293-ecc6-4494-aee9-a54d23b90f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230031596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.4230031596
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.107970732
Short name T748
Test name
Test status
Simulation time 18794236804 ps
CPU time 103 seconds
Started Aug 08 06:10:20 PM PDT 24
Finished Aug 08 06:12:03 PM PDT 24
Peak memory 266276 kb
Host smart-8561c16a-56ca-44ba-9350-a1b5dcb4ad62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107970732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.107970732
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.2486308264
Short name T921
Test name
Test status
Simulation time 27665140923 ps
CPU time 235.52 seconds
Started Aug 08 06:10:21 PM PDT 24
Finished Aug 08 06:14:17 PM PDT 24
Peak memory 254684 kb
Host smart-624836e8-14aa-4125-a1fd-7a9eeb1940be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486308264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.2486308264
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.4182781901
Short name T271
Test name
Test status
Simulation time 23371227770 ps
CPU time 125.43 seconds
Started Aug 08 06:10:20 PM PDT 24
Finished Aug 08 06:12:25 PM PDT 24
Peak memory 258156 kb
Host smart-bbf2c6d7-aa38-4eae-ad6f-d82112d51bc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182781901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.4182781901
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.2978196629
Short name T900
Test name
Test status
Simulation time 24343499252 ps
CPU time 22.54 seconds
Started Aug 08 06:10:19 PM PDT 24
Finished Aug 08 06:10:42 PM PDT 24
Peak memory 241632 kb
Host smart-fac827fd-5594-4566-8e50-b8dd63a40382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978196629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.2978196629
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.1537650386
Short name T86
Test name
Test status
Simulation time 7983738861 ps
CPU time 62.65 seconds
Started Aug 08 06:10:19 PM PDT 24
Finished Aug 08 06:11:22 PM PDT 24
Peak memory 249916 kb
Host smart-92229bb9-9ab1-4fb9-be95-b07ab5de116f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537650386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds
.1537650386
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/3.spi_device_intercept.2896503849
Short name T735
Test name
Test status
Simulation time 319203505 ps
CPU time 5.51 seconds
Started Aug 08 06:10:21 PM PDT 24
Finished Aug 08 06:10:27 PM PDT 24
Peak memory 225256 kb
Host smart-6ed29ac5-2324-48a1-9fe7-44f941dca827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896503849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.2896503849
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.3786916810
Short name T393
Test name
Test status
Simulation time 1184718544 ps
CPU time 14.16 seconds
Started Aug 08 06:10:23 PM PDT 24
Finished Aug 08 06:10:38 PM PDT 24
Peak memory 233420 kb
Host smart-a0b2cc49-ed13-46cf-bfff-62ed5af4ea39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786916810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.3786916810
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.3489037363
Short name T988
Test name
Test status
Simulation time 15225185 ps
CPU time 1.06 seconds
Started Aug 08 06:10:18 PM PDT 24
Finished Aug 08 06:10:19 PM PDT 24
Peak memory 217256 kb
Host smart-bac4e394-f0cd-4153-b002-e5d79a8fc51f
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489037363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.spi_device_mem_parity.3489037363
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.2994643214
Short name T984
Test name
Test status
Simulation time 691527975 ps
CPU time 2.61 seconds
Started Aug 08 06:10:21 PM PDT 24
Finished Aug 08 06:10:24 PM PDT 24
Peak memory 225252 kb
Host smart-d2e76550-4561-4be8-9db0-53937499caaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994643214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.2994643214
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.1559081015
Short name T637
Test name
Test status
Simulation time 887325326 ps
CPU time 6.67 seconds
Started Aug 08 06:10:20 PM PDT 24
Finished Aug 08 06:10:27 PM PDT 24
Peak memory 241284 kb
Host smart-68d11457-0173-434b-8bad-c848dd5f1273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559081015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.1559081015
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.3260700963
Short name T858
Test name
Test status
Simulation time 4140531979 ps
CPU time 6.93 seconds
Started Aug 08 06:10:17 PM PDT 24
Finished Aug 08 06:10:24 PM PDT 24
Peak memory 223756 kb
Host smart-1298c99e-eca5-43c6-a25c-9e1587eb3590
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3260700963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.3260700963
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.3166960178
Short name T65
Test name
Test status
Simulation time 84592003 ps
CPU time 0.96 seconds
Started Aug 08 06:10:20 PM PDT 24
Finished Aug 08 06:10:21 PM PDT 24
Peak memory 235960 kb
Host smart-e660b2c1-0d66-41ac-a658-628b0575ad6f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166960178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.3166960178
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.1364658095
Short name T212
Test name
Test status
Simulation time 9482598920 ps
CPU time 100.25 seconds
Started Aug 08 06:10:17 PM PDT 24
Finished Aug 08 06:11:58 PM PDT 24
Peak memory 271628 kb
Host smart-3c3ed693-9e0b-4d14-b0f9-36571fb8e0eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364658095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.1364658095
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.469282531
Short name T612
Test name
Test status
Simulation time 1251050184 ps
CPU time 3.76 seconds
Started Aug 08 06:10:19 PM PDT 24
Finished Aug 08 06:10:23 PM PDT 24
Peak memory 217028 kb
Host smart-be8365dc-7491-4ed0-ba2f-b5df53c41e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469282531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.469282531
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.371699068
Short name T840
Test name
Test status
Simulation time 3872834484 ps
CPU time 12.54 seconds
Started Aug 08 06:10:18 PM PDT 24
Finished Aug 08 06:10:30 PM PDT 24
Peak memory 217004 kb
Host smart-c9c8fdca-cc12-439d-9ffc-759a48d63734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371699068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.371699068
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.3783140481
Short name T341
Test name
Test status
Simulation time 12378367 ps
CPU time 0.69 seconds
Started Aug 08 06:10:22 PM PDT 24
Finished Aug 08 06:10:22 PM PDT 24
Peak memory 206196 kb
Host smart-4af54caf-7a61-4905-b3d3-f88dec4b26e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783140481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.3783140481
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.2253333768
Short name T455
Test name
Test status
Simulation time 170026921 ps
CPU time 0.94 seconds
Started Aug 08 06:10:17 PM PDT 24
Finished Aug 08 06:10:18 PM PDT 24
Peak memory 207776 kb
Host smart-62911ebf-d117-4d62-a86a-070c059d422f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253333768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.2253333768
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.2330611424
Short name T757
Test name
Test status
Simulation time 201518181 ps
CPU time 5.08 seconds
Started Aug 08 06:10:18 PM PDT 24
Finished Aug 08 06:10:23 PM PDT 24
Peak memory 233360 kb
Host smart-b5256641-2c88-466f-b14f-ab0b48659f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330611424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.2330611424
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.4273255945
Short name T318
Test name
Test status
Simulation time 39012239 ps
CPU time 0.73 seconds
Started Aug 08 06:11:59 PM PDT 24
Finished Aug 08 06:12:00 PM PDT 24
Peak memory 205284 kb
Host smart-106e2edd-7dc0-4a77-877a-640b341ccca0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273255945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
4273255945
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.1644352467
Short name T151
Test name
Test status
Simulation time 436915651 ps
CPU time 5.37 seconds
Started Aug 08 06:11:57 PM PDT 24
Finished Aug 08 06:12:03 PM PDT 24
Peak memory 233388 kb
Host smart-818b4509-e85f-4de0-b4a7-5e956fd40c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644352467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.1644352467
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.1404245290
Short name T827
Test name
Test status
Simulation time 57491599 ps
CPU time 0.78 seconds
Started Aug 08 06:11:48 PM PDT 24
Finished Aug 08 06:11:49 PM PDT 24
Peak memory 207064 kb
Host smart-35132c4b-6b92-437f-94b0-dfbca5319428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404245290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.1404245290
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.3331704005
Short name T181
Test name
Test status
Simulation time 18208623029 ps
CPU time 54.9 seconds
Started Aug 08 06:11:58 PM PDT 24
Finished Aug 08 06:12:53 PM PDT 24
Peak memory 257180 kb
Host smart-397cd9f8-ee46-4c6e-907b-145c8f4905d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331704005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.3331704005
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.376624434
Short name T681
Test name
Test status
Simulation time 1952392457 ps
CPU time 21.61 seconds
Started Aug 08 06:11:57 PM PDT 24
Finished Aug 08 06:12:19 PM PDT 24
Peak memory 254168 kb
Host smart-9fd258dd-9b3e-436f-ab66-d1e7d2b3ac56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376624434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.376624434
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.845971252
Short name T633
Test name
Test status
Simulation time 132955360526 ps
CPU time 197.23 seconds
Started Aug 08 06:11:58 PM PDT 24
Finished Aug 08 06:15:15 PM PDT 24
Peak memory 268576 kb
Host smart-dc5687e3-84e8-4ba3-b3d2-7a77c73fbf96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845971252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idle
.845971252
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.535467077
Short name T753
Test name
Test status
Simulation time 862273130 ps
CPU time 20.89 seconds
Started Aug 08 06:12:02 PM PDT 24
Finished Aug 08 06:12:22 PM PDT 24
Peak memory 239324 kb
Host smart-19b06758-2fb4-44e7-aeab-9a9108d3a1e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535467077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmds
.535467077
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/30.spi_device_intercept.1209767755
Short name T1028
Test name
Test status
Simulation time 1882259437 ps
CPU time 17.37 seconds
Started Aug 08 06:11:51 PM PDT 24
Finished Aug 08 06:12:09 PM PDT 24
Peak memory 229736 kb
Host smart-2742655e-e68f-490f-b446-6a2713b91c02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209767755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.1209767755
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.398813795
Short name T731
Test name
Test status
Simulation time 808882378 ps
CPU time 4.69 seconds
Started Aug 08 06:11:52 PM PDT 24
Finished Aug 08 06:11:57 PM PDT 24
Peak memory 233412 kb
Host smart-a58be64e-6929-41ae-99fb-d52d832f5a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398813795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.398813795
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.1652806222
Short name T529
Test name
Test status
Simulation time 1529980903 ps
CPU time 2.91 seconds
Started Aug 08 06:11:48 PM PDT 24
Finished Aug 08 06:11:51 PM PDT 24
Peak memory 233404 kb
Host smart-b230e2e6-1e7b-40b4-88d0-667f24f5b78b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652806222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.1652806222
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.1014942197
Short name T28
Test name
Test status
Simulation time 2999156622 ps
CPU time 11.41 seconds
Started Aug 08 06:11:46 PM PDT 24
Finished Aug 08 06:11:57 PM PDT 24
Peak memory 233420 kb
Host smart-2c7eeb09-5bbd-4763-866f-3af3bd7a8105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014942197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.1014942197
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.1037689216
Short name T357
Test name
Test status
Simulation time 1686339556 ps
CPU time 3.92 seconds
Started Aug 08 06:11:54 PM PDT 24
Finished Aug 08 06:11:58 PM PDT 24
Peak memory 223036 kb
Host smart-15c3ce0b-dcec-45b8-84fc-1166aaeec9be
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1037689216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.1037689216
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.380540611
Short name T1026
Test name
Test status
Simulation time 2359400376 ps
CPU time 15.71 seconds
Started Aug 08 06:11:46 PM PDT 24
Finished Aug 08 06:12:01 PM PDT 24
Peak memory 217048 kb
Host smart-58d4d4ff-838f-45fd-aafe-70107c6d35ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380540611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.380540611
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.205756927
Short name T996
Test name
Test status
Simulation time 1176547966 ps
CPU time 6.07 seconds
Started Aug 08 06:11:46 PM PDT 24
Finished Aug 08 06:11:52 PM PDT 24
Peak memory 216964 kb
Host smart-ca62be96-4b83-4720-bde1-f8d0ebd9e30a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205756927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.205756927
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.3456013386
Short name T334
Test name
Test status
Simulation time 41688844 ps
CPU time 1.16 seconds
Started Aug 08 06:11:46 PM PDT 24
Finished Aug 08 06:11:47 PM PDT 24
Peak memory 208352 kb
Host smart-7258eaba-f9f7-4921-bb0e-8ce027edbdca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456013386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.3456013386
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.2743157561
Short name T647
Test name
Test status
Simulation time 128797325 ps
CPU time 0.84 seconds
Started Aug 08 06:11:53 PM PDT 24
Finished Aug 08 06:11:54 PM PDT 24
Peak memory 206544 kb
Host smart-4556142c-de49-4481-986d-7959f3ace918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743157561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.2743157561
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.3840972533
Short name T750
Test name
Test status
Simulation time 1864292776 ps
CPU time 3.43 seconds
Started Aug 08 06:11:56 PM PDT 24
Finished Aug 08 06:11:59 PM PDT 24
Peak memory 225220 kb
Host smart-1078cfa9-6e9d-46f2-83b2-2f5ee26ce3fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840972533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.3840972533
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.1493569307
Short name T746
Test name
Test status
Simulation time 15698667 ps
CPU time 0.75 seconds
Started Aug 08 06:12:01 PM PDT 24
Finished Aug 08 06:12:02 PM PDT 24
Peak memory 206260 kb
Host smart-59e60d3a-881a-4021-b80d-1488e5e97266
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493569307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
1493569307
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.3969183451
Short name T933
Test name
Test status
Simulation time 4330507528 ps
CPU time 33.69 seconds
Started Aug 08 06:11:56 PM PDT 24
Finished Aug 08 06:12:30 PM PDT 24
Peak memory 233440 kb
Host smart-82437e55-fe39-41f6-b073-af63f7920ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969183451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.3969183451
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.1095254237
Short name T322
Test name
Test status
Simulation time 26652473 ps
CPU time 0.72 seconds
Started Aug 08 06:11:54 PM PDT 24
Finished Aug 08 06:11:55 PM PDT 24
Peak memory 206332 kb
Host smart-abf948d0-bd8e-4982-a412-fce9e25a8f87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095254237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.1095254237
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.109463209
Short name T872
Test name
Test status
Simulation time 1360913463 ps
CPU time 32.81 seconds
Started Aug 08 06:11:59 PM PDT 24
Finished Aug 08 06:12:32 PM PDT 24
Peak memory 251552 kb
Host smart-1209a844-91aa-4a9e-9087-bf414142a962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109463209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.109463209
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.3784532617
Short name T512
Test name
Test status
Simulation time 2691569521 ps
CPU time 43.22 seconds
Started Aug 08 06:11:53 PM PDT 24
Finished Aug 08 06:12:37 PM PDT 24
Peak memory 241756 kb
Host smart-eecb3050-f8a3-4c30-a9ee-e841f72b7deb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784532617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.3784532617
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.1787375129
Short name T278
Test name
Test status
Simulation time 306653237842 ps
CPU time 667.29 seconds
Started Aug 08 06:11:57 PM PDT 24
Finished Aug 08 06:23:05 PM PDT 24
Peak memory 269384 kb
Host smart-152311da-cdaa-4537-8f93-d732aff632eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787375129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.1787375129
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.2913291205
Short name T421
Test name
Test status
Simulation time 39412905 ps
CPU time 2.9 seconds
Started Aug 08 06:11:57 PM PDT 24
Finished Aug 08 06:12:00 PM PDT 24
Peak memory 225304 kb
Host smart-3cf3ccbf-1b8d-4cc4-86e5-80a7a7ae3bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913291205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.2913291205
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.2597701870
Short name T674
Test name
Test status
Simulation time 435330987 ps
CPU time 3.79 seconds
Started Aug 08 06:11:57 PM PDT 24
Finished Aug 08 06:12:01 PM PDT 24
Peak memory 234616 kb
Host smart-4e0877ed-a528-4daf-9901-5ad4a7c3e64b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597701870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmd
s.2597701870
Directory /workspace/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/31.spi_device_intercept.2016583906
Short name T327
Test name
Test status
Simulation time 316550110 ps
CPU time 3.88 seconds
Started Aug 08 06:12:01 PM PDT 24
Finished Aug 08 06:12:05 PM PDT 24
Peak memory 225208 kb
Host smart-8dc054d1-3a3d-485a-aa9e-35738ff7a9a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016583906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.2016583906
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.1128522370
Short name T375
Test name
Test status
Simulation time 19645356151 ps
CPU time 35.52 seconds
Started Aug 08 06:11:57 PM PDT 24
Finished Aug 08 06:12:32 PM PDT 24
Peak memory 225236 kb
Host smart-6e7b2341-2684-47bb-91ea-880370d9bfd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128522370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.1128522370
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.1028877390
Short name T480
Test name
Test status
Simulation time 3618646212 ps
CPU time 6.1 seconds
Started Aug 08 06:11:55 PM PDT 24
Finished Aug 08 06:12:01 PM PDT 24
Peak memory 225256 kb
Host smart-0fceace1-76c9-4fad-85f5-c8a55098f701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028877390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.1028877390
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.1504825462
Short name T387
Test name
Test status
Simulation time 1475157757 ps
CPU time 5.62 seconds
Started Aug 08 06:11:56 PM PDT 24
Finished Aug 08 06:12:02 PM PDT 24
Peak memory 219592 kb
Host smart-b154e04b-d0c6-4d98-b190-955bcf21adb7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1504825462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.1504825462
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.1448718847
Short name T652
Test name
Test status
Simulation time 41614826 ps
CPU time 1.01 seconds
Started Aug 08 06:11:56 PM PDT 24
Finished Aug 08 06:11:57 PM PDT 24
Peak memory 208300 kb
Host smart-82d28788-f11d-49f9-b475-f0549535fbb7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448718847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.1448718847
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.2823199141
Short name T697
Test name
Test status
Simulation time 6182005112 ps
CPU time 22.34 seconds
Started Aug 08 06:11:58 PM PDT 24
Finished Aug 08 06:12:20 PM PDT 24
Peak memory 220840 kb
Host smart-4888e606-d442-47db-9395-abb0941cd0ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823199141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.2823199141
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.750316942
Short name T477
Test name
Test status
Simulation time 410767602 ps
CPU time 1.94 seconds
Started Aug 08 06:12:01 PM PDT 24
Finished Aug 08 06:12:03 PM PDT 24
Peak memory 208588 kb
Host smart-e387cf40-c481-47e8-9e22-da9e819db1a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750316942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.750316942
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.3586188067
Short name T543
Test name
Test status
Simulation time 19158400 ps
CPU time 1.14 seconds
Started Aug 08 06:11:57 PM PDT 24
Finished Aug 08 06:11:58 PM PDT 24
Peak memory 208564 kb
Host smart-b9fa9b3e-4c05-4ad2-a8a5-c41b9b070cc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586188067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.3586188067
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.1969841504
Short name T909
Test name
Test status
Simulation time 50046603 ps
CPU time 0.81 seconds
Started Aug 08 06:11:54 PM PDT 24
Finished Aug 08 06:11:55 PM PDT 24
Peak memory 206476 kb
Host smart-679e969b-d7fc-4107-abb8-98b458103498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969841504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.1969841504
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.967455045
Short name T362
Test name
Test status
Simulation time 21185655677 ps
CPU time 19.63 seconds
Started Aug 08 06:11:58 PM PDT 24
Finished Aug 08 06:12:18 PM PDT 24
Peak memory 237172 kb
Host smart-50bacf33-494b-4f3d-9072-d70e8f069441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967455045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.967455045
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.2043309721
Short name T474
Test name
Test status
Simulation time 14928568 ps
CPU time 0.71 seconds
Started Aug 08 06:11:59 PM PDT 24
Finished Aug 08 06:12:00 PM PDT 24
Peak memory 205952 kb
Host smart-a774a113-98c6-40b5-9215-a5bae1a54a38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043309721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
2043309721
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.2751930587
Short name T959
Test name
Test status
Simulation time 877577976 ps
CPU time 6.63 seconds
Started Aug 08 06:11:55 PM PDT 24
Finished Aug 08 06:12:02 PM PDT 24
Peak memory 233432 kb
Host smart-324cad6c-6efa-4588-a352-91b61e9861f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751930587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.2751930587
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.2464372477
Short name T338
Test name
Test status
Simulation time 73516175 ps
CPU time 0.83 seconds
Started Aug 08 06:11:58 PM PDT 24
Finished Aug 08 06:11:59 PM PDT 24
Peak memory 207004 kb
Host smart-4571fe49-0816-4ea8-a9d3-a31fef6c9ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464372477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.2464372477
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.1139084192
Short name T520
Test name
Test status
Simulation time 58337266464 ps
CPU time 367.34 seconds
Started Aug 08 06:11:55 PM PDT 24
Finished Aug 08 06:18:03 PM PDT 24
Peak memory 252104 kb
Host smart-72221aa2-2bb7-440a-a30a-9990cbf85624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139084192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.1139084192
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.1506322208
Short name T592
Test name
Test status
Simulation time 3653561243 ps
CPU time 22.83 seconds
Started Aug 08 06:11:56 PM PDT 24
Finished Aug 08 06:12:19 PM PDT 24
Peak memory 225332 kb
Host smart-cf0322d0-719e-4aeb-acfb-0f8ca069d73f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506322208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.1506322208
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.1419329551
Short name T469
Test name
Test status
Simulation time 3390265693 ps
CPU time 12.19 seconds
Started Aug 08 06:11:57 PM PDT 24
Finished Aug 08 06:12:09 PM PDT 24
Peak memory 225264 kb
Host smart-22898f8f-a512-4643-b579-4dba951f97fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419329551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.1419329551
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.113614076
Short name T173
Test name
Test status
Simulation time 43040284240 ps
CPU time 220.9 seconds
Started Aug 08 06:11:56 PM PDT 24
Finished Aug 08 06:15:37 PM PDT 24
Peak memory 266128 kb
Host smart-3b4315b7-e652-4ea9-a17e-fb1b0139d78f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113614076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmds
.113614076
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/32.spi_device_intercept.2946374480
Short name T230
Test name
Test status
Simulation time 1598107648 ps
CPU time 10.05 seconds
Started Aug 08 06:11:56 PM PDT 24
Finished Aug 08 06:12:06 PM PDT 24
Peak memory 225248 kb
Host smart-e3f07c4b-5646-4896-b190-2c8f27fa6942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946374480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.2946374480
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.558125988
Short name T945
Test name
Test status
Simulation time 1319703494 ps
CPU time 6.87 seconds
Started Aug 08 06:12:01 PM PDT 24
Finished Aug 08 06:12:08 PM PDT 24
Peak memory 225200 kb
Host smart-3e5b8cf6-9c94-4c92-a8bf-7726c60f6a10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558125988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.558125988
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.3068781424
Short name T250
Test name
Test status
Simulation time 579395512 ps
CPU time 5.89 seconds
Started Aug 08 06:11:57 PM PDT 24
Finished Aug 08 06:12:03 PM PDT 24
Peak memory 235232 kb
Host smart-6a340d10-b949-4898-95b6-56e310979589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068781424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.3068781424
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.2541046398
Short name T614
Test name
Test status
Simulation time 1116265569 ps
CPU time 7.15 seconds
Started Aug 08 06:11:56 PM PDT 24
Finished Aug 08 06:12:04 PM PDT 24
Peak memory 233480 kb
Host smart-ac6bde0f-1991-4b88-80a7-ebc736f3491a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541046398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.2541046398
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.2745106029
Short name T40
Test name
Test status
Simulation time 410563620 ps
CPU time 3.36 seconds
Started Aug 08 06:12:05 PM PDT 24
Finished Aug 08 06:12:08 PM PDT 24
Peak memory 222960 kb
Host smart-fece4888-2f1d-48b7-b2f5-15db790fb3be
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2745106029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.2745106029
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.3331285589
Short name T914
Test name
Test status
Simulation time 15955015933 ps
CPU time 238.95 seconds
Started Aug 08 06:11:57 PM PDT 24
Finished Aug 08 06:15:56 PM PDT 24
Peak memory 256652 kb
Host smart-088ed7d4-07a9-44a8-a30c-3b7a06873b77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331285589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.3331285589
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.462798318
Short name T907
Test name
Test status
Simulation time 1496061935 ps
CPU time 6.45 seconds
Started Aug 08 06:11:59 PM PDT 24
Finished Aug 08 06:12:05 PM PDT 24
Peak memory 219856 kb
Host smart-89233952-809b-4bbb-b15f-2f7750050d0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462798318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.462798318
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.3777963133
Short name T347
Test name
Test status
Simulation time 10256934 ps
CPU time 0.73 seconds
Started Aug 08 06:12:01 PM PDT 24
Finished Aug 08 06:12:02 PM PDT 24
Peak memory 206164 kb
Host smart-6f395ff2-3aaf-4c17-9468-b0632e88c440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777963133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.3777963133
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.3525704208
Short name T632
Test name
Test status
Simulation time 61756066 ps
CPU time 1.54 seconds
Started Aug 08 06:11:57 PM PDT 24
Finished Aug 08 06:11:58 PM PDT 24
Peak memory 217012 kb
Host smart-e7e63795-96ba-4f98-8c7e-b76ce8522f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525704208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.3525704208
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.1411879064
Short name T353
Test name
Test status
Simulation time 14506540 ps
CPU time 0.75 seconds
Started Aug 08 06:11:55 PM PDT 24
Finished Aug 08 06:11:56 PM PDT 24
Peak memory 206556 kb
Host smart-8b1766f9-d624-4344-a566-547add272fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411879064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.1411879064
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.716162440
Short name T896
Test name
Test status
Simulation time 13338285540 ps
CPU time 10.39 seconds
Started Aug 08 06:12:01 PM PDT 24
Finished Aug 08 06:12:12 PM PDT 24
Peak memory 240128 kb
Host smart-a6f13b00-8c49-44ed-a434-efc7ea3d4de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716162440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.716162440
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.32197754
Short name T606
Test name
Test status
Simulation time 39130335 ps
CPU time 0.7 seconds
Started Aug 08 06:12:09 PM PDT 24
Finished Aug 08 06:12:10 PM PDT 24
Peak memory 205888 kb
Host smart-de7677bd-c843-4961-9150-18a003165ae3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32197754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.32197754
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.70204755
Short name T178
Test name
Test status
Simulation time 1868994572 ps
CPU time 7.12 seconds
Started Aug 08 06:12:08 PM PDT 24
Finished Aug 08 06:12:16 PM PDT 24
Peak memory 225348 kb
Host smart-807d9430-3d49-4aad-bff5-fe34b494a6b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70204755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.70204755
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.441801036
Short name T317
Test name
Test status
Simulation time 55145746 ps
CPU time 0.78 seconds
Started Aug 08 06:11:57 PM PDT 24
Finished Aug 08 06:11:58 PM PDT 24
Peak memory 207076 kb
Host smart-d73405a4-98f0-4eac-a1d1-9b92b635b62e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441801036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.441801036
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.250638525
Short name T189
Test name
Test status
Simulation time 65843971935 ps
CPU time 489.16 seconds
Started Aug 08 06:12:15 PM PDT 24
Finished Aug 08 06:20:25 PM PDT 24
Peak memory 266796 kb
Host smart-66ae6c39-aafe-4e0a-a7f4-984f566456da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250638525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.250638525
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.1598575696
Short name T621
Test name
Test status
Simulation time 25345024442 ps
CPU time 280.57 seconds
Started Aug 08 06:12:10 PM PDT 24
Finished Aug 08 06:16:51 PM PDT 24
Peak memory 268328 kb
Host smart-fc0c32fe-417d-4be8-91f7-42f1b40cb55d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598575696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.1598575696
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.1313125482
Short name T986
Test name
Test status
Simulation time 3971968194 ps
CPU time 105.11 seconds
Started Aug 08 06:12:13 PM PDT 24
Finished Aug 08 06:13:58 PM PDT 24
Peak memory 266376 kb
Host smart-0f7b3a1f-8584-46a1-afe0-47507638bc3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313125482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.1313125482
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.1711872072
Short name T7
Test name
Test status
Simulation time 1689695364 ps
CPU time 3.5 seconds
Started Aug 08 06:12:08 PM PDT 24
Finished Aug 08 06:12:12 PM PDT 24
Peak memory 225272 kb
Host smart-55555cc7-5007-4601-b03b-5aeacfa7289f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711872072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.1711872072
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.635047508
Short name T38
Test name
Test status
Simulation time 23043059374 ps
CPU time 41.11 seconds
Started Aug 08 06:12:12 PM PDT 24
Finished Aug 08 06:12:53 PM PDT 24
Peak memory 233684 kb
Host smart-d378b403-c07c-479c-86bc-7fe9bd5ca869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635047508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmds
.635047508
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/33.spi_device_intercept.1627522262
Short name T244
Test name
Test status
Simulation time 728859910 ps
CPU time 4.59 seconds
Started Aug 08 06:12:08 PM PDT 24
Finished Aug 08 06:12:13 PM PDT 24
Peak memory 233348 kb
Host smart-2764351a-3873-481c-821a-63cf9e24cd92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627522262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.1627522262
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.82035667
Short name T695
Test name
Test status
Simulation time 8117821227 ps
CPU time 53.66 seconds
Started Aug 08 06:12:13 PM PDT 24
Finished Aug 08 06:13:07 PM PDT 24
Peak memory 225164 kb
Host smart-02d3b4e8-c468-44f3-aa1b-7b50fe353dc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82035667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.82035667
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.2927036777
Short name T688
Test name
Test status
Simulation time 12727744277 ps
CPU time 13.56 seconds
Started Aug 08 06:12:10 PM PDT 24
Finished Aug 08 06:12:24 PM PDT 24
Peak memory 233504 kb
Host smart-e071eae0-08d0-4f40-8227-9d08695ea71d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927036777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.2927036777
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.2476801079
Short name T234
Test name
Test status
Simulation time 222625049 ps
CPU time 2.98 seconds
Started Aug 08 06:12:10 PM PDT 24
Finished Aug 08 06:12:13 PM PDT 24
Peak memory 225156 kb
Host smart-7db8a263-c0ee-4b6e-b8e9-02209e39b93f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476801079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.2476801079
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.1462326222
Short name T906
Test name
Test status
Simulation time 10834974200 ps
CPU time 13.95 seconds
Started Aug 08 06:12:08 PM PDT 24
Finished Aug 08 06:12:22 PM PDT 24
Peak memory 223676 kb
Host smart-5c112620-a669-4ac8-aa44-c0bcd7b9e1d4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1462326222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.1462326222
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.628773955
Short name T50
Test name
Test status
Simulation time 7883638729 ps
CPU time 165.31 seconds
Started Aug 08 06:12:09 PM PDT 24
Finished Aug 08 06:14:54 PM PDT 24
Peak memory 270124 kb
Host smart-35ca210f-e6ef-412a-857f-f78be94315e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628773955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stres
s_all.628773955
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.2438674707
Short name T630
Test name
Test status
Simulation time 8878866714 ps
CPU time 45.71 seconds
Started Aug 08 06:11:58 PM PDT 24
Finished Aug 08 06:12:44 PM PDT 24
Peak memory 216968 kb
Host smart-19a05aaa-ddd1-4c87-91bb-2158a69d6712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438674707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.2438674707
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.568599322
Short name T1021
Test name
Test status
Simulation time 88833496916 ps
CPU time 16.71 seconds
Started Aug 08 06:12:01 PM PDT 24
Finished Aug 08 06:12:17 PM PDT 24
Peak memory 217096 kb
Host smart-acac8cfd-c622-4111-af39-305046fd6801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568599322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.568599322
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.968836363
Short name T656
Test name
Test status
Simulation time 263878988 ps
CPU time 1.27 seconds
Started Aug 08 06:12:11 PM PDT 24
Finished Aug 08 06:12:12 PM PDT 24
Peak memory 208548 kb
Host smart-a1c60fee-9b34-4c9a-a5b3-afc85a290088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968836363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.968836363
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.3979335977
Short name T538
Test name
Test status
Simulation time 21316008 ps
CPU time 0.71 seconds
Started Aug 08 06:11:55 PM PDT 24
Finished Aug 08 06:11:56 PM PDT 24
Peak memory 206112 kb
Host smart-bdfe6e03-5ae9-4a6c-8bb8-0a42a04000ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979335977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.3979335977
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.1411627765
Short name T809
Test name
Test status
Simulation time 49660001 ps
CPU time 2.57 seconds
Started Aug 08 06:12:08 PM PDT 24
Finished Aug 08 06:12:11 PM PDT 24
Peak memory 224872 kb
Host smart-53064a00-0c79-421d-8dd4-2e94471bc3f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411627765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.1411627765
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.3553078359
Short name T472
Test name
Test status
Simulation time 46283851 ps
CPU time 0.74 seconds
Started Aug 08 06:12:14 PM PDT 24
Finished Aug 08 06:12:14 PM PDT 24
Peak memory 205276 kb
Host smart-455222d2-dc20-47e6-a75c-97eb9de067a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553078359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
3553078359
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.2274867494
Short name T587
Test name
Test status
Simulation time 676459743 ps
CPU time 7.53 seconds
Started Aug 08 06:12:10 PM PDT 24
Finished Aug 08 06:12:17 PM PDT 24
Peak memory 225236 kb
Host smart-7d3216aa-e856-442f-a897-d506029553f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274867494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.2274867494
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.3768508352
Short name T135
Test name
Test status
Simulation time 20620486 ps
CPU time 0.79 seconds
Started Aug 08 06:12:08 PM PDT 24
Finished Aug 08 06:12:09 PM PDT 24
Peak memory 207424 kb
Host smart-a03e1d6e-29e1-4fc1-b0e9-4af40533b9a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768508352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.3768508352
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.2402704890
Short name T185
Test name
Test status
Simulation time 18605379107 ps
CPU time 69.6 seconds
Started Aug 08 06:12:10 PM PDT 24
Finished Aug 08 06:13:20 PM PDT 24
Peak memory 249892 kb
Host smart-414cb873-7a6d-4f12-a1c0-3486f379a989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402704890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.2402704890
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.1388654548
Short name T887
Test name
Test status
Simulation time 120534336574 ps
CPU time 294.69 seconds
Started Aug 08 06:12:09 PM PDT 24
Finished Aug 08 06:17:04 PM PDT 24
Peak memory 257960 kb
Host smart-9db23921-bfd4-4325-8271-0a922af36d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388654548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.1388654548
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.1258866347
Short name T666
Test name
Test status
Simulation time 157638166960 ps
CPU time 233.32 seconds
Started Aug 08 06:12:11 PM PDT 24
Finished Aug 08 06:16:05 PM PDT 24
Peak memory 249976 kb
Host smart-1897883c-8354-4302-a7e8-0cbd7b1fe8e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258866347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.1258866347
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.1999216314
Short name T144
Test name
Test status
Simulation time 299508181 ps
CPU time 7.6 seconds
Started Aug 08 06:12:09 PM PDT 24
Finished Aug 08 06:12:17 PM PDT 24
Peak memory 225256 kb
Host smart-56e7e753-d985-46da-9f05-c6eeccd3448f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999216314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.1999216314
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.4151564159
Short name T61
Test name
Test status
Simulation time 23780104875 ps
CPU time 46.34 seconds
Started Aug 08 06:12:11 PM PDT 24
Finished Aug 08 06:12:57 PM PDT 24
Peak memory 238364 kb
Host smart-fb7cf017-b9c5-488a-b961-eb94014ff37f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151564159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmd
s.4151564159
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/34.spi_device_intercept.4061194763
Short name T728
Test name
Test status
Simulation time 63394137 ps
CPU time 1.95 seconds
Started Aug 08 06:12:10 PM PDT 24
Finished Aug 08 06:12:13 PM PDT 24
Peak memory 225280 kb
Host smart-6a4b2ea1-523d-44c9-af76-b59c354e1eaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061194763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.4061194763
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.2350411872
Short name T517
Test name
Test status
Simulation time 264123021 ps
CPU time 3.16 seconds
Started Aug 08 06:12:11 PM PDT 24
Finished Aug 08 06:12:15 PM PDT 24
Peak memory 233468 kb
Host smart-c64fcac3-a555-4a7c-b7ba-1a7a7cb9e32f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350411872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.2350411872
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.2223738092
Short name T962
Test name
Test status
Simulation time 763065165 ps
CPU time 7.71 seconds
Started Aug 08 06:12:08 PM PDT 24
Finished Aug 08 06:12:16 PM PDT 24
Peak memory 233448 kb
Host smart-e71cacf0-76c1-4288-8cdd-2bcfb546e86c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223738092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.2223738092
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.2065279350
Short name T501
Test name
Test status
Simulation time 11284701563 ps
CPU time 5.66 seconds
Started Aug 08 06:12:13 PM PDT 24
Finished Aug 08 06:12:19 PM PDT 24
Peak memory 225268 kb
Host smart-ad2ee0de-cd91-4c1d-b7ea-3670cf169180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065279350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.2065279350
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.77309682
Short name T1001
Test name
Test status
Simulation time 544104985 ps
CPU time 8.37 seconds
Started Aug 08 06:12:11 PM PDT 24
Finished Aug 08 06:12:19 PM PDT 24
Peak memory 223768 kb
Host smart-ee392606-7f93-43a3-9fbf-fb5c8b639bfe
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=77309682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_direc
t.77309682
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.2348393482
Short name T719
Test name
Test status
Simulation time 1866497692 ps
CPU time 12.49 seconds
Started Aug 08 06:12:11 PM PDT 24
Finished Aug 08 06:12:24 PM PDT 24
Peak memory 217040 kb
Host smart-f53c72d5-c347-4ff3-8fac-7af7179427c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348393482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.2348393482
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.2587776400
Short name T499
Test name
Test status
Simulation time 6181287062 ps
CPU time 5.68 seconds
Started Aug 08 06:12:09 PM PDT 24
Finished Aug 08 06:12:15 PM PDT 24
Peak memory 216976 kb
Host smart-48e19b54-02fc-4231-883c-bb788dc43fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587776400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.2587776400
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.736569636
Short name T492
Test name
Test status
Simulation time 488880085 ps
CPU time 9.88 seconds
Started Aug 08 06:12:09 PM PDT 24
Finished Aug 08 06:12:19 PM PDT 24
Peak memory 217000 kb
Host smart-30454f3c-2ccd-4368-a782-2da8497a6cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736569636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.736569636
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.3509079235
Short name T622
Test name
Test status
Simulation time 79612393 ps
CPU time 0.72 seconds
Started Aug 08 06:12:09 PM PDT 24
Finished Aug 08 06:12:09 PM PDT 24
Peak memory 206588 kb
Host smart-f21f8500-e8b1-4c39-ac49-73e002ec3651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509079235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.3509079235
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.1324990194
Short name T236
Test name
Test status
Simulation time 261001917 ps
CPU time 6.22 seconds
Started Aug 08 06:12:11 PM PDT 24
Finished Aug 08 06:12:18 PM PDT 24
Peak memory 233520 kb
Host smart-615cb66a-c630-4927-a0ee-753070d0f708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324990194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.1324990194
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.3542181167
Short name T934
Test name
Test status
Simulation time 13250494 ps
CPU time 0.71 seconds
Started Aug 08 06:12:10 PM PDT 24
Finished Aug 08 06:12:11 PM PDT 24
Peak memory 206196 kb
Host smart-28bb6a3b-d062-442d-a5b0-02ee79d942aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542181167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
3542181167
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.282138751
Short name T882
Test name
Test status
Simulation time 1429265386 ps
CPU time 5.06 seconds
Started Aug 08 06:12:11 PM PDT 24
Finished Aug 08 06:12:16 PM PDT 24
Peak memory 225228 kb
Host smart-7948e777-e5f9-438b-9e5b-38db0a254461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282138751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.282138751
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.2433542733
Short name T930
Test name
Test status
Simulation time 35845205 ps
CPU time 0.76 seconds
Started Aug 08 06:12:11 PM PDT 24
Finished Aug 08 06:12:12 PM PDT 24
Peak memory 207464 kb
Host smart-ff7f2dcb-6bfc-4a9a-b487-5f269e10a0b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433542733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.2433542733
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.1000168599
Short name T725
Test name
Test status
Simulation time 15857127275 ps
CPU time 56.64 seconds
Started Aug 08 06:12:10 PM PDT 24
Finished Aug 08 06:13:07 PM PDT 24
Peak memory 251736 kb
Host smart-8d1a8b0c-ed15-49fa-b65e-9d87b68e23e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000168599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.1000168599
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.2266763297
Short name T610
Test name
Test status
Simulation time 909344641 ps
CPU time 9.91 seconds
Started Aug 08 06:12:12 PM PDT 24
Finished Aug 08 06:12:22 PM PDT 24
Peak memory 225224 kb
Host smart-43edbcde-0369-47db-9eaa-becf79087c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266763297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.2266763297
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.4007401548
Short name T749
Test name
Test status
Simulation time 3505037766 ps
CPU time 50.56 seconds
Started Aug 08 06:12:13 PM PDT 24
Finished Aug 08 06:13:03 PM PDT 24
Peak memory 254508 kb
Host smart-e08685c0-ecf7-42de-a0e8-e7ba87b8032b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007401548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.4007401548
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.136654470
Short name T299
Test name
Test status
Simulation time 635938876 ps
CPU time 6.54 seconds
Started Aug 08 06:12:13 PM PDT 24
Finished Aug 08 06:12:20 PM PDT 24
Peak memory 225004 kb
Host smart-d6b6adae-35c6-41a6-8845-4d7eb72c1b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136654470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.136654470
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.2760181557
Short name T1014
Test name
Test status
Simulation time 39642407 ps
CPU time 0.79 seconds
Started Aug 08 06:12:11 PM PDT 24
Finished Aug 08 06:12:12 PM PDT 24
Peak memory 216436 kb
Host smart-9c9bda1a-fb6b-49ec-9b64-49b06b999cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760181557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmd
s.2760181557
Directory /workspace/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/35.spi_device_intercept.2324343862
Short name T243
Test name
Test status
Simulation time 914040570 ps
CPU time 5.15 seconds
Started Aug 08 06:12:07 PM PDT 24
Finished Aug 08 06:12:12 PM PDT 24
Peak memory 233452 kb
Host smart-1c10917d-9154-4d17-a8c8-b63e85e5f96f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324343862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.2324343862
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.2119897593
Short name T624
Test name
Test status
Simulation time 7993373221 ps
CPU time 70.19 seconds
Started Aug 08 06:12:11 PM PDT 24
Finished Aug 08 06:13:21 PM PDT 24
Peak memory 249632 kb
Host smart-074a081d-97ce-49eb-b5c5-28929c722fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119897593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.2119897593
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.2571527928
Short name T1023
Test name
Test status
Simulation time 73320569310 ps
CPU time 45.1 seconds
Started Aug 08 06:12:12 PM PDT 24
Finished Aug 08 06:12:57 PM PDT 24
Peak memory 233468 kb
Host smart-76ef3690-3dd2-476e-ba60-249f308dacc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571527928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.2571527928
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.665252291
Short name T897
Test name
Test status
Simulation time 4215265624 ps
CPU time 9.1 seconds
Started Aug 08 06:12:10 PM PDT 24
Finished Aug 08 06:12:19 PM PDT 24
Peak memory 232192 kb
Host smart-2188dce0-b6ea-4b25-b8ae-4b7aaee97f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665252291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.665252291
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.2982438131
Short name T381
Test name
Test status
Simulation time 1175221218 ps
CPU time 5.29 seconds
Started Aug 08 06:12:12 PM PDT 24
Finished Aug 08 06:12:17 PM PDT 24
Peak memory 223008 kb
Host smart-1cab1b23-aba3-4487-a041-ad05b9c368bf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2982438131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.2982438131
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.3704811774
Short name T345
Test name
Test status
Simulation time 1943588428 ps
CPU time 11.24 seconds
Started Aug 08 06:12:10 PM PDT 24
Finished Aug 08 06:12:22 PM PDT 24
Peak memory 217160 kb
Host smart-97718124-8258-4841-89f4-de91cf63004f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704811774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.3704811774
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.571168941
Short name T57
Test name
Test status
Simulation time 1502456760 ps
CPU time 7.55 seconds
Started Aug 08 06:12:09 PM PDT 24
Finished Aug 08 06:12:17 PM PDT 24
Peak memory 216972 kb
Host smart-17caeece-da79-4983-8d98-6dddb044557f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571168941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.571168941
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.2494443462
Short name T670
Test name
Test status
Simulation time 128268494 ps
CPU time 1 seconds
Started Aug 08 06:12:09 PM PDT 24
Finished Aug 08 06:12:11 PM PDT 24
Peak memory 207164 kb
Host smart-fe159876-f483-4f55-b5df-428333c0fa00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494443462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.2494443462
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.1736352563
Short name T797
Test name
Test status
Simulation time 76120729 ps
CPU time 0.92 seconds
Started Aug 08 06:12:11 PM PDT 24
Finished Aug 08 06:12:12 PM PDT 24
Peak memory 206560 kb
Host smart-9a41f3a9-5762-4f81-aa9b-1588b11e6c43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736352563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.1736352563
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.238576737
Short name T730
Test name
Test status
Simulation time 2027070779 ps
CPU time 8.4 seconds
Started Aug 08 06:12:09 PM PDT 24
Finished Aug 08 06:12:17 PM PDT 24
Peak memory 241632 kb
Host smart-a78bcf46-e834-483a-b418-a81493096b5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238576737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.238576737
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.4033907786
Short name T732
Test name
Test status
Simulation time 26564937 ps
CPU time 0.77 seconds
Started Aug 08 06:12:23 PM PDT 24
Finished Aug 08 06:12:23 PM PDT 24
Peak memory 205284 kb
Host smart-bd962dc0-4a50-4e3a-b99b-767b25357d64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033907786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
4033907786
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.2251298907
Short name T264
Test name
Test status
Simulation time 122407105 ps
CPU time 3.4 seconds
Started Aug 08 06:12:21 PM PDT 24
Finished Aug 08 06:12:25 PM PDT 24
Peak memory 233444 kb
Host smart-0e7fde83-e825-45ac-b5cb-fed74a5be181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251298907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.2251298907
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.1508205941
Short name T355
Test name
Test status
Simulation time 19917624 ps
CPU time 0.81 seconds
Started Aug 08 06:12:13 PM PDT 24
Finished Aug 08 06:12:14 PM PDT 24
Peak memory 207032 kb
Host smart-d74c8301-9792-4ef6-8abb-4f6f9cf06c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508205941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.1508205941
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.3292720168
Short name T3
Test name
Test status
Simulation time 33689045805 ps
CPU time 26.69 seconds
Started Aug 08 06:12:24 PM PDT 24
Finished Aug 08 06:12:51 PM PDT 24
Peak memory 225256 kb
Host smart-9b12f479-467d-4465-b108-32814c537bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292720168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.3292720168
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.1744544125
Short name T951
Test name
Test status
Simulation time 65068139348 ps
CPU time 152.55 seconds
Started Aug 08 06:12:23 PM PDT 24
Finished Aug 08 06:14:56 PM PDT 24
Peak memory 254380 kb
Host smart-7fc1883e-ea42-4ae8-81f4-712bca49f9f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744544125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.1744544125
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.2137510306
Short name T293
Test name
Test status
Simulation time 3193207229 ps
CPU time 29.41 seconds
Started Aug 08 06:12:24 PM PDT 24
Finished Aug 08 06:12:54 PM PDT 24
Peak memory 233448 kb
Host smart-52cb85dd-00f2-416a-a417-cc7ede0c70dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137510306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.2137510306
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.1402941872
Short name T1017
Test name
Test status
Simulation time 9360317217 ps
CPU time 28.88 seconds
Started Aug 08 06:12:21 PM PDT 24
Finished Aug 08 06:12:50 PM PDT 24
Peak memory 239204 kb
Host smart-2ece5fa7-b8cc-40f9-8c24-a6d36b38151e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402941872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmd
s.1402941872
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_intercept.2218125536
Short name T536
Test name
Test status
Simulation time 1844499575 ps
CPU time 6.9 seconds
Started Aug 08 06:12:12 PM PDT 24
Finished Aug 08 06:12:19 PM PDT 24
Peak memory 233420 kb
Host smart-3d37410e-f025-485f-bc2b-5c86965256c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218125536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.2218125536
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.3102234447
Short name T762
Test name
Test status
Simulation time 2041247744 ps
CPU time 9.84 seconds
Started Aug 08 06:12:12 PM PDT 24
Finished Aug 08 06:12:22 PM PDT 24
Peak memory 233448 kb
Host smart-b11eebae-6bea-4587-a6ec-b0ef7bfcdfda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102234447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.3102234447
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.1861683605
Short name T255
Test name
Test status
Simulation time 5014289196 ps
CPU time 16.79 seconds
Started Aug 08 06:12:16 PM PDT 24
Finished Aug 08 06:12:33 PM PDT 24
Peak memory 237396 kb
Host smart-79e31f18-924e-43ee-ac03-641118f0ec38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861683605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.1861683605
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.3510072827
Short name T204
Test name
Test status
Simulation time 794033393 ps
CPU time 5.69 seconds
Started Aug 08 06:12:13 PM PDT 24
Finished Aug 08 06:12:19 PM PDT 24
Peak memory 241256 kb
Host smart-0dcb7d76-2627-448b-9551-1de1c72d06ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510072827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.3510072827
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.3812350197
Short name T528
Test name
Test status
Simulation time 11126992904 ps
CPU time 14.3 seconds
Started Aug 08 06:12:22 PM PDT 24
Finished Aug 08 06:12:36 PM PDT 24
Peak memory 223828 kb
Host smart-31210aed-982a-40a5-987c-7e8a42ca41e5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3812350197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.3812350197
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.2274794569
Short name T440
Test name
Test status
Simulation time 20859580723 ps
CPU time 196.22 seconds
Started Aug 08 06:12:22 PM PDT 24
Finished Aug 08 06:15:38 PM PDT 24
Peak memory 249980 kb
Host smart-f4386b27-f2b6-474a-8b69-90eb15bbf1aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274794569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.2274794569
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.3143099922
Short name T607
Test name
Test status
Simulation time 23723847 ps
CPU time 0.71 seconds
Started Aug 08 06:12:13 PM PDT 24
Finished Aug 08 06:12:14 PM PDT 24
Peak memory 206140 kb
Host smart-a58b85b0-3be0-4d78-b3b8-1a6caeb705be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143099922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.3143099922
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.310999431
Short name T799
Test name
Test status
Simulation time 32030903611 ps
CPU time 24.79 seconds
Started Aug 08 06:12:13 PM PDT 24
Finished Aug 08 06:12:38 PM PDT 24
Peak memory 217028 kb
Host smart-24cea73a-c91a-4c81-b5fa-7257fe5b2093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310999431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.310999431
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.425186691
Short name T899
Test name
Test status
Simulation time 56591200 ps
CPU time 1.69 seconds
Started Aug 08 06:12:10 PM PDT 24
Finished Aug 08 06:12:12 PM PDT 24
Peak memory 216908 kb
Host smart-a57ce5d6-c25b-4011-b545-c773bdfe0fc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425186691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.425186691
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.3587384151
Short name T849
Test name
Test status
Simulation time 39464990 ps
CPU time 0.82 seconds
Started Aug 08 06:12:16 PM PDT 24
Finished Aug 08 06:12:17 PM PDT 24
Peak memory 206524 kb
Host smart-ba64efd4-a7fd-4a91-a611-12edf1f135a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587384151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.3587384151
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.2263338925
Short name T246
Test name
Test status
Simulation time 4823264575 ps
CPU time 18.76 seconds
Started Aug 08 06:12:12 PM PDT 24
Finished Aug 08 06:12:31 PM PDT 24
Peak memory 225300 kb
Host smart-ceff09eb-e3b1-40ac-96ee-08449788ee73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263338925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.2263338925
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.4291520948
Short name T496
Test name
Test status
Simulation time 28573116 ps
CPU time 0.69 seconds
Started Aug 08 06:12:21 PM PDT 24
Finished Aug 08 06:12:22 PM PDT 24
Peak memory 205192 kb
Host smart-ee4d7563-08de-4842-be01-c5570d5fd986
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291520948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
4291520948
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.2762129490
Short name T660
Test name
Test status
Simulation time 633276679 ps
CPU time 2.39 seconds
Started Aug 08 06:12:21 PM PDT 24
Finished Aug 08 06:12:24 PM PDT 24
Peak memory 225228 kb
Host smart-d8944b69-a878-4cde-978a-e87ae52237e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762129490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.2762129490
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.2718090583
Short name T999
Test name
Test status
Simulation time 22620643 ps
CPU time 0.78 seconds
Started Aug 08 06:12:23 PM PDT 24
Finished Aug 08 06:12:23 PM PDT 24
Peak memory 207036 kb
Host smart-579361e5-49d4-4d1c-9721-ff6e3456f818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718090583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.2718090583
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.2668739631
Short name T663
Test name
Test status
Simulation time 2695433683 ps
CPU time 22.06 seconds
Started Aug 08 06:12:24 PM PDT 24
Finished Aug 08 06:12:46 PM PDT 24
Peak memory 234960 kb
Host smart-f79cf353-deb0-47d6-8038-f5e8d40bf058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668739631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.2668739631
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.3546147878
Short name T926
Test name
Test status
Simulation time 12567406710 ps
CPU time 57.32 seconds
Started Aug 08 06:12:21 PM PDT 24
Finished Aug 08 06:13:19 PM PDT 24
Peak memory 251024 kb
Host smart-2fcc1305-891c-4b75-a5f2-24fc96a5229e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546147878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.3546147878
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.2494837770
Short name T208
Test name
Test status
Simulation time 11336356288 ps
CPU time 74.61 seconds
Started Aug 08 06:12:21 PM PDT 24
Finished Aug 08 06:13:35 PM PDT 24
Peak memory 257124 kb
Host smart-f17fec16-b470-436c-80d7-2d7234fb4f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494837770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.2494837770
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.1562246538
Short name T301
Test name
Test status
Simulation time 87294238 ps
CPU time 3.85 seconds
Started Aug 08 06:12:21 PM PDT 24
Finished Aug 08 06:12:25 PM PDT 24
Peak memory 233472 kb
Host smart-9b782873-410b-44cc-8a79-54a9144e149e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562246538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.1562246538
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.3965031138
Short name T383
Test name
Test status
Simulation time 6501427308 ps
CPU time 23.67 seconds
Started Aug 08 06:12:24 PM PDT 24
Finished Aug 08 06:12:48 PM PDT 24
Peak memory 234908 kb
Host smart-e12db1ba-1a05-40c2-b763-501b4ab64ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965031138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmd
s.3965031138
Directory /workspace/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/37.spi_device_intercept.1301483939
Short name T263
Test name
Test status
Simulation time 15511111911 ps
CPU time 10.94 seconds
Started Aug 08 06:12:23 PM PDT 24
Finished Aug 08 06:12:34 PM PDT 24
Peak memory 225272 kb
Host smart-31bb8e8d-3261-414e-b399-bcfde8e0faa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301483939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.1301483939
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.1431177320
Short name T885
Test name
Test status
Simulation time 120801472 ps
CPU time 2.19 seconds
Started Aug 08 06:12:24 PM PDT 24
Finished Aug 08 06:12:27 PM PDT 24
Peak memory 225280 kb
Host smart-00865bb4-1b30-42dc-ba51-22aec218a736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431177320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.1431177320
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.4110295888
Short name T698
Test name
Test status
Simulation time 3828053674 ps
CPU time 4.56 seconds
Started Aug 08 06:12:23 PM PDT 24
Finished Aug 08 06:12:28 PM PDT 24
Peak memory 225220 kb
Host smart-dca84a39-76da-4dee-af8d-bded2d1b242a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110295888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.4110295888
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.3484043939
Short name T514
Test name
Test status
Simulation time 42764670 ps
CPU time 2.54 seconds
Started Aug 08 06:12:21 PM PDT 24
Finished Aug 08 06:12:23 PM PDT 24
Peak memory 233416 kb
Host smart-38956f21-2c67-4657-8031-c3b97a7803fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484043939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.3484043939
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.1778265158
Short name T389
Test name
Test status
Simulation time 530243426 ps
CPU time 4.61 seconds
Started Aug 08 06:12:23 PM PDT 24
Finished Aug 08 06:12:27 PM PDT 24
Peak memory 220804 kb
Host smart-ca1eb61e-f74a-434b-bb4a-9992580ba856
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1778265158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.1778265158
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.3651380785
Short name T565
Test name
Test status
Simulation time 28279697955 ps
CPU time 181.05 seconds
Started Aug 08 06:12:23 PM PDT 24
Finished Aug 08 06:15:24 PM PDT 24
Peak memory 255096 kb
Host smart-eef6fba5-1338-4512-b96d-4bf24687a281
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651380785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.3651380785
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.1487421342
Short name T406
Test name
Test status
Simulation time 41777622 ps
CPU time 0.71 seconds
Started Aug 08 06:12:22 PM PDT 24
Finished Aug 08 06:12:23 PM PDT 24
Peak memory 206124 kb
Host smart-2bf39e06-ec8a-4501-b5e2-c3cbedbd0fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487421342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.1487421342
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.4886989
Short name T791
Test name
Test status
Simulation time 1198385725 ps
CPU time 6.75 seconds
Started Aug 08 06:12:25 PM PDT 24
Finished Aug 08 06:12:32 PM PDT 24
Peak memory 216976 kb
Host smart-fdb99bdb-1146-4f82-8fd2-7a7160edb5d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4886989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.4886989
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.3613046528
Short name T471
Test name
Test status
Simulation time 65901605 ps
CPU time 1.41 seconds
Started Aug 08 06:12:25 PM PDT 24
Finished Aug 08 06:12:26 PM PDT 24
Peak memory 217024 kb
Host smart-a07248fd-b67e-453e-90b0-3fe237d235a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613046528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.3613046528
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.4215868381
Short name T949
Test name
Test status
Simulation time 371358594 ps
CPU time 0.87 seconds
Started Aug 08 06:12:22 PM PDT 24
Finished Aug 08 06:12:23 PM PDT 24
Peak memory 206628 kb
Host smart-ec9f1f3c-bdd5-42e4-9a05-d83481dcf704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215868381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.4215868381
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.649923735
Short name T862
Test name
Test status
Simulation time 985724265 ps
CPU time 7.51 seconds
Started Aug 08 06:12:22 PM PDT 24
Finished Aug 08 06:12:30 PM PDT 24
Peak memory 225320 kb
Host smart-2b0036ea-dedd-47f4-a9ae-c1c40ad45ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649923735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.649923735
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.3441167413
Short name T358
Test name
Test status
Simulation time 33979233 ps
CPU time 0.7 seconds
Started Aug 08 06:12:26 PM PDT 24
Finished Aug 08 06:12:27 PM PDT 24
Peak memory 205844 kb
Host smart-d33e663c-55c4-4431-a500-6f3e6ca2ebf8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441167413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
3441167413
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.4099040688
Short name T578
Test name
Test status
Simulation time 40863660 ps
CPU time 2.51 seconds
Started Aug 08 06:12:25 PM PDT 24
Finished Aug 08 06:12:28 PM PDT 24
Peak memory 233408 kb
Host smart-5b77f580-effa-4caf-ac75-7d4a6cb08076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099040688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.4099040688
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.1030361365
Short name T671
Test name
Test status
Simulation time 50334819 ps
CPU time 0.76 seconds
Started Aug 08 06:12:23 PM PDT 24
Finished Aug 08 06:12:24 PM PDT 24
Peak memory 205952 kb
Host smart-88d331d9-e264-449e-a465-4a252f1a2387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030361365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.1030361365
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.3117169154
Short name T531
Test name
Test status
Simulation time 16138958824 ps
CPU time 59.09 seconds
Started Aug 08 06:12:26 PM PDT 24
Finished Aug 08 06:13:25 PM PDT 24
Peak memory 256712 kb
Host smart-eecb03d4-1eb0-455a-a31c-fda2fbe4e0e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117169154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.3117169154
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.2222058597
Short name T668
Test name
Test status
Simulation time 60121465640 ps
CPU time 576.57 seconds
Started Aug 08 06:12:24 PM PDT 24
Finished Aug 08 06:22:01 PM PDT 24
Peak memory 261924 kb
Host smart-0b5db737-b184-46f3-a475-fd65dadc9d08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222058597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.2222058597
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.1173321525
Short name T994
Test name
Test status
Simulation time 126521059357 ps
CPU time 249.98 seconds
Started Aug 08 06:12:22 PM PDT 24
Finished Aug 08 06:16:32 PM PDT 24
Peak memory 254028 kb
Host smart-9e5456ed-6b7d-4248-85b2-406ff2ab7838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173321525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.1173321525
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.411441783
Short name T837
Test name
Test status
Simulation time 31274215195 ps
CPU time 60.37 seconds
Started Aug 08 06:12:21 PM PDT 24
Finished Aug 08 06:13:21 PM PDT 24
Peak memory 233544 kb
Host smart-258f81d1-c7a7-48bb-abd6-427b317977d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411441783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.411441783
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.4232262493
Short name T239
Test name
Test status
Simulation time 3625422702 ps
CPU time 79.54 seconds
Started Aug 08 06:12:24 PM PDT 24
Finished Aug 08 06:13:43 PM PDT 24
Peak memory 257908 kb
Host smart-f025cdb8-bdac-44e3-8f3f-6b7502fab5ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232262493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmd
s.4232262493
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/38.spi_device_intercept.3484191724
Short name T772
Test name
Test status
Simulation time 640943108 ps
CPU time 4.74 seconds
Started Aug 08 06:12:21 PM PDT 24
Finished Aug 08 06:12:26 PM PDT 24
Peak memory 225200 kb
Host smart-47aafcd2-c33b-4bc2-a19d-f1125fbbf9bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484191724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.3484191724
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.174881298
Short name T417
Test name
Test status
Simulation time 2299358762 ps
CPU time 7.5 seconds
Started Aug 08 06:12:22 PM PDT 24
Finished Aug 08 06:12:30 PM PDT 24
Peak memory 225368 kb
Host smart-228a7a7f-463a-46e2-8412-ff8a1d8990be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174881298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.174881298
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.3965625699
Short name T225
Test name
Test status
Simulation time 4362713179 ps
CPU time 8.27 seconds
Started Aug 08 06:12:21 PM PDT 24
Finished Aug 08 06:12:29 PM PDT 24
Peak memory 233504 kb
Host smart-f575465b-559c-4d98-959f-5f0e53ff638a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965625699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.3965625699
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.3719781589
Short name T672
Test name
Test status
Simulation time 71065936 ps
CPU time 2.8 seconds
Started Aug 08 06:12:20 PM PDT 24
Finished Aug 08 06:12:23 PM PDT 24
Peak memory 233376 kb
Host smart-22ac4d5c-2a40-487e-9839-68e1127d1cca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719781589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.3719781589
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.2969761132
Short name T148
Test name
Test status
Simulation time 2817549447 ps
CPU time 19.1 seconds
Started Aug 08 06:12:23 PM PDT 24
Finished Aug 08 06:12:42 PM PDT 24
Peak memory 223840 kb
Host smart-1b54f520-c52e-4072-be55-eed06ae7ba00
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2969761132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.2969761132
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.3984927526
Short name T937
Test name
Test status
Simulation time 58740850345 ps
CPU time 189.72 seconds
Started Aug 08 06:12:24 PM PDT 24
Finished Aug 08 06:15:34 PM PDT 24
Peak memory 254908 kb
Host smart-018df43e-9ddd-4485-a033-c750b8c09c96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984927526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.3984927526
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.202856113
Short name T755
Test name
Test status
Simulation time 3952603750 ps
CPU time 22.63 seconds
Started Aug 08 06:12:21 PM PDT 24
Finished Aug 08 06:12:44 PM PDT 24
Peak memory 217080 kb
Host smart-acbf18be-d08f-4ea7-a040-6bf469be1f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202856113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.202856113
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.382447283
Short name T790
Test name
Test status
Simulation time 778241662 ps
CPU time 6.12 seconds
Started Aug 08 06:12:20 PM PDT 24
Finished Aug 08 06:12:27 PM PDT 24
Peak memory 217048 kb
Host smart-faf23b2d-0ce6-4313-b31e-72a714bdb50d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382447283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.382447283
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.3879588933
Short name T352
Test name
Test status
Simulation time 129352926 ps
CPU time 1.37 seconds
Started Aug 08 06:12:24 PM PDT 24
Finished Aug 08 06:12:25 PM PDT 24
Peak memory 217212 kb
Host smart-d4f4585f-2e7f-471e-8249-b222e05c103b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879588933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.3879588933
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.563228850
Short name T740
Test name
Test status
Simulation time 102141010 ps
CPU time 0.9 seconds
Started Aug 08 06:12:23 PM PDT 24
Finished Aug 08 06:12:24 PM PDT 24
Peak memory 206992 kb
Host smart-eabfa78f-c5b4-4d30-a323-964aaa1a6f4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563228850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.563228850
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.942230797
Short name T839
Test name
Test status
Simulation time 4507676244 ps
CPU time 7.56 seconds
Started Aug 08 06:12:23 PM PDT 24
Finished Aug 08 06:12:31 PM PDT 24
Peak memory 234500 kb
Host smart-d440f475-5e2e-434d-b17c-a3df337f576e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942230797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.942230797
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.3181749791
Short name T365
Test name
Test status
Simulation time 16223948 ps
CPU time 0.72 seconds
Started Aug 08 06:12:26 PM PDT 24
Finished Aug 08 06:12:27 PM PDT 24
Peak memory 205896 kb
Host smart-4fc7ba6b-fe0c-4e26-82fb-95772be3cb4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181749791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
3181749791
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.444393076
Short name T1024
Test name
Test status
Simulation time 19933769 ps
CPU time 0.78 seconds
Started Aug 08 06:12:25 PM PDT 24
Finished Aug 08 06:12:25 PM PDT 24
Peak memory 207008 kb
Host smart-1d48ed35-a3b9-41ee-836d-a81e4ecd0e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444393076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.444393076
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.3817294964
Short name T943
Test name
Test status
Simulation time 9328330860 ps
CPU time 88.54 seconds
Started Aug 08 06:12:24 PM PDT 24
Finished Aug 08 06:13:53 PM PDT 24
Peak memory 249944 kb
Host smart-101a792e-bd64-4147-8af4-56824292e300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817294964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.3817294964
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.3923505603
Short name T439
Test name
Test status
Simulation time 2927473930 ps
CPU time 4.51 seconds
Started Aug 08 06:12:23 PM PDT 24
Finished Aug 08 06:12:28 PM PDT 24
Peak memory 218520 kb
Host smart-93b74dc2-9b88-4f8d-90bf-9d754a6cfc0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923505603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.3923505603
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.2078168247
Short name T253
Test name
Test status
Simulation time 7516894260 ps
CPU time 50.33 seconds
Started Aug 08 06:12:30 PM PDT 24
Finished Aug 08 06:13:21 PM PDT 24
Peak memory 250624 kb
Host smart-2eb3f005-2f6b-4af5-bae6-e60d95de1051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078168247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.2078168247
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.4182935858
Short name T654
Test name
Test status
Simulation time 158823607 ps
CPU time 3.67 seconds
Started Aug 08 06:12:29 PM PDT 24
Finished Aug 08 06:12:33 PM PDT 24
Peak memory 225264 kb
Host smart-b6a34e78-ce1c-46c2-99f9-15d3c073312e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182935858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.4182935858
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.977251842
Short name T1019
Test name
Test status
Simulation time 114447842725 ps
CPU time 234.32 seconds
Started Aug 08 06:12:29 PM PDT 24
Finished Aug 08 06:16:23 PM PDT 24
Peak memory 268688 kb
Host smart-ae755980-0506-4226-ae55-89176005f070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977251842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmds
.977251842
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/39.spi_device_intercept.1850903451
Short name T947
Test name
Test status
Simulation time 6407073091 ps
CPU time 10.92 seconds
Started Aug 08 06:12:30 PM PDT 24
Finished Aug 08 06:12:42 PM PDT 24
Peak memory 233552 kb
Host smart-7fb9ceaf-d912-4c04-a6ee-a0488afc9ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850903451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.1850903451
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.1286000054
Short name T842
Test name
Test status
Simulation time 108760751 ps
CPU time 2.29 seconds
Started Aug 08 06:12:26 PM PDT 24
Finished Aug 08 06:12:28 PM PDT 24
Peak memory 233072 kb
Host smart-d8a527a5-c98f-4126-9e58-7fb8a25fdec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286000054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.1286000054
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.4265522936
Short name T560
Test name
Test status
Simulation time 14112056050 ps
CPU time 18.05 seconds
Started Aug 08 06:12:24 PM PDT 24
Finished Aug 08 06:12:42 PM PDT 24
Peak memory 233424 kb
Host smart-19fd6f82-5a23-4980-9df3-35cb8aa96ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265522936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.4265522936
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.1483261227
Short name T912
Test name
Test status
Simulation time 6796258883 ps
CPU time 18.52 seconds
Started Aug 08 06:12:21 PM PDT 24
Finished Aug 08 06:12:40 PM PDT 24
Peak memory 225292 kb
Host smart-f047e1d8-be63-4e30-903a-ab9f2a86545a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483261227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.1483261227
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.1513901163
Short name T147
Test name
Test status
Simulation time 2036485934 ps
CPU time 23.36 seconds
Started Aug 08 06:12:24 PM PDT 24
Finished Aug 08 06:12:48 PM PDT 24
Peak memory 222308 kb
Host smart-6681c8a3-3d86-4df0-9a3b-8cd54bc3b298
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1513901163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.1513901163
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.824482868
Short name T434
Test name
Test status
Simulation time 128764719 ps
CPU time 1.17 seconds
Started Aug 08 06:12:24 PM PDT 24
Finished Aug 08 06:12:26 PM PDT 24
Peak memory 207536 kb
Host smart-50e35552-654c-48ef-8193-78e91633288e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824482868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stres
s_all.824482868
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.838792637
Short name T307
Test name
Test status
Simulation time 2616603733 ps
CPU time 21.38 seconds
Started Aug 08 06:12:22 PM PDT 24
Finished Aug 08 06:12:43 PM PDT 24
Peak memory 217060 kb
Host smart-aaece35b-cde6-447f-ab51-2de1486920a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838792637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.838792637
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.334087204
Short name T775
Test name
Test status
Simulation time 2746704555 ps
CPU time 8.84 seconds
Started Aug 08 06:12:26 PM PDT 24
Finished Aug 08 06:12:35 PM PDT 24
Peak memory 217036 kb
Host smart-4883f57d-2474-44b6-820c-5fd67bb1ef1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334087204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.334087204
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.3103222115
Short name T569
Test name
Test status
Simulation time 37926211 ps
CPU time 0.68 seconds
Started Aug 08 06:12:26 PM PDT 24
Finished Aug 08 06:12:27 PM PDT 24
Peak memory 206096 kb
Host smart-de049dfe-32e6-4e3b-a369-a8bb6dd8c9c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103222115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.3103222115
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.3429928406
Short name T648
Test name
Test status
Simulation time 24914218 ps
CPU time 0.76 seconds
Started Aug 08 06:12:22 PM PDT 24
Finished Aug 08 06:12:23 PM PDT 24
Peak memory 206560 kb
Host smart-09cc111c-3210-4ed3-87b6-3b0f85972ed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429928406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.3429928406
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.1942262920
Short name T891
Test name
Test status
Simulation time 7447905036 ps
CPU time 23.83 seconds
Started Aug 08 06:12:24 PM PDT 24
Finished Aug 08 06:12:48 PM PDT 24
Peak memory 233536 kb
Host smart-fb1b942a-cd05-433e-8b6e-845b260ce5a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942262920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.1942262920
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.1271262450
Short name T324
Test name
Test status
Simulation time 22843325 ps
CPU time 0.69 seconds
Started Aug 08 06:10:19 PM PDT 24
Finished Aug 08 06:10:20 PM PDT 24
Peak memory 205832 kb
Host smart-7b93e753-a38f-4987-a149-5820df6677a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271262450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.1
271262450
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.715295799
Short name T808
Test name
Test status
Simulation time 591179038 ps
CPU time 3.25 seconds
Started Aug 08 06:10:21 PM PDT 24
Finished Aug 08 06:10:24 PM PDT 24
Peak memory 233340 kb
Host smart-e02c167d-9258-4045-a715-daa4064b7922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715295799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.715295799
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.532695918
Short name T339
Test name
Test status
Simulation time 71772266 ps
CPU time 0.78 seconds
Started Aug 08 06:10:21 PM PDT 24
Finished Aug 08 06:10:22 PM PDT 24
Peak memory 207048 kb
Host smart-ffffcf15-ad84-40e7-8c92-382bc0ef2a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532695918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.532695918
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.1935394244
Short name T515
Test name
Test status
Simulation time 438094209 ps
CPU time 9.86 seconds
Started Aug 08 06:10:23 PM PDT 24
Finished Aug 08 06:10:33 PM PDT 24
Peak memory 249872 kb
Host smart-b6e664a6-51c8-4358-9047-945f72b09dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935394244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.1935394244
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.1935275269
Short name T963
Test name
Test status
Simulation time 75461384244 ps
CPU time 220.02 seconds
Started Aug 08 06:10:21 PM PDT 24
Finished Aug 08 06:14:02 PM PDT 24
Peak memory 257168 kb
Host smart-80fda00a-a60e-4b73-9aaa-54fc3186ad4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935275269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.1935275269
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.3430382905
Short name T203
Test name
Test status
Simulation time 17208197604 ps
CPU time 98.15 seconds
Started Aug 08 06:10:22 PM PDT 24
Finished Aug 08 06:12:00 PM PDT 24
Peak memory 273652 kb
Host smart-9fb2ca35-8fcc-47ce-99c6-791cc2a33006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430382905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.3430382905
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.4061670097
Short name T172
Test name
Test status
Simulation time 26910097314 ps
CPU time 71.88 seconds
Started Aug 08 06:10:21 PM PDT 24
Finished Aug 08 06:11:33 PM PDT 24
Peak memory 256776 kb
Host smart-75baad8f-6389-4f71-ab19-7b51211f4773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061670097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds
.4061670097
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/4.spi_device_intercept.3762490674
Short name T443
Test name
Test status
Simulation time 1716898625 ps
CPU time 7.96 seconds
Started Aug 08 06:10:20 PM PDT 24
Finished Aug 08 06:10:28 PM PDT 24
Peak memory 233400 kb
Host smart-69519300-e9ee-48ad-84fd-a00c72e935b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762490674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.3762490674
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.3224506497
Short name T431
Test name
Test status
Simulation time 1709134493 ps
CPU time 15.2 seconds
Started Aug 08 06:10:21 PM PDT 24
Finished Aug 08 06:10:36 PM PDT 24
Peak memory 249556 kb
Host smart-4885695b-8f16-4300-9edf-a81cbd75b1bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224506497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.3224506497
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.2180886121
Short name T73
Test name
Test status
Simulation time 28037829 ps
CPU time 1.1 seconds
Started Aug 08 06:10:23 PM PDT 24
Finished Aug 08 06:10:24 PM PDT 24
Peak memory 217244 kb
Host smart-51a5de01-333c-4a71-bea1-d14dc78043da
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180886121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.spi_device_mem_parity.2180886121
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.3758662986
Short name T657
Test name
Test status
Simulation time 460136661 ps
CPU time 6.2 seconds
Started Aug 08 06:10:19 PM PDT 24
Finished Aug 08 06:10:25 PM PDT 24
Peak memory 225116 kb
Host smart-93ac7f03-687e-4630-8f12-30d6aff59da2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758662986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.3758662986
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.2099098807
Short name T702
Test name
Test status
Simulation time 4369362046 ps
CPU time 5.35 seconds
Started Aug 08 06:10:20 PM PDT 24
Finished Aug 08 06:10:26 PM PDT 24
Peak memory 233448 kb
Host smart-e6b722c8-348f-42db-850f-c79150ec12a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099098807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.2099098807
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.183111675
Short name T354
Test name
Test status
Simulation time 408298013 ps
CPU time 5.32 seconds
Started Aug 08 06:10:23 PM PDT 24
Finished Aug 08 06:10:29 PM PDT 24
Peak memory 222120 kb
Host smart-aa7a6b80-1b36-40a3-b9ec-3b2e425a9225
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=183111675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_direc
t.183111675
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.1150249845
Short name T64
Test name
Test status
Simulation time 79728643 ps
CPU time 1.01 seconds
Started Aug 08 06:10:21 PM PDT 24
Finished Aug 08 06:10:22 PM PDT 24
Peak memory 235552 kb
Host smart-9ca3d685-d6da-447e-ae51-6b4666cc000a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150249845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.1150249845
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.2326537855
Short name T316
Test name
Test status
Simulation time 10869151410 ps
CPU time 159.67 seconds
Started Aug 08 06:10:21 PM PDT 24
Finished Aug 08 06:13:01 PM PDT 24
Peak memory 269120 kb
Host smart-fa41cc40-56dd-4af4-8977-d852c7ad485c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326537855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.2326537855
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.785468559
Short name T833
Test name
Test status
Simulation time 2877116095 ps
CPU time 27.57 seconds
Started Aug 08 06:10:18 PM PDT 24
Finished Aug 08 06:10:46 PM PDT 24
Peak memory 217060 kb
Host smart-7b4910a0-d71e-4162-a3f8-13b0a114b35c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785468559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.785468559
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.993600718
Short name T783
Test name
Test status
Simulation time 3920731641 ps
CPU time 7.51 seconds
Started Aug 08 06:10:20 PM PDT 24
Finished Aug 08 06:10:28 PM PDT 24
Peak memory 217048 kb
Host smart-edf0d163-a49a-4d99-9d6c-78ac79798e40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993600718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.993600718
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.501128309
Short name T705
Test name
Test status
Simulation time 44390325 ps
CPU time 0.99 seconds
Started Aug 08 06:10:19 PM PDT 24
Finished Aug 08 06:10:20 PM PDT 24
Peak memory 208552 kb
Host smart-26cb6600-21e1-48f7-9721-066b276d6ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501128309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.501128309
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.3870828348
Short name T714
Test name
Test status
Simulation time 34676826 ps
CPU time 0.68 seconds
Started Aug 08 06:10:19 PM PDT 24
Finished Aug 08 06:10:20 PM PDT 24
Peak memory 206592 kb
Host smart-82cdfde6-920d-47c9-99e6-b8741486f9b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870828348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.3870828348
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.270980046
Short name T436
Test name
Test status
Simulation time 656980596 ps
CPU time 6.23 seconds
Started Aug 08 06:10:20 PM PDT 24
Finished Aug 08 06:10:26 PM PDT 24
Peak memory 240996 kb
Host smart-92c015c1-e9d2-4fab-9bf1-12ea003f54d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270980046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.270980046
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.3723715640
Short name T703
Test name
Test status
Simulation time 14609186 ps
CPU time 0.73 seconds
Started Aug 08 06:12:31 PM PDT 24
Finished Aug 08 06:12:32 PM PDT 24
Peak memory 206044 kb
Host smart-23d9f7d1-ec01-49b4-9544-8b51cc876cd1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723715640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
3723715640
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.2810642715
Short name T590
Test name
Test status
Simulation time 107683381 ps
CPU time 2.29 seconds
Started Aug 08 06:12:31 PM PDT 24
Finished Aug 08 06:12:34 PM PDT 24
Peak memory 225148 kb
Host smart-d9d72672-9b80-495b-97dd-ba2903b8eb9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810642715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.2810642715
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.3668206582
Short name T400
Test name
Test status
Simulation time 30010083 ps
CPU time 0.76 seconds
Started Aug 08 06:12:26 PM PDT 24
Finished Aug 08 06:12:27 PM PDT 24
Peak memory 207396 kb
Host smart-0e07888e-a0c8-4c01-8fa1-6707deb04263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668206582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.3668206582
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.3079470042
Short name T283
Test name
Test status
Simulation time 11987441488 ps
CPU time 24.55 seconds
Started Aug 08 06:12:32 PM PDT 24
Finished Aug 08 06:12:57 PM PDT 24
Peak memory 225236 kb
Host smart-a0ebd691-f327-4f96-b67e-c5f7e2617db0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079470042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.3079470042
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.1968301062
Short name T645
Test name
Test status
Simulation time 41838399614 ps
CPU time 325.84 seconds
Started Aug 08 06:12:32 PM PDT 24
Finished Aug 08 06:17:58 PM PDT 24
Peak memory 258156 kb
Host smart-031b12e8-85ac-4ff4-b88f-247afff69359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968301062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.1968301062
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.4162884961
Short name T881
Test name
Test status
Simulation time 37397985940 ps
CPU time 149.16 seconds
Started Aug 08 06:12:34 PM PDT 24
Finished Aug 08 06:15:03 PM PDT 24
Peak memory 266372 kb
Host smart-070cd0f5-9268-417a-b9bd-c1916ddfebd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162884961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.4162884961
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.1381807885
Short name T773
Test name
Test status
Simulation time 5665219483 ps
CPU time 37.06 seconds
Started Aug 08 06:12:30 PM PDT 24
Finished Aug 08 06:13:08 PM PDT 24
Peak memory 233520 kb
Host smart-b098a1be-04cb-456f-9312-57a0fc22b316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381807885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.1381807885
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.3382652265
Short name T661
Test name
Test status
Simulation time 6259690127 ps
CPU time 10.6 seconds
Started Aug 08 06:12:30 PM PDT 24
Finished Aug 08 06:12:41 PM PDT 24
Peak memory 233568 kb
Host smart-cefc47cb-845e-4138-b0e8-ecb8536bf3e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382652265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmd
s.3382652265
Directory /workspace/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/40.spi_device_intercept.513952199
Short name T83
Test name
Test status
Simulation time 1656526508 ps
CPU time 5.68 seconds
Started Aug 08 06:12:31 PM PDT 24
Finished Aug 08 06:12:37 PM PDT 24
Peak memory 225196 kb
Host smart-c277871d-52e0-4c21-a836-8481ae5d30bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513952199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.513952199
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.3178141571
Short name T99
Test name
Test status
Simulation time 375325726 ps
CPU time 5.64 seconds
Started Aug 08 06:12:31 PM PDT 24
Finished Aug 08 06:12:37 PM PDT 24
Peak memory 239088 kb
Host smart-bf7f0bb5-3fff-4a42-9b8d-2ef2c864707c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178141571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.3178141571
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.2070633623
Short name T207
Test name
Test status
Simulation time 7529509693 ps
CPU time 6.26 seconds
Started Aug 08 06:12:32 PM PDT 24
Finished Aug 08 06:12:39 PM PDT 24
Peak memory 225320 kb
Host smart-1b3702d2-15e9-4dfb-9744-516b9b94709d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070633623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.2070633623
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.1643835422
Short name T575
Test name
Test status
Simulation time 1050532187 ps
CPU time 3.97 seconds
Started Aug 08 06:12:32 PM PDT 24
Finished Aug 08 06:12:36 PM PDT 24
Peak memory 225224 kb
Host smart-e39f0a47-edda-423d-a0e4-311976ca2f70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643835422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.1643835422
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.3621136604
Short name T507
Test name
Test status
Simulation time 421381471 ps
CPU time 4.09 seconds
Started Aug 08 06:12:31 PM PDT 24
Finished Aug 08 06:12:36 PM PDT 24
Peak memory 223240 kb
Host smart-97becd6d-0efd-4f2d-a7a4-1160ddc491d1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3621136604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.3621136604
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.2339688717
Short name T447
Test name
Test status
Simulation time 104098179760 ps
CPU time 503.44 seconds
Started Aug 08 06:12:32 PM PDT 24
Finished Aug 08 06:20:55 PM PDT 24
Peak memory 274136 kb
Host smart-a2e6455a-4919-4c61-a89a-680d3b61d6d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339688717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.2339688717
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.272765534
Short name T713
Test name
Test status
Simulation time 7856909078 ps
CPU time 30.69 seconds
Started Aug 08 06:12:25 PM PDT 24
Finished Aug 08 06:12:55 PM PDT 24
Peak memory 220796 kb
Host smart-8c5acf5e-6f1f-4ab0-b07c-cada03c55393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272765534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.272765534
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.3766462743
Short name T852
Test name
Test status
Simulation time 14135772726 ps
CPU time 7.95 seconds
Started Aug 08 06:12:26 PM PDT 24
Finished Aug 08 06:12:34 PM PDT 24
Peak memory 217088 kb
Host smart-e229783c-c34f-4161-8c39-c32b5a01cb05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766462743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.3766462743
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.493881647
Short name T552
Test name
Test status
Simulation time 338478530 ps
CPU time 3.04 seconds
Started Aug 08 06:12:25 PM PDT 24
Finished Aug 08 06:12:28 PM PDT 24
Peak memory 216976 kb
Host smart-7f6331c5-50ce-49ed-9f14-e75e10c497ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493881647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.493881647
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.4260051038
Short name T326
Test name
Test status
Simulation time 34525422 ps
CPU time 0.85 seconds
Started Aug 08 06:12:24 PM PDT 24
Finished Aug 08 06:12:25 PM PDT 24
Peak memory 206552 kb
Host smart-53243ee3-8a60-42b8-a033-515d8e0d6563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260051038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.4260051038
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.1367761128
Short name T957
Test name
Test status
Simulation time 428123266 ps
CPU time 7.86 seconds
Started Aug 08 06:12:34 PM PDT 24
Finished Aug 08 06:12:42 PM PDT 24
Peak memory 236544 kb
Host smart-2047824f-c218-4a03-84f7-ab51f08dd5c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367761128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.1367761128
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.1133745389
Short name T759
Test name
Test status
Simulation time 10755985 ps
CPU time 0.69 seconds
Started Aug 08 06:12:32 PM PDT 24
Finished Aug 08 06:12:33 PM PDT 24
Peak memory 205280 kb
Host smart-0fb37294-24e0-4b3e-90e7-d8ebaee001fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133745389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
1133745389
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.3713368061
Short name T629
Test name
Test status
Simulation time 325328138 ps
CPU time 2.25 seconds
Started Aug 08 06:12:31 PM PDT 24
Finished Aug 08 06:12:34 PM PDT 24
Peak memory 224648 kb
Host smart-74e2c88e-b3f0-42bf-8cb6-d3d798838b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713368061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.3713368061
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.629067722
Short name T898
Test name
Test status
Simulation time 13682824 ps
CPU time 0.75 seconds
Started Aug 08 06:12:34 PM PDT 24
Finished Aug 08 06:12:35 PM PDT 24
Peak memory 206048 kb
Host smart-328518e7-08fb-475f-82da-4e2fe25cceed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629067722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.629067722
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.1911900793
Short name T275
Test name
Test status
Simulation time 11850739455 ps
CPU time 80.81 seconds
Started Aug 08 06:12:37 PM PDT 24
Finished Aug 08 06:13:58 PM PDT 24
Peak memory 242072 kb
Host smart-8360b197-6de2-44eb-a343-408f2797a8e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911900793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.1911900793
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.3438209548
Short name T261
Test name
Test status
Simulation time 25193861315 ps
CPU time 91.44 seconds
Started Aug 08 06:12:31 PM PDT 24
Finished Aug 08 06:14:03 PM PDT 24
Peak memory 266320 kb
Host smart-8c51d4fd-036b-4cfd-b3f7-cc7fd8cb3c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438209548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.3438209548
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.1635811425
Short name T146
Test name
Test status
Simulation time 570764392 ps
CPU time 10.37 seconds
Started Aug 08 06:12:31 PM PDT 24
Finished Aug 08 06:12:41 PM PDT 24
Peak memory 225324 kb
Host smart-2f377d3a-f46e-49b1-996f-3c81902aca62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635811425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.1635811425
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.4056247761
Short name T280
Test name
Test status
Simulation time 65788528407 ps
CPU time 103.44 seconds
Started Aug 08 06:12:30 PM PDT 24
Finished Aug 08 06:14:13 PM PDT 24
Peak memory 249972 kb
Host smart-4413b7e6-e421-4714-ac3e-80dddcdf11f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056247761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmd
s.4056247761
Directory /workspace/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/41.spi_device_intercept.2003470009
Short name T824
Test name
Test status
Simulation time 200435165 ps
CPU time 4.42 seconds
Started Aug 08 06:12:32 PM PDT 24
Finished Aug 08 06:12:36 PM PDT 24
Peak memory 233460 kb
Host smart-6fc34679-c602-4824-aae1-1f0a5450b8c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003470009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.2003470009
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.2840108673
Short name T690
Test name
Test status
Simulation time 128666301 ps
CPU time 4.13 seconds
Started Aug 08 06:12:37 PM PDT 24
Finished Aug 08 06:12:41 PM PDT 24
Peak memory 233476 kb
Host smart-2c9977f8-7a7c-4bfc-9a62-3cfaf8331195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840108673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.2840108673
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.3460059858
Short name T254
Test name
Test status
Simulation time 44203271402 ps
CPU time 20.87 seconds
Started Aug 08 06:12:34 PM PDT 24
Finished Aug 08 06:12:55 PM PDT 24
Peak memory 238224 kb
Host smart-98dc4780-44e6-42d1-8d98-1eaf6ebdf412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460059858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.3460059858
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.3685012021
Short name T8
Test name
Test status
Simulation time 9580442959 ps
CPU time 13.91 seconds
Started Aug 08 06:12:37 PM PDT 24
Finished Aug 08 06:12:51 PM PDT 24
Peak memory 233500 kb
Host smart-b54f91de-9f0a-473a-8125-7dd0890fa499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685012021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.3685012021
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.435653508
Short name T796
Test name
Test status
Simulation time 1783575542 ps
CPU time 14.82 seconds
Started Aug 08 06:12:31 PM PDT 24
Finished Aug 08 06:12:46 PM PDT 24
Peak memory 222408 kb
Host smart-5ba893aa-20c8-4d4f-b462-6d0990bac46e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=435653508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dire
ct.435653508
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.3540265013
Short name T160
Test name
Test status
Simulation time 4418618269 ps
CPU time 22.25 seconds
Started Aug 08 06:12:32 PM PDT 24
Finished Aug 08 06:12:54 PM PDT 24
Peak memory 225364 kb
Host smart-6c0bc4ba-c74b-43ad-ae6c-c4e45ae2ccf6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540265013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.3540265013
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.1854550269
Short name T591
Test name
Test status
Simulation time 4156834481 ps
CPU time 12.44 seconds
Started Aug 08 06:12:30 PM PDT 24
Finished Aug 08 06:12:42 PM PDT 24
Peak memory 217080 kb
Host smart-f2e4eaea-e4d7-4d4f-990d-3f620434c3c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854550269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.1854550269
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.524858370
Short name T321
Test name
Test status
Simulation time 1742629234 ps
CPU time 3.61 seconds
Started Aug 08 06:12:31 PM PDT 24
Finished Aug 08 06:12:35 PM PDT 24
Peak memory 216780 kb
Host smart-84d9be63-263e-40ed-817b-51514a109971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524858370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.524858370
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.3696183519
Short name T564
Test name
Test status
Simulation time 772028119 ps
CPU time 2.21 seconds
Started Aug 08 06:12:32 PM PDT 24
Finished Aug 08 06:12:34 PM PDT 24
Peak memory 217036 kb
Host smart-1d1e2bd8-b9a2-4ff3-aee1-0b7cbdff7529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696183519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.3696183519
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.2575252439
Short name T371
Test name
Test status
Simulation time 12705994 ps
CPU time 0.71 seconds
Started Aug 08 06:12:30 PM PDT 24
Finished Aug 08 06:12:31 PM PDT 24
Peak memory 206036 kb
Host smart-71439378-e368-439e-b4fc-3f4bdfca346f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575252439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.2575252439
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.4251301947
Short name T235
Test name
Test status
Simulation time 75186027 ps
CPU time 2.74 seconds
Started Aug 08 06:12:31 PM PDT 24
Finished Aug 08 06:12:34 PM PDT 24
Peak memory 233416 kb
Host smart-a6441b4a-3298-4a49-bedf-536f51b7e221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251301947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.4251301947
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.3053378594
Short name T901
Test name
Test status
Simulation time 22048161 ps
CPU time 0.7 seconds
Started Aug 08 06:12:31 PM PDT 24
Finished Aug 08 06:12:32 PM PDT 24
Peak memory 206100 kb
Host smart-4258b628-1135-4864-8f0d-a6df5fa50432
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053378594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
3053378594
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.2615098481
Short name T888
Test name
Test status
Simulation time 769509303 ps
CPU time 4.94 seconds
Started Aug 08 06:12:31 PM PDT 24
Finished Aug 08 06:12:36 PM PDT 24
Peak memory 233408 kb
Host smart-98f3bfb9-5f00-4f9b-8d5d-5d38a9275c12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615098481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.2615098481
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.2721677424
Short name T582
Test name
Test status
Simulation time 31933411 ps
CPU time 0.78 seconds
Started Aug 08 06:12:32 PM PDT 24
Finished Aug 08 06:12:33 PM PDT 24
Peak memory 207388 kb
Host smart-d2988670-16bd-43aa-94c4-8e295efcea7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721677424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.2721677424
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.1658631745
Short name T272
Test name
Test status
Simulation time 46458119034 ps
CPU time 236 seconds
Started Aug 08 06:12:30 PM PDT 24
Finished Aug 08 06:16:26 PM PDT 24
Peak memory 252636 kb
Host smart-954b83c6-3df8-4bcd-b653-a6c851103eb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658631745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.1658631745
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.4034521409
Short name T788
Test name
Test status
Simulation time 13292986412 ps
CPU time 95.36 seconds
Started Aug 08 06:12:36 PM PDT 24
Finished Aug 08 06:14:12 PM PDT 24
Peak memory 255540 kb
Host smart-eb2ef89a-96b6-4556-8342-177347806c67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034521409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.4034521409
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.1582749836
Short name T774
Test name
Test status
Simulation time 27056064015 ps
CPU time 261.21 seconds
Started Aug 08 06:12:33 PM PDT 24
Finished Aug 08 06:16:54 PM PDT 24
Peak memory 258072 kb
Host smart-68ceb950-fab1-4870-80e8-32146f0813e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582749836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.1582749836
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.2090242468
Short name T41
Test name
Test status
Simulation time 3814702846 ps
CPU time 10.53 seconds
Started Aug 08 06:12:34 PM PDT 24
Finished Aug 08 06:12:44 PM PDT 24
Peak memory 223868 kb
Host smart-94a5f5b4-417b-425d-b23f-10b4c851a532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090242468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.2090242468
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.1150641979
Short name T330
Test name
Test status
Simulation time 53259837181 ps
CPU time 35.44 seconds
Started Aug 08 06:12:33 PM PDT 24
Finished Aug 08 06:13:09 PM PDT 24
Peak memory 249892 kb
Host smart-c01ce691-695e-4034-8303-856ae628b5ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150641979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmd
s.1150641979
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/42.spi_device_intercept.2811884498
Short name T983
Test name
Test status
Simulation time 290357386 ps
CPU time 2.3 seconds
Started Aug 08 06:12:31 PM PDT 24
Finished Aug 08 06:12:33 PM PDT 24
Peak memory 219184 kb
Host smart-dc805670-5628-4ff9-89a9-bbda5abb4687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811884498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.2811884498
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.525277766
Short name T832
Test name
Test status
Simulation time 32076864 ps
CPU time 2.19 seconds
Started Aug 08 06:12:34 PM PDT 24
Finished Aug 08 06:12:36 PM PDT 24
Peak memory 233008 kb
Host smart-bf7792cd-9f4e-426a-a4d8-d87d50704b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525277766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.525277766
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.648068386
Short name T922
Test name
Test status
Simulation time 229318913 ps
CPU time 4.56 seconds
Started Aug 08 06:12:30 PM PDT 24
Finished Aug 08 06:12:35 PM PDT 24
Peak memory 233480 kb
Host smart-e0b4f0e6-165e-448b-b842-27e8479a98c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648068386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swap
.648068386
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.306056385
Short name T677
Test name
Test status
Simulation time 569738270 ps
CPU time 4.71 seconds
Started Aug 08 06:12:31 PM PDT 24
Finished Aug 08 06:12:36 PM PDT 24
Peak memory 233412 kb
Host smart-ed0afe9d-4fec-4ebe-bc31-0e6d01894a2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306056385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.306056385
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.3420490646
Short name T380
Test name
Test status
Simulation time 525796685 ps
CPU time 4.38 seconds
Started Aug 08 06:12:34 PM PDT 24
Finished Aug 08 06:12:39 PM PDT 24
Peak memory 220760 kb
Host smart-951ac9e1-d581-4ef7-956c-9452cc9f024b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3420490646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.3420490646
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.2563488831
Short name T138
Test name
Test status
Simulation time 39373546753 ps
CPU time 372.13 seconds
Started Aug 08 06:12:34 PM PDT 24
Finished Aug 08 06:18:47 PM PDT 24
Peak memory 274408 kb
Host smart-a2582825-e670-4f33-931e-0b8b1c52db7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563488831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.2563488831
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.3389195678
Short name T715
Test name
Test status
Simulation time 9890073005 ps
CPU time 28.05 seconds
Started Aug 08 06:12:32 PM PDT 24
Finished Aug 08 06:13:00 PM PDT 24
Peak memory 218876 kb
Host smart-bd8561c8-e4d2-4398-8aac-487126731142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389195678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.3389195678
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.3024550369
Short name T12
Test name
Test status
Simulation time 22387771581 ps
CPU time 9.23 seconds
Started Aug 08 06:12:30 PM PDT 24
Finished Aug 08 06:12:39 PM PDT 24
Peak memory 217080 kb
Host smart-ac5af9e4-8d81-4d34-8ec0-ed5f5d934599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024550369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.3024550369
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.3655710535
Short name T604
Test name
Test status
Simulation time 862697430 ps
CPU time 3.13 seconds
Started Aug 08 06:12:34 PM PDT 24
Finished Aug 08 06:12:38 PM PDT 24
Peak memory 216912 kb
Host smart-f34cb942-2a8a-4a18-8760-c5331ececfaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655710535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.3655710535
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.340508678
Short name T69
Test name
Test status
Simulation time 21712825 ps
CPU time 0.69 seconds
Started Aug 08 06:12:34 PM PDT 24
Finished Aug 08 06:12:35 PM PDT 24
Peak memory 206060 kb
Host smart-5ae1f1cc-1f0d-4def-9a61-df04b643b84c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340508678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.340508678
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.587929146
Short name T468
Test name
Test status
Simulation time 6900785236 ps
CPU time 10.26 seconds
Started Aug 08 06:12:34 PM PDT 24
Finished Aug 08 06:12:44 PM PDT 24
Peak memory 241640 kb
Host smart-9104e018-4d94-427f-96bb-8ee4d584a13b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587929146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.587929146
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.655390678
Short name T476
Test name
Test status
Simulation time 44051159 ps
CPU time 0.76 seconds
Started Aug 08 06:12:46 PM PDT 24
Finished Aug 08 06:12:47 PM PDT 24
Peak memory 206260 kb
Host smart-806084d0-5c8f-4f26-8806-ba5ed43ebc1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655390678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.655390678
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.135317555
Short name T950
Test name
Test status
Simulation time 2055246507 ps
CPU time 6.12 seconds
Started Aug 08 06:12:38 PM PDT 24
Finished Aug 08 06:12:44 PM PDT 24
Peak memory 225228 kb
Host smart-15ea6e04-736b-469d-8ca2-20fffcecfe1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135317555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.135317555
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.3116154369
Short name T737
Test name
Test status
Simulation time 38954697 ps
CPU time 0.77 seconds
Started Aug 08 06:12:37 PM PDT 24
Finished Aug 08 06:12:38 PM PDT 24
Peak memory 207088 kb
Host smart-de5d607f-1c1b-43c2-9b46-afecddf1ba1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116154369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.3116154369
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.4055317549
Short name T461
Test name
Test status
Simulation time 25881298570 ps
CPU time 49.52 seconds
Started Aug 08 06:12:34 PM PDT 24
Finished Aug 08 06:13:24 PM PDT 24
Peak memory 238988 kb
Host smart-e5466fcf-0cc6-4cc9-a57e-045f1f5a3f1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055317549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.4055317549
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.223130125
Short name T286
Test name
Test status
Simulation time 23697050447 ps
CPU time 83.45 seconds
Started Aug 08 06:12:33 PM PDT 24
Finished Aug 08 06:13:56 PM PDT 24
Peak memory 249940 kb
Host smart-02dc9946-9b33-4ba4-8539-6762c096c3da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223130125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.223130125
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.4278466549
Short name T133
Test name
Test status
Simulation time 308503133 ps
CPU time 5.41 seconds
Started Aug 08 06:12:38 PM PDT 24
Finished Aug 08 06:12:44 PM PDT 24
Peak memory 241620 kb
Host smart-0f44b676-5db0-4c4e-b0aa-02b66e364565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278466549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.4278466549
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.910308771
Short name T56
Test name
Test status
Simulation time 1768406678 ps
CPU time 21.15 seconds
Started Aug 08 06:12:37 PM PDT 24
Finished Aug 08 06:12:58 PM PDT 24
Peak memory 239320 kb
Host smart-5dfb8b7b-9a7d-4c35-95a9-78f6f083aeb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910308771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmds
.910308771
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/43.spi_device_intercept.661611992
Short name T723
Test name
Test status
Simulation time 343168451 ps
CPU time 2.37 seconds
Started Aug 08 06:12:34 PM PDT 24
Finished Aug 08 06:12:37 PM PDT 24
Peak memory 225180 kb
Host smart-88aa2391-21fe-4c50-9cef-688bef52608d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661611992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.661611992
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.2255617797
Short name T320
Test name
Test status
Simulation time 201821496 ps
CPU time 2.31 seconds
Started Aug 08 06:12:34 PM PDT 24
Finished Aug 08 06:12:36 PM PDT 24
Peak memory 218220 kb
Host smart-1769128d-a65d-4b0e-9fb2-84c1b35fcbc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255617797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.2255617797
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.2579948938
Short name T985
Test name
Test status
Simulation time 25805785607 ps
CPU time 18.34 seconds
Started Aug 08 06:12:38 PM PDT 24
Finished Aug 08 06:12:56 PM PDT 24
Peak memory 225268 kb
Host smart-ac6f7f7d-7ee9-438a-834d-9605f767f1a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579948938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.2579948938
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.4134145190
Short name T903
Test name
Test status
Simulation time 585417481 ps
CPU time 6.95 seconds
Started Aug 08 06:12:34 PM PDT 24
Finished Aug 08 06:12:41 PM PDT 24
Peak memory 241408 kb
Host smart-96dd0340-bc65-4735-b2a9-f9cd2cd9e0cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134145190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.4134145190
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.4092753258
Short name T845
Test name
Test status
Simulation time 232118008 ps
CPU time 3.56 seconds
Started Aug 08 06:12:34 PM PDT 24
Finished Aug 08 06:12:38 PM PDT 24
Peak memory 219476 kb
Host smart-79479543-8d7a-4f67-a405-17b5bbfd24ae
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4092753258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.4092753258
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.2884262752
Short name T1006
Test name
Test status
Simulation time 112083018 ps
CPU time 1.09 seconds
Started Aug 08 06:12:38 PM PDT 24
Finished Aug 08 06:12:39 PM PDT 24
Peak memory 207624 kb
Host smart-df642ad8-d7f9-4efa-82a7-8c1b349b6a45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884262752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.2884262752
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.384531415
Short name T902
Test name
Test status
Simulation time 759567981 ps
CPU time 7.38 seconds
Started Aug 08 06:12:33 PM PDT 24
Finished Aug 08 06:12:40 PM PDT 24
Peak memory 219668 kb
Host smart-30358d50-2b43-400f-acf6-7ed54f53a36e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384531415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.384531415
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.3558220921
Short name T929
Test name
Test status
Simulation time 11004579336 ps
CPU time 28.16 seconds
Started Aug 08 06:12:37 PM PDT 24
Finished Aug 08 06:13:05 PM PDT 24
Peak memory 217028 kb
Host smart-8fd30b21-9e49-4417-ae37-e9f062add038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558220921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.3558220921
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.717827001
Short name T396
Test name
Test status
Simulation time 47997534 ps
CPU time 1.38 seconds
Started Aug 08 06:12:36 PM PDT 24
Finished Aug 08 06:12:38 PM PDT 24
Peak memory 216988 kb
Host smart-e23bd542-31c2-48cb-af67-054543d93a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717827001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.717827001
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.2000036753
Short name T653
Test name
Test status
Simulation time 537756676 ps
CPU time 0.84 seconds
Started Aug 08 06:12:33 PM PDT 24
Finished Aug 08 06:12:34 PM PDT 24
Peak memory 206500 kb
Host smart-908c256c-81dc-4ac2-be1b-86b5e8a0d89f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000036753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.2000036753
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.267659848
Short name T553
Test name
Test status
Simulation time 1042923805 ps
CPU time 6.64 seconds
Started Aug 08 06:12:37 PM PDT 24
Finished Aug 08 06:12:43 PM PDT 24
Peak memory 225200 kb
Host smart-2d8610d6-aade-4eb3-a6fb-b1bd74b859b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267659848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.267659848
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.1811640369
Short name T331
Test name
Test status
Simulation time 27651728 ps
CPU time 0.79 seconds
Started Aug 08 06:12:43 PM PDT 24
Finished Aug 08 06:12:44 PM PDT 24
Peak memory 206144 kb
Host smart-d9ba5cdd-e302-4e07-af49-577c89ee9719
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811640369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
1811640369
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.3878675454
Short name T873
Test name
Test status
Simulation time 710683991 ps
CPU time 6.59 seconds
Started Aug 08 06:12:46 PM PDT 24
Finished Aug 08 06:12:53 PM PDT 24
Peak memory 225180 kb
Host smart-6f3dfd95-7dc3-442e-93f3-9f2375467159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878675454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.3878675454
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.3483427553
Short name T618
Test name
Test status
Simulation time 66321089 ps
CPU time 0.76 seconds
Started Aug 08 06:12:42 PM PDT 24
Finished Aug 08 06:12:43 PM PDT 24
Peak memory 206064 kb
Host smart-ccb18e44-2208-4d02-9853-58a34ddea71e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483427553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.3483427553
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.2378568353
Short name T369
Test name
Test status
Simulation time 39441073556 ps
CPU time 109.22 seconds
Started Aug 08 06:12:46 PM PDT 24
Finished Aug 08 06:14:36 PM PDT 24
Peak memory 264160 kb
Host smart-90294b7e-0423-4748-a4b5-b8be43f2b522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378568353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.2378568353
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.215314279
Short name T217
Test name
Test status
Simulation time 25346864379 ps
CPU time 208.57 seconds
Started Aug 08 06:12:47 PM PDT 24
Finished Aug 08 06:16:16 PM PDT 24
Peak memory 250284 kb
Host smart-2f5c23ca-01d7-4da6-93d2-02820a1d52eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215314279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idle
.215314279
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.603109030
Short name T825
Test name
Test status
Simulation time 1097338468 ps
CPU time 10.62 seconds
Started Aug 08 06:12:43 PM PDT 24
Finished Aug 08 06:12:53 PM PDT 24
Peak memory 233460 kb
Host smart-0cb43ea0-dcc7-4ba5-a5fb-7d58e3210404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603109030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.603109030
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.3790230807
Short name T593
Test name
Test status
Simulation time 10285988788 ps
CPU time 58.51 seconds
Started Aug 08 06:12:43 PM PDT 24
Finished Aug 08 06:13:42 PM PDT 24
Peak memory 250908 kb
Host smart-5ec2f89a-f306-47d6-b102-572ab35ccb85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790230807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmd
s.3790230807
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/44.spi_device_intercept.2662353044
Short name T814
Test name
Test status
Simulation time 1598139355 ps
CPU time 4.3 seconds
Started Aug 08 06:12:42 PM PDT 24
Finished Aug 08 06:12:46 PM PDT 24
Peak memory 225256 kb
Host smart-6b758b53-b4ca-47ad-9c51-945fa617b1e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662353044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.2662353044
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.113903870
Short name T1013
Test name
Test status
Simulation time 266808875 ps
CPU time 5.69 seconds
Started Aug 08 06:12:42 PM PDT 24
Finished Aug 08 06:12:47 PM PDT 24
Peak memory 233524 kb
Host smart-a5600306-ac3c-42c2-804a-58b55eb6b3c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113903870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.113903870
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.235375882
Short name T258
Test name
Test status
Simulation time 3336742667 ps
CPU time 3.81 seconds
Started Aug 08 06:12:43 PM PDT 24
Finished Aug 08 06:12:47 PM PDT 24
Peak memory 225240 kb
Host smart-e21ffd33-fe05-4e54-9900-f4f74adad7d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235375882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swap
.235375882
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.1679282957
Short name T585
Test name
Test status
Simulation time 1569363356 ps
CPU time 6.39 seconds
Started Aug 08 06:12:47 PM PDT 24
Finished Aug 08 06:12:54 PM PDT 24
Peak memory 233496 kb
Host smart-ae3b6708-c893-43d5-b334-a28dc1b57eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679282957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.1679282957
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.2413561124
Short name T789
Test name
Test status
Simulation time 239356610 ps
CPU time 3.5 seconds
Started Aug 08 06:12:45 PM PDT 24
Finished Aug 08 06:12:48 PM PDT 24
Peak memory 219820 kb
Host smart-79f94f87-4d37-4621-a7b9-95ff26a3cc82
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2413561124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.2413561124
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.2660255693
Short name T20
Test name
Test status
Simulation time 134943470620 ps
CPU time 336.01 seconds
Started Aug 08 06:12:42 PM PDT 24
Finished Aug 08 06:18:18 PM PDT 24
Peak memory 251280 kb
Host smart-a375d52c-4599-4b26-b79d-23611181b7ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660255693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.2660255693
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.1068995213
Short name T850
Test name
Test status
Simulation time 13916512661 ps
CPU time 22.32 seconds
Started Aug 08 06:12:42 PM PDT 24
Finished Aug 08 06:13:04 PM PDT 24
Peak memory 221336 kb
Host smart-ed3324d9-a55c-4287-96c1-99d417688363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068995213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.1068995213
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.2219296382
Short name T420
Test name
Test status
Simulation time 3622486767 ps
CPU time 5.89 seconds
Started Aug 08 06:12:45 PM PDT 24
Finished Aug 08 06:12:51 PM PDT 24
Peak memory 216988 kb
Host smart-7b16cff2-65f2-4c62-a001-be21eef06191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219296382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.2219296382
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.491871084
Short name T152
Test name
Test status
Simulation time 274222153 ps
CPU time 2.87 seconds
Started Aug 08 06:12:46 PM PDT 24
Finished Aug 08 06:12:49 PM PDT 24
Peak memory 216956 kb
Host smart-e7d758a5-0406-46f1-976f-47e7f850f82c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491871084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.491871084
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.1027891487
Short name T370
Test name
Test status
Simulation time 113576540 ps
CPU time 0.87 seconds
Started Aug 08 06:12:43 PM PDT 24
Finished Aug 08 06:12:44 PM PDT 24
Peak memory 206584 kb
Host smart-0af00208-3ffa-4ebf-888f-b808727e8bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027891487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.1027891487
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.2961671996
Short name T245
Test name
Test status
Simulation time 3332684263 ps
CPU time 10.39 seconds
Started Aug 08 06:12:45 PM PDT 24
Finished Aug 08 06:12:55 PM PDT 24
Peak memory 225100 kb
Host smart-a2454b68-becf-4f9a-8db3-221e2b299065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961671996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.2961671996
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.4286456662
Short name T498
Test name
Test status
Simulation time 14581423 ps
CPU time 0.74 seconds
Started Aug 08 06:12:45 PM PDT 24
Finished Aug 08 06:12:45 PM PDT 24
Peak memory 206252 kb
Host smart-64f2ff7d-6c6b-43ce-81bf-7c9038487fd5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286456662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
4286456662
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.1124619811
Short name T98
Test name
Test status
Simulation time 31147991179 ps
CPU time 15.54 seconds
Started Aug 08 06:12:41 PM PDT 24
Finished Aug 08 06:12:57 PM PDT 24
Peak memory 233448 kb
Host smart-882bac35-5349-4385-938f-822ee4364ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124619811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.1124619811
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.2883286304
Short name T720
Test name
Test status
Simulation time 54026249 ps
CPU time 0.76 seconds
Started Aug 08 06:12:43 PM PDT 24
Finished Aug 08 06:12:44 PM PDT 24
Peak memory 207036 kb
Host smart-2ba105a5-d39a-4d6f-a9b4-457389e11733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883286304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.2883286304
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.2834970179
Short name T820
Test name
Test status
Simulation time 960459572 ps
CPU time 17.84 seconds
Started Aug 08 06:12:46 PM PDT 24
Finished Aug 08 06:13:04 PM PDT 24
Peak memory 241268 kb
Host smart-cb9b1955-ae10-4e82-887e-cf9c3f9378e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834970179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.2834970179
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.2898927825
Short name T465
Test name
Test status
Simulation time 2539554650 ps
CPU time 49.6 seconds
Started Aug 08 06:12:48 PM PDT 24
Finished Aug 08 06:13:38 PM PDT 24
Peak memory 241296 kb
Host smart-a3a5f06e-38e0-4a55-9de8-2b0112412195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898927825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.2898927825
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.2211628244
Short name T164
Test name
Test status
Simulation time 4457878685 ps
CPU time 55.51 seconds
Started Aug 08 06:12:46 PM PDT 24
Finished Aug 08 06:13:41 PM PDT 24
Peak memory 249400 kb
Host smart-2094dd48-0431-4648-b321-f4477d5584e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211628244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.2211628244
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.2465046620
Short name T577
Test name
Test status
Simulation time 2241817964 ps
CPU time 6.23 seconds
Started Aug 08 06:12:42 PM PDT 24
Finished Aug 08 06:12:48 PM PDT 24
Peak memory 225320 kb
Host smart-4e59fc82-4e15-48c0-8beb-ada68cb8138c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465046620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.2465046620
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_intercept.2873952298
Short name T267
Test name
Test status
Simulation time 266221521 ps
CPU time 4.61 seconds
Started Aug 08 06:12:41 PM PDT 24
Finished Aug 08 06:12:46 PM PDT 24
Peak memory 233492 kb
Host smart-e3906bc7-4a50-454d-8077-49386fe68887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873952298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.2873952298
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.1126039800
Short name T485
Test name
Test status
Simulation time 6019723610 ps
CPU time 41.53 seconds
Started Aug 08 06:12:46 PM PDT 24
Finished Aug 08 06:13:28 PM PDT 24
Peak memory 233460 kb
Host smart-de24176d-cc91-4ace-bc8b-00dfdf5f8535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126039800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.1126039800
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.473457295
Short name T523
Test name
Test status
Simulation time 970623080 ps
CPU time 8.58 seconds
Started Aug 08 06:12:45 PM PDT 24
Finished Aug 08 06:12:53 PM PDT 24
Peak memory 233476 kb
Host smart-9fd2721d-c0eb-47ef-b78d-dd1147fa91c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473457295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swap
.473457295
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.2696089197
Short name T918
Test name
Test status
Simulation time 109781056 ps
CPU time 2.52 seconds
Started Aug 08 06:12:41 PM PDT 24
Finished Aug 08 06:12:43 PM PDT 24
Peak memory 233420 kb
Host smart-d328f45d-b324-404e-88d3-e3abba0561ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696089197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.2696089197
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.1876341658
Short name T635
Test name
Test status
Simulation time 722989912 ps
CPU time 3.31 seconds
Started Aug 08 06:12:41 PM PDT 24
Finished Aug 08 06:12:44 PM PDT 24
Peak memory 222500 kb
Host smart-fd447ff0-95c2-49c4-9f00-3b78ca469cb4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1876341658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.1876341658
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.3536021164
Short name T21
Test name
Test status
Simulation time 107885048 ps
CPU time 1.09 seconds
Started Aug 08 06:12:43 PM PDT 24
Finished Aug 08 06:12:44 PM PDT 24
Peak memory 207524 kb
Host smart-6e47edca-0759-48bc-b126-3ccf33df653d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536021164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.3536021164
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.2768157315
Short name T494
Test name
Test status
Simulation time 5912642776 ps
CPU time 25.61 seconds
Started Aug 08 06:12:45 PM PDT 24
Finished Aug 08 06:13:10 PM PDT 24
Peak memory 221660 kb
Host smart-78bba765-e949-4d2b-a3e6-6090dd3410f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768157315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.2768157315
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.1309033789
Short name T27
Test name
Test status
Simulation time 1302861254 ps
CPU time 5.33 seconds
Started Aug 08 06:12:40 PM PDT 24
Finished Aug 08 06:12:46 PM PDT 24
Peak memory 216904 kb
Host smart-df938f12-6cee-4277-9503-b81252bae6c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309033789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.1309033789
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.2374483237
Short name T1005
Test name
Test status
Simulation time 91085980 ps
CPU time 2.45 seconds
Started Aug 08 06:12:43 PM PDT 24
Finished Aug 08 06:12:46 PM PDT 24
Peak memory 216972 kb
Host smart-fd6ea52c-4fed-4b35-8df9-ff8b0c5232bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374483237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.2374483237
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.1045854021
Short name T589
Test name
Test status
Simulation time 42331793 ps
CPU time 0.7 seconds
Started Aug 08 06:12:42 PM PDT 24
Finished Aug 08 06:12:43 PM PDT 24
Peak memory 206100 kb
Host smart-21ac0d45-06d0-4e3e-b7f3-93136c321475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045854021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.1045854021
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.4120284665
Short name T202
Test name
Test status
Simulation time 4331008055 ps
CPU time 7.73 seconds
Started Aug 08 06:12:42 PM PDT 24
Finished Aug 08 06:12:50 PM PDT 24
Peak memory 225328 kb
Host smart-a1dfef08-0d48-4978-8019-cac88c167db1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120284665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.4120284665
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.1522440637
Short name T913
Test name
Test status
Simulation time 15717926 ps
CPU time 0.71 seconds
Started Aug 08 06:12:54 PM PDT 24
Finished Aug 08 06:12:54 PM PDT 24
Peak memory 205336 kb
Host smart-c03b0681-771e-4473-87e0-083364109ed7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522440637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
1522440637
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.1035233522
Short name T248
Test name
Test status
Simulation time 1263650556 ps
CPU time 17 seconds
Started Aug 08 06:12:48 PM PDT 24
Finished Aug 08 06:13:05 PM PDT 24
Peak memory 233456 kb
Host smart-969732f1-2ddc-44d1-97e6-2b6f2a551b9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035233522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.1035233522
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.3459537071
Short name T60
Test name
Test status
Simulation time 24463968 ps
CPU time 0.82 seconds
Started Aug 08 06:12:48 PM PDT 24
Finished Aug 08 06:12:49 PM PDT 24
Peak memory 207052 kb
Host smart-fb0d7798-62ad-4e79-a8b0-6f60a268221c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459537071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.3459537071
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.2658403487
Short name T291
Test name
Test status
Simulation time 38022824681 ps
CPU time 191.95 seconds
Started Aug 08 06:12:46 PM PDT 24
Finished Aug 08 06:15:58 PM PDT 24
Peak memory 250264 kb
Host smart-bd014c1a-d684-4614-9d09-116872de3145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658403487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.2658403487
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.765339763
Short name T920
Test name
Test status
Simulation time 86401816961 ps
CPU time 140.61 seconds
Started Aug 08 06:12:54 PM PDT 24
Finished Aug 08 06:15:15 PM PDT 24
Peak memory 256972 kb
Host smart-351d86d3-9089-49dd-8acd-938f6a37fd04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765339763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.765339763
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.520014347
Short name T71
Test name
Test status
Simulation time 17653846552 ps
CPU time 57.84 seconds
Started Aug 08 06:12:55 PM PDT 24
Finished Aug 08 06:13:53 PM PDT 24
Peak memory 252788 kb
Host smart-4f8e61d5-d0db-417b-b1a4-1f8f1afb65ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520014347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idle
.520014347
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.3855204108
Short name T500
Test name
Test status
Simulation time 6756926567 ps
CPU time 27.6 seconds
Started Aug 08 06:12:48 PM PDT 24
Finished Aug 08 06:13:16 PM PDT 24
Peak memory 234796 kb
Host smart-685030c9-c639-4e40-ab54-4a6d76f1c82c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855204108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.3855204108
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.3732019616
Short name T273
Test name
Test status
Simulation time 11435270015 ps
CPU time 144.27 seconds
Started Aug 08 06:12:42 PM PDT 24
Finished Aug 08 06:15:07 PM PDT 24
Peak memory 265312 kb
Host smart-92fa7bbb-bbe9-44c8-8a88-38026c72b645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732019616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmd
s.3732019616
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_intercept.1559061991
Short name T410
Test name
Test status
Simulation time 908043221 ps
CPU time 7.59 seconds
Started Aug 08 06:12:44 PM PDT 24
Finished Aug 08 06:12:52 PM PDT 24
Peak memory 225180 kb
Host smart-8f068e03-2497-4330-8a85-3032dc988d5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559061991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.1559061991
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.930427243
Short name T847
Test name
Test status
Simulation time 13926521724 ps
CPU time 51.68 seconds
Started Aug 08 06:12:42 PM PDT 24
Finished Aug 08 06:13:34 PM PDT 24
Peak memory 241636 kb
Host smart-196de755-e365-4260-88fe-0024f3c291c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930427243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.930427243
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.2259636254
Short name T764
Test name
Test status
Simulation time 262892235 ps
CPU time 4.24 seconds
Started Aug 08 06:12:46 PM PDT 24
Finished Aug 08 06:12:51 PM PDT 24
Peak memory 233456 kb
Host smart-c05cde1a-d9b4-4ec5-abe9-98b81379d066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259636254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.2259636254
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.486319672
Short name T222
Test name
Test status
Simulation time 1995280478 ps
CPU time 5.73 seconds
Started Aug 08 06:12:48 PM PDT 24
Finished Aug 08 06:12:54 PM PDT 24
Peak memory 225252 kb
Host smart-a14b3476-f5ea-49f0-b4de-8c23e8bf4632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486319672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.486319672
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.3781293811
Short name T938
Test name
Test status
Simulation time 1645843782 ps
CPU time 9.81 seconds
Started Aug 08 06:12:46 PM PDT 24
Finished Aug 08 06:12:55 PM PDT 24
Peak memory 218828 kb
Host smart-9dd02edb-0906-4f92-9e1e-f6edc31bd153
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3781293811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.3781293811
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.1633006910
Short name T843
Test name
Test status
Simulation time 1578812260 ps
CPU time 8.74 seconds
Started Aug 08 06:12:47 PM PDT 24
Finished Aug 08 06:12:56 PM PDT 24
Peak memory 217048 kb
Host smart-fda84295-dc21-4303-8039-e873baa7d0ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633006910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.1633006910
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.3912209565
Short name T13
Test name
Test status
Simulation time 1795139480 ps
CPU time 3.29 seconds
Started Aug 08 06:12:43 PM PDT 24
Finished Aug 08 06:12:47 PM PDT 24
Peak memory 216736 kb
Host smart-98d01060-efd9-4034-837c-9e10f77572ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912209565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.3912209565
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.3045609317
Short name T442
Test name
Test status
Simulation time 37262242 ps
CPU time 0.83 seconds
Started Aug 08 06:12:46 PM PDT 24
Finished Aug 08 06:12:47 PM PDT 24
Peak memory 206596 kb
Host smart-ef38db41-21af-4197-b632-70ab4829d265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045609317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.3045609317
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.2060000390
Short name T651
Test name
Test status
Simulation time 25336241 ps
CPU time 0.68 seconds
Started Aug 08 06:12:43 PM PDT 24
Finished Aug 08 06:12:43 PM PDT 24
Peak memory 206120 kb
Host smart-44f80a53-b0a7-4712-8221-7f7f53fcd2ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060000390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.2060000390
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.708809416
Short name T941
Test name
Test status
Simulation time 1655783080 ps
CPU time 5.42 seconds
Started Aug 08 06:12:46 PM PDT 24
Finished Aug 08 06:12:51 PM PDT 24
Peak memory 233412 kb
Host smart-df7461ed-3dd7-4955-b2f3-bce01e044627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708809416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.708809416
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.2137081844
Short name T905
Test name
Test status
Simulation time 33002124 ps
CPU time 0.69 seconds
Started Aug 08 06:12:56 PM PDT 24
Finished Aug 08 06:12:57 PM PDT 24
Peak memory 205880 kb
Host smart-86c7b996-23a3-4247-a2cc-9aab307cbd36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137081844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
2137081844
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.2180253842
Short name T533
Test name
Test status
Simulation time 52524561 ps
CPU time 2.44 seconds
Started Aug 08 06:12:55 PM PDT 24
Finished Aug 08 06:12:57 PM PDT 24
Peak memory 233432 kb
Host smart-a7d532b1-4472-4159-8224-ecc5ed68f9c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180253842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.2180253842
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.3485991355
Short name T425
Test name
Test status
Simulation time 15554508 ps
CPU time 0.75 seconds
Started Aug 08 06:12:56 PM PDT 24
Finished Aug 08 06:12:57 PM PDT 24
Peak memory 206372 kb
Host smart-2d98e1bc-b913-4118-981d-5a29f8f81d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485991355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.3485991355
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.4198400726
Short name T395
Test name
Test status
Simulation time 18239882 ps
CPU time 0.79 seconds
Started Aug 08 06:12:54 PM PDT 24
Finished Aug 08 06:12:55 PM PDT 24
Peak memory 216460 kb
Host smart-3a1d47e7-b845-4d59-a053-3d603f5ee2b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198400726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.4198400726
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.631616352
Short name T281
Test name
Test status
Simulation time 34315733439 ps
CPU time 223.74 seconds
Started Aug 08 06:12:55 PM PDT 24
Finished Aug 08 06:16:39 PM PDT 24
Peak memory 255484 kb
Host smart-7228002f-6217-41a4-927f-2ace01f0d260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631616352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.631616352
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.1658917305
Short name T834
Test name
Test status
Simulation time 24415656394 ps
CPU time 158.99 seconds
Started Aug 08 06:12:56 PM PDT 24
Finished Aug 08 06:15:35 PM PDT 24
Peak memory 258168 kb
Host smart-9bdda5db-a24c-4335-9f90-058ee380054a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658917305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.1658917305
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.2200735217
Short name T579
Test name
Test status
Simulation time 96164069 ps
CPU time 3.43 seconds
Started Aug 08 06:12:55 PM PDT 24
Finished Aug 08 06:12:59 PM PDT 24
Peak memory 225296 kb
Host smart-54ca26cc-f4ca-4ecd-b10e-a2b7150efcc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200735217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.2200735217
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.1859761931
Short name T262
Test name
Test status
Simulation time 1969655612 ps
CPU time 27.25 seconds
Started Aug 08 06:12:56 PM PDT 24
Finished Aug 08 06:13:24 PM PDT 24
Peak memory 237012 kb
Host smart-513f6599-d56b-4011-ab7b-6dfc651796dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859761931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmd
s.1859761931
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/47.spi_device_intercept.1964360509
Short name T976
Test name
Test status
Simulation time 176156276 ps
CPU time 4.27 seconds
Started Aug 08 06:12:54 PM PDT 24
Finished Aug 08 06:12:59 PM PDT 24
Peak memory 233400 kb
Host smart-f3764510-e412-42e8-b69b-514dd7c3150b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964360509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.1964360509
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.506175808
Short name T516
Test name
Test status
Simulation time 7221361802 ps
CPU time 38.89 seconds
Started Aug 08 06:12:56 PM PDT 24
Finished Aug 08 06:13:35 PM PDT 24
Peak memory 225380 kb
Host smart-fe19d5f0-310b-4eed-aa39-249128ae221b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506175808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.506175808
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.1143574299
Short name T58
Test name
Test status
Simulation time 12064202505 ps
CPU time 26.6 seconds
Started Aug 08 06:12:56 PM PDT 24
Finished Aug 08 06:13:22 PM PDT 24
Peak memory 233544 kb
Host smart-ca4c5e3b-9f5b-4a83-bf6a-40e8c1f4784c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143574299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.1143574299
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.3104976445
Short name T540
Test name
Test status
Simulation time 1388616785 ps
CPU time 5.76 seconds
Started Aug 08 06:12:55 PM PDT 24
Finished Aug 08 06:13:01 PM PDT 24
Peak memory 225216 kb
Host smart-9042e93d-04e5-4a71-8b6a-df73ebfa884a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104976445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.3104976445
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.2234453559
Short name T489
Test name
Test status
Simulation time 4332140639 ps
CPU time 7.06 seconds
Started Aug 08 06:12:56 PM PDT 24
Finished Aug 08 06:13:03 PM PDT 24
Peak memory 219488 kb
Host smart-e1405425-8a72-476a-b76c-5ed704e285cc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2234453559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.2234453559
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.3208181162
Short name T892
Test name
Test status
Simulation time 154389136 ps
CPU time 1 seconds
Started Aug 08 06:12:57 PM PDT 24
Finished Aug 08 06:12:58 PM PDT 24
Peak memory 216524 kb
Host smart-29a9c0bf-be0b-4ee8-9165-c72188bbb5ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208181162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.3208181162
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.2033005469
Short name T309
Test name
Test status
Simulation time 4449373897 ps
CPU time 24.39 seconds
Started Aug 08 06:12:54 PM PDT 24
Finished Aug 08 06:13:18 PM PDT 24
Peak memory 217132 kb
Host smart-e2acd43f-0cf2-4478-9d44-7bb8c7ce8491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033005469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.2033005469
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.4118722691
Short name T599
Test name
Test status
Simulation time 6029162304 ps
CPU time 6.24 seconds
Started Aug 08 06:12:56 PM PDT 24
Finished Aug 08 06:13:02 PM PDT 24
Peak memory 217044 kb
Host smart-f143f2fb-661d-41f0-9627-18d6dbb06557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118722691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.4118722691
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.3222309448
Short name T798
Test name
Test status
Simulation time 162918457 ps
CPU time 4.86 seconds
Started Aug 08 06:12:56 PM PDT 24
Finished Aug 08 06:13:01 PM PDT 24
Peak memory 216976 kb
Host smart-2456347a-8021-47bb-9c70-ed60b26ea5c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222309448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.3222309448
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.786266319
Short name T448
Test name
Test status
Simulation time 52140288 ps
CPU time 0.84 seconds
Started Aug 08 06:12:54 PM PDT 24
Finished Aug 08 06:12:55 PM PDT 24
Peak memory 206760 kb
Host smart-8beea0c6-b714-4cfe-a5a0-ac46c2b0b468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786266319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.786266319
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.71486878
Short name T718
Test name
Test status
Simulation time 2985558219 ps
CPU time 12.95 seconds
Started Aug 08 06:12:56 PM PDT 24
Finished Aug 08 06:13:09 PM PDT 24
Peak memory 240588 kb
Host smart-2a6d2307-a934-49b0-933b-9f8f7f41cc47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71486878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.71486878
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.4196803264
Short name T5
Test name
Test status
Simulation time 20415342 ps
CPU time 0.73 seconds
Started Aug 08 06:12:55 PM PDT 24
Finished Aug 08 06:12:56 PM PDT 24
Peak memory 205256 kb
Host smart-a8eace1f-cd2c-452a-af96-a09ab1775cce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196803264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
4196803264
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.3192517130
Short name T81
Test name
Test status
Simulation time 61186811 ps
CPU time 2.71 seconds
Started Aug 08 06:12:53 PM PDT 24
Finished Aug 08 06:12:56 PM PDT 24
Peak memory 233408 kb
Host smart-25e4926a-1270-48af-8b2f-117696a3f7eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192517130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.3192517130
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.1554754158
Short name T378
Test name
Test status
Simulation time 33385329 ps
CPU time 0.77 seconds
Started Aug 08 06:12:56 PM PDT 24
Finished Aug 08 06:12:56 PM PDT 24
Peak memory 206040 kb
Host smart-80e1896a-dea2-4e1c-b7de-adfeef822f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554754158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.1554754158
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.168237671
Short name T1009
Test name
Test status
Simulation time 9548639979 ps
CPU time 66.35 seconds
Started Aug 08 06:12:59 PM PDT 24
Finished Aug 08 06:14:05 PM PDT 24
Peak memory 251832 kb
Host smart-8b6ce3f1-0341-4fcb-bf70-e3b0cbe58299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168237671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.168237671
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.3206275581
Short name T966
Test name
Test status
Simulation time 8293822713 ps
CPU time 44.09 seconds
Started Aug 08 06:12:54 PM PDT 24
Finished Aug 08 06:13:38 PM PDT 24
Peak memory 255888 kb
Host smart-c40b12cb-57de-4b35-ab4c-bf6ecd118d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206275581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.3206275581
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.3859862807
Short name T52
Test name
Test status
Simulation time 72426604255 ps
CPU time 64.05 seconds
Started Aug 08 06:12:54 PM PDT 24
Finished Aug 08 06:13:58 PM PDT 24
Peak memory 240168 kb
Host smart-e0550ce2-1896-4340-a4d0-ddb1b25668d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859862807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.3859862807
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.3609944272
Short name T953
Test name
Test status
Simulation time 135533897 ps
CPU time 2.73 seconds
Started Aug 08 06:12:54 PM PDT 24
Finished Aug 08 06:12:57 PM PDT 24
Peak memory 233404 kb
Host smart-9de40d1e-257b-48d2-9d24-1ab945e02182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609944272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.3609944272
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.1328686425
Short name T806
Test name
Test status
Simulation time 70136438329 ps
CPU time 153.17 seconds
Started Aug 08 06:12:57 PM PDT 24
Finished Aug 08 06:15:30 PM PDT 24
Peak memory 249932 kb
Host smart-e2137dcf-8fc7-4a29-805b-22f6abdd13d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328686425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmd
s.1328686425
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/48.spi_device_intercept.1099859370
Short name T686
Test name
Test status
Simulation time 46757009936 ps
CPU time 32.2 seconds
Started Aug 08 06:12:55 PM PDT 24
Finished Aug 08 06:13:27 PM PDT 24
Peak memory 225208 kb
Host smart-7b14e0c9-a3f9-4bc5-be94-a1137e7aaff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099859370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.1099859370
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.2673387612
Short name T350
Test name
Test status
Simulation time 32846437 ps
CPU time 2.55 seconds
Started Aug 08 06:12:58 PM PDT 24
Finished Aug 08 06:13:00 PM PDT 24
Peak memory 233108 kb
Host smart-0e9d8789-a0c4-46e9-8312-0655f15066b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673387612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.2673387612
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.4268730943
Short name T284
Test name
Test status
Simulation time 57261172199 ps
CPU time 25.06 seconds
Started Aug 08 06:12:54 PM PDT 24
Finished Aug 08 06:13:19 PM PDT 24
Peak memory 234380 kb
Host smart-f6b20543-bba6-478b-b76d-65fbde0b22ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268730943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.4268730943
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.3121930528
Short name T910
Test name
Test status
Simulation time 413050841 ps
CPU time 3.39 seconds
Started Aug 08 06:12:55 PM PDT 24
Finished Aug 08 06:12:58 PM PDT 24
Peak memory 235832 kb
Host smart-3ae14224-20d0-4652-a33b-7ce7f0c178bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121930528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.3121930528
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.1322597541
Short name T391
Test name
Test status
Simulation time 273030576 ps
CPU time 3.42 seconds
Started Aug 08 06:12:55 PM PDT 24
Finished Aug 08 06:12:58 PM PDT 24
Peak memory 219796 kb
Host smart-767679c9-eab9-494d-8fe9-5b9aa2e92d2c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1322597541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.1322597541
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.3164185788
Short name T198
Test name
Test status
Simulation time 30949991736 ps
CPU time 291.06 seconds
Started Aug 08 06:12:54 PM PDT 24
Finished Aug 08 06:17:45 PM PDT 24
Peak memory 264964 kb
Host smart-c8bafef5-e450-4128-8849-d572e148887d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164185788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.3164185788
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.2488383507
Short name T958
Test name
Test status
Simulation time 1355699673 ps
CPU time 3.59 seconds
Started Aug 08 06:12:58 PM PDT 24
Finished Aug 08 06:13:01 PM PDT 24
Peak memory 217360 kb
Host smart-04dd380d-3803-473b-b59a-a06f0b0bb4d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488383507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.2488383507
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.1700486239
Short name T344
Test name
Test status
Simulation time 9566062139 ps
CPU time 7.28 seconds
Started Aug 08 06:12:56 PM PDT 24
Finished Aug 08 06:13:03 PM PDT 24
Peak memory 217016 kb
Host smart-aaa87935-fec6-4d23-9fbe-2fce35776f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700486239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.1700486239
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.4173513798
Short name T495
Test name
Test status
Simulation time 89762038 ps
CPU time 1.32 seconds
Started Aug 08 06:12:57 PM PDT 24
Finished Aug 08 06:12:58 PM PDT 24
Peak memory 216996 kb
Host smart-c019470c-dfa2-49c0-b94b-3282e98cb25a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173513798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.4173513798
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.1797092648
Short name T676
Test name
Test status
Simulation time 263942607 ps
CPU time 0.78 seconds
Started Aug 08 06:12:54 PM PDT 24
Finished Aug 08 06:12:55 PM PDT 24
Peak memory 206584 kb
Host smart-817ffd93-c986-42b2-89ca-90083e07c955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797092648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.1797092648
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.1693506473
Short name T134
Test name
Test status
Simulation time 270169742 ps
CPU time 2.43 seconds
Started Aug 08 06:12:53 PM PDT 24
Finished Aug 08 06:12:55 PM PDT 24
Peak memory 224928 kb
Host smart-d1327230-07cf-4747-a86c-53ea9f9d6f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693506473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.1693506473
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.121802317
Short name T2
Test name
Test status
Simulation time 43740134 ps
CPU time 0.73 seconds
Started Aug 08 06:13:01 PM PDT 24
Finished Aug 08 06:13:02 PM PDT 24
Peak memory 205264 kb
Host smart-a1e24cdc-40ba-4243-871e-0a5de26b08ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121802317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.121802317
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.471307858
Short name T454
Test name
Test status
Simulation time 1060503490 ps
CPU time 3.19 seconds
Started Aug 08 06:13:00 PM PDT 24
Finished Aug 08 06:13:03 PM PDT 24
Peak memory 225220 kb
Host smart-64daab47-8f2e-4c68-b447-e379d4d8c95e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471307858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.471307858
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.2196641669
Short name T781
Test name
Test status
Simulation time 22102807 ps
CPU time 0.74 seconds
Started Aug 08 06:12:56 PM PDT 24
Finished Aug 08 06:12:57 PM PDT 24
Peak memory 206956 kb
Host smart-d54fdd82-bce3-4bb1-90a5-db476e0be569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196641669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.2196641669
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.2152990467
Short name T199
Test name
Test status
Simulation time 17142922131 ps
CPU time 203.45 seconds
Started Aug 08 06:13:02 PM PDT 24
Finished Aug 08 06:16:25 PM PDT 24
Peak memory 267236 kb
Host smart-20df83fb-fadd-4270-919c-34843177ac8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152990467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.2152990467
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.3461229084
Short name T544
Test name
Test status
Simulation time 7347764302 ps
CPU time 120.9 seconds
Started Aug 08 06:13:02 PM PDT 24
Finished Aug 08 06:15:03 PM PDT 24
Peak memory 257592 kb
Host smart-e555349b-f8c9-406d-9de2-4b226b26d60a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461229084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.3461229084
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.548911325
Short name T298
Test name
Test status
Simulation time 967752049 ps
CPU time 12.83 seconds
Started Aug 08 06:13:01 PM PDT 24
Finished Aug 08 06:13:14 PM PDT 24
Peak memory 225276 kb
Host smart-b6647a3d-bdaf-42b9-b43d-82c6944dcb72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548911325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.548911325
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.2070800089
Short name T733
Test name
Test status
Simulation time 3335556053 ps
CPU time 74.91 seconds
Started Aug 08 06:13:01 PM PDT 24
Finished Aug 08 06:14:16 PM PDT 24
Peak memory 262184 kb
Host smart-6d2d3ffb-fcb7-4b0f-acfb-ae531fcd1d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070800089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmd
s.2070800089
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/49.spi_device_intercept.2477836860
Short name T787
Test name
Test status
Simulation time 1594159066 ps
CPU time 8.97 seconds
Started Aug 08 06:13:01 PM PDT 24
Finished Aug 08 06:13:10 PM PDT 24
Peak memory 225144 kb
Host smart-71c46332-0606-4982-bbc7-51c80e67609c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477836860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.2477836860
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.3195611176
Short name T85
Test name
Test status
Simulation time 615248705 ps
CPU time 11.31 seconds
Started Aug 08 06:13:04 PM PDT 24
Finished Aug 08 06:13:16 PM PDT 24
Peak memory 235076 kb
Host smart-81eaf237-a885-44c0-a86a-cf113adb23c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195611176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.3195611176
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.2567524328
Short name T869
Test name
Test status
Simulation time 226628282 ps
CPU time 2.72 seconds
Started Aug 08 06:13:03 PM PDT 24
Finished Aug 08 06:13:06 PM PDT 24
Peak memory 225124 kb
Host smart-b3bf93e3-4d81-44c4-b32b-b2d931036420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567524328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.2567524328
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.498564987
Short name T743
Test name
Test status
Simulation time 406929386 ps
CPU time 6.03 seconds
Started Aug 08 06:13:03 PM PDT 24
Finished Aug 08 06:13:09 PM PDT 24
Peak memory 225180 kb
Host smart-a19f6c4e-9be9-4b38-b197-d523a8f9c9d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498564987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.498564987
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.4228481385
Short name T399
Test name
Test status
Simulation time 177754498 ps
CPU time 3.82 seconds
Started Aug 08 06:13:03 PM PDT 24
Finished Aug 08 06:13:06 PM PDT 24
Peak memory 219936 kb
Host smart-bf8bfd8a-e67d-4c8c-8410-7060fd33f93b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4228481385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.4228481385
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.4048409346
Short name T936
Test name
Test status
Simulation time 236490985 ps
CPU time 1.14 seconds
Started Aug 08 06:13:04 PM PDT 24
Finished Aug 08 06:13:05 PM PDT 24
Peak memory 207408 kb
Host smart-9117b7f4-cc70-426c-96dd-0803088fd170
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048409346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.4048409346
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.2793769919
Short name T310
Test name
Test status
Simulation time 3338838814 ps
CPU time 5.83 seconds
Started Aug 08 06:12:56 PM PDT 24
Finished Aug 08 06:13:01 PM PDT 24
Peak memory 217068 kb
Host smart-33f84dbe-a262-45cd-8c81-6aad4137dc8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793769919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.2793769919
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.4060335557
Short name T1012
Test name
Test status
Simulation time 36955100190 ps
CPU time 17.48 seconds
Started Aug 08 06:12:55 PM PDT 24
Finished Aug 08 06:13:13 PM PDT 24
Peak memory 218064 kb
Host smart-0e048d23-fd00-4e69-b8d7-5171e6b9d2b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060335557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.4060335557
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.3288346616
Short name T596
Test name
Test status
Simulation time 209411080 ps
CPU time 1.88 seconds
Started Aug 08 06:12:56 PM PDT 24
Finished Aug 08 06:12:58 PM PDT 24
Peak memory 208716 kb
Host smart-56046f3b-7ab5-4c56-bfd8-53f5e971fc0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288346616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.3288346616
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.4152240158
Short name T853
Test name
Test status
Simulation time 188405286 ps
CPU time 0.81 seconds
Started Aug 08 06:12:56 PM PDT 24
Finished Aug 08 06:12:57 PM PDT 24
Peak memory 206600 kb
Host smart-cc52d34c-f680-4968-b554-dca39787abdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152240158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.4152240158
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.1042031452
Short name T193
Test name
Test status
Simulation time 8527193223 ps
CPU time 28.55 seconds
Started Aug 08 06:13:01 PM PDT 24
Finished Aug 08 06:13:30 PM PDT 24
Peak memory 233536 kb
Host smart-2472959a-7cc4-464a-adc9-4b68ec71738c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042031452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.1042031452
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.1394418915
Short name T484
Test name
Test status
Simulation time 40740483 ps
CPU time 0.76 seconds
Started Aug 08 06:10:29 PM PDT 24
Finished Aug 08 06:10:30 PM PDT 24
Peak memory 205856 kb
Host smart-6d87940a-b1e0-4191-94ae-4551335f2115
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394418915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.1
394418915
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.1935941033
Short name T424
Test name
Test status
Simulation time 543273370 ps
CPU time 3.94 seconds
Started Aug 08 06:10:18 PM PDT 24
Finished Aug 08 06:10:22 PM PDT 24
Peak memory 233456 kb
Host smart-0b4f1ae5-036b-49ec-a39d-9ac21fde9b2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935941033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.1935941033
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.798945030
Short name T332
Test name
Test status
Simulation time 49925316 ps
CPU time 0.7 seconds
Started Aug 08 06:10:21 PM PDT 24
Finished Aug 08 06:10:22 PM PDT 24
Peak memory 205996 kb
Host smart-211e9394-3e6d-4167-9a0f-fa82687d3a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798945030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.798945030
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.2280081969
Short name T588
Test name
Test status
Simulation time 1033572759 ps
CPU time 17.56 seconds
Started Aug 08 06:10:28 PM PDT 24
Finished Aug 08 06:10:46 PM PDT 24
Peak memory 237332 kb
Host smart-5ee73cf3-fc57-4409-8998-4538b915b039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280081969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.2280081969
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.2628704279
Short name T49
Test name
Test status
Simulation time 16947007772 ps
CPU time 15.5 seconds
Started Aug 08 06:10:29 PM PDT 24
Finished Aug 08 06:10:45 PM PDT 24
Peak memory 225388 kb
Host smart-c285793b-9371-4fdf-9636-11f76e7aea87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628704279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.2628704279
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.2375521066
Short name T419
Test name
Test status
Simulation time 10866731371 ps
CPU time 19.54 seconds
Started Aug 08 06:10:28 PM PDT 24
Finished Aug 08 06:10:48 PM PDT 24
Peak memory 218404 kb
Host smart-ced855b6-b672-4081-a67c-33318e09d484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375521066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.2375521066
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.1154140675
Short name T481
Test name
Test status
Simulation time 2232347908 ps
CPU time 13.49 seconds
Started Aug 08 06:10:21 PM PDT 24
Finished Aug 08 06:10:34 PM PDT 24
Peak memory 249864 kb
Host smart-5134e153-aa09-4c8a-9e41-4269b967f636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154140675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.1154140675
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.841660416
Short name T694
Test name
Test status
Simulation time 28132955723 ps
CPU time 58.97 seconds
Started Aug 08 06:10:29 PM PDT 24
Finished Aug 08 06:11:29 PM PDT 24
Peak memory 252940 kb
Host smart-c7a86f42-3098-4b46-afe9-651a264df4cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841660416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds.
841660416
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/5.spi_device_intercept.1446674005
Short name T704
Test name
Test status
Simulation time 1049188624 ps
CPU time 4.58 seconds
Started Aug 08 06:10:19 PM PDT 24
Finished Aug 08 06:10:24 PM PDT 24
Peak memory 225196 kb
Host smart-21b8024b-80d1-46f4-8f81-2b0e410435ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446674005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.1446674005
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.1884088148
Short name T426
Test name
Test status
Simulation time 54575221 ps
CPU time 2.81 seconds
Started Aug 08 06:10:19 PM PDT 24
Finished Aug 08 06:10:22 PM PDT 24
Peak memory 233492 kb
Host smart-343d54a8-976a-4987-9b13-adaaadd9f4c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884088148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.1884088148
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.1572471029
Short name T927
Test name
Test status
Simulation time 24819724 ps
CPU time 1.13 seconds
Started Aug 08 06:10:20 PM PDT 24
Finished Aug 08 06:10:22 PM PDT 24
Peak memory 217236 kb
Host smart-20258952-b142-4411-bcc6-0a3cd47a1279
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572471029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.spi_device_mem_parity.1572471029
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.2473685843
Short name T923
Test name
Test status
Simulation time 703536354 ps
CPU time 6.53 seconds
Started Aug 08 06:10:18 PM PDT 24
Finished Aug 08 06:10:25 PM PDT 24
Peak memory 234676 kb
Host smart-a365ed60-32a8-4a2a-b1a4-efd1caae25f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473685843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.2473685843
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.2962483503
Short name T874
Test name
Test status
Simulation time 4440296044 ps
CPU time 17.99 seconds
Started Aug 08 06:10:19 PM PDT 24
Finished Aug 08 06:10:37 PM PDT 24
Peak memory 233448 kb
Host smart-816e38f1-b0bc-4d65-9d71-7d9689af8ef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962483503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.2962483503
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.1843875072
Short name T685
Test name
Test status
Simulation time 310293320 ps
CPU time 4.98 seconds
Started Aug 08 06:10:30 PM PDT 24
Finished Aug 08 06:10:35 PM PDT 24
Peak memory 219908 kb
Host smart-9ff06d73-bde0-48cc-bc40-11b92f1ed89a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1843875072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.1843875072
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.1133237537
Short name T19
Test name
Test status
Simulation time 30985748289 ps
CPU time 171.27 seconds
Started Aug 08 06:10:30 PM PDT 24
Finished Aug 08 06:13:22 PM PDT 24
Peak memory 268048 kb
Host smart-7225ed89-0c83-44a2-880a-789381aecb75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133237537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.1133237537
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.2393934549
Short name T634
Test name
Test status
Simulation time 2038858078 ps
CPU time 11.94 seconds
Started Aug 08 06:10:23 PM PDT 24
Finished Aug 08 06:10:36 PM PDT 24
Peak memory 216928 kb
Host smart-8d256bcd-f3db-4416-b5d9-f63712a96ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393934549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.2393934549
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.3126509551
Short name T1015
Test name
Test status
Simulation time 2286666591 ps
CPU time 8.18 seconds
Started Aug 08 06:10:21 PM PDT 24
Finished Aug 08 06:10:30 PM PDT 24
Peak memory 217028 kb
Host smart-35a561ce-886c-4796-acc4-4b8fd2f0f878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126509551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.3126509551
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.710478176
Short name T711
Test name
Test status
Simulation time 38917422 ps
CPU time 2.16 seconds
Started Aug 08 06:10:19 PM PDT 24
Finished Aug 08 06:10:21 PM PDT 24
Peak memory 216940 kb
Host smart-e6e41e9c-e9b1-464b-b253-da0ff6835ef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710478176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.710478176
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.2828802235
Short name T691
Test name
Test status
Simulation time 158564756 ps
CPU time 0.9 seconds
Started Aug 08 06:10:18 PM PDT 24
Finished Aug 08 06:10:19 PM PDT 24
Peak memory 206976 kb
Host smart-cf9d7638-f1fe-4625-94a8-df5cfed179d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828802235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.2828802235
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.2988691642
Short name T240
Test name
Test status
Simulation time 1935972241 ps
CPU time 4.85 seconds
Started Aug 08 06:10:21 PM PDT 24
Finished Aug 08 06:10:26 PM PDT 24
Peak memory 225344 kb
Host smart-f521ca7c-a2dd-4b5a-abf3-d90fc0f11cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988691642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.2988691642
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.132059081
Short name T886
Test name
Test status
Simulation time 40832469 ps
CPU time 0.72 seconds
Started Aug 08 06:10:30 PM PDT 24
Finished Aug 08 06:10:31 PM PDT 24
Peak memory 205340 kb
Host smart-5631cb05-619b-4ebd-b60d-9cff4d6b0b21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132059081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.132059081
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.3436428245
Short name T721
Test name
Test status
Simulation time 2262595683 ps
CPU time 7.11 seconds
Started Aug 08 06:10:29 PM PDT 24
Finished Aug 08 06:10:37 PM PDT 24
Peak memory 225320 kb
Host smart-0aeaa24e-53a8-42be-b98e-8cec7efe80e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436428245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.3436428245
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.2336198188
Short name T386
Test name
Test status
Simulation time 36173431 ps
CPU time 0.79 seconds
Started Aug 08 06:10:27 PM PDT 24
Finished Aug 08 06:10:28 PM PDT 24
Peak memory 207068 kb
Host smart-7704e56d-4239-4bb7-931f-4a09e8373ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336198188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.2336198188
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.3085011550
Short name T186
Test name
Test status
Simulation time 143013532472 ps
CPU time 76.64 seconds
Started Aug 08 06:10:29 PM PDT 24
Finished Aug 08 06:11:47 PM PDT 24
Peak memory 241724 kb
Host smart-dfa2ab33-dddc-4bfe-bf20-7d14319f9683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085011550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.3085011550
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.3686597070
Short name T9
Test name
Test status
Simulation time 24906715189 ps
CPU time 252.57 seconds
Started Aug 08 06:10:29 PM PDT 24
Finished Aug 08 06:14:42 PM PDT 24
Peak memory 263020 kb
Host smart-bb9dd4e1-38c3-4805-8276-8b416ba9cb21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686597070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.3686597070
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.2894967877
Short name T970
Test name
Test status
Simulation time 1189640266 ps
CPU time 6.65 seconds
Started Aug 08 06:10:29 PM PDT 24
Finished Aug 08 06:10:35 PM PDT 24
Peak memory 225260 kb
Host smart-d1de0678-33b6-42b5-89f8-cd0d098cf5de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894967877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.2894967877
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.2964634464
Short name T649
Test name
Test status
Simulation time 31557487390 ps
CPU time 45.25 seconds
Started Aug 08 06:10:29 PM PDT 24
Finished Aug 08 06:11:15 PM PDT 24
Peak memory 233464 kb
Host smart-9d16afce-bba1-492f-b13e-45f5b414b1e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964634464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds
.2964634464
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/6.spi_device_intercept.1908471205
Short name T965
Test name
Test status
Simulation time 59878509 ps
CPU time 2.68 seconds
Started Aug 08 06:10:29 PM PDT 24
Finished Aug 08 06:10:31 PM PDT 24
Peak memory 225200 kb
Host smart-ba8ce356-d5b7-412c-a81b-06bf194f3df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908471205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.1908471205
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.3358129146
Short name T673
Test name
Test status
Simulation time 12101493731 ps
CPU time 19.06 seconds
Started Aug 08 06:10:32 PM PDT 24
Finished Aug 08 06:10:51 PM PDT 24
Peak memory 225380 kb
Host smart-83a3fddf-c740-4e58-a433-8d1ad10e051c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358129146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.3358129146
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.3062067301
Short name T581
Test name
Test status
Simulation time 50645950 ps
CPU time 0.98 seconds
Started Aug 08 06:10:26 PM PDT 24
Finished Aug 08 06:10:27 PM PDT 24
Peak memory 217196 kb
Host smart-1d4bfb42-1f39-4a65-91a0-70dcfdd13823
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062067301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.spi_device_mem_parity.3062067301
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.2987366523
Short name T576
Test name
Test status
Simulation time 138212756 ps
CPU time 2.5 seconds
Started Aug 08 06:10:27 PM PDT 24
Finished Aug 08 06:10:30 PM PDT 24
Peak memory 225196 kb
Host smart-99c77b02-778a-480e-bae5-c78048c79926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987366523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.2987366523
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.3029710796
Short name T479
Test name
Test status
Simulation time 15582782371 ps
CPU time 17.34 seconds
Started Aug 08 06:10:28 PM PDT 24
Finished Aug 08 06:10:45 PM PDT 24
Peak memory 225268 kb
Host smart-164b071a-2a9e-434a-924f-2d6bff085944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029710796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.3029710796
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.643929761
Short name T667
Test name
Test status
Simulation time 2484070034 ps
CPU time 8.99 seconds
Started Aug 08 06:10:27 PM PDT 24
Finished Aug 08 06:10:37 PM PDT 24
Peak memory 219652 kb
Host smart-520f1e16-77bc-46da-8cd4-4de17d849f84
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=643929761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_direc
t.643929761
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.4077872001
Short name T586
Test name
Test status
Simulation time 809507701 ps
CPU time 5.87 seconds
Started Aug 08 06:10:28 PM PDT 24
Finished Aug 08 06:10:34 PM PDT 24
Peak memory 217236 kb
Host smart-66c6523d-34b5-4f67-a94b-abb7397f385c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077872001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.4077872001
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.3138925825
Short name T1016
Test name
Test status
Simulation time 1441817959 ps
CPU time 3.7 seconds
Started Aug 08 06:10:30 PM PDT 24
Finished Aug 08 06:10:34 PM PDT 24
Peak memory 217000 kb
Host smart-0b2e2e46-49dc-495f-b6ac-6f5beadad1a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138925825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.3138925825
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.2648806944
Short name T542
Test name
Test status
Simulation time 133466362 ps
CPU time 1.18 seconds
Started Aug 08 06:10:29 PM PDT 24
Finished Aug 08 06:10:31 PM PDT 24
Peak memory 208568 kb
Host smart-136419ff-e1d3-46d4-962f-9adfd9706e0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648806944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.2648806944
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.1192319429
Short name T359
Test name
Test status
Simulation time 79945674 ps
CPU time 0.74 seconds
Started Aug 08 06:10:31 PM PDT 24
Finished Aug 08 06:10:32 PM PDT 24
Peak memory 206608 kb
Host smart-50430f54-dade-474b-8505-95320ee10829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192319429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.1192319429
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.329522665
Short name T745
Test name
Test status
Simulation time 2715969883 ps
CPU time 12.8 seconds
Started Aug 08 06:10:33 PM PDT 24
Finished Aug 08 06:10:45 PM PDT 24
Peak memory 233448 kb
Host smart-e8eedafa-f82c-4e4a-a580-f0d7e537508c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329522665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.329522665
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.42614090
Short name T684
Test name
Test status
Simulation time 32338644 ps
CPU time 0.7 seconds
Started Aug 08 06:10:37 PM PDT 24
Finished Aug 08 06:10:38 PM PDT 24
Peak memory 205280 kb
Host smart-698b4613-a696-4f7d-b7f2-d35b56ee49b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42614090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.42614090
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.3148863640
Short name T709
Test name
Test status
Simulation time 17492036113 ps
CPU time 14.36 seconds
Started Aug 08 06:10:28 PM PDT 24
Finished Aug 08 06:10:43 PM PDT 24
Peak memory 225304 kb
Host smart-ff6e4f0d-fb9f-430e-ba3f-2425be879a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148863640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.3148863640
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.576949733
Short name T482
Test name
Test status
Simulation time 21404855 ps
CPU time 0.88 seconds
Started Aug 08 06:10:29 PM PDT 24
Finished Aug 08 06:10:30 PM PDT 24
Peak memory 206988 kb
Host smart-36c866c1-37b8-46f2-84fb-749ebd6eaf6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576949733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.576949733
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.2424422931
Short name T752
Test name
Test status
Simulation time 10513877768 ps
CPU time 104.43 seconds
Started Aug 08 06:10:39 PM PDT 24
Finished Aug 08 06:12:23 PM PDT 24
Peak memory 239548 kb
Host smart-9b2f89d2-70fe-4dbb-9377-597321e63dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424422931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.2424422931
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.946038899
Short name T303
Test name
Test status
Simulation time 4107375109 ps
CPU time 97.53 seconds
Started Aug 08 06:10:38 PM PDT 24
Finished Aug 08 06:12:15 PM PDT 24
Peak memory 257940 kb
Host smart-70d979b2-3485-4907-b624-ebb490dda80f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946038899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.946038899
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.2638377803
Short name T889
Test name
Test status
Simulation time 2447637414 ps
CPU time 17.47 seconds
Started Aug 08 06:10:41 PM PDT 24
Finished Aug 08 06:10:58 PM PDT 24
Peak memory 224104 kb
Host smart-c9a83b55-181e-4e59-bd6f-a35c6a5d9069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638377803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.2638377803
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.2562347222
Short name T860
Test name
Test status
Simulation time 455588369 ps
CPU time 6.84 seconds
Started Aug 08 06:10:30 PM PDT 24
Finished Aug 08 06:10:37 PM PDT 24
Peak memory 236448 kb
Host smart-054d6ce8-5788-4ae8-9585-7ac92bcd6668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562347222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.2562347222
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.2559397855
Short name T373
Test name
Test status
Simulation time 30354341 ps
CPU time 0.74 seconds
Started Aug 08 06:10:27 PM PDT 24
Finished Aug 08 06:10:28 PM PDT 24
Peak memory 216496 kb
Host smart-bb36e98c-e22f-4ffa-9452-91948b1fcc3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559397855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds
.2559397855
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_intercept.2709394172
Short name T931
Test name
Test status
Simulation time 463859146 ps
CPU time 3.32 seconds
Started Aug 08 06:10:30 PM PDT 24
Finished Aug 08 06:10:34 PM PDT 24
Peak memory 233448 kb
Host smart-16341f4b-25c1-4caa-8997-5baa33f7ea1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709394172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.2709394172
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.1153836019
Short name T987
Test name
Test status
Simulation time 8133646054 ps
CPU time 74.08 seconds
Started Aug 08 06:10:28 PM PDT 24
Finished Aug 08 06:11:42 PM PDT 24
Peak memory 234752 kb
Host smart-6ebe5dff-00ee-4b28-ba94-3577090f588a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153836019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.1153836019
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.3257340906
Short name T33
Test name
Test status
Simulation time 30555812 ps
CPU time 1.05 seconds
Started Aug 08 06:10:32 PM PDT 24
Finished Aug 08 06:10:33 PM PDT 24
Peak memory 218532 kb
Host smart-ac477d94-a8a0-4329-b3b4-efa39c33a01e
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257340906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.spi_device_mem_parity.3257340906
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.2658195675
Short name T42
Test name
Test status
Simulation time 632119510 ps
CPU time 3.38 seconds
Started Aug 08 06:10:30 PM PDT 24
Finished Aug 08 06:10:34 PM PDT 24
Peak memory 233384 kb
Host smart-34032311-6c49-4616-9160-2aa644ca8c65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658195675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.2658195675
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.3663304999
Short name T518
Test name
Test status
Simulation time 441659796 ps
CPU time 6.17 seconds
Started Aug 08 06:10:28 PM PDT 24
Finished Aug 08 06:10:34 PM PDT 24
Peak memory 239996 kb
Host smart-d2a74428-ef83-4db0-b4c4-c5b1c91105bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663304999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.3663304999
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.3736100685
Short name T145
Test name
Test status
Simulation time 176265149 ps
CPU time 3.44 seconds
Started Aug 08 06:10:36 PM PDT 24
Finished Aug 08 06:10:40 PM PDT 24
Peak memory 223796 kb
Host smart-f3f2d2b0-d607-4d29-80da-d4e577b12110
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3736100685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.3736100685
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.2970868316
Short name T462
Test name
Test status
Simulation time 132311738 ps
CPU time 0.93 seconds
Started Aug 08 06:10:36 PM PDT 24
Finished Aug 08 06:10:37 PM PDT 24
Peak memory 207156 kb
Host smart-c7260a0c-5dd7-45f2-a769-5725309e95c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970868316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.2970868316
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.3090446536
Short name T304
Test name
Test status
Simulation time 1362631223 ps
CPU time 9.53 seconds
Started Aug 08 06:10:27 PM PDT 24
Finished Aug 08 06:10:37 PM PDT 24
Peak memory 217144 kb
Host smart-24967791-44eb-4c63-ba63-3416f5b355e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090446536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.3090446536
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.1071870431
Short name T75
Test name
Test status
Simulation time 11364010 ps
CPU time 0.73 seconds
Started Aug 08 06:10:31 PM PDT 24
Finished Aug 08 06:10:32 PM PDT 24
Peak memory 206124 kb
Host smart-3d063c6a-2237-4bf7-bd0c-fe3c2085640f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071870431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.1071870431
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.821587492
Short name T692
Test name
Test status
Simulation time 381423025 ps
CPU time 3.44 seconds
Started Aug 08 06:10:29 PM PDT 24
Finished Aug 08 06:10:32 PM PDT 24
Peak memory 216888 kb
Host smart-c35a47f4-8fd9-43d7-b8c4-119657608984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821587492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.821587492
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.125788585
Short name T835
Test name
Test status
Simulation time 123263602 ps
CPU time 0.92 seconds
Started Aug 08 06:10:29 PM PDT 24
Finished Aug 08 06:10:31 PM PDT 24
Peak memory 206972 kb
Host smart-b2f3ba87-ce2b-497d-8050-7803a4a946e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125788585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.125788585
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.2577440215
Short name T879
Test name
Test status
Simulation time 109098455 ps
CPU time 2.74 seconds
Started Aug 08 06:10:29 PM PDT 24
Finished Aug 08 06:10:33 PM PDT 24
Peak memory 233484 kb
Host smart-d1bcf31b-5fe0-4297-b65a-2c7c3a0817e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577440215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.2577440215
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.1526136015
Short name T372
Test name
Test status
Simulation time 17868135 ps
CPU time 0.72 seconds
Started Aug 08 06:10:38 PM PDT 24
Finished Aug 08 06:10:39 PM PDT 24
Peak memory 205856 kb
Host smart-9a21cd7d-2cea-41b1-8d1c-79e0496418c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526136015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.1
526136015
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.4189987314
Short name T232
Test name
Test status
Simulation time 66972305 ps
CPU time 2.46 seconds
Started Aug 08 06:10:37 PM PDT 24
Finished Aug 08 06:10:40 PM PDT 24
Peak memory 233360 kb
Host smart-07b9f348-d644-4f5c-a4f1-7bbd535417f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189987314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.4189987314
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.676563231
Short name T414
Test name
Test status
Simulation time 50469644 ps
CPU time 0.76 seconds
Started Aug 08 06:10:37 PM PDT 24
Finished Aug 08 06:10:38 PM PDT 24
Peak memory 205984 kb
Host smart-877e77c2-29a1-4f77-8de2-ebdce77c1f0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676563231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.676563231
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.3455322468
Short name T30
Test name
Test status
Simulation time 6741074502 ps
CPU time 101.03 seconds
Started Aug 08 06:10:37 PM PDT 24
Finished Aug 08 06:12:18 PM PDT 24
Peak memory 257748 kb
Host smart-863e232f-e06c-427e-946d-1c8ca09209fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455322468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.3455322468
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.1581527430
Short name T292
Test name
Test status
Simulation time 14581651079 ps
CPU time 33.48 seconds
Started Aug 08 06:10:37 PM PDT 24
Finished Aug 08 06:11:11 PM PDT 24
Peak memory 233544 kb
Host smart-0d0b6212-7fe9-4fbe-890c-86d229848e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581527430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.1581527430
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.1603519764
Short name T617
Test name
Test status
Simulation time 577405071 ps
CPU time 5.89 seconds
Started Aug 08 06:10:37 PM PDT 24
Finished Aug 08 06:10:43 PM PDT 24
Peak memory 235160 kb
Host smart-3d09d179-ca8f-4293-981e-2461ec7b7643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603519764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.1603519764
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.41345136
Short name T174
Test name
Test status
Simulation time 27756238342 ps
CPU time 57.48 seconds
Started Aug 08 06:10:41 PM PDT 24
Finished Aug 08 06:11:39 PM PDT 24
Peak memory 249932 kb
Host smart-4610c4a7-7b2c-4dd8-9525-bbb1c5546f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41345136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds.41345136
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/8.spi_device_intercept.3253368592
Short name T804
Test name
Test status
Simulation time 21294890019 ps
CPU time 26.44 seconds
Started Aug 08 06:10:38 PM PDT 24
Finished Aug 08 06:11:05 PM PDT 24
Peak memory 225224 kb
Host smart-83bb2b09-7678-4a05-b97f-1a5fa13a6f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253368592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.3253368592
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.3515341658
Short name T600
Test name
Test status
Simulation time 69047090534 ps
CPU time 184.16 seconds
Started Aug 08 06:10:36 PM PDT 24
Finished Aug 08 06:13:41 PM PDT 24
Peak memory 225328 kb
Host smart-4391c90d-857c-4a15-af4c-60ee64794d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515341658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.3515341658
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.1302231958
Short name T549
Test name
Test status
Simulation time 91065192 ps
CPU time 1.04 seconds
Started Aug 08 06:10:38 PM PDT 24
Finished Aug 08 06:10:39 PM PDT 24
Peak memory 217176 kb
Host smart-70caf564-fd9a-411a-8b35-d7a04b38ecae
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302231958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.spi_device_mem_parity.1302231958
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.208071993
Short name T919
Test name
Test status
Simulation time 440128411 ps
CPU time 2.56 seconds
Started Aug 08 06:10:38 PM PDT 24
Finished Aug 08 06:10:41 PM PDT 24
Peak memory 225180 kb
Host smart-ef203e16-751f-4ad2-b9e8-77d394ce8e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208071993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap.
208071993
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.1129536635
Short name T665
Test name
Test status
Simulation time 4754537768 ps
CPU time 19.8 seconds
Started Aug 08 06:10:37 PM PDT 24
Finished Aug 08 06:10:57 PM PDT 24
Peak memory 233520 kb
Host smart-a7e6b069-592e-4883-9121-7ffcf0cb0f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129536635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.1129536635
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.92503669
Short name T478
Test name
Test status
Simulation time 309846612 ps
CPU time 3.83 seconds
Started Aug 08 06:10:40 PM PDT 24
Finished Aug 08 06:10:44 PM PDT 24
Peak memory 221112 kb
Host smart-68d86caa-ff46-45e4-be48-4d7d035149b7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=92503669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_direct
.92503669
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.91259212
Short name T161
Test name
Test status
Simulation time 2859954901 ps
CPU time 29.68 seconds
Started Aug 08 06:10:39 PM PDT 24
Finished Aug 08 06:11:09 PM PDT 24
Peak memory 241724 kb
Host smart-b174551b-a405-4a19-944b-47e59ec1b543
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91259212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stress_
all.91259212
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.2658445728
Short name T521
Test name
Test status
Simulation time 451346876 ps
CPU time 5.04 seconds
Started Aug 08 06:10:39 PM PDT 24
Finished Aug 08 06:10:44 PM PDT 24
Peak memory 216996 kb
Host smart-de83adec-c029-4488-a464-db2b3108fd88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658445728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.2658445728
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.2027049975
Short name T449
Test name
Test status
Simulation time 8661758058 ps
CPU time 4.89 seconds
Started Aug 08 06:10:38 PM PDT 24
Finished Aug 08 06:10:43 PM PDT 24
Peak memory 217040 kb
Host smart-b28f44d9-00d9-4ab7-b0d7-5ef5129df0ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027049975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.2027049975
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.2515156170
Short name T398
Test name
Test status
Simulation time 143275071 ps
CPU time 1.13 seconds
Started Aug 08 06:10:42 PM PDT 24
Finished Aug 08 06:10:43 PM PDT 24
Peak memory 208516 kb
Host smart-4a77851f-3df1-49b2-865f-197c8b10a25b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515156170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.2515156170
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.4189629062
Short name T807
Test name
Test status
Simulation time 335273460 ps
CPU time 0.76 seconds
Started Aug 08 06:10:37 PM PDT 24
Finished Aug 08 06:10:38 PM PDT 24
Peak memory 206540 kb
Host smart-78e0275b-aab1-4cbb-af81-73c375c80a4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189629062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.4189629062
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.4281682529
Short name T878
Test name
Test status
Simulation time 1092979235 ps
CPU time 7.33 seconds
Started Aug 08 06:10:38 PM PDT 24
Finished Aug 08 06:10:46 PM PDT 24
Peak memory 225228 kb
Host smart-97ae7fd2-6fc7-411f-849d-cf4cf84249c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281682529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.4281682529
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.2970427312
Short name T716
Test name
Test status
Simulation time 20352596 ps
CPU time 0.72 seconds
Started Aug 08 06:10:39 PM PDT 24
Finished Aug 08 06:10:40 PM PDT 24
Peak memory 205864 kb
Host smart-28b064d7-b980-40e5-b637-9fb35569c445
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970427312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.2
970427312
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.3899497818
Short name T444
Test name
Test status
Simulation time 119127092 ps
CPU time 2.76 seconds
Started Aug 08 06:10:40 PM PDT 24
Finished Aug 08 06:10:43 PM PDT 24
Peak memory 233496 kb
Host smart-cb9c5223-ff43-478b-b556-b259d53159d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899497818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.3899497818
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.745896151
Short name T55
Test name
Test status
Simulation time 38143861 ps
CPU time 0.76 seconds
Started Aug 08 06:10:38 PM PDT 24
Finished Aug 08 06:10:39 PM PDT 24
Peak memory 206028 kb
Host smart-3039c9db-54ac-4e72-86cb-21286058d882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745896151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.745896151
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.108525916
Short name T619
Test name
Test status
Simulation time 1372816937 ps
CPU time 26.57 seconds
Started Aug 08 06:10:40 PM PDT 24
Finished Aug 08 06:11:06 PM PDT 24
Peak memory 249836 kb
Host smart-aced27f5-b94d-4064-a30e-a79bff2be16c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108525916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.108525916
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.2597222552
Short name T519
Test name
Test status
Simulation time 51571315492 ps
CPU time 128.41 seconds
Started Aug 08 06:10:42 PM PDT 24
Finished Aug 08 06:12:50 PM PDT 24
Peak memory 266368 kb
Host smart-417ba1d5-5dfa-4995-8b7c-ec5d0d63aca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597222552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.2597222552
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.587772176
Short name T256
Test name
Test status
Simulation time 6003225600 ps
CPU time 58.22 seconds
Started Aug 08 06:10:41 PM PDT 24
Finished Aug 08 06:11:40 PM PDT 24
Peak memory 256180 kb
Host smart-4fbfc7cb-6043-4baa-8870-6da9e2bd6cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587772176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle.
587772176
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.1946484056
Short name T972
Test name
Test status
Simulation time 87470430719 ps
CPU time 186.02 seconds
Started Aug 08 06:10:41 PM PDT 24
Finished Aug 08 06:13:47 PM PDT 24
Peak memory 252300 kb
Host smart-646066a8-783d-4177-92bf-27a2d545d3f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946484056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds
.1946484056
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/9.spi_device_intercept.457088111
Short name T72
Test name
Test status
Simulation time 1582470029 ps
CPU time 5.85 seconds
Started Aug 08 06:10:40 PM PDT 24
Finished Aug 08 06:10:46 PM PDT 24
Peak memory 233504 kb
Host smart-4834b79b-33f1-41c5-8520-3a3510c17f74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457088111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.457088111
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.1143038010
Short name T955
Test name
Test status
Simulation time 961349000 ps
CPU time 9.47 seconds
Started Aug 08 06:10:38 PM PDT 24
Finished Aug 08 06:10:48 PM PDT 24
Peak memory 233492 kb
Host smart-5dc3fa3d-9512-43ff-b7b0-38e1deb6e66d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143038010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.1143038010
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.2031719694
Short name T487
Test name
Test status
Simulation time 95567304 ps
CPU time 1.04 seconds
Started Aug 08 06:10:37 PM PDT 24
Finished Aug 08 06:10:38 PM PDT 24
Peak memory 217228 kb
Host smart-d9e1e8ea-1c63-4a8b-9ea6-6eed472aad33
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031719694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.spi_device_mem_parity.2031719694
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.1181846587
Short name T571
Test name
Test status
Simulation time 1196697671 ps
CPU time 8.57 seconds
Started Aug 08 06:10:41 PM PDT 24
Finished Aug 08 06:10:49 PM PDT 24
Peak memory 239988 kb
Host smart-2cf86a99-e432-4b98-a901-42f916af9fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181846587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.1181846587
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.2639306967
Short name T854
Test name
Test status
Simulation time 7413353668 ps
CPU time 12.61 seconds
Started Aug 08 06:10:37 PM PDT 24
Finished Aug 08 06:10:50 PM PDT 24
Peak memory 233532 kb
Host smart-04051eea-4121-448e-b19f-b0b2391714ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639306967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.2639306967
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.2933906024
Short name T952
Test name
Test status
Simulation time 1370524475 ps
CPU time 10.85 seconds
Started Aug 08 06:10:42 PM PDT 24
Finished Aug 08 06:10:52 PM PDT 24
Peak memory 222196 kb
Host smart-b01d94c3-b937-494a-b3cf-bab317bf0365
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2933906024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.2933906024
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.1345349297
Short name T26
Test name
Test status
Simulation time 3900393554 ps
CPU time 26.09 seconds
Started Aug 08 06:10:37 PM PDT 24
Finished Aug 08 06:11:04 PM PDT 24
Peak memory 217044 kb
Host smart-4735222b-a92d-4549-8ad4-eea937c6c301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345349297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.1345349297
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.3320800597
Short name T451
Test name
Test status
Simulation time 1524533430 ps
CPU time 3.1 seconds
Started Aug 08 06:10:36 PM PDT 24
Finished Aug 08 06:10:39 PM PDT 24
Peak memory 216948 kb
Host smart-6ec4ffce-1088-4166-96d1-b54df2aacf1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320800597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.3320800597
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.1917133653
Short name T876
Test name
Test status
Simulation time 26198819 ps
CPU time 0.78 seconds
Started Aug 08 06:10:40 PM PDT 24
Finished Aug 08 06:10:41 PM PDT 24
Peak memory 206572 kb
Host smart-26839965-9ab1-4623-b646-397800a9d4a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917133653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.1917133653
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.1866596808
Short name T346
Test name
Test status
Simulation time 81207641 ps
CPU time 0.91 seconds
Started Aug 08 06:10:37 PM PDT 24
Finished Aug 08 06:10:38 PM PDT 24
Peak memory 206516 kb
Host smart-58b9fcf3-7b6a-4b08-a68e-777e6474cc62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866596808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.1866596808
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.3186451399
Short name T446
Test name
Test status
Simulation time 33470749 ps
CPU time 2.51 seconds
Started Aug 08 06:10:39 PM PDT 24
Finished Aug 08 06:10:42 PM PDT 24
Peak memory 233160 kb
Host smart-ce932e2c-0ae2-4b9b-8a65-5af7938a67d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186451399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.3186451399
Directory /workspace/9.spi_device_upload/latest
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