Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2369628	1			T1	1064		T2	186		T3	16712
all_values[1]	2369628	1			T1	1064		T2	186		T3	16712
all_values[2]	2369628	1			T1	1064		T2	186		T3	16712
all_values[3]	2369628	1			T1	1064		T2	186		T3	16712
all_values[4]	2369628	1			T1	1064		T2	186		T3	16712
all_values[5]	2369628	1			T1	1064		T2	186		T3	16712
all_values[6]	2369628	1			T1	1064		T2	186		T3	16712
all_values[7]	2369628	1			T1	1064		T2	186		T3	16712

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18290385

1

T1

8512

T2

1488

T3

49864

auto[1]

666639

1

T3

83832

T7

53

T18

77

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18928996

1

T1

8512

T2

1488

T3

133033

auto[1]

28028

1

T3

663

T7

229

T18

130

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2271543	1			T1	1064		T2	186		T3	2617
all_values[0]	auto[0]	auto[1]	13001	1			T3	124		T7	101		T18	33
all_values[0]	auto[1]	auto[0]	84271	1			T3	13807		T7	8		T18	4
all_values[0]	auto[1]	auto[1]	813	1			T3	164		T7	1		T18	5
all_values[1]	auto[0]	auto[0]	2282495	1			T1	1064		T2	186		T3	2621
all_values[1]	auto[0]	auto[1]	8305	1			T3	119		T7	70		T18	34
all_values[1]	auto[1]	auto[0]	78337	1			T3	13871		T7	3		T18	5
all_values[1]	auto[1]	auto[1]	491	1			T3	101		T7	5		T18	2
all_values[2]	auto[0]	auto[0]	2272309	1			T1	1064		T2	186		T3	2622
all_values[2]	auto[0]	auto[1]	3233	1			T3	120		T7	34		T18	24
all_values[2]	auto[1]	auto[0]	93867	1			T3	13964		T7	8		T18	2
all_values[2]	auto[1]	auto[1]	219	1			T3	6		T7	1		T18	2
all_values[3]	auto[0]	auto[0]	2301901	1			T1	1064		T2	186		T3	16705
all_values[3]	auto[0]	auto[1]	235	1			T3	5		T7	2		T18	2
all_values[3]	auto[1]	auto[0]	67295	1			T3	1		T7	7		T18	8
all_values[3]	auto[1]	auto[1]	197	1			T3	1		T7	1		T18	2
all_values[4]	auto[0]	auto[0]	2322233	1			T1	1064		T2	186		T3	16704
all_values[4]	auto[0]	auto[1]	195	1			T3	5		T7	2		T18	5
all_values[4]	auto[1]	auto[0]	46977	1			T3	2		T7	4		T18	6
all_values[4]	auto[1]	auto[1]	223	1			T3	1		T7	1		T18	4
all_values[5]	auto[0]	auto[0]	2289677	1			T1	1064		T2	186		T3	2740
all_values[5]	auto[0]	auto[1]	167	1			T3	2		T7	3		T18	1
all_values[5]	auto[1]	auto[0]	79616	1			T3	13968		T7	4		T18	10
all_values[5]	auto[1]	auto[1]	168	1			T3	2		T7	1		T18	5
all_values[6]	auto[0]	auto[0]	2280385	1			T1	1064		T2	186		T3	2739
all_values[6]	auto[0]	auto[1]	206	1			T7	4		T18	3		T21	7
all_values[6]	auto[1]	auto[0]	88840	1			T3	13969		T7	5		T18	8
all_values[6]	auto[1]	auto[1]	197	1			T3	4		T7	1		T21	7
all_values[7]	auto[0]	auto[0]	2244319	1			T1	1064		T2	186		T3	2738
all_values[7]	auto[0]	auto[1]	181	1			T3	3		T18	3		T21	7
all_values[7]	auto[1]	auto[0]	124931	1			T3	13965		T7	1		T18	9
all_values[7]	auto[1]	auto[1]	197	1			T3	6		T7	2		T18	5