Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	36449	1			T1	58		T2	2		T3	174
auto[SpiFlashAddrCfg]	7924	1			T1	17		T3	27		T7	20
auto[SpiFlashAddr3b]	9317	1			T1	26		T2	2		T3	52
auto[SpiFlashAddr4b]	7776	1			T1	19		T3	56		T7	26

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34300

1

T1

70

T2

4

T3

164

auto[1]

27166

1

T1

50

T3

145

T7

78

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33473

1

T1

66

T2

2

T3

127

auto[1]

27993

1

T1

54

T2

2

T3

182

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	41246	1			T1	64		T2	4		T3	193
values[1]	1140	1			T1	6		T3	7		T7	1
values[2]	1454	1			T1	7		T3	6		T7	2
values[3]	1430	1			T1	2		T3	1		T7	1
values[4]	1521	1			T1	6		T3	11		T7	1
values[5]	1494	1			T1	3		T3	3		T7	9
values[6]	1500	1			T1	3		T3	7		T7	3
values[7]	1401	1			T1	3		T3	7		T7	6
values[8]	10280	1			T1	26		T3	74		T7	38

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27830

1

T2

4

T3

74

T4

4

auto[1]

33636

1

T1

120

T3

235

T136

3

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

58047

1

T1

115

T2

4

T3

285

write

3419

1

T1

5

T3

24

T7

19

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

19840

1

T1

53

T3

104

T7

56

valids[0x1]

41626

1

T1

67

T2

4

T3

205

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1672	1			T1	4		T2	2		T3	8
internal_process_ops[0x5a]	1592	1			T1	3		T2	2		T3	9
internal_process_ops[0x05]	21841	1			T1	5		T3	75		T7	92
internal_process_ops[0x35]	1690	1			T1	8		T3	5		T7	4
internal_process_ops[0x15]	1593	1			T1	4		T3	13		T7	1
internal_process_ops[0x03]	1039	1			T1	1		T3	4		T4	2
internal_process_ops[0x0b]	1087	1			T1	2		T3	4		T7	7
internal_process_ops[0x3b]	1081	1			T1	1		T3	1		T7	5
internal_process_ops[0x6b]	991	1			T3	3		T7	5		T16	2
internal_process_ops[0xbb]	1075	1			T1	1		T3	4		T7	4
internal_process_ops[0xeb]	1000	1			T1	1		T3	5		T7	2

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

59792

1

T1

115

T2

4

T3

298

auto[1]

1674

1

T1

5

T3

11

T7

9

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

59019

1

T1

114

T2

4

T3

289

auto[1]

2447

1

T1

6

T3

20

T7

14

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

8653

1

T2

2

T3

7

T7

83

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6159

1

T3

39

T7

41

T13

6

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1933

1

T3

2

T7

14

T11

6

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1769

1

T3

4

T7

5

T13

4

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2246

1

T2

2

T3

4

T4

4

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2009

1

T3

2

T7

10

T13

4

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1936

1

T3

6

T7

9

T39

6

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1660

1

T3

3

T7

10

T13

4

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

104

1

T7

2

T33

2

T34

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

74

1

T7

3

T40

4

T43

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

85

1

T3

3

T7

2

T40

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

112

1

T7

3

T40

2

T18

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

114

1

T11

2

T40

2

T43

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

74

1

T40

4

T171

1

T35

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

76

1

T40

2

T34

1

T43

5

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

108

1

T7

1

T33

1

T40

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

90

1

T11

4

T33

3

T40

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

90

1

T33

1

T18

2

T42

4

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

93

1

T7

1

T40

1

T43

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

83

1

T33

2

T40

3

T18

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

79

1

T33

3

T19

1

T172

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

91

1

T3

2

T7

2

T33

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

92

1

T7

5

T33

1

T171

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

100

1

T3

2

T40

4

T18

3

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

12289

1

T1

37

T3

84

T38

73

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

8516

1

T1

18

T3

36

T38

39

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1751

1

T1

8

T3

15

T136

1

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1602

1

T1

9

T3

4

T38

10

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2073

1

T1

12

T3

19

T38

32

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2110

1

T1

13

T3

22

T38

25

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1695

1

T1

9

T3

21

T136

2

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1646

1

T1

9

T3

17

T38

13

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

109

1

T3

1

T38

4

T173

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

146

1

T1

3

T48

1

T173

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

117

1

T3

2

T38

1

T59

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

85

1

T3

2

T38

4

T70

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

119

1

T3

2

T19

1

T70

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

143

1

T38

1

T48

1

T19

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

129

1

T38

8

T19

3

T173

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

106

1

T70

6

T174

1

T79

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

142

1

T70

2

T79

1

T162

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

117

1

T38

1

T59

1

T70

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

134

1

T3

1

T59

2

T173

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

130

1

T1

1

T3

4

T38

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

123

1

T3

1

T38

2

T48

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

109

1

T1

1

T38

1

T48

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

139

1

T3

3

T38

3

T173

6

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

106

1

T3

1

T38

2

T48

2

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3483	1			T3	8		T7	23		T41	6
auto[0]	values[0]	valids[0x1]	14005	1			T2	4		T3	46		T4	4
auto[0]	values[1]	valids[0x1]	530	1			T7	1		T13	4		T33	1
auto[0]	values[2]	valids[0x0]	479	1			T16	6		T33	5		T40	2
auto[0]	values[2]	valids[0x1]	247	1			T7	2		T33	10		T40	1
auto[0]	values[3]	valids[0x0]	503	1			T7	1		T33	4		T40	17
auto[0]	values[3]	valids[0x1]	242	1			T13	4		T33	1		T40	5
auto[0]	values[4]	valids[0x0]	502	1			T3	1		T7	1		T40	10
auto[0]	values[4]	valids[0x1]	293	1			T33	4		T40	4		T69	4
auto[0]	values[5]	valids[0x0]	473	1			T7	5		T33	4		T67	2
auto[0]	values[5]	valids[0x1]	295	1			T7	4		T83	4		T33	3
auto[0]	values[6]	valids[0x0]	497	1			T7	2		T11	2		T39	2
auto[0]	values[6]	valids[0x1]	301	1			T7	1		T13	2		T40	2
auto[0]	values[7]	valids[0x0]	436	1			T3	1		T7	2		T39	4
auto[0]	values[7]	valids[0x1]	267	1			T7	4		T11	2		T39	2
auto[0]	values[8]	valids[0x0]	3348	1			T3	8		T7	22		T13	4
auto[0]	values[8]	valids[0x1]	1929	1			T3	10		T7	16		T11	2
auto[1]	values[0]	valids[0x0]	4652	1			T1	26		T3	45		T38	53
auto[1]	values[0]	valids[0x1]	19106	1			T1	38		T3	94		T136	2
auto[1]	values[1]	valids[0x1]	610	1			T1	6		T3	7		T38	1
auto[1]	values[2]	valids[0x0]	406	1			T1	3		T3	1		T38	3
auto[1]	values[2]	valids[0x1]	322	1			T1	4		T3	5		T38	5
auto[1]	values[3]	valids[0x0]	396	1			T1	1		T3	1		T38	5
auto[1]	values[3]	valids[0x1]	289	1			T1	1		T38	4		T48	5
auto[1]	values[4]	valids[0x0]	458	1			T1	4		T3	5		T38	5
auto[1]	values[4]	valids[0x1]	268	1			T1	2		T3	5		T38	4
auto[1]	values[5]	valids[0x0]	429	1			T1	1		T3	3		T136	1
auto[1]	values[5]	valids[0x1]	297	1			T1	2		T38	1		T48	4
auto[1]	values[6]	valids[0x0]	400	1			T1	2		T3	3		T38	5
auto[1]	values[6]	valids[0x1]	302	1			T1	1		T3	4		T38	12
auto[1]	values[7]	valids[0x0]	412	1			T1	3		T3	4		T38	4
auto[1]	values[7]	valids[0x1]	286	1			T3	2		T38	3		T48	5
auto[1]	values[8]	valids[0x0]	2966	1			T1	13		T3	24		T38	30
auto[1]	values[8]	valids[0x1]	2037	1			T1	13		T3	32		T38	28