Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3339995

1

T1

7600

T2

1

T3

6339

auto[1]

32000

1

T1

142

T3

69

T7

88

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

968341

1

T1

277

T2

1

T3

66

auto[1]

2403654

1

T1

7465

T3

6342

T7

9385

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	713763	1			T1	27		T2	1		T3	2472
auto[524288:1048575]	391832	1			T1	1140		T3	1756		T4	2
auto[1048576:1572863]	402688	1			T1	572		T3	390		T41	3
auto[1572864:2097151]	392036	1			T1	1165		T3	516		T4	27
auto[2097152:2621439]	340534	1			T1	537		T3	17		T4	2
auto[2621440:3145727]	399522	1			T1	2353		T3	681		T7	289
auto[3145728:3670015]	342960	1			T1	486		T3	567		T7	3764
auto[3670016:4194303]	388660	1			T1	1462		T3	9		T4	24

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2437608

1

T1

7737

T2

1

T3

6407

auto[1]

934387

1

T1

5

T3

1

T4

110

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2911783

1

T1

4966

T2

1

T3

6386

auto[1]

460212

1

T1

2776

T3

22

T7

281

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	250408	1			T1	27		T2	1		T3	4
auto[0]	auto[0]	auto[0:524287]	auto[1]	382136	1			T3	2462		T7	5295		T11	4014
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	92649	1			T1	24		T3	4		T4	2
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	238840	1			T1	1116		T3	1739		T7	5
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	124503	1			T1	27		T3	2		T41	3
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	221611	1			T3	385		T33	388		T40	5900
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	101912	1			T1	26		T3	4		T4	27
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	229212	1			T1	1139		T3	512		T7	8
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	94753	1			T1	22		T3	2		T4	2
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	196344	1			T1	512		T3	3		T33	128
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	107240	1			T1	29		T3	8		T7	7
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	226510	1			T1	85		T3	667		T7	5
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	88988	1			T1	23		T3	14		T7	2
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	207846	1			T1	458		T3	518		T7	3738
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	96522	1			T1	43		T3	3		T4	24
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	225823	1			T1	1416		T3	4		T33	2
auto[0]	auto[1]	auto[0:524287]	auto[0]	2231	1			T3	1		T7	2		T33	1
auto[0]	auto[1]	auto[0:524287]	auto[1]	73942	1			T3	1		T33	3097		T38	512
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	733	1			T3	3		T33	2		T40	3
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	56149	1			T3	1		T33	129		T38	1988
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	633	1			T1	29		T33	1		T40	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	51750	1			T1	393		T38	2546		T48	256
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	825	1			T7	2		T33	2		T38	8
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	56892	1			T33	256		T38	256		T48	4
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	788	1			T3	1		T40	3		T38	10
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	44550	1			T3	1		T40	1		T48	1025
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	616	1			T1	4		T40	2		T48	28
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	60554	1			T1	2225		T7	256		T173	772
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	746	1			T1	2		T7	5		T40	3
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	41693	1			T7	4		T38	5		T34	260
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	705	1			T33	3		T40	2		T38	29
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	61891	1			T33	7		T40	1		T38	576
auto[1]	auto[0]	auto[0:524287]	auto[0]	510	1			T7	1		T11	4		T33	1
auto[1]	auto[0]	auto[0:524287]	auto[1]	3792	1			T7	1		T11	48		T33	17
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	449	1			T3	2		T33	2		T40	1
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	2379	1			T3	4		T33	24		T40	12
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	341	1			T3	1		T33	4		T40	3
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	3284	1			T3	2		T33	54		T40	39
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	389	1			T7	3		T33	3		T40	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	1993	1			T7	47		T33	18		T40	15
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	387	1			T1	3		T3	3		T40	2
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	2920	1			T40	50		T18	4		T34	586
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	460	1			T1	8		T3	3		T7	5
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	3421	1			T1	2		T3	3		T7	16
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	374	1			T1	3		T3	6		T7	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	2775	1			T3	29		T7	2		T40	51
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	453	1			T1	3		T3	2		T33	2
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	2559	1			T33	6		T40	102		T19	11
auto[1]	auto[1]	auto[0:524287]	auto[0]	94	1			T3	1		T38	5		T173	2
auto[1]	auto[1]	auto[0:524287]	auto[1]	650	1			T3	3		T173	4		T213	37
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	142	1			T3	1		T33	1		T38	25
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	491	1			T3	2		T33	1		T43	2
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	62	1			T1	4		T173	2		T213	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	504	1			T1	119		T173	5		T213	65
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	89	1			T59	2		T197	3		T174	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	724	1			T197	3		T174	4		T242	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	90	1			T3	1		T40	1		T48	3
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	702	1			T3	6		T40	25		T48	223
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	97	1			T173	1		T70	1		T174	4
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	624	1			T70	2		T174	31		T208	30
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	82	1			T7	4		T38	7		T70	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	456	1			T7	8		T70	5		T174	9
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	70	1			T33	2		T40	1		T38	9
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	637	1			T33	24		T40	6		T35	2

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1953702	1			T1	4947		T2	1		T3	6330
auto[0]	auto[0]	auto[1]	931595	1			T3	1		T4	110		T7	1
auto[0]	auto[1]	auto[0]	452544	1			T1	2653		T3	8		T7	269
auto[0]	auto[1]	auto[1]	2154	1			T33	1		T174	1		T213	2
auto[1]	auto[0]	auto[0]	25955	1			T1	15		T3	55		T7	76
auto[1]	auto[0]	auto[1]	531	1			T1	4		T11	4		T33	9
auto[1]	auto[1]	auto[0]	5407	1			T1	122		T3	14		T7	12
auto[1]	auto[1]	auto[1]	107	1			T1	1		T33	1		T38	6