Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2369628	1			T1	1064		T2	186		T3	16712
all_pins[1]	2369628	1			T1	1064		T2	186		T3	16712
all_pins[2]	2369628	1			T1	1064		T2	186		T3	16712
all_pins[3]	2369628	1			T1	1064		T2	186		T3	16712
all_pins[4]	2369628	1			T1	1064		T2	186		T3	16712
all_pins[5]	2369628	1			T1	1064		T2	186		T3	16712
all_pins[6]	2369628	1			T1	1064		T2	186		T3	16712
all_pins[7]	2369628	1			T1	1064		T2	186		T3	16712

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	18863492	1			T1	8512		T2	1488		T3	118938
values[0x1]	93532	1			T3	14758		T7	13		T18	25
transitions[0x0=>0x1]	90662	1			T3	14135		T7	13		T18	25
transitions[0x1=>0x0]	90668	1			T3	14135		T7	13		T18	25

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2368731	1			T1	1064		T2	186		T3	16534
all_pins[0]	values[0x1]	897	1			T3	178		T7	1		T18	5
all_pins[0]	transitions[0x0=>0x1]	622	1			T3	70		T7	1		T18	5
all_pins[0]	transitions[0x1=>0x0]	259	1			T3	2		T7	5		T18	2
all_pins[1]	values[0x0]	2369094	1			T1	1064		T2	186		T3	16602
all_pins[1]	values[0x1]	534	1			T3	110		T7	5		T18	2
all_pins[1]	transitions[0x0=>0x1]	448	1			T3	102		T7	5		T18	2
all_pins[1]	transitions[0x1=>0x0]	143	1			T7	1		T18	2		T21	7
all_pins[2]	values[0x0]	2369399	1			T1	1064		T2	186		T3	16704
all_pins[2]	values[0x1]	229	1			T3	8		T7	1		T18	2
all_pins[2]	transitions[0x0=>0x1]	191	1			T3	8		T7	1		T18	2
all_pins[2]	transitions[0x1=>0x0]	159	1			T3	1		T7	1		T18	2
all_pins[3]	values[0x0]	2369431	1			T1	1064		T2	186		T3	16711
all_pins[3]	values[0x1]	197	1			T3	1		T7	1		T18	2
all_pins[3]	transitions[0x0=>0x1]	138	1			T3	1		T7	1		T18	2
all_pins[3]	transitions[0x1=>0x0]	164	1			T3	1		T7	1		T18	4
all_pins[4]	values[0x0]	2369405	1			T1	1064		T2	186		T3	16711
all_pins[4]	values[0x1]	223	1			T3	1		T7	1		T18	4
all_pins[4]	transitions[0x0=>0x1]	177	1			T3	1		T7	1		T18	4
all_pins[4]	transitions[0x1=>0x0]	2576	1			T3	503		T7	1		T18	5
all_pins[5]	values[0x0]	2367006	1			T1	1064		T2	186		T3	16209
all_pins[5]	values[0x1]	2622	1			T3	503		T7	1		T18	5
all_pins[5]	transitions[0x0=>0x1]	364	1			T3	2		T7	1		T18	5
all_pins[5]	transitions[0x1=>0x0]	86375	1			T3	13450		T7	1		T21	6
all_pins[6]	values[0x0]	2280995	1			T1	1064		T2	186		T3	2761
all_pins[6]	values[0x1]	88633	1			T3	13951		T7	1		T21	7
all_pins[6]	transitions[0x0=>0x1]	88579	1			T3	13948		T7	1		T21	7
all_pins[6]	transitions[0x1=>0x0]	143	1			T3	3		T7	2		T18	5
all_pins[7]	values[0x0]	2369431	1			T1	1064		T2	186		T3	16706
all_pins[7]	values[0x1]	197	1			T3	6		T7	2		T18	5
all_pins[7]	transitions[0x0=>0x1]	143	1			T3	3		T7	2		T18	5
all_pins[7]	transitions[0x1=>0x0]	849	1			T3	175		T7	1		T18	5