Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

15484

1

T2

4

T3

21

T4

4

auto[1]

12346

1

T3

53

T7

78

T13

18

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3673	1			T2	4		T7	73		T13	18
values[1]	3038	1			T4	4		T33	115		T40	91
values[2]	3265	1			T3	23		T7	46		T16	8
values[3]	3141	1			T11	66		T40	36		T18	20
values[4]	4190	1			T3	51		T7	89		T33	129
values[5]	3465	1			T33	30		T67	4		T18	46
values[6]	3333	1			T39	24		T40	63		T42	40
values[7]	3725	1			T83	6		T33	22		T40	200

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3174	1			T7	46		T16	8		T41	6
values[1]	3953	1			T83	6		T33	22		T40	117
values[2]	3810	1			T7	51		T33	98		T40	171
values[3]	3106	1			T2	4		T3	51		T7	44
values[4]	3833	1			T4	4		T40	210		T18	28
values[5]	3066	1			T7	67		T11	66		T33	123
values[6]	3635	1			T3	23		T39	24		T33	31
values[7]	3253	1			T13	18		T33	69		T40	119

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	328	1			T36	15		T230	48		T216	77
auto[0]	values[0]	values[1]	166	1			T40	7		T178	10		T243	21
auto[0]	values[0]	values[2]	265	1			T7	20		T43	8		T159	15
auto[0]	values[0]	values[3]	166	1			T2	4		T7	18		T190	12
auto[0]	values[0]	values[4]	272	1			T34	16		T43	13		T203	10
auto[0]	values[0]	values[5]	167	1			T214	14		T244	8		T205	24
auto[0]	values[0]	values[6]	360	1			T40	13		T34	15		T43	11
auto[0]	values[0]	values[7]	291	1			T33	11		T224	16		T204	12
auto[0]	values[1]	values[0]	117	1			T245	2		T233	11		T188	8
auto[0]	values[1]	values[1]	281	1			T33	15		T18	8		T246	10
auto[0]	values[1]	values[2]	330	1			T34	8		T43	15		T247	20
auto[0]	values[1]	values[3]	260	1			T35	11		T80	12		T195	9
auto[0]	values[1]	values[4]	160	1			T4	4		T35	9		T246	17
auto[0]	values[1]	values[5]	180	1			T33	62		T154	12		T178	10
auto[0]	values[1]	values[6]	231	1			T40	54		T34	9		T248	16
auto[0]	values[1]	values[7]	148	1			T40	23		T171	24		T226	18
auto[0]	values[2]	values[0]	187	1			T7	24		T16	8		T41	6
auto[0]	values[2]	values[1]	286	1			T213	117		T205	8		T249	2
auto[0]	values[2]	values[2]	256	1			T250	16		T241	12		T195	24
auto[0]	values[2]	values[3]	259	1			T36	5		T251	12		T252	12
auto[0]	values[2]	values[4]	333	1			T40	50		T18	17		T35	43
auto[0]	values[2]	values[5]	170	1			T19	10		T213	9		T35	12
auto[0]	values[2]	values[6]	351	1			T3	11		T19	11		T191	9
auto[0]	values[2]	values[7]	184	1			T40	11		T36	9		T203	11
auto[0]	values[3]	values[0]	157	1			T253	6		T239	11		T217	2
auto[0]	values[3]	values[1]	203	1			T216	11		T229	11		T254	20
auto[0]	values[3]	values[2]	152	1			T19	28		T207	13		T188	18
auto[0]	values[3]	values[3]	145	1			T255	8		T256	6		T257	2
auto[0]	values[3]	values[4]	170	1			T213	14		T191	10		T36	17
auto[0]	values[3]	values[5]	240	1			T11	66		T214	8		T258	8
auto[0]	values[3]	values[6]	283	1			T40	12		T43	6		T36	34
auto[0]	values[3]	values[7]	327	1			T18	9		T36	31		T190	113
auto[0]	values[4]	values[0]	381	1			T229	11		T207	131		T205	14
auto[0]	values[4]	values[1]	241	1			T192	12		T81	16		T188	9
auto[0]	values[4]	values[2]	274	1			T7	12		T33	80		T40	9
auto[0]	values[4]	values[3]	259	1			T3	10		T34	6		T43	11
auto[0]	values[4]	values[4]	331	1			T34	13		T191	7		T36	8
auto[0]	values[4]	values[5]	317	1			T7	56		T195	11		T203	13
auto[0]	values[4]	values[6]	335	1			T33	11		T19	19		T35	44
auto[0]	values[4]	values[7]	168	1			T18	11		T209	9		T229	9
auto[0]	values[5]	values[0]	158	1			T18	19		T241	9		T203	11
auto[0]	values[5]	values[1]	241	1			T19	20		T36	7		T178	10
auto[0]	values[5]	values[2]	422	1			T34	12		T154	67		T216	11
auto[0]	values[5]	values[3]	292	1			T216	36		T195	14		T207	12
auto[0]	values[5]	values[4]	293	1			T178	17		T230	9		T259	6
auto[0]	values[5]	values[5]	240	1			T33	24		T18	10		T230	6
auto[0]	values[5]	values[6]	254	1			T67	4		T190	39		T260	15
auto[0]	values[5]	values[7]	172	1			T34	10		T96	10		T159	8
auto[0]	values[6]	values[0]	382	1			T35	14		T154	74		T158	25
auto[0]	values[6]	values[1]	228	1			T40	10		T209	23		T260	12
auto[0]	values[6]	values[2]	206	1			T43	14		T35	19		T178	13
auto[0]	values[6]	values[3]	123	1			T84	8		T213	7		T160	6
auto[0]	values[6]	values[4]	192	1			T40	11		T189	8		T150	13
auto[0]	values[6]	values[5]	162	1			T42	9		T261	2		T241	25
auto[0]	values[6]	values[6]	265	1			T39	24		T42	8		T248	10
auto[0]	values[6]	values[7]	275	1			T34	14		T191	9		T190	9
auto[0]	values[7]	values[0]	215	1			T68	2		T19	7		T35	6
auto[0]	values[7]	values[1]	220	1			T83	6		T230	30		T229	12
auto[0]	values[7]	values[2]	257	1			T40	20		T171	16		T190	13
auto[0]	values[7]	values[3]	299	1			T18	17		T262	6		T207	7
auto[0]	values[7]	values[4]	283	1			T40	98		T171	8		T263	6
auto[0]	values[7]	values[5]	308	1			T18	10		T172	23		T264	10
auto[0]	values[7]	values[6]	82	1			T35	15		T157	2		T265	4
auto[0]	values[7]	values[7]	184	1			T33	17		T35	11		T231	20
auto[1]	values[0]	values[0]	119	1			T36	8		T230	12		T216	9
auto[1]	values[0]	values[1]	366	1			T40	90		T178	10		T185	8
auto[1]	values[0]	values[2]	170	1			T7	9		T43	14		T159	25
auto[1]	values[0]	values[3]	231	1			T7	26		T190	18		T188	8
auto[1]	values[0]	values[4]	160	1			T34	4		T43	9		T203	10
auto[1]	values[0]	values[5]	156	1			T214	6		T205	16		T266	12
auto[1]	values[0]	values[6]	181	1			T40	33		T34	5		T43	10
auto[1]	values[0]	values[7]	275	1			T13	18		T33	36		T209	7
auto[1]	values[1]	values[0]	116	1			T233	9		T188	13		T236	12
auto[1]	values[1]	values[1]	284	1			T33	7		T18	12		T246	48
auto[1]	values[1]	values[2]	239	1			T34	12		T43	12		T205	14
auto[1]	values[1]	values[3]	190	1			T35	13		T195	11		T203	12
auto[1]	values[1]	values[4]	162	1			T35	11		T246	8		T241	18
auto[1]	values[1]	values[5]	133	1			T33	31		T69	20		T154	8
auto[1]	values[1]	values[6]	104	1			T40	4		T34	11		T248	6
auto[1]	values[1]	values[7]	103	1			T40	10		T171	8		T186	11
auto[1]	values[2]	values[0]	162	1			T7	22		T40	13		T43	10
auto[1]	values[2]	values[1]	101	1			T213	7		T205	12		T188	19
auto[1]	values[2]	values[2]	261	1			T241	8		T195	16		T229	40
auto[1]	values[2]	values[3]	114	1			T36	15		T260	4		T201	15
auto[1]	values[2]	values[4]	152	1			T40	10		T18	11		T35	5
auto[1]	values[2]	values[5]	93	1			T19	10		T213	11		T35	9
auto[1]	values[2]	values[6]	194	1			T3	12		T19	10		T191	12
auto[1]	values[2]	values[7]	162	1			T40	75		T36	13		T203	9
auto[1]	values[3]	values[0]	127	1			T239	9		T205	7		T188	58
auto[1]	values[3]	values[1]	100	1			T216	9		T229	9		T254	20
auto[1]	values[3]	values[2]	257	1			T19	11		T207	10		T188	11
auto[1]	values[3]	values[3]	120	1			T186	6		T267	6		T129	8
auto[1]	values[3]	values[4]	147	1			T213	39		T191	21		T36	6
auto[1]	values[3]	values[5]	261	1			T214	12		T233	11		T267	8
auto[1]	values[3]	values[6]	259	1			T40	24		T43	14		T36	13
auto[1]	values[3]	values[7]	193	1			T18	11		T36	12		T190	5
auto[1]	values[4]	values[0]	221	1			T229	14		T207	4		T205	6
auto[1]	values[4]	values[1]	278	1			T188	11		T186	6		T268	6
auto[1]	values[4]	values[2]	219	1			T7	10		T33	18		T40	69
auto[1]	values[4]	values[3]	266	1			T3	41		T34	14		T43	9
auto[1]	values[4]	values[4]	187	1			T34	7		T191	18		T36	12
auto[1]	values[4]	values[5]	221	1			T7	11		T269	10		T195	9
auto[1]	values[4]	values[6]	248	1			T33	20		T19	5		T35	4
auto[1]	values[4]	values[7]	244	1			T18	16		T221	4		T209	25
auto[1]	values[5]	values[0]	111	1			T18	7		T241	11		T203	9
auto[1]	values[5]	values[1]	234	1			T19	3		T36	13		T178	10
auto[1]	values[5]	values[2]	145	1			T34	8		T154	7		T216	9
auto[1]	values[5]	values[3]	174	1			T216	11		T195	6		T207	31
auto[1]	values[5]	values[4]	210	1			T178	3		T230	67		T241	12
auto[1]	values[5]	values[5]	161	1			T33	6		T18	10		T230	95
auto[1]	values[5]	values[6]	225	1			T190	9		T260	5		T239	5
auto[1]	values[5]	values[7]	133	1			T34	10		T159	12		T178	14
auto[1]	values[6]	values[0]	219	1			T35	6		T154	8		T36	8
auto[1]	values[6]	values[1]	299	1			T40	10		T209	17		T260	8
auto[1]	values[6]	values[2]	135	1			T43	9		T35	10		T178	7
auto[1]	values[6]	values[3]	56	1			T213	13		T203	10		T236	7
auto[1]	values[6]	values[4]	330	1			T40	32		T150	7		T270	27
auto[1]	values[6]	values[5]	91	1			T42	11		T241	5		T207	7
auto[1]	values[6]	values[6]	183	1			T42	12		T248	26		T159	5
auto[1]	values[6]	values[7]	187	1			T34	6		T44	6		T191	11
auto[1]	values[7]	values[0]	174	1			T19	13		T35	22		T154	11
auto[1]	values[7]	values[1]	425	1			T230	8		T229	98		T188	40
auto[1]	values[7]	values[2]	222	1			T40	73		T171	13		T190	7
auto[1]	values[7]	values[3]	152	1			T18	6		T207	26		T188	11
auto[1]	values[7]	values[4]	451	1			T40	9		T171	12		T190	43
auto[1]	values[7]	values[5]	166	1			T18	10		T241	16		T229	10
auto[1]	values[7]	values[6]	80	1			T35	5		T195	12		T186	12
auto[1]	values[7]	values[7]	207	1			T33	5		T35	11		T241	8