Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	353	1			T3	2		T33	5		T40	8
auto[ReadAddrCrossIntoMailbox]	275	1			T7	4		T33	5		T40	5
auto[ReadAddrCrossOutOfMailbox]	297	1			T3	2		T33	5		T40	6
auto[ReadAddrCrossAllMailbox]	254	1			T7	2		T33	2		T40	4
auto[ReadAddrOutsideMailbox]	3323	1			T3	7		T4	2		T7	22

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2181

1

T3

5

T4

1

T7

21

auto[1]

2321

1

T3

6

T4

1

T7

7

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	753	1			T3	3		T4	2		T7	5
read_ops[0x0b]	788	1			T3	2		T7	7		T13	4
read_ops[0x3b]	797	1			T7	5		T13	2		T39	4
read_ops[0x6b]	693	1			T7	5		T16	2		T33	9
read_ops[0xbb]	780	1			T3	3		T7	4		T83	2
read_ops[0xeb]	691	1			T3	3		T7	2		T13	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	38	1			T3	1		T40	2		T43	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	42	1			T43	2		T213	1		T191	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	18	1			T34	1		T213	1		T35	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	19	1			T33	1		T40	2		T36	2
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	23	1			T3	1		T33	1		T213	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	19	1			T33	1		T34	1		T191	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	19	1			T7	1		T213	1		T229	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	22	1			T33	1		T34	1		T216	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	272	1			T3	1		T4	1		T33	3
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	281	1			T4	1		T7	4		T33	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	24	1			T40	1		T34	1		T35	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	28	1			T33	1		T36	1		T178	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	15	1			T7	2		T246	1		T241	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	23	1			T33	1		T35	1		T36	2
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	27	1			T33	2		T40	2		T250	2
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	25	1			T3	1		T19	1		T191	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	32	1			T40	2		T248	1		T36	2
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	20	1			T250	1		T195	1		T260	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	296	1			T7	4		T13	2		T39	2
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	298	1			T3	1		T7	1		T13	2
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	25	1			T40	1		T18	1		T216	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	29	1			T33	3		T40	1		T19	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	24	1			T34	1		T43	1		T191	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	26	1			T34	2		T213	1		T191	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	21	1			T35	1		T248	2		T178	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	30	1			T40	1		T19	1		T213	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	24	1			T18	1		T96	1		T36	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	27	1			T40	1		T96	1		T250	3
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	297	1			T7	4		T13	1		T39	2
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	294	1			T7	1		T13	1		T39	2
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	33	1			T43	1		T36	1		T178	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	24	1			T40	2		T36	1		T190	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	28	1			T7	2		T33	1		T40	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	28	1			T33	1		T40	1		T154	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	31	1			T40	1		T18	1		T248	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	20	1			T33	1		T34	1		T154	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T40	1		T231	2		T229	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	24	1			T42	1		T191	1		T36	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	239	1			T7	3		T16	1		T33	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	248	1			T16	1		T33	4		T40	5
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	27	1			T40	1		T213	2		T36	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	33	1			T3	1		T33	1		T154	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	26	1			T213	1		T36	1		T178	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	27	1			T34	1		T191	1		T178	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	24	1			T18	1		T34	1		T43	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	17	1			T43	1		T154	2		T207	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	12	1			T96	1		T195	1		T188	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	25	1			T7	1		T96	1		T19	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	270	1			T3	2		T7	3		T83	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	319	1			T83	1		T33	1		T40	6
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	22	1			T213	1		T191	1		T195	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	28	1			T34	1		T36	1		T190	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	13	1			T36	1		T178	1		T179	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	28	1			T33	1		T40	1		T43	2
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	29	1			T34	1		T262	1		T195	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	31	1			T40	2		T213	1		T248	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	11	1			T33	1		T262	1		T36	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	20	1			T19	1		T262	1		T178	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	243	1			T7	2		T13	1		T40	4
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	266	1			T3	3		T13	1		T33	2