Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3330	1			T13	18		T67	4		T18	40
values[1]	2985	1			T3	51		T16	8		T83	6
values[2]	3687	1			T7	23		T40	142		T69	20
values[3]	3845	1			T3	23		T7	118		T33	53
values[4]	3114	1			T33	75		T40	36		T42	20
values[5]	4009	1			T7	23		T41	6		T39	24
values[6]	3248	1			T2	4		T7	44		T11	66
values[7]	3612	1			T4	4		T40	152		T34	20

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3657	1			T7	67		T83	6		T33	29
values[1]	2995	1			T39	24		T33	47		T40	58
values[2]	3371	1			T2	4		T41	6		T67	4
values[3]	3386	1			T7	29		T40	128		T69	20
values[4]	3751	1			T7	23		T11	66		T13	18
values[5]	3487	1			T3	51		T4	4		T7	23
values[6]	3621	1			T33	156		T40	97		T18	43
values[7]	3562	1			T3	23		T7	66		T18	66

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27098

1

T2

4

T3

70

T4

4

auto[1]

732

1

T3

4

T7

9

T33

6

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	327	1			T42	18		T247	20		T271	16
auto[0]	values[0]	values[1]	352	1			T44	4		T213	20		T171	31
auto[0]	values[0]	values[2]	327	1			T67	4		T216	86		T188	52
auto[0]	values[0]	values[3]	615	1			T19	45		T36	20		T272	4
auto[0]	values[0]	values[4]	405	1			T13	18		T18	20		T154	80
auto[0]	values[0]	values[5]	217	1			T191	24		T36	20		T241	20
auto[0]	values[0]	values[6]	316	1			T34	20		T96	10		T35	45
auto[0]	values[0]	values[7]	685	1			T18	19		T19	20		T190	55
auto[0]	values[1]	values[0]	293	1			T83	6		T18	26		T35	44
auto[0]	values[1]	values[1]	238	1			T239	20		T212	24		T273	2
auto[0]	values[1]	values[2]	440	1			T34	20		T231	20		T214	18
auto[0]	values[1]	values[3]	325	1			T35	28		T159	20		T223	14
auto[0]	values[1]	values[4]	363	1			T16	8		T33	29		T251	12
auto[0]	values[1]	values[5]	527	1			T3	49		T36	22		T195	20
auto[0]	values[1]	values[6]	472	1			T34	40		T250	16		T274	8
auto[0]	values[1]	values[7]	234	1			T43	21		T189	8		T207	45
auto[0]	values[2]	values[0]	483	1			T40	78		T275	8		T195	56
auto[0]	values[2]	values[1]	519	1			T178	20		T230	37		T255	8
auto[0]	values[2]	values[2]	422	1			T34	20		T207	30		T276	2
auto[0]	values[2]	values[3]	570	1			T40	19		T69	20		T18	27
auto[0]	values[2]	values[4]	553	1			T7	21		T34	19		T43	21
auto[0]	values[2]	values[5]	412	1			T40	40		T154	20		T178	18
auto[0]	values[2]	values[6]	321	1			T35	20		T155	6		T216	20
auto[0]	values[2]	values[7]	317	1			T18	25		T35	22		T205	20
auto[0]	values[3]	values[0]	699	1			T7	67		T159	19		T36	20
auto[0]	values[3]	values[1]	327	1			T34	19		T277	14		T239	60
auto[0]	values[3]	values[2]	311	1			T35	42		T241	54		T212	22
auto[0]	values[3]	values[3]	671	1			T7	28		T40	106		T191	19
auto[0]	values[3]	values[4]	336	1			T33	29		T216	40		T278	2
auto[0]	values[3]	values[5]	389	1			T33	22		T193	12		T241	19
auto[0]	values[3]	values[6]	673	1			T18	21		T35	23		T36	22
auto[0]	values[3]	values[7]	331	1			T3	21		T7	21		T18	18
auto[0]	values[4]	values[0]	285	1			T19	39		T36	23		T207	20
auto[0]	values[4]	values[1]	251	1			T33	45		T19	18		T248	36
auto[0]	values[4]	values[2]	574	1			T248	22		T195	20		T205	33
auto[0]	values[4]	values[3]	306	1			T42	16		T213	123		T191	20
auto[0]	values[4]	values[4]	243	1			T33	28		T36	23		T190	28
auto[0]	values[4]	values[5]	561	1			T40	33		T35	24		T159	18
auto[0]	values[4]	values[6]	402	1			T214	20		T229	43		T207	20
auto[0]	values[4]	values[7]	419	1			T213	53		T239	44		T205	30
auto[0]	values[5]	values[0]	787	1			T33	28		T40	60		T230	60
auto[0]	values[5]	values[1]	423	1			T39	24		T36	47		T230	75
auto[0]	values[5]	values[2]	378	1			T41	6		T40	32		T241	23
auto[0]	values[5]	values[3]	296	1			T241	20		T279	18		T188	42
auto[0]	values[5]	values[4]	566	1			T190	20		T230	24		T203	20
auto[0]	values[5]	values[5]	385	1			T7	23		T40	15		T68	2
auto[0]	values[5]	values[6]	472	1			T171	20		T154	74		T195	20
auto[0]	values[5]	values[7]	614	1			T43	20		T171	28		T269	10
auto[0]	values[6]	values[0]	148	1			T157	2		T190	20		T224	16
auto[0]	values[6]	values[1]	485	1			T40	58		T43	39		T213	20
auto[0]	values[6]	values[2]	431	1			T2	4		T191	20		T229	31
auto[0]	values[6]	values[3]	188	1			T36	19		T214	20		T209	20
auto[0]	values[6]	values[4]	533	1			T11	66		T40	72		T203	17
auto[0]	values[6]	values[5]	269	1			T263	6		T218	20		T188	74
auto[0]	values[6]	values[6]	592	1			T33	156		T40	95		T18	20
auto[0]	values[6]	values[7]	516	1			T7	39		T159	19		T265	4
auto[0]	values[7]	values[0]	560	1			T190	118		T230	101		T205	33
auto[0]	values[7]	values[1]	318	1			T43	22		T84	8		T35	67
auto[0]	values[7]	values[2]	402	1			T191	31		T195	18		T214	20
auto[0]	values[7]	values[3]	321	1			T203	20		T280	10		T281	20
auto[0]	values[7]	values[4]	647	1			T40	85		T172	23		T282	8
auto[0]	values[7]	values[5]	640	1			T4	4		T40	62		T34	20
auto[0]	values[7]	values[6]	274	1			T43	24		T178	36		T252	12
auto[0]	values[7]	values[7]	342	1			T262	6		T178	20		T253	6
auto[1]	values[0]	values[0]	11	1			T42	2		T212	2		T188	2
auto[1]	values[0]	values[1]	11	1			T44	2		T171	1		T246	4
auto[1]	values[0]	values[2]	1	1			T188	1		-	-		-	-
auto[1]	values[0]	values[3]	17	1			T19	2		T36	1		T260	1
auto[1]	values[0]	values[4]	12	1			T154	2		T36	1		T195	1
auto[1]	values[0]	values[5]	4	1			T191	1		T188	1		T283	1
auto[1]	values[0]	values[6]	10	1			T35	3		T178	1		T284	1
auto[1]	values[0]	values[7]	20	1			T18	1		T19	1		T199	2
auto[1]	values[1]	values[0]	13	1			T18	2		T236	3		T133	4
auto[1]	values[1]	values[1]	5	1			T212	1		T285	1		T286	2
auto[1]	values[1]	values[2]	19	1			T214	2		T239	1		T185	1
auto[1]	values[1]	values[3]	6	1			T35	1		T229	1		T129	1
auto[1]	values[1]	values[4]	10	1			T33	1		T214	1		T201	2
auto[1]	values[1]	values[5]	11	1			T3	2		T266	4		T254	1
auto[1]	values[1]	values[6]	18	1			T274	14		T188	1		T185	1
auto[1]	values[1]	values[7]	11	1			T43	1		T207	1		T188	1
auto[1]	values[2]	values[0]	15	1			T195	4		T209	2		T260	1
auto[1]	values[2]	values[1]	10	1			T230	1		T205	1		T287	1
auto[1]	values[2]	values[2]	11	1			T207	3		T288	1		T289	2
auto[1]	values[2]	values[3]	16	1			T40	2		T34	2		T19	1
auto[1]	values[2]	values[4]	14	1			T7	2		T34	1		T154	2
auto[1]	values[2]	values[5]	9	1			T40	3		T178	2		T229	4
auto[1]	values[2]	values[6]	6	1			T186	3		T268	1		T132	2
auto[1]	values[2]	values[7]	9	1			T18	1		T285	2		T290	1
auto[1]	values[3]	values[0]	14	1			T159	1		T130	2		T291	2
auto[1]	values[3]	values[1]	10	1			T34	1		T233	1		T287	1
auto[1]	values[3]	values[2]	14	1			T35	6		T241	3		T188	1
auto[1]	values[3]	values[3]	19	1			T7	1		T40	1		T191	1
auto[1]	values[3]	values[4]	10	1			T33	2		T150	2		T292	3
auto[1]	values[3]	values[5]	8	1			T241	1		T293	1		T294	2
auto[1]	values[3]	values[6]	17	1			T18	2		T35	1		T214	1
auto[1]	values[3]	values[7]	16	1			T3	2		T7	1		T18	2
auto[1]	values[4]	values[0]	4	1			T188	2		T295	1		T296	1
auto[1]	values[4]	values[1]	11	1			T33	2		T19	2		T150	3
auto[1]	values[4]	values[2]	10	1			T205	3		T297	3		T285	2
auto[1]	values[4]	values[3]	9	1			T42	4		T213	1		T191	1
auto[1]	values[4]	values[4]	6	1			T190	2		T298	3		T286	1
auto[1]	values[4]	values[5]	17	1			T40	3		T159	2		T36	1
auto[1]	values[4]	values[6]	11	1			T188	5		T179	3		T299	2
auto[1]	values[4]	values[7]	5	1			T239	1		T292	1		T225	1
auto[1]	values[5]	values[0]	5	1			T33	1		T207	1		T300	1
auto[1]	values[5]	values[1]	9	1			T230	1		T236	1		T200	1
auto[1]	values[5]	values[2]	9	1			T40	1		T241	1		T267	2
auto[1]	values[5]	values[3]	9	1			T188	1		T185	1		T301	2
auto[1]	values[5]	values[4]	20	1			T188	1		T302	1		T267	7
auto[1]	values[5]	values[5]	21	1			T40	5		T203	2		T254	1
auto[1]	values[5]	values[6]	9	1			T236	1		T254	3		T133	3
auto[1]	values[5]	values[7]	6	1			T171	1		T188	2		T198	1
auto[1]	values[6]	values[0]	2	1			T241	2		-	-		-	-
auto[1]	values[6]	values[1]	21	1			T43	7		T185	1		T303	3
auto[1]	values[6]	values[2]	12	1			T229	1		T130	3		T304	4
auto[1]	values[6]	values[3]	1	1			T36	1		-	-		-	-
auto[1]	values[6]	values[4]	19	1			T203	3		T254	5		T297	1
auto[1]	values[6]	values[5]	4	1			T188	1		T297	3		-	-
auto[1]	values[6]	values[6]	7	1			T40	2		T216	1		T195	2
auto[1]	values[6]	values[7]	20	1			T7	5		T159	1		T216	1
auto[1]	values[7]	values[0]	11	1			T305	2		T306	4		T51	4
auto[1]	values[7]	values[1]	5	1			T35	2		T268	1		T307	1
auto[1]	values[7]	values[2]	10	1			T195	2		T292	2		T289	2
auto[1]	values[7]	values[3]	17	1			T188	6		T235	3		T307	2
auto[1]	values[7]	values[4]	14	1			T40	1		T282	2		T188	3
auto[1]	values[7]	values[5]	13	1			T40	4		T195	1		T308	4
auto[1]	values[7]	values[6]	21	1			T43	3		T178	4		T229	3
auto[1]	values[7]	values[7]	17	1			T209	4		T287	3		T188	2