Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	810	1			T3	10		T7	10		T18	17
all_values[1]	810	1			T3	10		T7	10		T18	17
all_values[2]	810	1			T3	10		T7	10		T18	17
all_values[3]	810	1			T3	10		T7	10		T18	17
all_values[4]	810	1			T3	10		T7	10		T18	17
all_values[5]	810	1			T3	10		T7	10		T18	17
all_values[6]	810	1			T3	10		T7	10		T18	17
all_values[7]	810	1			T3	10		T7	10		T18	17

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3459

1

T3

45

T7

37

T18

75

auto[1]

3021

1

T3

35

T7

43

T18

61

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2526

1

T3

29

T7

35

T18

60

auto[1]

3954

1

T3

51

T7

45

T18

76

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3661

1

T3

45

T7

44

T18

78

auto[1]

2819

1

T3

35

T7

36

T18

58

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	156	1			T3	2		T7	3		T18	4
all_values[0]	auto[0]	auto[0]	auto[1]	82	1			T3	1		T18	1		T21	3
all_values[0]	auto[0]	auto[1]	auto[0]	136	1			T7	3		T18	2		T19	1
all_values[0]	auto[0]	auto[1]	auto[1]	79	1			T3	3		T7	1		T18	2
all_values[0]	auto[1]	auto[0]	auto[1]	178	1			T3	1		T18	5		T19	2
all_values[0]	auto[1]	auto[1]	auto[1]	179	1			T3	3		T7	3		T18	3
all_values[1]	auto[0]	auto[0]	auto[0]	174	1			T3	2		T18	8		T19	3
all_values[1]	auto[0]	auto[0]	auto[1]	82	1			T7	2		T18	1		T19	1
all_values[1]	auto[0]	auto[1]	auto[0]	120	1			T3	1		T18	2		T19	1
all_values[1]	auto[0]	auto[1]	auto[1]	80	1			T3	1		T7	2		T21	1
all_values[1]	auto[1]	auto[0]	auto[1]	195	1			T3	4		T7	2		T18	3
all_values[1]	auto[1]	auto[1]	auto[1]	159	1			T3	2		T7	4		T18	3
all_values[2]	auto[0]	auto[0]	auto[0]	176	1			T3	2		T7	1		T18	2
all_values[2]	auto[0]	auto[0]	auto[1]	80	1			T3	2		T18	2		T19	2
all_values[2]	auto[0]	auto[1]	auto[0]	135	1			T3	3		T7	6		T18	1
all_values[2]	auto[0]	auto[1]	auto[1]	73	1			T18	2		T21	3		T23	1
all_values[2]	auto[1]	auto[0]	auto[1]	201	1			T3	3		T7	1		T18	8
all_values[2]	auto[1]	auto[1]	auto[1]	145	1			T7	2		T18	2		T19	2
all_values[3]	auto[0]	auto[0]	auto[0]	143	1			T3	3		T7	1		T18	5
all_values[3]	auto[0]	auto[0]	auto[1]	92	1			T3	1		T19	1		T21	1
all_values[3]	auto[0]	auto[1]	auto[0]	131	1			T7	3		T18	5		T19	1
all_values[3]	auto[0]	auto[1]	auto[1]	79	1			T3	1		T18	1		T21	1
all_values[3]	auto[1]	auto[0]	auto[1]	202	1			T3	5		T7	3		T18	5
all_values[3]	auto[1]	auto[1]	auto[1]	163	1			T7	3		T18	1		T19	1
all_values[4]	auto[0]	auto[0]	auto[0]	148	1			T3	3		T7	3		T18	1
all_values[4]	auto[0]	auto[0]	auto[1]	74	1			T3	1		T7	1		T18	3
all_values[4]	auto[0]	auto[1]	auto[0]	139	1			T3	1		T7	1		T18	4
all_values[4]	auto[0]	auto[1]	auto[1]	97	1			T3	1		T7	1		T18	1
all_values[4]	auto[1]	auto[0]	auto[1]	192	1			T3	4		T18	5		T19	1
all_values[4]	auto[1]	auto[1]	auto[1]	160	1			T7	4		T18	3		T19	2
all_values[5]	auto[0]	auto[0]	auto[0]	263	1			T3	3		T7	4		T18	3
all_values[5]	auto[0]	auto[1]	auto[0]	212	1			T3	3		T7	2		T18	8
all_values[5]	auto[1]	auto[0]	auto[1]	179	1			T3	1		T7	2		T18	3
all_values[5]	auto[1]	auto[1]	auto[1]	156	1			T3	3		T7	2		T18	3
all_values[6]	auto[0]	auto[0]	auto[0]	152	1			T3	2		T7	2		T18	4
all_values[6]	auto[0]	auto[0]	auto[1]	87	1			T7	2		T18	1		T21	1
all_values[6]	auto[0]	auto[1]	auto[0]	130	1			T3	4		T7	2		T18	3
all_values[6]	auto[0]	auto[1]	auto[1]	75	1			T3	1		T21	2		T23	3
all_values[6]	auto[1]	auto[0]	auto[1]	196	1			T3	1		T7	2		T18	5
all_values[6]	auto[1]	auto[1]	auto[1]	170	1			T3	2		T7	2		T18	4
all_values[7]	auto[0]	auto[0]	auto[0]	167	1			T7	4		T18	4		T19	3
all_values[7]	auto[0]	auto[0]	auto[1]	76	1			T3	2		T18	1		T21	5
all_values[7]	auto[0]	auto[1]	auto[0]	144	1			T18	4		T19	1		T21	5
all_values[7]	auto[0]	auto[1]	auto[1]	79	1			T3	2		T18	3		T19	2
all_values[7]	auto[1]	auto[0]	auto[1]	164	1			T3	2		T7	4		T18	1
all_values[7]	auto[1]	auto[1]	auto[1]	180	1			T3	4		T7	2		T18	4

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal