Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1902

1

T3

19

T6

5

T7

14

auto[1]

1887

1

T3

12

T6

7

T7

10

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2019

1

T3

31

T7

24

T8

6

auto[1]

1770

1

T6

12

T8

6

T9

27

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2996

1

T3

23

T6

12

T7

14

auto[1]

793

1

T3

8

T7

10

T8

2

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	748	1			T3	4		T6	2		T7	10
valid[1]	745	1			T3	5		T6	3		T7	2
valid[2]	750	1			T3	4		T6	3		T7	3
valid[3]	783	1			T3	5		T6	1		T7	3
valid[4]	763	1			T3	13		T6	3		T7	6

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	144	1			T7	1		T319	1		T43	1
auto[0]	auto[0]	valid[0]	auto[1]	160	1			T6	1		T9	4		T24	4
auto[0]	auto[0]	valid[1]	auto[0]	118	1			T3	2		T7	2		T43	2
auto[0]	auto[0]	valid[1]	auto[1]	163	1			T6	1		T9	1		T24	2
auto[0]	auto[0]	valid[2]	auto[0]	136	1			T3	1		T7	1		T26	2
auto[0]	auto[0]	valid[2]	auto[1]	170	1			T6	2		T9	5		T24	1
auto[0]	auto[0]	valid[3]	auto[0]	133	1			T3	3		T7	1		T8	1
auto[0]	auto[0]	valid[3]	auto[1]	171	1			T9	2		T24	1		T25	1
auto[0]	auto[0]	valid[4]	auto[0]	116	1			T3	7		T7	1		T8	1
auto[0]	auto[0]	valid[4]	auto[1]	184	1			T6	1		T9	1		T24	4
auto[0]	auto[1]	valid[0]	auto[0]	140	1			T3	1		T7	4		T26	3
auto[0]	auto[1]	valid[0]	auto[1]	144	1			T6	1		T8	2		T9	2
auto[0]	auto[1]	valid[1]	auto[0]	116	1			T3	2		T8	1		T26	1
auto[0]	auto[1]	valid[1]	auto[1]	191	1			T6	2		T8	1		T9	1
auto[0]	auto[1]	valid[2]	auto[0]	105	1			T3	1		T7	2		T8	1
auto[0]	auto[1]	valid[2]	auto[1]	173	1			T6	1		T8	1		T9	3
auto[0]	auto[1]	valid[3]	auto[0]	102	1			T3	2		T7	1		T26	2
auto[0]	auto[1]	valid[3]	auto[1]	209	1			T6	1		T8	1		T9	5
auto[0]	auto[1]	valid[4]	auto[0]	116	1			T3	4		T7	1		T27	1
auto[0]	auto[1]	valid[4]	auto[1]	205	1			T6	2		T8	1		T9	3
auto[1]	auto[0]	valid[0]	auto[0]	91	1			T3	3		T7	4		T26	1
auto[1]	auto[0]	valid[1]	auto[0]	72	1			T3	1		T27	1		T28	2
auto[1]	auto[0]	valid[2]	auto[0]	79	1			T3	1		T26	1		T28	1
auto[1]	auto[0]	valid[3]	auto[0]	96	1			T7	1		T28	2		T327	1
auto[1]	auto[0]	valid[4]	auto[0]	69	1			T3	1		T7	3		T27	1
auto[1]	auto[1]	valid[0]	auto[0]	69	1			T7	1		T27	2		T28	2
auto[1]	auto[1]	valid[1]	auto[0]	85	1			T26	1		T28	1		T18	1
auto[1]	auto[1]	valid[2]	auto[0]	87	1			T3	1		T26	1		T28	1
auto[1]	auto[1]	valid[3]	auto[0]	72	1			T27	1		T28	1		T47	1
auto[1]	auto[1]	valid[4]	auto[0]	73	1			T3	1		T7	1		T8	2

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal