Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

51527

1

T3

879

T7

431

T8

357

auto[1]

19335

1

T6

150

T8

67

T9

352

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

51908

1

T3

606

T6

150

T7

276

auto[1]

18954

1

T3

273

T7

155

T8

133

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	36656	1			T3	454		T6	83		T7	211
others[1]	5934	1			T3	79		T6	10		T7	34
others[2]	6011	1			T3	86		T6	13		T7	36
others[3]	6640	1			T3	74		T6	12		T7	40
interest[1]	3871	1			T3	64		T6	10		T7	25
interest[4]	23912	1			T3	287		T6	54		T7	147
interest[64]	11750	1			T3	122		T6	22		T7	85

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	16670	1			T3	316		T7	130		T8	120
auto[0]	auto[0]	others[1]	2836	1			T3	60		T7	25		T8	14
auto[0]	auto[0]	others[2]	2820	1			T3	61		T7	26		T8	25
auto[0]	auto[0]	others[3]	3041	1			T3	39		T7	24		T8	26
auto[0]	auto[0]	interest[1]	1780	1			T3	46		T7	12		T8	7
auto[0]	auto[0]	interest[4]	10788	1			T3	199		T7	88		T8	73
auto[0]	auto[0]	interest[64]	5426	1			T3	84		T7	59		T8	32
auto[0]	auto[1]	others[0]	10152	1			T6	83		T8	38		T9	177
auto[0]	auto[1]	others[1]	1552	1			T6	10		T8	7		T9	25
auto[0]	auto[1]	others[2]	1610	1			T6	13		T8	4		T9	28
auto[0]	auto[1]	others[3]	1770	1			T6	12		T8	8		T9	34
auto[0]	auto[1]	interest[1]	1026	1			T6	10		T9	23		T24	20
auto[0]	auto[1]	interest[4]	6686	1			T6	54		T8	26		T9	115
auto[0]	auto[1]	interest[64]	3225	1			T6	22		T8	10		T9	65
auto[1]	auto[0]	others[0]	9834	1			T3	138		T7	81		T8	56
auto[1]	auto[0]	others[1]	1546	1			T3	19		T7	9		T8	16
auto[1]	auto[0]	others[2]	1581	1			T3	25		T7	10		T8	12
auto[1]	auto[0]	others[3]	1829	1			T3	35		T7	16		T8	15
auto[1]	auto[0]	interest[1]	1065	1			T3	18		T7	13		T8	9
auto[1]	auto[0]	interest[4]	6438	1			T3	88		T7	59		T8	42
auto[1]	auto[0]	interest[64]	3099	1			T3	38		T7	26		T8	25

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal