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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.06 98.44 94.08 98.62 89.36 97.28 95.43 99.21


Total test records in report: 1151
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T1045 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.3723285048 Aug 09 06:40:01 PM PDT 24 Aug 09 06:40:02 PM PDT 24 16817863 ps
T1046 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2345142824 Aug 09 06:40:30 PM PDT 24 Aug 09 06:40:31 PM PDT 24 12141113 ps
T1047 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.1889821107 Aug 09 06:40:13 PM PDT 24 Aug 09 06:40:15 PM PDT 24 207604034 ps
T1048 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.56214551 Aug 09 06:40:29 PM PDT 24 Aug 09 06:40:30 PM PDT 24 19666700 ps
T1049 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.3321047068 Aug 09 06:39:53 PM PDT 24 Aug 09 06:39:54 PM PDT 24 15245564 ps
T1050 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.1443397530 Aug 09 06:40:20 PM PDT 24 Aug 09 06:40:22 PM PDT 24 48867515 ps
T93 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.4231267919 Aug 09 06:40:02 PM PDT 24 Aug 09 06:40:14 PM PDT 24 1075067526 ps
T1051 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.3821937758 Aug 09 06:40:27 PM PDT 24 Aug 09 06:40:27 PM PDT 24 13085688 ps
T1052 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.2068010604 Aug 09 06:40:13 PM PDT 24 Aug 09 06:40:19 PM PDT 24 101660635 ps
T1053 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.3735442773 Aug 09 06:40:28 PM PDT 24 Aug 09 06:40:29 PM PDT 24 11412024 ps
T163 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.1824021583 Aug 09 06:40:05 PM PDT 24 Aug 09 06:40:13 PM PDT 24 3377127320 ps
T1054 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.1131675532 Aug 09 06:40:09 PM PDT 24 Aug 09 06:40:10 PM PDT 24 13313007 ps
T1055 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.3824467345 Aug 09 06:40:21 PM PDT 24 Aug 09 06:40:23 PM PDT 24 63173778 ps
T1056 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2777048813 Aug 09 06:40:06 PM PDT 24 Aug 09 06:40:10 PM PDT 24 897779501 ps
T1057 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.3036945522 Aug 09 06:40:31 PM PDT 24 Aug 09 06:40:32 PM PDT 24 19235454 ps
T142 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3499577694 Aug 09 06:40:15 PM PDT 24 Aug 09 06:40:17 PM PDT 24 81061638 ps
T100 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.3326962304 Aug 09 06:39:58 PM PDT 24 Aug 09 06:40:14 PM PDT 24 549294920 ps
T110 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.1284983364 Aug 09 06:40:16 PM PDT 24 Aug 09 06:40:17 PM PDT 24 71250423 ps
T165 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.700266141 Aug 09 06:39:58 PM PDT 24 Aug 09 06:40:04 PM PDT 24 674037968 ps
T111 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.158644963 Aug 09 06:40:21 PM PDT 24 Aug 09 06:40:24 PM PDT 24 517787368 ps
T164 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.2579806853 Aug 09 06:40:19 PM PDT 24 Aug 09 06:40:31 PM PDT 24 291901567 ps
T1058 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.549938064 Aug 09 06:40:29 PM PDT 24 Aug 09 06:40:30 PM PDT 24 36282440 ps
T97 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.3776821411 Aug 09 06:39:57 PM PDT 24 Aug 09 06:40:02 PM PDT 24 628400325 ps
T1059 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.253084700 Aug 09 06:40:14 PM PDT 24 Aug 09 06:40:15 PM PDT 24 158723073 ps
T1060 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1921804592 Aug 09 06:40:12 PM PDT 24 Aug 09 06:40:13 PM PDT 24 29893729 ps
T176 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.4026286287 Aug 09 06:40:07 PM PDT 24 Aug 09 06:40:15 PM PDT 24 903439951 ps
T1061 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3948018169 Aug 09 06:40:02 PM PDT 24 Aug 09 06:40:28 PM PDT 24 3545559142 ps
T1062 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.3392500278 Aug 09 06:40:27 PM PDT 24 Aug 09 06:40:28 PM PDT 24 46717419 ps
T1063 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.1509956019 Aug 09 06:40:01 PM PDT 24 Aug 09 06:40:03 PM PDT 24 130067625 ps
T1064 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.248616322 Aug 09 06:40:31 PM PDT 24 Aug 09 06:40:31 PM PDT 24 128651515 ps
T1065 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.4127690497 Aug 09 06:40:30 PM PDT 24 Aug 09 06:40:31 PM PDT 24 17627858 ps
T143 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.2876598236 Aug 09 06:40:05 PM PDT 24 Aug 09 06:40:07 PM PDT 24 302402120 ps
T1066 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.2679392621 Aug 09 06:40:28 PM PDT 24 Aug 09 06:40:29 PM PDT 24 13899448 ps
T73 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2851716785 Aug 09 06:39:55 PM PDT 24 Aug 09 06:39:56 PM PDT 24 40849186 ps
T1067 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3425109328 Aug 09 06:40:06 PM PDT 24 Aug 09 06:40:10 PM PDT 24 1232927547 ps
T112 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1242922795 Aug 09 06:39:54 PM PDT 24 Aug 09 06:40:16 PM PDT 24 1063230027 ps
T1068 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.92314535 Aug 09 06:39:55 PM PDT 24 Aug 09 06:39:57 PM PDT 24 95175303 ps
T144 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.2090508611 Aug 09 06:40:27 PM PDT 24 Aug 09 06:40:35 PM PDT 24 698770228 ps
T113 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.2255348611 Aug 09 06:39:54 PM PDT 24 Aug 09 06:40:18 PM PDT 24 355638319 ps
T145 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.4112939090 Aug 09 06:39:57 PM PDT 24 Aug 09 06:40:00 PM PDT 24 371147858 ps
T146 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.3433478088 Aug 09 06:40:03 PM PDT 24 Aug 09 06:40:07 PM PDT 24 335503504 ps
T1069 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.2276741166 Aug 09 06:40:28 PM PDT 24 Aug 09 06:40:28 PM PDT 24 12771796 ps
T1070 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.587211922 Aug 09 06:40:07 PM PDT 24 Aug 09 06:40:08 PM PDT 24 17526090 ps
T1071 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.1891617949 Aug 09 06:40:02 PM PDT 24 Aug 09 06:40:03 PM PDT 24 21598166 ps
T98 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.2230999323 Aug 09 06:40:14 PM PDT 24 Aug 09 06:40:21 PM PDT 24 533540542 ps
T1072 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.1611007226 Aug 09 06:40:15 PM PDT 24 Aug 09 06:40:16 PM PDT 24 36793164 ps
T1073 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.3006681553 Aug 09 06:40:07 PM PDT 24 Aug 09 06:40:18 PM PDT 24 202569902 ps
T101 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3220392635 Aug 09 06:40:05 PM PDT 24 Aug 09 06:40:09 PM PDT 24 314836124 ps
T1074 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.3669763730 Aug 09 06:40:04 PM PDT 24 Aug 09 06:40:05 PM PDT 24 12869832 ps
T177 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.2002999904 Aug 09 06:40:17 PM PDT 24 Aug 09 06:40:29 PM PDT 24 1423650559 ps
T1075 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.267842029 Aug 09 06:40:07 PM PDT 24 Aug 09 06:40:11 PM PDT 24 53178188 ps
T114 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.4273852544 Aug 09 06:40:04 PM PDT 24 Aug 09 06:40:06 PM PDT 24 388233477 ps
T1076 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.965409280 Aug 09 06:40:08 PM PDT 24 Aug 09 06:40:11 PM PDT 24 633000953 ps
T147 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3458480079 Aug 09 06:39:59 PM PDT 24 Aug 09 06:40:03 PM PDT 24 781257100 ps
T115 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.295670533 Aug 09 06:40:07 PM PDT 24 Aug 09 06:40:09 PM PDT 24 93714032 ps
T99 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.1180763065 Aug 09 06:40:21 PM PDT 24 Aug 09 06:40:23 PM PDT 24 32531630 ps
T116 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.4247044371 Aug 09 06:40:03 PM PDT 24 Aug 09 06:40:05 PM PDT 24 43138994 ps
T117 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.2179178359 Aug 09 06:40:14 PM PDT 24 Aug 09 06:40:17 PM PDT 24 161806528 ps
T1077 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.1271545839 Aug 09 06:40:28 PM PDT 24 Aug 09 06:40:29 PM PDT 24 32030860 ps
T1078 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.3386515741 Aug 09 06:40:31 PM PDT 24 Aug 09 06:40:32 PM PDT 24 15754366 ps
T1079 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.2153708484 Aug 09 06:40:13 PM PDT 24 Aug 09 06:40:16 PM PDT 24 78618975 ps
T118 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1357082154 Aug 09 06:40:27 PM PDT 24 Aug 09 06:40:30 PM PDT 24 36302883 ps
T120 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.2144132259 Aug 09 06:40:09 PM PDT 24 Aug 09 06:40:11 PM PDT 24 304806154 ps
T1080 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.1787734273 Aug 09 06:40:20 PM PDT 24 Aug 09 06:40:21 PM PDT 24 11918018 ps
T168 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.918051202 Aug 09 06:40:04 PM PDT 24 Aug 09 06:40:27 PM PDT 24 3200119107 ps
T1081 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.2214704352 Aug 09 06:39:56 PM PDT 24 Aug 09 06:39:57 PM PDT 24 46351370 ps
T122 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.4076044786 Aug 09 06:39:55 PM PDT 24 Aug 09 06:39:58 PM PDT 24 169958749 ps
T169 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.1970573957 Aug 09 06:40:02 PM PDT 24 Aug 09 06:40:19 PM PDT 24 1446814508 ps
T1082 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3452914770 Aug 09 06:40:11 PM PDT 24 Aug 09 06:40:14 PM PDT 24 135047182 ps
T1083 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.2811521078 Aug 09 06:40:21 PM PDT 24 Aug 09 06:40:21 PM PDT 24 12629852 ps
T121 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.1494936809 Aug 09 06:40:02 PM PDT 24 Aug 09 06:40:05 PM PDT 24 58351761 ps
T1084 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.1603264195 Aug 09 06:40:09 PM PDT 24 Aug 09 06:40:12 PM PDT 24 169139064 ps
T1085 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.2129500686 Aug 09 06:40:00 PM PDT 24 Aug 09 06:40:02 PM PDT 24 199970777 ps
T1086 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.194243906 Aug 09 06:40:30 PM PDT 24 Aug 09 06:40:31 PM PDT 24 131734123 ps
T1087 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.2809311226 Aug 09 06:40:29 PM PDT 24 Aug 09 06:40:30 PM PDT 24 45126430 ps
T1088 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.2904271555 Aug 09 06:40:26 PM PDT 24 Aug 09 06:40:27 PM PDT 24 48337528 ps
T1089 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2091374350 Aug 09 06:40:08 PM PDT 24 Aug 09 06:40:11 PM PDT 24 52995063 ps
T1090 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.2864814314 Aug 09 06:39:57 PM PDT 24 Aug 09 06:39:59 PM PDT 24 26802312 ps
T123 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.2538830032 Aug 09 06:39:57 PM PDT 24 Aug 09 06:40:04 PM PDT 24 270328523 ps
T1091 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.3523128674 Aug 09 06:40:20 PM PDT 24 Aug 09 06:40:20 PM PDT 24 24379002 ps
T124 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.760834500 Aug 09 06:40:19 PM PDT 24 Aug 09 06:40:21 PM PDT 24 64205430 ps
T1092 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.2737138742 Aug 09 06:39:52 PM PDT 24 Aug 09 06:40:01 PM PDT 24 365640477 ps
T1093 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.1733601173 Aug 09 06:40:17 PM PDT 24 Aug 09 06:40:19 PM PDT 24 115024848 ps
T1094 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.2134301803 Aug 09 06:40:11 PM PDT 24 Aug 09 06:40:13 PM PDT 24 347382884 ps
T1095 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.2619545127 Aug 09 06:40:01 PM PDT 24 Aug 09 06:40:24 PM PDT 24 3759184616 ps
T1096 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2448834535 Aug 09 06:40:18 PM PDT 24 Aug 09 06:40:22 PM PDT 24 146454474 ps
T102 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.2336180037 Aug 09 06:40:04 PM PDT 24 Aug 09 06:40:06 PM PDT 24 37126605 ps
T1097 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.194355059 Aug 09 06:40:13 PM PDT 24 Aug 09 06:40:13 PM PDT 24 44892292 ps
T1098 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.738055052 Aug 09 06:40:04 PM PDT 24 Aug 09 06:40:05 PM PDT 24 146189802 ps
T103 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3318446170 Aug 09 06:40:07 PM PDT 24 Aug 09 06:40:12 PM PDT 24 382650409 ps
T1099 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.103686001 Aug 09 06:39:55 PM PDT 24 Aug 09 06:39:58 PM PDT 24 475855610 ps
T1100 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.1935795050 Aug 09 06:40:28 PM PDT 24 Aug 09 06:40:29 PM PDT 24 40366017 ps
T104 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.1814736906 Aug 09 06:40:13 PM PDT 24 Aug 09 06:40:17 PM PDT 24 205601744 ps
T1101 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.3086549525 Aug 09 06:40:05 PM PDT 24 Aug 09 06:40:06 PM PDT 24 15266937 ps
T1102 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.2290803489 Aug 09 06:40:08 PM PDT 24 Aug 09 06:40:10 PM PDT 24 163836171 ps
T1103 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.507553037 Aug 09 06:40:27 PM PDT 24 Aug 09 06:40:29 PM PDT 24 206638103 ps
T170 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.2291556074 Aug 09 06:40:09 PM PDT 24 Aug 09 06:40:18 PM PDT 24 4425642461 ps
T1104 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.4232003479 Aug 09 06:40:09 PM PDT 24 Aug 09 06:40:10 PM PDT 24 12922344 ps
T1105 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.1242376842 Aug 09 06:40:29 PM PDT 24 Aug 09 06:40:30 PM PDT 24 15698903 ps
T1106 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.633384532 Aug 09 06:40:19 PM PDT 24 Aug 09 06:40:20 PM PDT 24 15170507 ps
T1107 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3760695855 Aug 09 06:40:17 PM PDT 24 Aug 09 06:40:19 PM PDT 24 98388098 ps
T175 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.352068055 Aug 09 06:40:02 PM PDT 24 Aug 09 06:40:07 PM PDT 24 1583197501 ps
T1108 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.4098184016 Aug 09 06:39:57 PM PDT 24 Aug 09 06:40:11 PM PDT 24 216105874 ps
T1109 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.2186522197 Aug 09 06:40:08 PM PDT 24 Aug 09 06:40:10 PM PDT 24 158226850 ps
T1110 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.2334190624 Aug 09 06:40:27 PM PDT 24 Aug 09 06:40:28 PM PDT 24 56995931 ps
T1111 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.3589998697 Aug 09 06:39:56 PM PDT 24 Aug 09 06:40:01 PM PDT 24 127309485 ps
T1112 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.390247112 Aug 09 06:40:26 PM PDT 24 Aug 09 06:40:30 PM PDT 24 210146153 ps
T1113 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.856061837 Aug 09 06:39:56 PM PDT 24 Aug 09 06:40:28 PM PDT 24 527271824 ps
T1114 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3990228252 Aug 09 06:40:02 PM PDT 24 Aug 09 06:40:05 PM PDT 24 41954400 ps
T74 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3863887820 Aug 09 06:39:57 PM PDT 24 Aug 09 06:39:58 PM PDT 24 100040773 ps
T1115 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3587509762 Aug 09 06:40:13 PM PDT 24 Aug 09 06:40:16 PM PDT 24 406881326 ps
T1116 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.384889221 Aug 09 06:40:05 PM PDT 24 Aug 09 06:40:06 PM PDT 24 52774479 ps
T1117 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.1536233082 Aug 09 06:40:20 PM PDT 24 Aug 09 06:40:39 PM PDT 24 319582387 ps
T1118 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.2602564825 Aug 09 06:40:31 PM PDT 24 Aug 09 06:40:32 PM PDT 24 37542309 ps
T1119 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1861444256 Aug 09 06:39:57 PM PDT 24 Aug 09 06:40:19 PM PDT 24 353031081 ps
T1120 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2119489518 Aug 09 06:39:54 PM PDT 24 Aug 09 06:39:55 PM PDT 24 14056058 ps
T166 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.3272377010 Aug 09 06:39:53 PM PDT 24 Aug 09 06:40:07 PM PDT 24 2421309203 ps
T1121 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2967748873 Aug 09 06:39:57 PM PDT 24 Aug 09 06:39:59 PM PDT 24 91891509 ps
T1122 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.1123996590 Aug 09 06:39:59 PM PDT 24 Aug 09 06:40:01 PM PDT 24 61755063 ps
T1123 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3403232048 Aug 09 06:39:57 PM PDT 24 Aug 09 06:40:00 PM PDT 24 354120905 ps
T1124 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3348787187 Aug 09 06:40:30 PM PDT 24 Aug 09 06:40:31 PM PDT 24 13699921 ps
T1125 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.2447700562 Aug 09 06:40:26 PM PDT 24 Aug 09 06:40:27 PM PDT 24 38877362 ps
T1126 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.1155465066 Aug 09 06:40:14 PM PDT 24 Aug 09 06:40:14 PM PDT 24 14641818 ps
T1127 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2000273983 Aug 09 06:40:19 PM PDT 24 Aug 09 06:40:24 PM PDT 24 905992868 ps
T1128 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.199495793 Aug 09 06:40:29 PM PDT 24 Aug 09 06:40:30 PM PDT 24 17853418 ps
T1129 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.1277914391 Aug 09 06:40:01 PM PDT 24 Aug 09 06:40:04 PM PDT 24 467639331 ps
T1130 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.4077290345 Aug 09 06:40:08 PM PDT 24 Aug 09 06:40:13 PM PDT 24 659418438 ps
T1131 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.4147991200 Aug 09 06:39:54 PM PDT 24 Aug 09 06:39:58 PM PDT 24 1491342559 ps
T1132 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3929690137 Aug 09 06:39:58 PM PDT 24 Aug 09 06:39:59 PM PDT 24 10199722 ps
T1133 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.3711801678 Aug 09 06:40:07 PM PDT 24 Aug 09 06:40:10 PM PDT 24 35303738 ps
T1134 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1773110347 Aug 09 06:39:59 PM PDT 24 Aug 09 06:40:27 PM PDT 24 1878665350 ps
T1135 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.1591108204 Aug 09 06:40:07 PM PDT 24 Aug 09 06:40:10 PM PDT 24 151174851 ps
T1136 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.2133579509 Aug 09 06:40:06 PM PDT 24 Aug 09 06:40:07 PM PDT 24 53680561 ps
T1137 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3079612590 Aug 09 06:39:55 PM PDT 24 Aug 09 06:39:58 PM PDT 24 42792805 ps
T1138 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.1648994232 Aug 09 06:39:53 PM PDT 24 Aug 09 06:39:55 PM PDT 24 52471709 ps
T1139 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.2475525792 Aug 09 06:40:04 PM PDT 24 Aug 09 06:40:06 PM PDT 24 166409019 ps
T1140 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.2795354928 Aug 09 06:40:29 PM PDT 24 Aug 09 06:40:30 PM PDT 24 30069212 ps
T75 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2146662036 Aug 09 06:39:54 PM PDT 24 Aug 09 06:39:55 PM PDT 24 81744769 ps
T1141 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.1361543869 Aug 09 06:40:05 PM PDT 24 Aug 09 06:40:10 PM PDT 24 132604953 ps
T1142 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3049921460 Aug 09 06:40:13 PM PDT 24 Aug 09 06:40:15 PM PDT 24 335905132 ps
T76 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.783000568 Aug 09 06:39:59 PM PDT 24 Aug 09 06:40:00 PM PDT 24 24616141 ps
T1143 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.1098462314 Aug 09 06:40:08 PM PDT 24 Aug 09 06:40:11 PM PDT 24 190867806 ps
T1144 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.1625706722 Aug 09 06:40:14 PM PDT 24 Aug 09 06:40:16 PM PDT 24 205270260 ps
T1145 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.3202467078 Aug 09 06:39:56 PM PDT 24 Aug 09 06:39:57 PM PDT 24 40004811 ps
T1146 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.2054098626 Aug 09 06:39:57 PM PDT 24 Aug 09 06:39:59 PM PDT 24 42465950 ps
T1147 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.2797616686 Aug 09 06:39:59 PM PDT 24 Aug 09 06:40:00 PM PDT 24 27232917 ps
T1148 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1960589800 Aug 09 06:40:29 PM PDT 24 Aug 09 06:40:30 PM PDT 24 24935047 ps
T1149 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.555906629 Aug 09 06:40:13 PM PDT 24 Aug 09 06:40:17 PM PDT 24 114363457 ps
T167 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.2276851579 Aug 09 06:40:13 PM PDT 24 Aug 09 06:40:26 PM PDT 24 200463213 ps
T1150 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.2614604591 Aug 09 06:40:05 PM PDT 24 Aug 09 06:40:13 PM PDT 24 447592215 ps
T1151 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.2524139642 Aug 09 06:40:06 PM PDT 24 Aug 09 06:40:09 PM PDT 24 41697107 ps

Test location /workspace/coverage/default/48.spi_device_stress_all.3015366465
Short name T3
Test name
Test status
Simulation time 15781590393 ps
CPU time 202.99 seconds
Started Aug 09 06:58:20 PM PDT 24
Finished Aug 09 07:01:43 PM PDT 24
Peak memory 273704 kb
Host smart-f7126ed2-459c-4a4b-95b8-907264c5d6db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015366465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.3015366465
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.1559609365
Short name T8
Test name
Test status
Simulation time 25971017368 ps
CPU time 35.9 seconds
Started Aug 09 06:58:11 PM PDT 24
Finished Aug 09 06:58:47 PM PDT 24
Peak memory 217024 kb
Host smart-feacd916-da57-4c93-814e-90c8129d3e76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559609365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.1559609365
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.224948259
Short name T19
Test name
Test status
Simulation time 9495564673 ps
CPU time 148.52 seconds
Started Aug 09 06:57:07 PM PDT 24
Finished Aug 09 06:59:35 PM PDT 24
Peak memory 249992 kb
Host smart-2875b790-2772-4a80-9dce-53a5dc254f28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224948259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stres
s_all.224948259
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.2388907948
Short name T107
Test name
Test status
Simulation time 309731559 ps
CPU time 3.79 seconds
Started Aug 09 06:40:19 PM PDT 24
Finished Aug 09 06:40:23 PM PDT 24
Peak memory 217356 kb
Host smart-d1631acb-706f-42da-9415-005fc69d128e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388907948 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.2388907948
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.3965265702
Short name T188
Test name
Test status
Simulation time 328298602440 ps
CPU time 888.49 seconds
Started Aug 09 06:52:40 PM PDT 24
Finished Aug 09 07:07:29 PM PDT 24
Peak memory 305636 kb
Host smart-7c8624a7-b867-44b8-a0c4-df9971f35530
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965265702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.3965265702
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.2360022580
Short name T40
Test name
Test status
Simulation time 21715967229 ps
CPU time 112.36 seconds
Started Aug 09 06:55:18 PM PDT 24
Finished Aug 09 06:57:10 PM PDT 24
Peak memory 262716 kb
Host smart-bc39ef8e-d6e5-4afd-88b8-31eaf154adb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360022580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.2360022580
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.2723448804
Short name T63
Test name
Test status
Simulation time 38336143 ps
CPU time 0.74 seconds
Started Aug 09 06:51:38 PM PDT 24
Finished Aug 09 06:51:38 PM PDT 24
Peak memory 216624 kb
Host smart-83893d17-071c-4ecc-b9e0-d76baf045938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723448804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.2723448804
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.2504150365
Short name T43
Test name
Test status
Simulation time 195118792735 ps
CPU time 468.28 seconds
Started Aug 09 06:56:13 PM PDT 24
Finished Aug 09 07:04:01 PM PDT 24
Peak memory 267592 kb
Host smart-ebf777dd-abcd-4613-b14d-3b9ecb1d03df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504150365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.2504150365
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.1611512
Short name T17
Test name
Test status
Simulation time 89550455 ps
CPU time 1.17 seconds
Started Aug 09 06:52:37 PM PDT 24
Finished Aug 09 06:52:39 PM PDT 24
Peak memory 235508 kb
Host smart-1b32e800-8f03-44c3-9959-dded82fabbe4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.1611512
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.717840450
Short name T35
Test name
Test status
Simulation time 15235135037 ps
CPU time 164.62 seconds
Started Aug 09 06:57:39 PM PDT 24
Finished Aug 09 07:00:24 PM PDT 24
Peak memory 274484 kb
Host smart-30e58f51-081d-4f69-9489-25f7b23eae6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717840450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idle
.717840450
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.1622704002
Short name T136
Test name
Test status
Simulation time 1470746221 ps
CPU time 26.82 seconds
Started Aug 09 06:57:47 PM PDT 24
Finished Aug 09 06:58:14 PM PDT 24
Peak memory 251992 kb
Host smart-a56e7146-7c69-4b0f-8060-641255455847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622704002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.1622704002
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.3572118163
Short name T36
Test name
Test status
Simulation time 142650378363 ps
CPU time 352.29 seconds
Started Aug 09 06:57:41 PM PDT 24
Finished Aug 09 07:03:34 PM PDT 24
Peak memory 257700 kb
Host smart-ad81afd5-1ee2-4a48-bc71-43286c2f962c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572118163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.3572118163
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.2360039755
Short name T70
Test name
Test status
Simulation time 16307743027 ps
CPU time 125.69 seconds
Started Aug 09 06:55:21 PM PDT 24
Finished Aug 09 06:57:26 PM PDT 24
Peak memory 255824 kb
Host smart-0f05270e-a839-4efa-8948-68584aa0dbdf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360039755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.2360039755
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.1787931180
Short name T18
Test name
Test status
Simulation time 137562082020 ps
CPU time 175.88 seconds
Started Aug 09 06:54:31 PM PDT 24
Finished Aug 09 06:57:27 PM PDT 24
Peak memory 257756 kb
Host smart-60490143-72b6-4957-ae3a-da94ab413991
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787931180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.1787931180
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.3326962304
Short name T100
Test name
Test status
Simulation time 549294920 ps
CPU time 15.32 seconds
Started Aug 09 06:39:58 PM PDT 24
Finished Aug 09 06:40:14 PM PDT 24
Peak memory 215500 kb
Host smart-e81176f2-7f9c-49ce-a1ae-6f8ddca9bed3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326962304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.3326962304
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.1944755442
Short name T186
Test name
Test status
Simulation time 448476832255 ps
CPU time 710.66 seconds
Started Aug 09 06:58:00 PM PDT 24
Finished Aug 09 07:09:50 PM PDT 24
Peak memory 258144 kb
Host smart-856a69d0-df1c-4561-8e87-c0ffd8aebe83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944755442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.1944755442
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.4061473416
Short name T90
Test name
Test status
Simulation time 321508744 ps
CPU time 4.75 seconds
Started Aug 09 06:40:19 PM PDT 24
Finished Aug 09 06:40:24 PM PDT 24
Peak memory 215768 kb
Host smart-ebadc556-db51-4299-bdff-4aeddecbebca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061473416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
4061473416
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1242922795
Short name T112
Test name
Test status
Simulation time 1063230027 ps
CPU time 22 seconds
Started Aug 09 06:39:54 PM PDT 24
Finished Aug 09 06:40:16 PM PDT 24
Peak memory 215628 kb
Host smart-b29db178-b6bb-4a10-8024-783c79f7c356
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242922795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.1242922795
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.3635903441
Short name T214
Test name
Test status
Simulation time 46776804125 ps
CPU time 305.38 seconds
Started Aug 09 06:57:55 PM PDT 24
Finished Aug 09 07:03:00 PM PDT 24
Peak memory 249864 kb
Host smart-49dbf8b6-05c3-4b08-97eb-5307279ec4b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635903441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmd
s.3635903441
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.3051525751
Short name T567
Test name
Test status
Simulation time 17078989 ps
CPU time 1.03 seconds
Started Aug 09 06:51:36 PM PDT 24
Finished Aug 09 06:51:37 PM PDT 24
Peak memory 217396 kb
Host smart-ce4a8164-fadd-4638-9531-23f0c970e57d
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051525751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.spi_device_mem_parity.3051525751
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.2849522796
Short name T33
Test name
Test status
Simulation time 136314081343 ps
CPU time 249.46 seconds
Started Aug 09 06:56:55 PM PDT 24
Finished Aug 09 07:01:05 PM PDT 24
Peak memory 249864 kb
Host smart-3b260ea8-b144-44fa-a435-269a6b2bf4ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849522796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.2849522796
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.4257918142
Short name T229
Test name
Test status
Simulation time 146645781460 ps
CPU time 303.41 seconds
Started Aug 09 06:58:28 PM PDT 24
Finished Aug 09 07:03:32 PM PDT 24
Peak memory 266340 kb
Host smart-77b0333e-1b35-4d76-acb5-cfef32941725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257918142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.4257918142
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.2639307057
Short name T23
Test name
Test status
Simulation time 15762383654 ps
CPU time 64.32 seconds
Started Aug 09 06:56:06 PM PDT 24
Finished Aug 09 06:57:11 PM PDT 24
Peak memory 265880 kb
Host smart-df47022c-9f48-4b47-b060-073419971328
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639307057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.2639307057
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.567633677
Short name T203
Test name
Test status
Simulation time 12981811110 ps
CPU time 91.85 seconds
Started Aug 09 06:54:43 PM PDT 24
Finished Aug 09 06:56:15 PM PDT 24
Peak memory 255356 kb
Host smart-6b7cc966-4748-44c4-8eed-b60642faaeca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567633677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmds
.567633677
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.2269716472
Short name T171
Test name
Test status
Simulation time 11151833139 ps
CPU time 100.91 seconds
Started Aug 09 06:55:11 PM PDT 24
Finished Aug 09 06:56:52 PM PDT 24
Peak memory 252860 kb
Host smart-8e232470-985e-492a-a33a-a02d9ebf77e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269716472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.2269716472
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.1499355372
Short name T285
Test name
Test status
Simulation time 1747674690 ps
CPU time 36.41 seconds
Started Aug 09 06:56:47 PM PDT 24
Finished Aug 09 06:57:24 PM PDT 24
Peak memory 261552 kb
Host smart-6efa581d-9559-49a6-b556-ca950651f2b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499355372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.1499355372
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.3261790297
Short name T338
Test name
Test status
Simulation time 55586523 ps
CPU time 0.71 seconds
Started Aug 09 06:54:10 PM PDT 24
Finished Aug 09 06:54:11 PM PDT 24
Peak memory 206100 kb
Host smart-67f3f866-de72-439a-bf6f-27936266f7fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261790297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
3261790297
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.3447760188
Short name T199
Test name
Test status
Simulation time 61451873490 ps
CPU time 419.39 seconds
Started Aug 09 06:54:31 PM PDT 24
Finished Aug 09 07:01:31 PM PDT 24
Peak memory 252536 kb
Host smart-6583654a-cc31-4e47-9641-df133e667bfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447760188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.3447760188
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.1142132130
Short name T306
Test name
Test status
Simulation time 209608551469 ps
CPU time 391.03 seconds
Started Aug 09 06:56:05 PM PDT 24
Finished Aug 09 07:02:36 PM PDT 24
Peak memory 267472 kb
Host smart-4db5e593-cda1-44a6-9422-fd102bf6fa2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142132130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmd
s.1142132130
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.918051202
Short name T168
Test name
Test status
Simulation time 3200119107 ps
CPU time 22.6 seconds
Started Aug 09 06:40:04 PM PDT 24
Finished Aug 09 06:40:27 PM PDT 24
Peak memory 216072 kb
Host smart-fd593c5d-0cf9-4934-8788-9a9eaf2228a2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918051202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_
tl_intg_err.918051202
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.1373825035
Short name T480
Test name
Test status
Simulation time 15175641014 ps
CPU time 155.13 seconds
Started Aug 09 06:54:15 PM PDT 24
Finished Aug 09 06:56:50 PM PDT 24
Peak memory 274148 kb
Host smart-9188a36a-516b-4820-9199-a87fd6ac5304
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373825035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.1373825035
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.3475045998
Short name T750
Test name
Test status
Simulation time 2351950885 ps
CPU time 24.36 seconds
Started Aug 09 06:54:19 PM PDT 24
Finished Aug 09 06:54:44 PM PDT 24
Peak memory 225292 kb
Host smart-31205a9b-66b3-4b91-8a58-46672d284c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475045998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.3475045998
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.3178684579
Short name T292
Test name
Test status
Simulation time 103388397734 ps
CPU time 229.62 seconds
Started Aug 09 06:54:21 PM PDT 24
Finished Aug 09 06:58:11 PM PDT 24
Peak memory 256116 kb
Host smart-c43914aa-4cf6-4f14-a906-22f7a6ba040e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178684579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.3178684579
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.2086415486
Short name T286
Test name
Test status
Simulation time 25311495233 ps
CPU time 84.24 seconds
Started Aug 09 06:56:17 PM PDT 24
Finished Aug 09 06:57:42 PM PDT 24
Peak memory 249924 kb
Host smart-07ba6971-8f51-46c8-bb2c-3fd0f4f3a4fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086415486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.2086415486
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.2204399257
Short name T49
Test name
Test status
Simulation time 5403907657 ps
CPU time 39.85 seconds
Started Aug 09 06:57:24 PM PDT 24
Finished Aug 09 06:58:04 PM PDT 24
Peak memory 240040 kb
Host smart-abfee2c1-7617-48a9-b963-308a82c21a26
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204399257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.2204399257
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.2421695467
Short name T178
Test name
Test status
Simulation time 19921596979 ps
CPU time 175.2 seconds
Started Aug 09 06:52:40 PM PDT 24
Finished Aug 09 06:55:35 PM PDT 24
Peak memory 255176 kb
Host smart-6efb30d2-a29f-4ab9-9c6c-59d1d5bcf6f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421695467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds
.2421695467
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.976879770
Short name T303
Test name
Test status
Simulation time 117904403548 ps
CPU time 509.36 seconds
Started Aug 09 06:54:53 PM PDT 24
Finished Aug 09 07:03:22 PM PDT 24
Peak memory 258088 kb
Host smart-2c5305f4-6dba-4cb5-9c0c-530eac5d0de9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976879770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.976879770
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.876155950
Short name T260
Test name
Test status
Simulation time 57381193625 ps
CPU time 185.63 seconds
Started Aug 09 06:54:50 PM PDT 24
Finished Aug 09 06:57:56 PM PDT 24
Peak memory 252576 kb
Host smart-f0620094-b8d3-42d8-88a6-817c6f045861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876155950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmds
.876155950
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.1783777330
Short name T241
Test name
Test status
Simulation time 315181247179 ps
CPU time 342.45 seconds
Started Aug 09 06:56:56 PM PDT 24
Finished Aug 09 07:02:39 PM PDT 24
Peak memory 253740 kb
Host smart-47e584bc-cdb9-4670-b462-303bc6266a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783777330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.1783777330
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.1361543869
Short name T1141
Test name
Test status
Simulation time 132604953 ps
CPU time 4.49 seconds
Started Aug 09 06:40:05 PM PDT 24
Finished Aug 09 06:40:10 PM PDT 24
Peak memory 215696 kb
Host smart-0780dcd0-468c-40f5-af5e-ed92eb3ed428
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361543869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
1361543869
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.2925400232
Short name T30
Test name
Test status
Simulation time 115884917226 ps
CPU time 329.43 seconds
Started Aug 09 06:57:44 PM PDT 24
Finished Aug 09 07:03:13 PM PDT 24
Peak memory 258136 kb
Host smart-0375afe1-dea5-474b-98f9-680a61d7fb9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925400232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.2925400232
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.3272377010
Short name T166
Test name
Test status
Simulation time 2421309203 ps
CPU time 13.48 seconds
Started Aug 09 06:39:53 PM PDT 24
Finished Aug 09 06:40:07 PM PDT 24
Peak memory 215784 kb
Host smart-bcde0dc5-3e48-46e1-b4b8-e54eb04b4124
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272377010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.3272377010
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.4211353615
Short name T1030
Test name
Test status
Simulation time 18244572988 ps
CPU time 84.87 seconds
Started Aug 09 06:52:36 PM PDT 24
Finished Aug 09 06:54:01 PM PDT 24
Peak memory 257760 kb
Host smart-b17458b2-be3e-4651-8269-2be3b18f62bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211353615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.4211353615
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.3489752494
Short name T194
Test name
Test status
Simulation time 14120948208 ps
CPU time 80.52 seconds
Started Aug 09 06:52:40 PM PDT 24
Finished Aug 09 06:54:00 PM PDT 24
Peak memory 256592 kb
Host smart-febffd3b-409a-48ff-9463-1cd3c8105b52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489752494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.3489752494
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.2867874366
Short name T320
Test name
Test status
Simulation time 50418643284 ps
CPU time 129.6 seconds
Started Aug 09 06:54:44 PM PDT 24
Finished Aug 09 06:56:54 PM PDT 24
Peak memory 258120 kb
Host smart-ec7ae6e3-8eeb-4489-a056-1127b9a5ddcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867874366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.2867874366
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.3840215474
Short name T593
Test name
Test status
Simulation time 15923725587 ps
CPU time 60.66 seconds
Started Aug 09 06:54:33 PM PDT 24
Finished Aug 09 06:55:34 PM PDT 24
Peak memory 237856 kb
Host smart-b6e2d61a-52ed-4463-804e-577af7ebe0b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840215474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.3840215474
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.3172344605
Short name T333
Test name
Test status
Simulation time 18662329824 ps
CPU time 180.5 seconds
Started Aug 09 06:56:19 PM PDT 24
Finished Aug 09 06:59:20 PM PDT 24
Peak memory 252092 kb
Host smart-944ef861-a4ff-4c08-be00-9772e0aba302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172344605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.3172344605
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.3559968437
Short name T254
Test name
Test status
Simulation time 4920757517 ps
CPU time 107.73 seconds
Started Aug 09 06:56:23 PM PDT 24
Finished Aug 09 06:58:11 PM PDT 24
Peak memory 269596 kb
Host smart-6b902ca3-890b-45f4-bdaa-ebe385d178e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559968437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmd
s.3559968437
Directory /workspace/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.2112302764
Short name T82
Test name
Test status
Simulation time 2101925308 ps
CPU time 46.13 seconds
Started Aug 09 06:51:41 PM PDT 24
Finished Aug 09 06:52:27 PM PDT 24
Peak memory 252356 kb
Host smart-6fe02758-443d-4b0c-abe7-df13de08c2bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112302764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds
.2112302764
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.4250904289
Short name T394
Test name
Test status
Simulation time 21438997467 ps
CPU time 12.55 seconds
Started Aug 09 06:54:10 PM PDT 24
Finished Aug 09 06:54:23 PM PDT 24
Peak memory 225308 kb
Host smart-4b14aa69-3748-43dc-8273-de29483def54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250904289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.4250904289
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2146662036
Short name T75
Test name
Test status
Simulation time 81744769 ps
CPU time 1.34 seconds
Started Aug 09 06:39:54 PM PDT 24
Finished Aug 09 06:39:55 PM PDT 24
Peak memory 215464 kb
Host smart-286f8225-b5af-425b-bc7e-c01064ac50e6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146662036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.2146662036
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.3589998697
Short name T1111
Test name
Test status
Simulation time 127309485 ps
CPU time 4.4 seconds
Started Aug 09 06:39:56 PM PDT 24
Finished Aug 09 06:40:01 PM PDT 24
Peak memory 215684 kb
Host smart-6b26144b-f6e3-41b6-9748-baccc36317d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589998697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.3
589998697
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.2255348611
Short name T113
Test name
Test status
Simulation time 355638319 ps
CPU time 23.66 seconds
Started Aug 09 06:39:54 PM PDT 24
Finished Aug 09 06:40:18 PM PDT 24
Peak memory 207224 kb
Host smart-9b491a93-1656-4b61-ae11-4284d701cb10
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255348611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.2255348611
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.92314535
Short name T1068
Test name
Test status
Simulation time 95175303 ps
CPU time 1.72 seconds
Started Aug 09 06:39:55 PM PDT 24
Finished Aug 09 06:39:57 PM PDT 24
Peak memory 215648 kb
Host smart-e310289e-0f36-41cf-a7f1-864b7dd3f4da
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92314535 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.92314535
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.4076044786
Short name T122
Test name
Test status
Simulation time 169958749 ps
CPU time 2.67 seconds
Started Aug 09 06:39:55 PM PDT 24
Finished Aug 09 06:39:58 PM PDT 24
Peak memory 215524 kb
Host smart-24535d05-966f-4267-b387-5d9408a2b84f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076044786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.4
076044786
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2119489518
Short name T1120
Test name
Test status
Simulation time 14056058 ps
CPU time 0.77 seconds
Started Aug 09 06:39:54 PM PDT 24
Finished Aug 09 06:39:55 PM PDT 24
Peak memory 204368 kb
Host smart-642dda52-c7ba-4868-b6e3-8d154b54573d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119489518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.2
119489518
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.1648994232
Short name T1138
Test name
Test status
Simulation time 52471709 ps
CPU time 1.76 seconds
Started Aug 09 06:39:53 PM PDT 24
Finished Aug 09 06:39:55 PM PDT 24
Peak memory 215572 kb
Host smart-5d218533-c31d-4449-85c4-eb011f110861
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648994232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.1648994232
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.402428430
Short name T1042
Test name
Test status
Simulation time 30146079 ps
CPU time 0.67 seconds
Started Aug 09 06:39:54 PM PDT 24
Finished Aug 09 06:39:54 PM PDT 24
Peak memory 203908 kb
Host smart-8d343901-20e3-4aed-bf8f-3ce12199c3f0
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402428430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_mem
_walk.402428430
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.103686001
Short name T1099
Test name
Test status
Simulation time 475855610 ps
CPU time 2.88 seconds
Started Aug 09 06:39:55 PM PDT 24
Finished Aug 09 06:39:58 PM PDT 24
Peak memory 215924 kb
Host smart-68c61d29-6242-4d80-882c-b2eeacf8db23
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103686001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sp
i_device_same_csr_outstanding.103686001
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.4147991200
Short name T1131
Test name
Test status
Simulation time 1491342559 ps
CPU time 3.97 seconds
Started Aug 09 06:39:54 PM PDT 24
Finished Aug 09 06:39:58 PM PDT 24
Peak memory 215784 kb
Host smart-961b284e-1791-4c20-a140-6879290a49a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147991200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.4
147991200
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.2737138742
Short name T1092
Test name
Test status
Simulation time 365640477 ps
CPU time 8.73 seconds
Started Aug 09 06:39:52 PM PDT 24
Finished Aug 09 06:40:01 PM PDT 24
Peak memory 215588 kb
Host smart-efb78be9-69ca-4dc3-a4cb-d189c3d9f90d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737138742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.2737138742
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.4098184016
Short name T1108
Test name
Test status
Simulation time 216105874 ps
CPU time 14.35 seconds
Started Aug 09 06:39:57 PM PDT 24
Finished Aug 09 06:40:11 PM PDT 24
Peak memory 207160 kb
Host smart-8f00b349-2f84-4de5-bc5f-ff0891ce66bf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098184016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.4098184016
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.856061837
Short name T1113
Test name
Test status
Simulation time 527271824 ps
CPU time 32.74 seconds
Started Aug 09 06:39:56 PM PDT 24
Finished Aug 09 06:40:28 PM PDT 24
Peak memory 207296 kb
Host smart-73dc1d4e-7cc1-4185-b057-e606692c5105
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856061837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_bit_bash.856061837
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3863887820
Short name T74
Test name
Test status
Simulation time 100040773 ps
CPU time 1.42 seconds
Started Aug 09 06:39:57 PM PDT 24
Finished Aug 09 06:39:58 PM PDT 24
Peak memory 207224 kb
Host smart-2b17dd62-6b9d-4610-9848-08e6ef7a8d77
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863887820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.3863887820
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.4112939090
Short name T145
Test name
Test status
Simulation time 371147858 ps
CPU time 2.58 seconds
Started Aug 09 06:39:57 PM PDT 24
Finished Aug 09 06:40:00 PM PDT 24
Peak memory 217960 kb
Host smart-16f0d091-2119-4190-a724-a4c77704743b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112939090 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.4112939090
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.2864814314
Short name T1090
Test name
Test status
Simulation time 26802312 ps
CPU time 1.62 seconds
Started Aug 09 06:39:57 PM PDT 24
Finished Aug 09 06:39:59 PM PDT 24
Peak memory 215516 kb
Host smart-c01939e3-d40c-4798-8bbf-e177f8a1b29f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864814314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.2
864814314
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.3321047068
Short name T1049
Test name
Test status
Simulation time 15245564 ps
CPU time 0.71 seconds
Started Aug 09 06:39:53 PM PDT 24
Finished Aug 09 06:39:54 PM PDT 24
Peak memory 204012 kb
Host smart-70f71890-3df5-4dc8-b2fa-4c9f967a81d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321047068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.3
321047068
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.3202467078
Short name T1145
Test name
Test status
Simulation time 40004811 ps
CPU time 1.28 seconds
Started Aug 09 06:39:56 PM PDT 24
Finished Aug 09 06:39:57 PM PDT 24
Peak memory 215380 kb
Host smart-110c7c5d-9c44-4e38-bea3-34201b512acf
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202467078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.3202467078
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.3815990864
Short name T1044
Test name
Test status
Simulation time 133521544 ps
CPU time 0.64 seconds
Started Aug 09 06:39:56 PM PDT 24
Finished Aug 09 06:39:56 PM PDT 24
Peak memory 203856 kb
Host smart-3e0dec9e-e499-42f1-951b-4b052f0b040e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815990864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.3815990864
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3079612590
Short name T1137
Test name
Test status
Simulation time 42792805 ps
CPU time 2.73 seconds
Started Aug 09 06:39:55 PM PDT 24
Finished Aug 09 06:39:58 PM PDT 24
Peak memory 215476 kb
Host smart-462148a7-de62-4859-8df4-4d0de7f20a06
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079612590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.3079612590
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.267842029
Short name T1075
Test name
Test status
Simulation time 53178188 ps
CPU time 3.39 seconds
Started Aug 09 06:40:07 PM PDT 24
Finished Aug 09 06:40:11 PM PDT 24
Peak memory 217292 kb
Host smart-dd0ac530-9cbc-4285-9c4c-9079b90c9fee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267842029 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.267842029
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.4273852544
Short name T114
Test name
Test status
Simulation time 388233477 ps
CPU time 2.23 seconds
Started Aug 09 06:40:04 PM PDT 24
Finished Aug 09 06:40:06 PM PDT 24
Peak memory 215584 kb
Host smart-f73e5cc5-efa7-472f-8775-380b5cced816
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273852544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
4273852544
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.2133579509
Short name T1136
Test name
Test status
Simulation time 53680561 ps
CPU time 0.74 seconds
Started Aug 09 06:40:06 PM PDT 24
Finished Aug 09 06:40:07 PM PDT 24
Peak memory 203952 kb
Host smart-e96a38ca-1ad3-42b4-92c5-be0737b0eefb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133579509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
2133579509
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.2876598236
Short name T143
Test name
Test status
Simulation time 302402120 ps
CPU time 1.88 seconds
Started Aug 09 06:40:05 PM PDT 24
Finished Aug 09 06:40:07 PM PDT 24
Peak memory 207324 kb
Host smart-c9fe0a6d-8493-44a5-b7b2-ebe208ff38e6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876598236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.2876598236
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.1824021583
Short name T163
Test name
Test status
Simulation time 3377127320 ps
CPU time 7.35 seconds
Started Aug 09 06:40:05 PM PDT 24
Finished Aug 09 06:40:13 PM PDT 24
Peak memory 216316 kb
Host smart-68e165c7-10f8-4928-914e-5095b6480514
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824021583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.1824021583
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.394272734
Short name T87
Test name
Test status
Simulation time 98270917 ps
CPU time 1.74 seconds
Started Aug 09 06:40:09 PM PDT 24
Finished Aug 09 06:40:11 PM PDT 24
Peak memory 215556 kb
Host smart-12583c4d-9838-4a25-ab8d-902629a74daf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394272734 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.394272734
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.738055052
Short name T1098
Test name
Test status
Simulation time 146189802 ps
CPU time 1.37 seconds
Started Aug 09 06:40:04 PM PDT 24
Finished Aug 09 06:40:05 PM PDT 24
Peak memory 207404 kb
Host smart-1638659d-1aa0-4bdb-8a0d-d8c76de4d5e5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738055052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.738055052
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.4232003479
Short name T1104
Test name
Test status
Simulation time 12922344 ps
CPU time 0.73 seconds
Started Aug 09 06:40:09 PM PDT 24
Finished Aug 09 06:40:10 PM PDT 24
Peak memory 204344 kb
Host smart-ad608bdb-bc1b-453f-ac3e-d03d6f9f36d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232003479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
4232003479
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2777048813
Short name T1056
Test name
Test status
Simulation time 897779501 ps
CPU time 3.87 seconds
Started Aug 09 06:40:06 PM PDT 24
Finished Aug 09 06:40:10 PM PDT 24
Peak memory 215612 kb
Host smart-614d3331-94e8-445c-8584-5b1f4eec24eb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777048813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.2777048813
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3318446170
Short name T103
Test name
Test status
Simulation time 382650409 ps
CPU time 4.49 seconds
Started Aug 09 06:40:07 PM PDT 24
Finished Aug 09 06:40:12 PM PDT 24
Peak memory 215760 kb
Host smart-ceea157a-76dd-4e69-b02b-5bc89293d8ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318446170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
3318446170
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.2614604591
Short name T1150
Test name
Test status
Simulation time 447592215 ps
CPU time 7.53 seconds
Started Aug 09 06:40:05 PM PDT 24
Finished Aug 09 06:40:13 PM PDT 24
Peak memory 215568 kb
Host smart-0d4fcdd5-d4c0-45e9-b3b9-9f3f7e02083c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614604591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.2614604591
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.1625706722
Short name T1144
Test name
Test status
Simulation time 205270260 ps
CPU time 1.92 seconds
Started Aug 09 06:40:14 PM PDT 24
Finished Aug 09 06:40:16 PM PDT 24
Peak memory 216588 kb
Host smart-0e12245e-f4c8-4a66-9da9-de2f762a75e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625706722 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.1625706722
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.1284983364
Short name T110
Test name
Test status
Simulation time 71250423 ps
CPU time 1.3 seconds
Started Aug 09 06:40:16 PM PDT 24
Finished Aug 09 06:40:17 PM PDT 24
Peak memory 215460 kb
Host smart-71248b34-10ee-48fa-8dd5-4d2a048e7d5b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284983364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
1284983364
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.737467859
Short name T1037
Test name
Test status
Simulation time 13635847 ps
CPU time 0.74 seconds
Started Aug 09 06:40:12 PM PDT 24
Finished Aug 09 06:40:13 PM PDT 24
Peak memory 204320 kb
Host smart-66634bfd-9942-47db-96a5-1ac8ce4dca48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737467859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.737467859
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3049921460
Short name T1142
Test name
Test status
Simulation time 335905132 ps
CPU time 2.11 seconds
Started Aug 09 06:40:13 PM PDT 24
Finished Aug 09 06:40:15 PM PDT 24
Peak memory 207288 kb
Host smart-62b20984-7c33-4803-8e7d-02d42e5ae340
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049921460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.3049921460
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3220392635
Short name T101
Test name
Test status
Simulation time 314836124 ps
CPU time 4.07 seconds
Started Aug 09 06:40:05 PM PDT 24
Finished Aug 09 06:40:09 PM PDT 24
Peak memory 215796 kb
Host smart-6493081a-c09f-48f2-82cb-5fb7a865b0c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220392635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
3220392635
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.2002999904
Short name T177
Test name
Test status
Simulation time 1423650559 ps
CPU time 11.85 seconds
Started Aug 09 06:40:17 PM PDT 24
Finished Aug 09 06:40:29 PM PDT 24
Peak memory 215576 kb
Host smart-728071e2-f284-4ec3-9105-77506379a7f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002999904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.2002999904
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.1733601173
Short name T1093
Test name
Test status
Simulation time 115024848 ps
CPU time 1.79 seconds
Started Aug 09 06:40:17 PM PDT 24
Finished Aug 09 06:40:19 PM PDT 24
Peak memory 216644 kb
Host smart-ce9d9c14-3bc2-45a3-a888-d6434ea7af9c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733601173 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.1733601173
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1921804592
Short name T1060
Test name
Test status
Simulation time 29893729 ps
CPU time 1.26 seconds
Started Aug 09 06:40:12 PM PDT 24
Finished Aug 09 06:40:13 PM PDT 24
Peak memory 215624 kb
Host smart-8af869c9-b3a3-48e4-8af6-7c55df829466
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921804592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
1921804592
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.1611007226
Short name T1072
Test name
Test status
Simulation time 36793164 ps
CPU time 0.73 seconds
Started Aug 09 06:40:15 PM PDT 24
Finished Aug 09 06:40:16 PM PDT 24
Peak memory 204016 kb
Host smart-ca44ed8b-e126-4924-beab-7e820be9f8ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611007226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
1611007226
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.555906629
Short name T1149
Test name
Test status
Simulation time 114363457 ps
CPU time 3.87 seconds
Started Aug 09 06:40:13 PM PDT 24
Finished Aug 09 06:40:17 PM PDT 24
Peak memory 215540 kb
Host smart-cc62177a-f03d-42b7-b6f3-d98039e63de7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555906629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.s
pi_device_same_csr_outstanding.555906629
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.234310009
Short name T88
Test name
Test status
Simulation time 71484542 ps
CPU time 2.25 seconds
Started Aug 09 06:40:11 PM PDT 24
Finished Aug 09 06:40:14 PM PDT 24
Peak memory 216740 kb
Host smart-b51784fc-a0ec-4315-a1e3-df22e99f4c08
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234310009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.234310009
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.2068010604
Short name T1052
Test name
Test status
Simulation time 101660635 ps
CPU time 6.46 seconds
Started Aug 09 06:40:13 PM PDT 24
Finished Aug 09 06:40:19 PM PDT 24
Peak memory 215800 kb
Host smart-d45c4956-1d6b-4517-add8-c98702a4cb75
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068010604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.2068010604
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3760695855
Short name T1107
Test name
Test status
Simulation time 98388098 ps
CPU time 1.7 seconds
Started Aug 09 06:40:17 PM PDT 24
Finished Aug 09 06:40:19 PM PDT 24
Peak memory 215644 kb
Host smart-b011666f-cd48-48b7-8761-f07ca6df4808
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760695855 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.3760695855
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.2179178359
Short name T117
Test name
Test status
Simulation time 161806528 ps
CPU time 2.36 seconds
Started Aug 09 06:40:14 PM PDT 24
Finished Aug 09 06:40:17 PM PDT 24
Peak memory 215512 kb
Host smart-6227aa03-0d04-42f7-8927-b167d939c5b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179178359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
2179178359
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.1155465066
Short name T1126
Test name
Test status
Simulation time 14641818 ps
CPU time 0.74 seconds
Started Aug 09 06:40:14 PM PDT 24
Finished Aug 09 06:40:14 PM PDT 24
Peak memory 204024 kb
Host smart-45a20f28-02a2-425c-af1b-f4e8f0ee5d4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155465066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
1155465066
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3499577694
Short name T142
Test name
Test status
Simulation time 81061638 ps
CPU time 2.1 seconds
Started Aug 09 06:40:15 PM PDT 24
Finished Aug 09 06:40:17 PM PDT 24
Peak memory 215520 kb
Host smart-8dae8a23-6967-4231-85f4-aa6f7cddca02
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499577694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.3499577694
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.2230999323
Short name T98
Test name
Test status
Simulation time 533540542 ps
CPU time 5.97 seconds
Started Aug 09 06:40:14 PM PDT 24
Finished Aug 09 06:40:21 PM PDT 24
Peak memory 216832 kb
Host smart-4e9b1c3e-2d52-4668-b8de-69b7482a53bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230999323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
2230999323
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.1364868262
Short name T91
Test name
Test status
Simulation time 1131820484 ps
CPU time 18.65 seconds
Started Aug 09 06:40:12 PM PDT 24
Finished Aug 09 06:40:31 PM PDT 24
Peak memory 215772 kb
Host smart-b9b66277-dcf5-46c9-9c44-dbd071e48cf1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364868262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.1364868262
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.3151540250
Short name T106
Test name
Test status
Simulation time 40685285 ps
CPU time 2.93 seconds
Started Aug 09 06:40:14 PM PDT 24
Finished Aug 09 06:40:18 PM PDT 24
Peak memory 218632 kb
Host smart-4593f411-7298-4517-b6fc-05b4e2a1fed5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151540250 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.3151540250
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.2153708484
Short name T1079
Test name
Test status
Simulation time 78618975 ps
CPU time 2.36 seconds
Started Aug 09 06:40:13 PM PDT 24
Finished Aug 09 06:40:16 PM PDT 24
Peak memory 215548 kb
Host smart-0c6fe4f2-acd8-4acd-8b5a-fb0087b537ef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153708484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
2153708484
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.253084700
Short name T1059
Test name
Test status
Simulation time 158723073 ps
CPU time 0.8 seconds
Started Aug 09 06:40:14 PM PDT 24
Finished Aug 09 06:40:15 PM PDT 24
Peak memory 204292 kb
Host smart-d179a27c-ff77-4335-b088-a50020000c1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253084700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.253084700
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.1889821107
Short name T1047
Test name
Test status
Simulation time 207604034 ps
CPU time 1.71 seconds
Started Aug 09 06:40:13 PM PDT 24
Finished Aug 09 06:40:15 PM PDT 24
Peak memory 207380 kb
Host smart-419c7867-a2c7-48fb-b12a-dafe3da9b141
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889821107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.1889821107
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.1708720876
Short name T89
Test name
Test status
Simulation time 250574198 ps
CPU time 3.43 seconds
Started Aug 09 06:40:14 PM PDT 24
Finished Aug 09 06:40:18 PM PDT 24
Peak memory 215716 kb
Host smart-aec5f772-c69d-4b5e-a4c6-5e7a58717190
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708720876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
1708720876
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.2276851579
Short name T167
Test name
Test status
Simulation time 200463213 ps
CPU time 13.11 seconds
Started Aug 09 06:40:13 PM PDT 24
Finished Aug 09 06:40:26 PM PDT 24
Peak memory 215676 kb
Host smart-3e3b3dc1-7702-4b48-bdfa-fab7af6da341
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276851579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.2276851579
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.390247112
Short name T1112
Test name
Test status
Simulation time 210146153 ps
CPU time 3.91 seconds
Started Aug 09 06:40:26 PM PDT 24
Finished Aug 09 06:40:30 PM PDT 24
Peak memory 217832 kb
Host smart-139df021-54d3-4b6b-9ea0-c00af296ed7e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390247112 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.390247112
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.2134301803
Short name T1094
Test name
Test status
Simulation time 347382884 ps
CPU time 2.04 seconds
Started Aug 09 06:40:11 PM PDT 24
Finished Aug 09 06:40:13 PM PDT 24
Peak memory 215468 kb
Host smart-c24b8d80-3fe7-4af4-a2f1-a269caf5ef0f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134301803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
2134301803
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.194355059
Short name T1097
Test name
Test status
Simulation time 44892292 ps
CPU time 0.79 seconds
Started Aug 09 06:40:13 PM PDT 24
Finished Aug 09 06:40:13 PM PDT 24
Peak memory 204004 kb
Host smart-a2e6043a-58f0-4e61-8a4b-7ac097dcb6a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194355059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.194355059
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3587509762
Short name T1115
Test name
Test status
Simulation time 406881326 ps
CPU time 2.73 seconds
Started Aug 09 06:40:13 PM PDT 24
Finished Aug 09 06:40:16 PM PDT 24
Peak memory 215472 kb
Host smart-1fdf7650-9b0a-4eff-8e52-2b6812057e36
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587509762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.3587509762
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.1814736906
Short name T104
Test name
Test status
Simulation time 205601744 ps
CPU time 3.61 seconds
Started Aug 09 06:40:13 PM PDT 24
Finished Aug 09 06:40:17 PM PDT 24
Peak memory 216788 kb
Host smart-cd7a31e2-adac-44a3-b877-bdd3b70def34
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814736906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
1814736906
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.3100491080
Short name T92
Test name
Test status
Simulation time 583783103 ps
CPU time 8.02 seconds
Started Aug 09 06:40:14 PM PDT 24
Finished Aug 09 06:40:23 PM PDT 24
Peak memory 216360 kb
Host smart-688f6250-38b7-4876-a4b8-bee35d1eef5a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100491080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.3100491080
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.158644963
Short name T111
Test name
Test status
Simulation time 517787368 ps
CPU time 2.54 seconds
Started Aug 09 06:40:21 PM PDT 24
Finished Aug 09 06:40:24 PM PDT 24
Peak memory 215588 kb
Host smart-a6c54d2a-ab55-46e2-802d-4240f7fb9813
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158644963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.158644963
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.3523128674
Short name T1091
Test name
Test status
Simulation time 24379002 ps
CPU time 0.7 seconds
Started Aug 09 06:40:20 PM PDT 24
Finished Aug 09 06:40:20 PM PDT 24
Peak memory 203980 kb
Host smart-0336401f-b6a5-42f7-9098-ed888d4317fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523128674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
3523128674
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.3824467345
Short name T1055
Test name
Test status
Simulation time 63173778 ps
CPU time 1.99 seconds
Started Aug 09 06:40:21 PM PDT 24
Finished Aug 09 06:40:23 PM PDT 24
Peak memory 215552 kb
Host smart-6fff13bc-bb1b-44e0-b43f-f6ca8f800327
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824467345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.3824467345
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.1180763065
Short name T99
Test name
Test status
Simulation time 32531630 ps
CPU time 2.02 seconds
Started Aug 09 06:40:21 PM PDT 24
Finished Aug 09 06:40:23 PM PDT 24
Peak memory 215788 kb
Host smart-d916da3f-d136-4954-a6e7-cc825c47813e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180763065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
1180763065
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.2090508611
Short name T144
Test name
Test status
Simulation time 698770228 ps
CPU time 8.02 seconds
Started Aug 09 06:40:27 PM PDT 24
Finished Aug 09 06:40:35 PM PDT 24
Peak memory 215560 kb
Host smart-c52e52f0-8bf0-4728-b8f7-012bf14aa72d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090508611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.2090508611
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.1443397530
Short name T1050
Test name
Test status
Simulation time 48867515 ps
CPU time 1.68 seconds
Started Aug 09 06:40:20 PM PDT 24
Finished Aug 09 06:40:22 PM PDT 24
Peak memory 215492 kb
Host smart-a2ae968c-160e-4e2f-a779-0fc6e5176644
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443397530 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.1443397530
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.760834500
Short name T124
Test name
Test status
Simulation time 64205430 ps
CPU time 1.76 seconds
Started Aug 09 06:40:19 PM PDT 24
Finished Aug 09 06:40:21 PM PDT 24
Peak memory 220292 kb
Host smart-65b320f5-20d4-4b2e-9b13-1e60c1a30631
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760834500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.760834500
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.633384532
Short name T1106
Test name
Test status
Simulation time 15170507 ps
CPU time 0.81 seconds
Started Aug 09 06:40:19 PM PDT 24
Finished Aug 09 06:40:20 PM PDT 24
Peak memory 203940 kb
Host smart-75c700db-6783-4a05-9916-b494f0a3286a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633384532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.633384532
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2448834535
Short name T1096
Test name
Test status
Simulation time 146454474 ps
CPU time 3.76 seconds
Started Aug 09 06:40:18 PM PDT 24
Finished Aug 09 06:40:22 PM PDT 24
Peak memory 215480 kb
Host smart-b1c771f3-a3ca-44c4-98fa-ba0c562af15f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448834535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.2448834535
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.1536233082
Short name T1117
Test name
Test status
Simulation time 319582387 ps
CPU time 18.97 seconds
Started Aug 09 06:40:20 PM PDT 24
Finished Aug 09 06:40:39 PM PDT 24
Peak memory 215512 kb
Host smart-a33a75bc-1141-4433-b741-952077c822c2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536233082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.1536233082
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.507553037
Short name T1103
Test name
Test status
Simulation time 206638103 ps
CPU time 1.88 seconds
Started Aug 09 06:40:27 PM PDT 24
Finished Aug 09 06:40:29 PM PDT 24
Peak memory 216660 kb
Host smart-2bb6036b-b586-43c0-85f9-17e55217933e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507553037 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.507553037
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1357082154
Short name T118
Test name
Test status
Simulation time 36302883 ps
CPU time 2.47 seconds
Started Aug 09 06:40:27 PM PDT 24
Finished Aug 09 06:40:30 PM PDT 24
Peak memory 215584 kb
Host smart-9438b252-355e-433c-8def-1aaa7734dbbe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357082154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
1357082154
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.1787734273
Short name T1080
Test name
Test status
Simulation time 11918018 ps
CPU time 0.71 seconds
Started Aug 09 06:40:20 PM PDT 24
Finished Aug 09 06:40:21 PM PDT 24
Peak memory 204352 kb
Host smart-290de3e3-4643-4213-b84f-d346b5281334
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787734273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
1787734273
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.3651244789
Short name T135
Test name
Test status
Simulation time 114561209 ps
CPU time 3.56 seconds
Started Aug 09 06:40:27 PM PDT 24
Finished Aug 09 06:40:30 PM PDT 24
Peak memory 215520 kb
Host smart-5f1d8da5-91b4-422d-ad8c-34f1985ddb7d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651244789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.3651244789
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2000273983
Short name T1127
Test name
Test status
Simulation time 905992868 ps
CPU time 5.37 seconds
Started Aug 09 06:40:19 PM PDT 24
Finished Aug 09 06:40:24 PM PDT 24
Peak memory 215908 kb
Host smart-7f9517bb-13a2-4102-b53f-1a20b4e58a03
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000273983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
2000273983
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.2579806853
Short name T164
Test name
Test status
Simulation time 291901567 ps
CPU time 12.52 seconds
Started Aug 09 06:40:19 PM PDT 24
Finished Aug 09 06:40:31 PM PDT 24
Peak memory 215552 kb
Host smart-4963c6fb-e849-41b7-80e5-518969fdde99
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579806853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.2579806853
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.2538830032
Short name T123
Test name
Test status
Simulation time 270328523 ps
CPU time 7.67 seconds
Started Aug 09 06:39:57 PM PDT 24
Finished Aug 09 06:40:04 PM PDT 24
Peak memory 207300 kb
Host smart-85edde22-9d4b-4207-9ebf-22caedb96d72
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538830032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.2538830032
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1861444256
Short name T1119
Test name
Test status
Simulation time 353031081 ps
CPU time 21.63 seconds
Started Aug 09 06:39:57 PM PDT 24
Finished Aug 09 06:40:19 PM PDT 24
Peak memory 215560 kb
Host smart-73af0e0c-2c74-4f29-bbf8-7d4c2fa4129e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861444256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.1861444256
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2851716785
Short name T73
Test name
Test status
Simulation time 40849186 ps
CPU time 1.36 seconds
Started Aug 09 06:39:55 PM PDT 24
Finished Aug 09 06:39:56 PM PDT 24
Peak memory 207352 kb
Host smart-53f795b1-3c12-4685-a70c-a03ac0c9d514
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851716785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.2851716785
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2091374350
Short name T1089
Test name
Test status
Simulation time 52995063 ps
CPU time 2.95 seconds
Started Aug 09 06:40:08 PM PDT 24
Finished Aug 09 06:40:11 PM PDT 24
Peak memory 216940 kb
Host smart-7d2875b6-ed9e-491d-86fa-a50142f0ad64
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091374350 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.2091374350
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.2054098626
Short name T1146
Test name
Test status
Simulation time 42465950 ps
CPU time 2.01 seconds
Started Aug 09 06:39:57 PM PDT 24
Finished Aug 09 06:39:59 PM PDT 24
Peak memory 207380 kb
Host smart-f4004e11-b692-44fc-b94e-9ca0ac7d014f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054098626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.2
054098626
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.2214704352
Short name T1081
Test name
Test status
Simulation time 46351370 ps
CPU time 0.8 seconds
Started Aug 09 06:39:56 PM PDT 24
Finished Aug 09 06:39:57 PM PDT 24
Peak memory 204080 kb
Host smart-7c44ddb1-8293-4238-b29d-d07ef44c4474
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214704352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.2
214704352
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2967748873
Short name T1121
Test name
Test status
Simulation time 91891509 ps
CPU time 1.6 seconds
Started Aug 09 06:39:57 PM PDT 24
Finished Aug 09 06:39:59 PM PDT 24
Peak memory 215544 kb
Host smart-2376571e-4b81-4f0e-8907-e4035fd7f363
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967748873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.2967748873
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3929690137
Short name T1132
Test name
Test status
Simulation time 10199722 ps
CPU time 0.65 seconds
Started Aug 09 06:39:58 PM PDT 24
Finished Aug 09 06:39:59 PM PDT 24
Peak memory 203936 kb
Host smart-209ba07d-7854-459d-9e6c-cecb08921261
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929690137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.3929690137
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3458480079
Short name T147
Test name
Test status
Simulation time 781257100 ps
CPU time 4.1 seconds
Started Aug 09 06:39:59 PM PDT 24
Finished Aug 09 06:40:03 PM PDT 24
Peak memory 215484 kb
Host smart-49ed8cd4-1763-4c20-b101-b2d708d0807f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458480079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.3458480079
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3403232048
Short name T1123
Test name
Test status
Simulation time 354120905 ps
CPU time 2.86 seconds
Started Aug 09 06:39:57 PM PDT 24
Finished Aug 09 06:40:00 PM PDT 24
Peak memory 215868 kb
Host smart-1bd3ac80-e52c-42fd-8719-4ab56fbd1a35
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403232048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.3
403232048
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.4231267919
Short name T93
Test name
Test status
Simulation time 1075067526 ps
CPU time 12.01 seconds
Started Aug 09 06:40:02 PM PDT 24
Finished Aug 09 06:40:14 PM PDT 24
Peak memory 216108 kb
Host smart-2058b799-6c8c-4db0-8eaa-1eac43c17a5c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231267919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.4231267919
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.2811521078
Short name T1083
Test name
Test status
Simulation time 12629852 ps
CPU time 0.78 seconds
Started Aug 09 06:40:21 PM PDT 24
Finished Aug 09 06:40:21 PM PDT 24
Peak memory 204332 kb
Host smart-1e5b14e0-4894-4f71-9602-0f49d635c06b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811521078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
2811521078
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.2904271555
Short name T1088
Test name
Test status
Simulation time 48337528 ps
CPU time 0.78 seconds
Started Aug 09 06:40:26 PM PDT 24
Finished Aug 09 06:40:27 PM PDT 24
Peak memory 204372 kb
Host smart-2f899598-261a-471b-b5c8-a83174957bc5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904271555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
2904271555
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.2294041716
Short name T1043
Test name
Test status
Simulation time 44219794 ps
CPU time 0.74 seconds
Started Aug 09 06:40:21 PM PDT 24
Finished Aug 09 06:40:21 PM PDT 24
Peak memory 204016 kb
Host smart-f330da53-0a61-4d78-bf02-fa26ca9927ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294041716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
2294041716
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.56214551
Short name T1048
Test name
Test status
Simulation time 19666700 ps
CPU time 0.79 seconds
Started Aug 09 06:40:29 PM PDT 24
Finished Aug 09 06:40:30 PM PDT 24
Peak memory 204352 kb
Host smart-10851436-6b9d-4c34-acbb-fe463e80049c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56214551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.56214551
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.3204773970
Short name T1041
Test name
Test status
Simulation time 43537749 ps
CPU time 0.71 seconds
Started Aug 09 06:40:29 PM PDT 24
Finished Aug 09 06:40:30 PM PDT 24
Peak memory 204064 kb
Host smart-7bf3298c-c591-4e81-a5c4-973f267567f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204773970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
3204773970
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.2795354928
Short name T1140
Test name
Test status
Simulation time 30069212 ps
CPU time 0.76 seconds
Started Aug 09 06:40:29 PM PDT 24
Finished Aug 09 06:40:30 PM PDT 24
Peak memory 204052 kb
Host smart-410db1c6-fc8b-4797-a6c6-3e87c12c5d25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795354928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
2795354928
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.1271545839
Short name T1077
Test name
Test status
Simulation time 32030860 ps
CPU time 0.7 seconds
Started Aug 09 06:40:28 PM PDT 24
Finished Aug 09 06:40:29 PM PDT 24
Peak memory 204044 kb
Host smart-96317a7f-736f-44f3-bb68-ca3c72aedbd9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271545839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
1271545839
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.2334190624
Short name T1110
Test name
Test status
Simulation time 56995931 ps
CPU time 0.79 seconds
Started Aug 09 06:40:27 PM PDT 24
Finished Aug 09 06:40:28 PM PDT 24
Peak memory 204008 kb
Host smart-3a4a4bf2-847b-4296-865a-8740009d4100
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334190624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
2334190624
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.2809311226
Short name T1087
Test name
Test status
Simulation time 45126430 ps
CPU time 0.75 seconds
Started Aug 09 06:40:29 PM PDT 24
Finished Aug 09 06:40:30 PM PDT 24
Peak memory 203940 kb
Host smart-3ba12f81-af54-4e33-989a-2a2750b258e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809311226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
2809311226
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.3735442773
Short name T1053
Test name
Test status
Simulation time 11412024 ps
CPU time 0.69 seconds
Started Aug 09 06:40:28 PM PDT 24
Finished Aug 09 06:40:29 PM PDT 24
Peak memory 204008 kb
Host smart-645f26a1-6106-47d4-bddf-51694903c340
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735442773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
3735442773
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.2619545127
Short name T1095
Test name
Test status
Simulation time 3759184616 ps
CPU time 22.1 seconds
Started Aug 09 06:40:01 PM PDT 24
Finished Aug 09 06:40:24 PM PDT 24
Peak memory 207380 kb
Host smart-4f1d217e-b27e-4067-b579-a1ab2ff417fd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619545127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.2619545127
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1773110347
Short name T1134
Test name
Test status
Simulation time 1878665350 ps
CPU time 27.91 seconds
Started Aug 09 06:39:59 PM PDT 24
Finished Aug 09 06:40:27 PM PDT 24
Peak memory 207352 kb
Host smart-e08ef42b-1ec3-4317-9b89-1bfdb37c2302
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773110347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.1773110347
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.783000568
Short name T76
Test name
Test status
Simulation time 24616141 ps
CPU time 1.32 seconds
Started Aug 09 06:39:59 PM PDT 24
Finished Aug 09 06:40:00 PM PDT 24
Peak memory 207268 kb
Host smart-e7db51f3-ceb4-47f3-9a73-1d6da3883ebc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783000568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_hw_reset.783000568
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.540030898
Short name T105
Test name
Test status
Simulation time 91165507 ps
CPU time 2.47 seconds
Started Aug 09 06:40:08 PM PDT 24
Finished Aug 09 06:40:10 PM PDT 24
Peak memory 216892 kb
Host smart-cf286aad-cb06-496c-bfb5-0307e945b11a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540030898 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.540030898
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.1494936809
Short name T121
Test name
Test status
Simulation time 58351761 ps
CPU time 2.54 seconds
Started Aug 09 06:40:02 PM PDT 24
Finished Aug 09 06:40:05 PM PDT 24
Peak memory 215508 kb
Host smart-cc81aa76-f87d-429b-9145-c2d2fd68dc95
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494936809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.1
494936809
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.3669763730
Short name T1074
Test name
Test status
Simulation time 12869832 ps
CPU time 0.72 seconds
Started Aug 09 06:40:04 PM PDT 24
Finished Aug 09 06:40:05 PM PDT 24
Peak memory 204012 kb
Host smart-78a8a42b-070a-4c99-8dfa-a5cf8c80dbc1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669763730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.3
669763730
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.295670533
Short name T115
Test name
Test status
Simulation time 93714032 ps
CPU time 1.67 seconds
Started Aug 09 06:40:07 PM PDT 24
Finished Aug 09 06:40:09 PM PDT 24
Peak memory 215436 kb
Host smart-34b46b7c-b5bf-4d0a-b40a-da4bc49291e0
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295670533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_
device_mem_partial_access.295670533
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.3672404299
Short name T1038
Test name
Test status
Simulation time 41800678 ps
CPU time 0.69 seconds
Started Aug 09 06:40:02 PM PDT 24
Finished Aug 09 06:40:03 PM PDT 24
Peak memory 203960 kb
Host smart-38ebc6dc-2b24-4509-adae-6fd6ed94ad8a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672404299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.3672404299
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.1591108204
Short name T1135
Test name
Test status
Simulation time 151174851 ps
CPU time 3.18 seconds
Started Aug 09 06:40:07 PM PDT 24
Finished Aug 09 06:40:10 PM PDT 24
Peak memory 215496 kb
Host smart-6ecee867-a071-40ca-98cc-f546b4f23a6c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591108204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.1591108204
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.3776821411
Short name T97
Test name
Test status
Simulation time 628400325 ps
CPU time 4.44 seconds
Started Aug 09 06:39:57 PM PDT 24
Finished Aug 09 06:40:02 PM PDT 24
Peak memory 215736 kb
Host smart-3be5d6e5-7dda-400a-b13b-aff21817b360
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776821411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.3
776821411
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.1970573957
Short name T169
Test name
Test status
Simulation time 1446814508 ps
CPU time 17.14 seconds
Started Aug 09 06:40:02 PM PDT 24
Finished Aug 09 06:40:19 PM PDT 24
Peak memory 215604 kb
Host smart-5d654aa9-f2e7-4050-b382-82a83c8524cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970573957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.1970573957
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.199495793
Short name T1128
Test name
Test status
Simulation time 17853418 ps
CPU time 0.67 seconds
Started Aug 09 06:40:29 PM PDT 24
Finished Aug 09 06:40:30 PM PDT 24
Peak memory 203960 kb
Host smart-b6215421-aa85-4844-b354-ca37b284fcdb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199495793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.199495793
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.3821937758
Short name T1051
Test name
Test status
Simulation time 13085688 ps
CPU time 0.69 seconds
Started Aug 09 06:40:27 PM PDT 24
Finished Aug 09 06:40:27 PM PDT 24
Peak memory 204000 kb
Host smart-35aa11d6-6c5b-4927-b893-e730a6340572
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821937758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
3821937758
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.549938064
Short name T1058
Test name
Test status
Simulation time 36282440 ps
CPU time 0.73 seconds
Started Aug 09 06:40:29 PM PDT 24
Finished Aug 09 06:40:30 PM PDT 24
Peak memory 203972 kb
Host smart-49e26d6c-ae0d-4d13-ba8d-b7926e4d90fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549938064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.549938064
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.2276741166
Short name T1069
Test name
Test status
Simulation time 12771796 ps
CPU time 0.72 seconds
Started Aug 09 06:40:28 PM PDT 24
Finished Aug 09 06:40:28 PM PDT 24
Peak memory 204348 kb
Host smart-e703cb88-4ff1-4fe1-a964-38ac2e5990d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276741166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
2276741166
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.3392500278
Short name T1062
Test name
Test status
Simulation time 46717419 ps
CPU time 0.72 seconds
Started Aug 09 06:40:27 PM PDT 24
Finished Aug 09 06:40:28 PM PDT 24
Peak memory 204008 kb
Host smart-f712923c-f625-405f-ac5f-cc2db40e7924
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392500278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
3392500278
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.2447700562
Short name T1125
Test name
Test status
Simulation time 38877362 ps
CPU time 0.71 seconds
Started Aug 09 06:40:26 PM PDT 24
Finished Aug 09 06:40:27 PM PDT 24
Peak memory 204004 kb
Host smart-fe4f9129-a64f-460c-9aa8-a962fa208b72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447700562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
2447700562
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.194243906
Short name T1086
Test name
Test status
Simulation time 131734123 ps
CPU time 0.81 seconds
Started Aug 09 06:40:30 PM PDT 24
Finished Aug 09 06:40:31 PM PDT 24
Peak memory 204008 kb
Host smart-9233bf51-29d0-4c8d-8fe9-5f97abeab86c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194243906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.194243906
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.248616322
Short name T1064
Test name
Test status
Simulation time 128651515 ps
CPU time 0.73 seconds
Started Aug 09 06:40:31 PM PDT 24
Finished Aug 09 06:40:31 PM PDT 24
Peak memory 204356 kb
Host smart-ba3c0e1f-9dd8-400b-87f1-e3a0830d78c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248616322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.248616322
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.4127690497
Short name T1065
Test name
Test status
Simulation time 17627858 ps
CPU time 0.8 seconds
Started Aug 09 06:40:30 PM PDT 24
Finished Aug 09 06:40:31 PM PDT 24
Peak memory 204056 kb
Host smart-5e03128f-eac4-4d58-8961-a521940fe96c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127690497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
4127690497
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.3036945522
Short name T1057
Test name
Test status
Simulation time 19235454 ps
CPU time 0.76 seconds
Started Aug 09 06:40:31 PM PDT 24
Finished Aug 09 06:40:32 PM PDT 24
Peak memory 204032 kb
Host smart-a03479cb-7591-4b68-91e6-03ba724798fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036945522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
3036945522
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3054977340
Short name T109
Test name
Test status
Simulation time 2644467388 ps
CPU time 15.98 seconds
Started Aug 09 06:39:59 PM PDT 24
Finished Aug 09 06:40:15 PM PDT 24
Peak memory 215684 kb
Host smart-77a55484-f7c6-4d88-b4af-b73557c2b832
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054977340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.3054977340
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3948018169
Short name T1061
Test name
Test status
Simulation time 3545559142 ps
CPU time 25.75 seconds
Started Aug 09 06:40:02 PM PDT 24
Finished Aug 09 06:40:28 PM PDT 24
Peak memory 207408 kb
Host smart-92da00e5-c99b-4e8a-95d2-4f662a982e46
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948018169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.3948018169
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.384889221
Short name T1116
Test name
Test status
Simulation time 52774479 ps
CPU time 1 seconds
Started Aug 09 06:40:05 PM PDT 24
Finished Aug 09 06:40:06 PM PDT 24
Peak memory 206884 kb
Host smart-634ef88e-b4ed-4ef9-8289-fb06df28a955
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384889221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_hw_reset.384889221
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3990228252
Short name T1114
Test name
Test status
Simulation time 41954400 ps
CPU time 2.91 seconds
Started Aug 09 06:40:02 PM PDT 24
Finished Aug 09 06:40:05 PM PDT 24
Peak memory 216996 kb
Host smart-839599b7-a262-47f0-a153-3b69b767deb3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990228252 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.3990228252
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.746779095
Short name T119
Test name
Test status
Simulation time 38740793 ps
CPU time 1.17 seconds
Started Aug 09 06:39:59 PM PDT 24
Finished Aug 09 06:40:00 PM PDT 24
Peak memory 215604 kb
Host smart-d1663982-d7ef-4795-b9bf-3c9766d5a23c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746779095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.746779095
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.1891617949
Short name T1071
Test name
Test status
Simulation time 21598166 ps
CPU time 0.79 seconds
Started Aug 09 06:40:02 PM PDT 24
Finished Aug 09 06:40:03 PM PDT 24
Peak memory 204008 kb
Host smart-576caf74-90bb-4490-a116-1b42a4bacb27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891617949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.1
891617949
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.4247044371
Short name T116
Test name
Test status
Simulation time 43138994 ps
CPU time 1.49 seconds
Started Aug 09 06:40:03 PM PDT 24
Finished Aug 09 06:40:05 PM PDT 24
Peak memory 215536 kb
Host smart-493b7db7-1fe4-4bc7-96fb-54834de207db
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247044371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.4247044371
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.3723285048
Short name T1045
Test name
Test status
Simulation time 16817863 ps
CPU time 0.66 seconds
Started Aug 09 06:40:01 PM PDT 24
Finished Aug 09 06:40:02 PM PDT 24
Peak memory 204284 kb
Host smart-fef35966-3569-42c2-91aa-096dacb7bb1e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723285048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.3723285048
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.1123996590
Short name T1122
Test name
Test status
Simulation time 61755063 ps
CPU time 1.73 seconds
Started Aug 09 06:39:59 PM PDT 24
Finished Aug 09 06:40:01 PM PDT 24
Peak memory 216764 kb
Host smart-229f383d-053e-49b9-9ad7-54420e075592
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123996590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.1123996590
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.352068055
Short name T175
Test name
Test status
Simulation time 1583197501 ps
CPU time 5.63 seconds
Started Aug 09 06:40:02 PM PDT 24
Finished Aug 09 06:40:07 PM PDT 24
Peak memory 215828 kb
Host smart-62fe49bd-b875-4d31-8790-ac0f2078d0cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352068055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.352068055
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.3386515741
Short name T1078
Test name
Test status
Simulation time 15754366 ps
CPU time 0.72 seconds
Started Aug 09 06:40:31 PM PDT 24
Finished Aug 09 06:40:32 PM PDT 24
Peak memory 203988 kb
Host smart-99ad6936-0538-4634-8a87-957d2e400bff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386515741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
3386515741
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.1935795050
Short name T1100
Test name
Test status
Simulation time 40366017 ps
CPU time 0.7 seconds
Started Aug 09 06:40:28 PM PDT 24
Finished Aug 09 06:40:29 PM PDT 24
Peak memory 203968 kb
Host smart-3619d891-6c18-43cf-8f87-408fc7285210
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935795050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
1935795050
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.2602564825
Short name T1118
Test name
Test status
Simulation time 37542309 ps
CPU time 0.7 seconds
Started Aug 09 06:40:31 PM PDT 24
Finished Aug 09 06:40:32 PM PDT 24
Peak memory 204332 kb
Host smart-dd6ebc06-4b7f-4516-b82a-6bfdab0166e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602564825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
2602564825
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.1242376842
Short name T1105
Test name
Test status
Simulation time 15698903 ps
CPU time 0.75 seconds
Started Aug 09 06:40:29 PM PDT 24
Finished Aug 09 06:40:30 PM PDT 24
Peak memory 204204 kb
Host smart-29596e46-cdf8-494f-9159-52abfbe16ff3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242376842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
1242376842
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1960589800
Short name T1148
Test name
Test status
Simulation time 24935047 ps
CPU time 0.73 seconds
Started Aug 09 06:40:29 PM PDT 24
Finished Aug 09 06:40:30 PM PDT 24
Peak memory 203996 kb
Host smart-746fbc90-d353-464d-ab95-0550564157c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960589800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
1960589800
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3348787187
Short name T1124
Test name
Test status
Simulation time 13699921 ps
CPU time 0.75 seconds
Started Aug 09 06:40:30 PM PDT 24
Finished Aug 09 06:40:31 PM PDT 24
Peak memory 203996 kb
Host smart-a57e59bc-5f57-4ac3-ab82-11d7776c9e28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348787187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
3348787187
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.505036106
Short name T1036
Test name
Test status
Simulation time 43591841 ps
CPU time 0.76 seconds
Started Aug 09 06:40:30 PM PDT 24
Finished Aug 09 06:40:31 PM PDT 24
Peak memory 204072 kb
Host smart-54af4836-377c-47b8-9e4a-45c5145ecade
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505036106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.505036106
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.2590315567
Short name T1039
Test name
Test status
Simulation time 11085038 ps
CPU time 0.69 seconds
Started Aug 09 06:40:30 PM PDT 24
Finished Aug 09 06:40:31 PM PDT 24
Peak memory 204380 kb
Host smart-f804f1ab-4064-4373-ba87-0351288421fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590315567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
2590315567
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2345142824
Short name T1046
Test name
Test status
Simulation time 12141113 ps
CPU time 0.72 seconds
Started Aug 09 06:40:30 PM PDT 24
Finished Aug 09 06:40:31 PM PDT 24
Peak memory 204380 kb
Host smart-c8037fb7-9d6c-4ddd-b9c5-d2c6a866295c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345142824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
2345142824
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.2679392621
Short name T1066
Test name
Test status
Simulation time 13899448 ps
CPU time 0.67 seconds
Started Aug 09 06:40:28 PM PDT 24
Finished Aug 09 06:40:29 PM PDT 24
Peak memory 204020 kb
Host smart-5b734cd2-9c12-477b-9c5a-c63f99d14088
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679392621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
2679392621
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.2129500686
Short name T1085
Test name
Test status
Simulation time 199970777 ps
CPU time 1.82 seconds
Started Aug 09 06:40:00 PM PDT 24
Finished Aug 09 06:40:02 PM PDT 24
Peak memory 215576 kb
Host smart-59e8d72c-6278-462a-8888-8ac5dd8eae7b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129500686 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.2129500686
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.1509956019
Short name T1063
Test name
Test status
Simulation time 130067625 ps
CPU time 2.06 seconds
Started Aug 09 06:40:01 PM PDT 24
Finished Aug 09 06:40:03 PM PDT 24
Peak memory 215536 kb
Host smart-7fe0b905-b295-48b7-9f4b-c09a640c4383
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509956019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.1
509956019
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.2797616686
Short name T1147
Test name
Test status
Simulation time 27232917 ps
CPU time 0.74 seconds
Started Aug 09 06:39:59 PM PDT 24
Finished Aug 09 06:40:00 PM PDT 24
Peak memory 204280 kb
Host smart-ae654ce4-8327-4445-890a-3b71d0331ac6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797616686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.2
797616686
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.3433478088
Short name T146
Test name
Test status
Simulation time 335503504 ps
CPU time 3.85 seconds
Started Aug 09 06:40:03 PM PDT 24
Finished Aug 09 06:40:07 PM PDT 24
Peak memory 215460 kb
Host smart-70b4b94e-9d6f-4a03-a403-680cc3699179
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433478088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.3433478088
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.2336180037
Short name T102
Test name
Test status
Simulation time 37126605 ps
CPU time 2.1 seconds
Started Aug 09 06:40:04 PM PDT 24
Finished Aug 09 06:40:06 PM PDT 24
Peak memory 215856 kb
Host smart-7ec16233-9889-4409-ba7c-be90c6b4b4fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336180037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.2
336180037
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.2149721722
Short name T86
Test name
Test status
Simulation time 160269510 ps
CPU time 1.83 seconds
Started Aug 09 06:40:02 PM PDT 24
Finished Aug 09 06:40:04 PM PDT 24
Peak memory 216648 kb
Host smart-0d1e3562-10dc-4c27-b732-192a9e3bffcc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149721722 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.2149721722
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.2186522197
Short name T1109
Test name
Test status
Simulation time 158226850 ps
CPU time 1.41 seconds
Started Aug 09 06:40:08 PM PDT 24
Finished Aug 09 06:40:10 PM PDT 24
Peak memory 207288 kb
Host smart-2798908d-b5dd-4588-b2ee-074fd54d78fb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186522197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.2
186522197
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.1131675532
Short name T1054
Test name
Test status
Simulation time 13313007 ps
CPU time 0.77 seconds
Started Aug 09 06:40:09 PM PDT 24
Finished Aug 09 06:40:10 PM PDT 24
Peak memory 203912 kb
Host smart-e6f134de-abe2-4101-9d23-6629a621b167
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131675532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.1
131675532
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.4077290345
Short name T1130
Test name
Test status
Simulation time 659418438 ps
CPU time 4.41 seconds
Started Aug 09 06:40:08 PM PDT 24
Finished Aug 09 06:40:13 PM PDT 24
Peak memory 215484 kb
Host smart-04995c7d-dc6a-48ea-a81e-99650726d2b5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077290345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.4077290345
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.1277914391
Short name T1129
Test name
Test status
Simulation time 467639331 ps
CPU time 3.37 seconds
Started Aug 09 06:40:01 PM PDT 24
Finished Aug 09 06:40:04 PM PDT 24
Peak memory 215820 kb
Host smart-ce1ee908-5080-4ff9-87dd-d2063c2524e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277914391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.1
277914391
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.700266141
Short name T165
Test name
Test status
Simulation time 674037968 ps
CPU time 6.25 seconds
Started Aug 09 06:39:58 PM PDT 24
Finished Aug 09 06:40:04 PM PDT 24
Peak memory 215624 kb
Host smart-60b0b937-455b-4466-b39e-398a679975ad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700266141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_
tl_intg_err.700266141
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.2290803489
Short name T1102
Test name
Test status
Simulation time 163836171 ps
CPU time 2.5 seconds
Started Aug 09 06:40:08 PM PDT 24
Finished Aug 09 06:40:10 PM PDT 24
Peak memory 218364 kb
Host smart-37d36511-885a-4206-a3e4-535f7801e3c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290803489 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.2290803489
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.3711801678
Short name T1133
Test name
Test status
Simulation time 35303738 ps
CPU time 2.31 seconds
Started Aug 09 06:40:07 PM PDT 24
Finished Aug 09 06:40:10 PM PDT 24
Peak memory 215524 kb
Host smart-310d3181-21c1-4445-aaf2-3414b3b4d762
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711801678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.3
711801678
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.27284610
Short name T1040
Test name
Test status
Simulation time 15631463 ps
CPU time 0.75 seconds
Started Aug 09 06:40:05 PM PDT 24
Finished Aug 09 06:40:06 PM PDT 24
Peak memory 203904 kb
Host smart-c3397d10-c702-4c51-abe6-a61783bc77af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27284610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.27284610
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.965409280
Short name T1076
Test name
Test status
Simulation time 633000953 ps
CPU time 2.93 seconds
Started Aug 09 06:40:08 PM PDT 24
Finished Aug 09 06:40:11 PM PDT 24
Peak memory 215532 kb
Host smart-1619dfe3-fe15-49dc-ba79-1f5ea63add29
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965409280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sp
i_device_same_csr_outstanding.965409280
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.2475525792
Short name T1139
Test name
Test status
Simulation time 166409019 ps
CPU time 2.46 seconds
Started Aug 09 06:40:04 PM PDT 24
Finished Aug 09 06:40:06 PM PDT 24
Peak memory 215924 kb
Host smart-43207ff9-bb4f-4550-83ba-a8b634d0082c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475525792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.2
475525792
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.4026286287
Short name T176
Test name
Test status
Simulation time 903439951 ps
CPU time 7.66 seconds
Started Aug 09 06:40:07 PM PDT 24
Finished Aug 09 06:40:15 PM PDT 24
Peak memory 215544 kb
Host smart-a9397f2a-4ece-4b51-9023-8392623472b7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026286287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.4026286287
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3425109328
Short name T1067
Test name
Test status
Simulation time 1232927547 ps
CPU time 3.69 seconds
Started Aug 09 06:40:06 PM PDT 24
Finished Aug 09 06:40:10 PM PDT 24
Peak memory 217316 kb
Host smart-5531b30b-551c-4908-adba-6ceb7c9a3e12
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425109328 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.3425109328
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.2524139642
Short name T1151
Test name
Test status
Simulation time 41697107 ps
CPU time 2.69 seconds
Started Aug 09 06:40:06 PM PDT 24
Finished Aug 09 06:40:09 PM PDT 24
Peak memory 215524 kb
Host smart-5b2a54e2-45e4-4869-b15b-c3419cc59590
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524139642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.2
524139642
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.3086549525
Short name T1101
Test name
Test status
Simulation time 15266937 ps
CPU time 0.74 seconds
Started Aug 09 06:40:05 PM PDT 24
Finished Aug 09 06:40:06 PM PDT 24
Peak memory 203964 kb
Host smart-8062ed48-7965-42f7-a32a-d8bb368d9da9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086549525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.3
086549525
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.1603264195
Short name T1084
Test name
Test status
Simulation time 169139064 ps
CPU time 2.87 seconds
Started Aug 09 06:40:09 PM PDT 24
Finished Aug 09 06:40:12 PM PDT 24
Peak memory 215468 kb
Host smart-45a66887-9e0a-4e3b-870d-beb92af1cd4e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603264195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.1603264195
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.3199406058
Short name T85
Test name
Test status
Simulation time 337204823 ps
CPU time 5.11 seconds
Started Aug 09 06:40:10 PM PDT 24
Finished Aug 09 06:40:16 PM PDT 24
Peak memory 215760 kb
Host smart-aed3943a-5a63-424f-8266-d8fb938f0698
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199406058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.3
199406058
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.2291556074
Short name T170
Test name
Test status
Simulation time 4425642461 ps
CPU time 8.25 seconds
Started Aug 09 06:40:09 PM PDT 24
Finished Aug 09 06:40:18 PM PDT 24
Peak memory 215696 kb
Host smart-1ce45ca6-b85a-4257-9d62-206ccba766ea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291556074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.2291556074
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.311788763
Short name T108
Test name
Test status
Simulation time 91985289 ps
CPU time 2.81 seconds
Started Aug 09 06:40:06 PM PDT 24
Finished Aug 09 06:40:09 PM PDT 24
Peak memory 216992 kb
Host smart-af9d20d2-d115-414d-85e5-e7faf107f631
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311788763 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.311788763
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.2144132259
Short name T120
Test name
Test status
Simulation time 304806154 ps
CPU time 1.95 seconds
Started Aug 09 06:40:09 PM PDT 24
Finished Aug 09 06:40:11 PM PDT 24
Peak memory 215456 kb
Host smart-f47eb6d0-0b5d-41d2-9b05-c113e133baf6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144132259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.2
144132259
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.587211922
Short name T1070
Test name
Test status
Simulation time 17526090 ps
CPU time 0.73 seconds
Started Aug 09 06:40:07 PM PDT 24
Finished Aug 09 06:40:08 PM PDT 24
Peak memory 204332 kb
Host smart-1bb8ae85-02de-40f0-8f45-132fb26be7fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587211922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.587211922
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3452914770
Short name T1082
Test name
Test status
Simulation time 135047182 ps
CPU time 2.97 seconds
Started Aug 09 06:40:11 PM PDT 24
Finished Aug 09 06:40:14 PM PDT 24
Peak memory 215532 kb
Host smart-f5314596-ea0b-479e-8482-968ad3ba0d93
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452914770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.3452914770
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.1098462314
Short name T1143
Test name
Test status
Simulation time 190867806 ps
CPU time 2.95 seconds
Started Aug 09 06:40:08 PM PDT 24
Finished Aug 09 06:40:11 PM PDT 24
Peak memory 215732 kb
Host smart-d9cfaa3a-0b17-4c80-aafc-2f506c0eeffa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098462314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.1
098462314
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.3006681553
Short name T1073
Test name
Test status
Simulation time 202569902 ps
CPU time 11.4 seconds
Started Aug 09 06:40:07 PM PDT 24
Finished Aug 09 06:40:18 PM PDT 24
Peak memory 216724 kb
Host smart-1df3bff5-d785-4640-95fe-460966ce8547
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006681553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.3006681553
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.1912006066
Short name T499
Test name
Test status
Simulation time 15376166 ps
CPU time 0.74 seconds
Started Aug 09 06:52:36 PM PDT 24
Finished Aug 09 06:52:37 PM PDT 24
Peak memory 205272 kb
Host smart-6375b214-189f-4b7c-832b-ba30122bbb49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912006066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.1
912006066
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.77818316
Short name T247
Test name
Test status
Simulation time 3281584852 ps
CPU time 7.05 seconds
Started Aug 09 06:51:44 PM PDT 24
Finished Aug 09 06:51:51 PM PDT 24
Peak memory 233500 kb
Host smart-69503fbe-1eb0-4d61-a559-35e1e7e8bca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77818316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.77818316
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.719208705
Short name T855
Test name
Test status
Simulation time 68987658 ps
CPU time 0.8 seconds
Started Aug 09 06:51:37 PM PDT 24
Finished Aug 09 06:51:38 PM PDT 24
Peak memory 207392 kb
Host smart-1bb98e30-819c-43c9-bfb1-af2a05dcd699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719208705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.719208705
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.2334013824
Short name T378
Test name
Test status
Simulation time 33154274844 ps
CPU time 58.65 seconds
Started Aug 09 06:52:38 PM PDT 24
Finished Aug 09 06:53:37 PM PDT 24
Peak memory 249812 kb
Host smart-f95e872b-d72d-4cf3-9ac8-2b878270fe65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334013824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.2334013824
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.397691202
Short name T539
Test name
Test status
Simulation time 63858757010 ps
CPU time 184.52 seconds
Started Aug 09 06:52:37 PM PDT 24
Finished Aug 09 06:55:42 PM PDT 24
Peak memory 257516 kb
Host smart-897c1d94-5321-4bb2-afbb-51c51c824b6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397691202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle.
397691202
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.3509327680
Short name T1016
Test name
Test status
Simulation time 13755452181 ps
CPU time 23.38 seconds
Started Aug 09 06:51:42 PM PDT 24
Finished Aug 09 06:52:06 PM PDT 24
Peak memory 241476 kb
Host smart-068af6fb-be00-46fe-99be-49f47a56549d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509327680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.3509327680
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_intercept.2506643114
Short name T935
Test name
Test status
Simulation time 201934833 ps
CPU time 3.05 seconds
Started Aug 09 06:51:36 PM PDT 24
Finished Aug 09 06:51:39 PM PDT 24
Peak memory 233356 kb
Host smart-5d239a18-5f72-453a-8743-c0dfe4aecfb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506643114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.2506643114
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.1501266440
Short name T872
Test name
Test status
Simulation time 26812347652 ps
CPU time 90.56 seconds
Started Aug 09 06:51:38 PM PDT 24
Finished Aug 09 06:53:09 PM PDT 24
Peak memory 233500 kb
Host smart-bde87273-d8dc-4a44-8ba3-d9554a175af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501266440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.1501266440
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.2202699825
Short name T848
Test name
Test status
Simulation time 175668244 ps
CPU time 2.96 seconds
Started Aug 09 06:51:38 PM PDT 24
Finished Aug 09 06:51:41 PM PDT 24
Peak memory 225208 kb
Host smart-611a2503-5222-421c-8ae0-95098a9ca689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202699825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.2202699825
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.952666450
Short name T275
Test name
Test status
Simulation time 7261582074 ps
CPU time 10.47 seconds
Started Aug 09 06:51:37 PM PDT 24
Finished Aug 09 06:51:48 PM PDT 24
Peak memory 233456 kb
Host smart-de90c557-5e32-4c80-abc9-49ee8788e66e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952666450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.952666450
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.1514002274
Short name T932
Test name
Test status
Simulation time 3378286216 ps
CPU time 5.43 seconds
Started Aug 09 06:51:42 PM PDT 24
Finished Aug 09 06:51:48 PM PDT 24
Peak memory 220056 kb
Host smart-bfc5b36f-fb71-4592-aabb-765e3c30d6af
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1514002274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.1514002274
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.4120312800
Short name T29
Test name
Test status
Simulation time 76087139 ps
CPU time 0.97 seconds
Started Aug 09 06:52:37 PM PDT 24
Finished Aug 09 06:52:38 PM PDT 24
Peak memory 208088 kb
Host smart-776ced26-f456-476c-bbd7-4cde4f865eda
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120312800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.4120312800
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.3939179544
Short name T870
Test name
Test status
Simulation time 4356221295 ps
CPU time 6.62 seconds
Started Aug 09 06:51:35 PM PDT 24
Finished Aug 09 06:51:42 PM PDT 24
Peak memory 217000 kb
Host smart-901f4429-7134-4150-b285-e8ac7db1af7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939179544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.3939179544
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.2011805453
Short name T6
Test name
Test status
Simulation time 1625726730 ps
CPU time 3.21 seconds
Started Aug 09 06:51:36 PM PDT 24
Finished Aug 09 06:51:39 PM PDT 24
Peak memory 216888 kb
Host smart-8b632958-1b5c-4eff-8f43-36123a261cf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011805453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.2011805453
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.233311745
Short name T868
Test name
Test status
Simulation time 184231474 ps
CPU time 2.04 seconds
Started Aug 09 06:51:38 PM PDT 24
Finished Aug 09 06:51:40 PM PDT 24
Peak memory 217016 kb
Host smart-f60bbb3e-6d78-4386-919a-57b9ea566474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233311745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.233311745
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.3264304683
Short name T914
Test name
Test status
Simulation time 458745709 ps
CPU time 0.97 seconds
Started Aug 09 06:51:37 PM PDT 24
Finished Aug 09 06:51:38 PM PDT 24
Peak memory 207540 kb
Host smart-7e0e3a29-a888-429c-aab0-4b737f4c52bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264304683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.3264304683
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.1850671045
Short name T2
Test name
Test status
Simulation time 1185641879 ps
CPU time 4.85 seconds
Started Aug 09 06:51:43 PM PDT 24
Finished Aug 09 06:51:48 PM PDT 24
Peak memory 225188 kb
Host smart-149a3cad-61c7-47d7-9455-f57a25d379de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850671045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.1850671045
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.3311272353
Short name T951
Test name
Test status
Simulation time 14090016 ps
CPU time 0.71 seconds
Started Aug 09 06:52:39 PM PDT 24
Finished Aug 09 06:52:40 PM PDT 24
Peak memory 206220 kb
Host smart-89f14447-9858-4ce6-83b6-7652363f1c1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311272353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.3
311272353
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.4133580831
Short name T1027
Test name
Test status
Simulation time 154639493 ps
CPU time 2.57 seconds
Started Aug 09 06:51:59 PM PDT 24
Finished Aug 09 06:52:01 PM PDT 24
Peak memory 233420 kb
Host smart-5574e82d-cda8-423e-9298-dfef83d05c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133580831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.4133580831
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.149135907
Short name T1034
Test name
Test status
Simulation time 58651125 ps
CPU time 0.74 seconds
Started Aug 09 06:52:37 PM PDT 24
Finished Aug 09 06:52:38 PM PDT 24
Peak memory 207292 kb
Host smart-9e4bb769-b434-46e3-8f3a-cae1574f732f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149135907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.149135907
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.2353470380
Short name T198
Test name
Test status
Simulation time 19855162314 ps
CPU time 102.07 seconds
Started Aug 09 06:52:38 PM PDT 24
Finished Aug 09 06:54:20 PM PDT 24
Peak memory 264208 kb
Host smart-417fff30-2a15-4336-b5a9-ee64a6761285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353470380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.2353470380
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.171591244
Short name T881
Test name
Test status
Simulation time 114851252273 ps
CPU time 256.93 seconds
Started Aug 09 06:52:40 PM PDT 24
Finished Aug 09 06:56:57 PM PDT 24
Peak memory 258100 kb
Host smart-9c4f8e8b-e7eb-4464-8533-52accc745fcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171591244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.171591244
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.4264001522
Short name T946
Test name
Test status
Simulation time 159739298 ps
CPU time 7.73 seconds
Started Aug 09 06:51:59 PM PDT 24
Finished Aug 09 06:52:07 PM PDT 24
Peak memory 241560 kb
Host smart-88989e58-6908-4c04-bf69-46871bc23891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264001522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.4264001522
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_intercept.2199278894
Short name T716
Test name
Test status
Simulation time 946855054 ps
CPU time 7.58 seconds
Started Aug 09 06:51:59 PM PDT 24
Finished Aug 09 06:52:07 PM PDT 24
Peak memory 225200 kb
Host smart-9523a01d-aad5-4477-8e6f-1a45456ce127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199278894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.2199278894
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.30808136
Short name T217
Test name
Test status
Simulation time 13928463974 ps
CPU time 24.23 seconds
Started Aug 09 06:51:58 PM PDT 24
Finished Aug 09 06:52:23 PM PDT 24
Peak memory 241472 kb
Host smart-2675156c-38a5-47be-8e8b-9dfdf26c11bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30808136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.30808136
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.30173430
Short name T489
Test name
Test status
Simulation time 27589242 ps
CPU time 1.1 seconds
Started Aug 09 06:52:40 PM PDT 24
Finished Aug 09 06:52:41 PM PDT 24
Peak memory 217180 kb
Host smart-efdc0f09-98c4-47e4-9f79-c31b5ddcb549
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30173430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TES
T_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.spi_device_mem_parity.30173430
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.2394755249
Short name T990
Test name
Test status
Simulation time 25092536254 ps
CPU time 15.13 seconds
Started Aug 09 06:51:59 PM PDT 24
Finished Aug 09 06:52:14 PM PDT 24
Peak memory 233444 kb
Host smart-e99972b3-3011-486c-89f8-312b468c7b27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394755249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.2394755249
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.2189742222
Short name T655
Test name
Test status
Simulation time 19770554601 ps
CPU time 16.68 seconds
Started Aug 09 06:51:58 PM PDT 24
Finished Aug 09 06:52:15 PM PDT 24
Peak memory 237104 kb
Host smart-18eccc00-6423-4e78-ac93-3fc39675b4fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189742222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.2189742222
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.340192606
Short name T958
Test name
Test status
Simulation time 1632987769 ps
CPU time 6.43 seconds
Started Aug 09 06:52:39 PM PDT 24
Finished Aug 09 06:52:46 PM PDT 24
Peak memory 221036 kb
Host smart-2f8689df-180c-4320-83f9-3210628997f2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=340192606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_direc
t.340192606
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.1147722345
Short name T64
Test name
Test status
Simulation time 60628633 ps
CPU time 1.08 seconds
Started Aug 09 06:52:41 PM PDT 24
Finished Aug 09 06:52:42 PM PDT 24
Peak memory 235596 kb
Host smart-b44d306c-3efe-457d-a43f-83990c4c375f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147722345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.1147722345
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.2123282125
Short name T472
Test name
Test status
Simulation time 3504411191 ps
CPU time 28.07 seconds
Started Aug 09 06:52:40 PM PDT 24
Finished Aug 09 06:53:08 PM PDT 24
Peak memory 224300 kb
Host smart-9da6bb24-24fe-4137-9d90-c232ceec6e90
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123282125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.2123282125
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.2106287412
Short name T735
Test name
Test status
Simulation time 4555752828 ps
CPU time 9.43 seconds
Started Aug 09 06:52:37 PM PDT 24
Finished Aug 09 06:52:47 PM PDT 24
Peak memory 217020 kb
Host smart-cb6bc923-86e2-45f6-8314-a90ae3c7908f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106287412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.2106287412
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.2814602339
Short name T846
Test name
Test status
Simulation time 587674106 ps
CPU time 2.07 seconds
Started Aug 09 06:52:38 PM PDT 24
Finished Aug 09 06:52:41 PM PDT 24
Peak memory 217016 kb
Host smart-473a513f-99c4-47a7-a8da-ecb96f55139d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814602339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.2814602339
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.793604224
Short name T975
Test name
Test status
Simulation time 25837969 ps
CPU time 0.83 seconds
Started Aug 09 06:52:40 PM PDT 24
Finished Aug 09 06:52:41 PM PDT 24
Peak memory 206112 kb
Host smart-2685ac9a-b9cf-4ddc-a90f-37c61e127a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793604224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.793604224
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.848455457
Short name T678
Test name
Test status
Simulation time 44463953 ps
CPU time 0.76 seconds
Started Aug 09 06:52:38 PM PDT 24
Finished Aug 09 06:52:39 PM PDT 24
Peak memory 206488 kb
Host smart-1b25eb84-d7a3-45ae-af72-65207fe9e4e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848455457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.848455457
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.262311157
Short name T852
Test name
Test status
Simulation time 15478614308 ps
CPU time 23.21 seconds
Started Aug 09 06:51:58 PM PDT 24
Finished Aug 09 06:52:21 PM PDT 24
Peak memory 233520 kb
Host smart-014ea739-65e7-4669-bcf5-fa29013b2843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262311157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.262311157
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.2297622773
Short name T754
Test name
Test status
Simulation time 143043924 ps
CPU time 4.2 seconds
Started Aug 09 06:54:01 PM PDT 24
Finished Aug 09 06:54:05 PM PDT 24
Peak memory 225208 kb
Host smart-f20b1a14-62fb-4bf3-b008-bb67eaacdaeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297622773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.2297622773
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.510500327
Short name T14
Test name
Test status
Simulation time 14403846 ps
CPU time 0.74 seconds
Started Aug 09 06:53:50 PM PDT 24
Finished Aug 09 06:53:51 PM PDT 24
Peak memory 206996 kb
Host smart-07fc1c9b-0c07-4084-9c2b-35034d6b3c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510500327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.510500327
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.3791940248
Short name T417
Test name
Test status
Simulation time 32126900267 ps
CPU time 62.77 seconds
Started Aug 09 06:54:05 PM PDT 24
Finished Aug 09 06:55:07 PM PDT 24
Peak memory 250188 kb
Host smart-e529991f-3ac3-475a-bb77-18bd697cc088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791940248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.3791940248
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.3980426331
Short name T397
Test name
Test status
Simulation time 12906920171 ps
CPU time 38.61 seconds
Started Aug 09 06:54:04 PM PDT 24
Finished Aug 09 06:54:43 PM PDT 24
Peak memory 249956 kb
Host smart-f381c639-ed13-4a52-9f69-d8ad9e16c8d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980426331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.3980426331
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.2375005840
Short name T331
Test name
Test status
Simulation time 39673597636 ps
CPU time 107.44 seconds
Started Aug 09 06:54:04 PM PDT 24
Finished Aug 09 06:55:52 PM PDT 24
Peak memory 266364 kb
Host smart-8fbf2e54-1735-4bd5-8d25-169b1619762b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375005840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.2375005840
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.466966776
Short name T624
Test name
Test status
Simulation time 252217179 ps
CPU time 3.87 seconds
Started Aug 09 06:54:01 PM PDT 24
Finished Aug 09 06:54:05 PM PDT 24
Peak memory 225244 kb
Host smart-941bc642-bfe5-4319-93c1-ca22aa33138a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466966776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.466966776
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.4186142617
Short name T525
Test name
Test status
Simulation time 21552623903 ps
CPU time 108.23 seconds
Started Aug 09 06:54:05 PM PDT 24
Finished Aug 09 06:55:53 PM PDT 24
Peak memory 258092 kb
Host smart-08eda282-ded0-4e6e-a22f-5de029b88370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186142617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmd
s.4186142617
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/10.spi_device_intercept.358550914
Short name T1000
Test name
Test status
Simulation time 332398598 ps
CPU time 4.28 seconds
Started Aug 09 06:54:03 PM PDT 24
Finished Aug 09 06:54:07 PM PDT 24
Peak memory 225172 kb
Host smart-4c3b1822-d0cc-4557-b7b7-cfc14ef1de8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358550914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.358550914
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.717519003
Short name T280
Test name
Test status
Simulation time 1171049061 ps
CPU time 7.62 seconds
Started Aug 09 06:54:00 PM PDT 24
Finished Aug 09 06:54:08 PM PDT 24
Peak memory 233456 kb
Host smart-63239f34-a895-44dd-945a-30bb00606464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717519003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.717519003
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.4099782111
Short name T923
Test name
Test status
Simulation time 93017031 ps
CPU time 1 seconds
Started Aug 09 06:53:49 PM PDT 24
Finished Aug 09 06:53:50 PM PDT 24
Peak memory 217216 kb
Host smart-7b9362e9-3878-43ad-9bc7-57e6c436f349
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099782111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.spi_device_mem_parity.4099782111
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.3193469062
Short name T291
Test name
Test status
Simulation time 33003700522 ps
CPU time 47.26 seconds
Started Aug 09 06:54:02 PM PDT 24
Finished Aug 09 06:54:49 PM PDT 24
Peak memory 250128 kb
Host smart-07902d24-8386-4ab1-b6b1-5382f86aea5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193469062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.3193469062
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.3796816396
Short name T435
Test name
Test status
Simulation time 5086094677 ps
CPU time 15.44 seconds
Started Aug 09 06:54:01 PM PDT 24
Finished Aug 09 06:54:16 PM PDT 24
Peak memory 233440 kb
Host smart-cfe1e907-c689-4ede-9bdd-9a48fd86c60b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796816396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.3796816396
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.2573771166
Short name T913
Test name
Test status
Simulation time 545399715 ps
CPU time 3.98 seconds
Started Aug 09 06:54:04 PM PDT 24
Finished Aug 09 06:54:08 PM PDT 24
Peak memory 219988 kb
Host smart-75a25b3a-535e-4fc8-80c5-2c67f0912fa7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2573771166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.2573771166
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.622804747
Short name T129
Test name
Test status
Simulation time 4734558567 ps
CPU time 95.32 seconds
Started Aug 09 06:54:10 PM PDT 24
Finished Aug 09 06:55:46 PM PDT 24
Peak memory 249964 kb
Host smart-006792bc-6807-495f-bfbb-79a721435120
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622804747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stres
s_all.622804747
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.3056779948
Short name T821
Test name
Test status
Simulation time 7805177763 ps
CPU time 40.39 seconds
Started Aug 09 06:54:00 PM PDT 24
Finished Aug 09 06:54:41 PM PDT 24
Peak memory 217048 kb
Host smart-19167581-1a1e-4a6e-b162-99cacc9a67dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056779948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.3056779948
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.2811604376
Short name T54
Test name
Test status
Simulation time 4403299356 ps
CPU time 14.14 seconds
Started Aug 09 06:53:50 PM PDT 24
Finished Aug 09 06:54:04 PM PDT 24
Peak memory 217060 kb
Host smart-b6ccde3e-efeb-49a1-87cb-587de8c891d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811604376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.2811604376
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.35204507
Short name T551
Test name
Test status
Simulation time 393543075 ps
CPU time 4.45 seconds
Started Aug 09 06:54:02 PM PDT 24
Finished Aug 09 06:54:06 PM PDT 24
Peak memory 216824 kb
Host smart-1ce1b44c-f1d3-41da-afe2-d0269aca8c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35204507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.35204507
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.1527352126
Short name T346
Test name
Test status
Simulation time 88479214 ps
CPU time 0.92 seconds
Started Aug 09 06:53:59 PM PDT 24
Finished Aug 09 06:54:00 PM PDT 24
Peak memory 206460 kb
Host smart-39eeb3a0-b906-4243-8183-b3c2f8d58aa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527352126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.1527352126
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.1998011996
Short name T437
Test name
Test status
Simulation time 4004743144 ps
CPU time 10.58 seconds
Started Aug 09 06:54:01 PM PDT 24
Finished Aug 09 06:54:12 PM PDT 24
Peak memory 225268 kb
Host smart-bf1cd3f3-34da-4415-bee3-47f62d88e787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998011996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.1998011996
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.2920964041
Short name T857
Test name
Test status
Simulation time 84118271 ps
CPU time 0.71 seconds
Started Aug 09 06:54:11 PM PDT 24
Finished Aug 09 06:54:12 PM PDT 24
Peak memory 205740 kb
Host smart-913d6d04-7069-4d93-88c8-4f377aa76ec4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920964041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
2920964041
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.4211834424
Short name T530
Test name
Test status
Simulation time 163679583 ps
CPU time 2.22 seconds
Started Aug 09 06:54:10 PM PDT 24
Finished Aug 09 06:54:12 PM PDT 24
Peak memory 224772 kb
Host smart-5300830c-b71c-42cc-afa1-9666a0792345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211834424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.4211834424
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.2844525353
Short name T484
Test name
Test status
Simulation time 43303488 ps
CPU time 0.75 seconds
Started Aug 09 06:54:10 PM PDT 24
Finished Aug 09 06:54:11 PM PDT 24
Peak memory 206028 kb
Host smart-85999933-8c39-4df5-a1a7-79e382535c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844525353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.2844525353
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.4146418653
Short name T818
Test name
Test status
Simulation time 10256108215 ps
CPU time 34.74 seconds
Started Aug 09 06:54:10 PM PDT 24
Finished Aug 09 06:54:45 PM PDT 24
Peak memory 249856 kb
Host smart-fe47ec8c-2156-4f4a-a512-24311f1521f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146418653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.4146418653
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.1988892211
Short name T323
Test name
Test status
Simulation time 19540939566 ps
CPU time 94.79 seconds
Started Aug 09 06:54:11 PM PDT 24
Finished Aug 09 06:55:45 PM PDT 24
Peak memory 254348 kb
Host smart-ecd7dd3a-b305-4ce4-8790-0eef83b59ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988892211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.1988892211
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.497957532
Short name T233
Test name
Test status
Simulation time 20412979457 ps
CPU time 224.48 seconds
Started Aug 09 06:54:10 PM PDT 24
Finished Aug 09 06:57:54 PM PDT 24
Peak memory 255908 kb
Host smart-78b17a05-31c5-422c-bf74-f521e3fe37c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497957532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idle
.497957532
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.4228944061
Short name T360
Test name
Test status
Simulation time 611688799 ps
CPU time 11.32 seconds
Started Aug 09 06:54:10 PM PDT 24
Finished Aug 09 06:54:22 PM PDT 24
Peak memory 234508 kb
Host smart-7dc89fdf-ccfb-4f37-8523-421b364128c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228944061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.4228944061
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.1735295253
Short name T195
Test name
Test status
Simulation time 237689055502 ps
CPU time 223.1 seconds
Started Aug 09 06:54:12 PM PDT 24
Finished Aug 09 06:57:56 PM PDT 24
Peak memory 249964 kb
Host smart-ff6d5900-1102-44b6-b6c9-dd6d30612f29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735295253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmd
s.1735295253
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_intercept.3499091038
Short name T464
Test name
Test status
Simulation time 1715871882 ps
CPU time 6.53 seconds
Started Aug 09 06:54:11 PM PDT 24
Finished Aug 09 06:54:17 PM PDT 24
Peak memory 225156 kb
Host smart-2b530bc8-d6c8-4941-a890-517cfb66375d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499091038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.3499091038
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.3047614816
Short name T675
Test name
Test status
Simulation time 518923462 ps
CPU time 3.16 seconds
Started Aug 09 06:54:11 PM PDT 24
Finished Aug 09 06:54:14 PM PDT 24
Peak memory 225472 kb
Host smart-530f8567-6e1e-465b-8701-fde931c86db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047614816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.3047614816
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.3665665604
Short name T1001
Test name
Test status
Simulation time 44759147 ps
CPU time 1.02 seconds
Started Aug 09 06:54:09 PM PDT 24
Finished Aug 09 06:54:10 PM PDT 24
Peak memory 217140 kb
Host smart-e41bd4ff-cced-4c66-a97c-3e60d52a5eca
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665665604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.spi_device_mem_parity.3665665604
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.1927358892
Short name T518
Test name
Test status
Simulation time 7267828533 ps
CPU time 9.85 seconds
Started Aug 09 06:54:12 PM PDT 24
Finished Aug 09 06:54:22 PM PDT 24
Peak memory 241656 kb
Host smart-3e057a77-40f3-4610-92b0-2ea628a94abc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927358892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.1927358892
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.1632821711
Short name T388
Test name
Test status
Simulation time 719392694 ps
CPU time 5.82 seconds
Started Aug 09 06:54:12 PM PDT 24
Finished Aug 09 06:54:18 PM PDT 24
Peak memory 220856 kb
Host smart-1afab51d-3438-4667-8757-8628bad0d661
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1632821711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.1632821711
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.1962004851
Short name T322
Test name
Test status
Simulation time 5814921422 ps
CPU time 31.63 seconds
Started Aug 09 06:54:09 PM PDT 24
Finished Aug 09 06:54:40 PM PDT 24
Peak memory 220460 kb
Host smart-0d6287f9-4f6f-4c26-b3c3-3fba85fd04ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962004851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.1962004851
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.3233320493
Short name T903
Test name
Test status
Simulation time 6826222294 ps
CPU time 9.88 seconds
Started Aug 09 06:54:09 PM PDT 24
Finished Aug 09 06:54:19 PM PDT 24
Peak memory 217048 kb
Host smart-d03aac8c-3383-4d10-90fe-2b164f484170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233320493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.3233320493
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.3569733015
Short name T711
Test name
Test status
Simulation time 59960965 ps
CPU time 0.68 seconds
Started Aug 09 06:54:10 PM PDT 24
Finished Aug 09 06:54:11 PM PDT 24
Peak memory 206076 kb
Host smart-5afe43ad-2a8c-4143-b124-a0fdfdda78a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569733015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.3569733015
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.1052070341
Short name T944
Test name
Test status
Simulation time 207208291 ps
CPU time 0.98 seconds
Started Aug 09 06:54:08 PM PDT 24
Finished Aug 09 06:54:09 PM PDT 24
Peak memory 206908 kb
Host smart-95e6866d-d552-4cea-9bcb-434a6cf58f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052070341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.1052070341
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.2741454072
Short name T39
Test name
Test status
Simulation time 25464556972 ps
CPU time 41.71 seconds
Started Aug 09 06:54:11 PM PDT 24
Finished Aug 09 06:54:53 PM PDT 24
Peak memory 233532 kb
Host smart-141063be-fbce-4c71-9382-5ca47655417f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741454072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.2741454072
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.3420053288
Short name T813
Test name
Test status
Simulation time 71548195 ps
CPU time 0.71 seconds
Started Aug 09 06:54:21 PM PDT 24
Finished Aug 09 06:54:22 PM PDT 24
Peak memory 206136 kb
Host smart-9aa94dbd-f412-4fa0-af92-ebb3c83afcad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420053288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
3420053288
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.1781514817
Short name T676
Test name
Test status
Simulation time 1633773090 ps
CPU time 8.92 seconds
Started Aug 09 06:54:21 PM PDT 24
Finished Aug 09 06:54:30 PM PDT 24
Peak memory 233404 kb
Host smart-bc27594b-9aa9-467b-904e-a8fe14b54a26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781514817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.1781514817
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.1573814799
Short name T540
Test name
Test status
Simulation time 37696152 ps
CPU time 0.76 seconds
Started Aug 09 06:54:10 PM PDT 24
Finished Aug 09 06:54:11 PM PDT 24
Peak memory 206036 kb
Host smart-dbcf91ab-ddc1-4cb5-9c4d-02587407edc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573814799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.1573814799
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.2653636015
Short name T182
Test name
Test status
Simulation time 57635705270 ps
CPU time 56.9 seconds
Started Aug 09 06:54:20 PM PDT 24
Finished Aug 09 06:55:17 PM PDT 24
Peak memory 241684 kb
Host smart-2a652340-36ba-4661-86ce-a41b9d6fbfe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653636015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.2653636015
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.4051846203
Short name T232
Test name
Test status
Simulation time 11169798841 ps
CPU time 41.87 seconds
Started Aug 09 06:54:20 PM PDT 24
Finished Aug 09 06:55:02 PM PDT 24
Peak memory 249904 kb
Host smart-54ce6afa-da4e-4d20-ad73-5d40a46dfab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051846203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.4051846203
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.2568545825
Short name T427
Test name
Test status
Simulation time 153506227624 ps
CPU time 261.77 seconds
Started Aug 09 06:54:19 PM PDT 24
Finished Aug 09 06:58:41 PM PDT 24
Peak memory 250200 kb
Host smart-1a593b11-bb64-46ab-a667-cf1675acb4dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568545825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.2568545825
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.1846836954
Short name T960
Test name
Test status
Simulation time 7200116095 ps
CPU time 52.29 seconds
Started Aug 09 06:54:18 PM PDT 24
Finished Aug 09 06:55:11 PM PDT 24
Peak memory 251516 kb
Host smart-c8791cac-0180-40eb-b6a2-efbe2067f6f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846836954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmd
s.1846836954
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_intercept.4129145418
Short name T1017
Test name
Test status
Simulation time 408718641 ps
CPU time 3.3 seconds
Started Aug 09 06:54:14 PM PDT 24
Finished Aug 09 06:54:18 PM PDT 24
Peak memory 233404 kb
Host smart-70e60d2c-91f9-4f5c-9ff8-b03300ceacbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129145418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.4129145418
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.2532471722
Short name T688
Test name
Test status
Simulation time 19510780030 ps
CPU time 25.38 seconds
Started Aug 09 06:54:17 PM PDT 24
Finished Aug 09 06:54:43 PM PDT 24
Peak memory 249900 kb
Host smart-765f95ed-9b90-4b6c-b056-c07a6e560a1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532471722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.2532471722
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.710524681
Short name T10
Test name
Test status
Simulation time 25554920 ps
CPU time 1.12 seconds
Started Aug 09 06:54:11 PM PDT 24
Finished Aug 09 06:54:12 PM PDT 24
Peak memory 217192 kb
Host smart-7023cf46-3cc5-44b9-80ea-48619da6061c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710524681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.spi_device_mem_parity.710524681
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.2343352602
Short name T760
Test name
Test status
Simulation time 101761136 ps
CPU time 2.26 seconds
Started Aug 09 06:54:12 PM PDT 24
Finished Aug 09 06:54:14 PM PDT 24
Peak memory 224332 kb
Host smart-39d6b9d3-fee1-4225-9887-ad03e13877d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343352602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.2343352602
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.1167590760
Short name T490
Test name
Test status
Simulation time 144809084 ps
CPU time 2.31 seconds
Started Aug 09 06:54:12 PM PDT 24
Finished Aug 09 06:54:14 PM PDT 24
Peak memory 225212 kb
Host smart-27d2730b-0b77-48ef-b817-17bf2075c47f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167590760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.1167590760
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.2968023530
Short name T535
Test name
Test status
Simulation time 885132512 ps
CPU time 4.3 seconds
Started Aug 09 06:54:23 PM PDT 24
Finished Aug 09 06:54:28 PM PDT 24
Peak memory 219824 kb
Host smart-b4ee3dfc-b103-49b6-bb5d-3d8d0f2c0ac6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2968023530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.2968023530
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.3177970910
Short name T148
Test name
Test status
Simulation time 13878426889 ps
CPU time 13.01 seconds
Started Aug 09 06:54:17 PM PDT 24
Finished Aug 09 06:54:31 PM PDT 24
Peak memory 225296 kb
Host smart-d21bf565-73be-4266-9f77-49a70848de47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177970910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.3177970910
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.1031364434
Short name T587
Test name
Test status
Simulation time 7888615951 ps
CPU time 15.87 seconds
Started Aug 09 06:54:11 PM PDT 24
Finished Aug 09 06:54:27 PM PDT 24
Peak memory 216944 kb
Host smart-f2efdac4-fbf9-4940-955d-46233a63c000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031364434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.1031364434
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.1718002926
Short name T512
Test name
Test status
Simulation time 476134573 ps
CPU time 2.12 seconds
Started Aug 09 06:54:15 PM PDT 24
Finished Aug 09 06:54:17 PM PDT 24
Peak memory 216924 kb
Host smart-473c124a-9933-44f4-8370-3efbd85e9701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718002926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.1718002926
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.3482606987
Short name T875
Test name
Test status
Simulation time 21991763 ps
CPU time 0.66 seconds
Started Aug 09 06:54:13 PM PDT 24
Finished Aug 09 06:54:14 PM PDT 24
Peak memory 206100 kb
Host smart-55048e6f-a24b-4f94-a7f7-3e802ca144c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482606987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.3482606987
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.2236553216
Short name T441
Test name
Test status
Simulation time 176252305 ps
CPU time 0.9 seconds
Started Aug 09 06:54:15 PM PDT 24
Finished Aug 09 06:54:16 PM PDT 24
Peak memory 206512 kb
Host smart-a7713373-4c49-466a-864d-be8f848b3638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236553216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.2236553216
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.2957364292
Short name T968
Test name
Test status
Simulation time 24035768673 ps
CPU time 18.9 seconds
Started Aug 09 06:54:20 PM PDT 24
Finished Aug 09 06:54:39 PM PDT 24
Peak memory 236056 kb
Host smart-4126afc3-6d0a-43f9-9243-52f264d4a663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957364292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.2957364292
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.1627492938
Short name T445
Test name
Test status
Simulation time 73093080 ps
CPU time 0.74 seconds
Started Aug 09 06:54:22 PM PDT 24
Finished Aug 09 06:54:23 PM PDT 24
Peak memory 205872 kb
Host smart-70f3b8d4-6f47-4289-9dfe-7100d0a5bcb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627492938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
1627492938
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.1147650183
Short name T669
Test name
Test status
Simulation time 34542255 ps
CPU time 2.57 seconds
Started Aug 09 06:54:23 PM PDT 24
Finished Aug 09 06:54:25 PM PDT 24
Peak memory 233396 kb
Host smart-b2a932d0-58b2-49af-ae8c-b1eb56489b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147650183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.1147650183
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.3612774679
Short name T732
Test name
Test status
Simulation time 12164415 ps
CPU time 0.72 seconds
Started Aug 09 06:54:18 PM PDT 24
Finished Aug 09 06:54:19 PM PDT 24
Peak memory 206028 kb
Host smart-d66830c8-6fa9-4481-ae33-b76dbe42f3b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612774679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.3612774679
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.826890379
Short name T386
Test name
Test status
Simulation time 6933575735 ps
CPU time 73.56 seconds
Started Aug 09 06:54:22 PM PDT 24
Finished Aug 09 06:55:36 PM PDT 24
Peak memory 249948 kb
Host smart-ea6a52bd-0555-4d14-b149-bab62929ae58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826890379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.826890379
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.2252099477
Short name T457
Test name
Test status
Simulation time 15812439688 ps
CPU time 82.06 seconds
Started Aug 09 06:54:21 PM PDT 24
Finished Aug 09 06:55:43 PM PDT 24
Peak memory 250616 kb
Host smart-cb9fb6e4-c56c-48ea-b14b-b89d2298e57a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252099477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.2252099477
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.266042784
Short name T799
Test name
Test status
Simulation time 1196860800 ps
CPU time 6.95 seconds
Started Aug 09 06:54:23 PM PDT 24
Finished Aug 09 06:54:30 PM PDT 24
Peak memory 235424 kb
Host smart-0e1beb75-54d6-4536-be39-a669eaede4a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266042784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.266042784
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.3472162229
Short name T79
Test name
Test status
Simulation time 26919908061 ps
CPU time 104.62 seconds
Started Aug 09 06:54:22 PM PDT 24
Finished Aug 09 06:56:07 PM PDT 24
Peak memory 257172 kb
Host smart-185691ee-d4f5-4ca9-8875-8a25f1466aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472162229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmd
s.3472162229
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/13.spi_device_intercept.1719496541
Short name T837
Test name
Test status
Simulation time 285161512 ps
CPU time 5.39 seconds
Started Aug 09 06:54:19 PM PDT 24
Finished Aug 09 06:54:25 PM PDT 24
Peak memory 233476 kb
Host smart-2dc95065-dff3-48cd-a044-c8cfe38b4bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719496541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.1719496541
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.2821493723
Short name T240
Test name
Test status
Simulation time 40947251 ps
CPU time 2.61 seconds
Started Aug 09 06:54:19 PM PDT 24
Finished Aug 09 06:54:22 PM PDT 24
Peak memory 233416 kb
Host smart-b2858d9f-a9e2-4977-95c3-4ba75fa2f406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821493723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.2821493723
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.3068924789
Short name T31
Test name
Test status
Simulation time 59233384 ps
CPU time 1.05 seconds
Started Aug 09 06:54:21 PM PDT 24
Finished Aug 09 06:54:23 PM PDT 24
Peak memory 217156 kb
Host smart-7baa7aac-d940-4b85-9752-799549d946e0
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068924789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.spi_device_mem_parity.3068924789
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.1651306253
Short name T988
Test name
Test status
Simulation time 436636945 ps
CPU time 4.72 seconds
Started Aug 09 06:54:19 PM PDT 24
Finished Aug 09 06:54:24 PM PDT 24
Peak memory 233472 kb
Host smart-3a13e1e0-c26d-4888-a7f2-1905f86435e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651306253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.1651306253
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.2837541498
Short name T823
Test name
Test status
Simulation time 469128851 ps
CPU time 8.08 seconds
Started Aug 09 06:54:22 PM PDT 24
Finished Aug 09 06:54:31 PM PDT 24
Peak memory 241420 kb
Host smart-a6ed1850-f295-4379-a614-04acf778b56d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837541498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.2837541498
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.2161868040
Short name T622
Test name
Test status
Simulation time 1839988125 ps
CPU time 16.01 seconds
Started Aug 09 06:54:19 PM PDT 24
Finished Aug 09 06:54:35 PM PDT 24
Peak memory 222740 kb
Host smart-863f15af-de1f-428e-844e-0761362b98eb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2161868040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.2161868040
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.4099028082
Short name T150
Test name
Test status
Simulation time 95088254095 ps
CPU time 454.87 seconds
Started Aug 09 06:54:22 PM PDT 24
Finished Aug 09 07:01:57 PM PDT 24
Peak memory 266368 kb
Host smart-0662a94e-4af3-4cda-9a11-a9685913dc39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099028082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.4099028082
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.2301862586
Short name T915
Test name
Test status
Simulation time 12374142369 ps
CPU time 33.49 seconds
Started Aug 09 06:54:20 PM PDT 24
Finished Aug 09 06:54:54 PM PDT 24
Peak memory 216964 kb
Host smart-3208a5ff-1360-4e24-b258-512d52985388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301862586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.2301862586
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.2211496013
Short name T727
Test name
Test status
Simulation time 26778366667 ps
CPU time 17.5 seconds
Started Aug 09 06:54:22 PM PDT 24
Finished Aug 09 06:54:40 PM PDT 24
Peak memory 218144 kb
Host smart-f5ac0dae-0cbd-44a8-9926-ade49341a119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211496013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.2211496013
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.3621954913
Short name T519
Test name
Test status
Simulation time 143558347 ps
CPU time 1.15 seconds
Started Aug 09 06:54:23 PM PDT 24
Finished Aug 09 06:54:24 PM PDT 24
Peak memory 208504 kb
Host smart-bca835f0-98b5-4023-b83a-4bc7271d3276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621954913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.3621954913
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.3739124243
Short name T687
Test name
Test status
Simulation time 112490544 ps
CPU time 0.79 seconds
Started Aug 09 06:54:19 PM PDT 24
Finished Aug 09 06:54:20 PM PDT 24
Peak memory 206520 kb
Host smart-f1c7072a-f257-436c-8770-6e700f888c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739124243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.3739124243
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.2292931919
Short name T439
Test name
Test status
Simulation time 5916773169 ps
CPU time 18.43 seconds
Started Aug 09 06:54:22 PM PDT 24
Finished Aug 09 06:54:40 PM PDT 24
Peak memory 233484 kb
Host smart-3ced5656-47d8-4dc0-84c4-3d237d2eb8dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292931919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.2292931919
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.1530883178
Short name T61
Test name
Test status
Simulation time 13255431 ps
CPU time 0.72 seconds
Started Aug 09 06:54:31 PM PDT 24
Finished Aug 09 06:54:31 PM PDT 24
Peak memory 205280 kb
Host smart-46dc9dd7-2ad8-4fd8-b798-2b6eb958e7a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530883178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
1530883178
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.3364971120
Short name T836
Test name
Test status
Simulation time 846609858 ps
CPU time 4.53 seconds
Started Aug 09 06:54:30 PM PDT 24
Finished Aug 09 06:54:34 PM PDT 24
Peak memory 233292 kb
Host smart-0bdd3268-9d85-4b43-9aea-540ba83cb0d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364971120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.3364971120
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.1655481971
Short name T856
Test name
Test status
Simulation time 19236374 ps
CPU time 0.81 seconds
Started Aug 09 06:54:23 PM PDT 24
Finished Aug 09 06:54:23 PM PDT 24
Peak memory 207052 kb
Host smart-8b627673-5713-43a7-b7a8-a3e7fd777759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655481971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.1655481971
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.640227386
Short name T508
Test name
Test status
Simulation time 6977628340 ps
CPU time 111.79 seconds
Started Aug 09 06:54:29 PM PDT 24
Finished Aug 09 06:56:21 PM PDT 24
Peak memory 256252 kb
Host smart-70c88c54-9f27-48f0-afc8-706227613bc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640227386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.640227386
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.2563527292
Short name T734
Test name
Test status
Simulation time 6238809286 ps
CPU time 40.1 seconds
Started Aug 09 06:54:24 PM PDT 24
Finished Aug 09 06:55:05 PM PDT 24
Peak memory 235444 kb
Host smart-85f1193c-f509-4e7a-b223-802bf7cb6e3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563527292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.2563527292
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.1770663295
Short name T1024
Test name
Test status
Simulation time 356148423 ps
CPU time 6.35 seconds
Started Aug 09 06:54:26 PM PDT 24
Finished Aug 09 06:54:33 PM PDT 24
Peak memory 234496 kb
Host smart-09672335-9d12-444e-b4f4-18f5aee653e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770663295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.1770663295
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.3700965240
Short name T159
Test name
Test status
Simulation time 86556757150 ps
CPU time 145.57 seconds
Started Aug 09 06:54:27 PM PDT 24
Finished Aug 09 06:56:52 PM PDT 24
Peak memory 241748 kb
Host smart-08fd4b03-7289-4489-bfd9-e7b04e387e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700965240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmd
s.3700965240
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/14.spi_device_intercept.3700820123
Short name T697
Test name
Test status
Simulation time 896581036 ps
CPU time 2.37 seconds
Started Aug 09 06:54:30 PM PDT 24
Finished Aug 09 06:54:32 PM PDT 24
Peak memory 224432 kb
Host smart-ded6c659-4dc8-45c9-873b-1c206e50ad31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700820123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.3700820123
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.708513537
Short name T517
Test name
Test status
Simulation time 4237585397 ps
CPU time 31.2 seconds
Started Aug 09 06:54:26 PM PDT 24
Finished Aug 09 06:54:57 PM PDT 24
Peak memory 225324 kb
Host smart-e0ae77ce-9bc3-44b9-a2b4-d97540aacc46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708513537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.708513537
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.2333018985
Short name T467
Test name
Test status
Simulation time 45119919 ps
CPU time 1.02 seconds
Started Aug 09 06:54:29 PM PDT 24
Finished Aug 09 06:54:30 PM PDT 24
Peak memory 217204 kb
Host smart-7fb7abdd-a997-43ca-b913-c4dc0c8936c6
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333018985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.spi_device_mem_parity.2333018985
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.1601754239
Short name T536
Test name
Test status
Simulation time 125652875 ps
CPU time 2.5 seconds
Started Aug 09 06:54:29 PM PDT 24
Finished Aug 09 06:54:31 PM PDT 24
Peak memory 225256 kb
Host smart-0e2d91a5-6379-498a-a0e9-0da86973d64a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601754239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.1601754239
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.1892892671
Short name T595
Test name
Test status
Simulation time 233667807 ps
CPU time 2.59 seconds
Started Aug 09 06:54:28 PM PDT 24
Finished Aug 09 06:54:31 PM PDT 24
Peak memory 225248 kb
Host smart-79ef9096-e35e-4f0d-88fe-2b02efeb5103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892892671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.1892892671
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.840801896
Short name T424
Test name
Test status
Simulation time 1111666488 ps
CPU time 4.12 seconds
Started Aug 09 06:54:26 PM PDT 24
Finished Aug 09 06:54:30 PM PDT 24
Peak memory 219584 kb
Host smart-8829080e-3583-41fa-a5b4-bf677fc6a98b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=840801896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dire
ct.840801896
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.2024535337
Short name T860
Test name
Test status
Simulation time 2555406041 ps
CPU time 14.04 seconds
Started Aug 09 06:54:30 PM PDT 24
Finished Aug 09 06:54:45 PM PDT 24
Peak memory 217364 kb
Host smart-1f4534eb-a7a7-4b86-b1cf-f281540c6c4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024535337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.2024535337
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.1697681594
Short name T772
Test name
Test status
Simulation time 240716050 ps
CPU time 2.1 seconds
Started Aug 09 06:54:26 PM PDT 24
Finished Aug 09 06:54:28 PM PDT 24
Peak memory 216732 kb
Host smart-242eeb75-fa4f-4a93-9b93-88b4ed1c308c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697681594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.1697681594
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.1483601911
Short name T880
Test name
Test status
Simulation time 54639295 ps
CPU time 1.09 seconds
Started Aug 09 06:54:25 PM PDT 24
Finished Aug 09 06:54:26 PM PDT 24
Peak memory 208244 kb
Host smart-aafdf683-d24f-43c6-a048-01d972f4994f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483601911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.1483601911
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.3968401854
Short name T352
Test name
Test status
Simulation time 47678873 ps
CPU time 0.73 seconds
Started Aug 09 06:54:29 PM PDT 24
Finished Aug 09 06:54:30 PM PDT 24
Peak memory 206576 kb
Host smart-70f53b6c-2827-4c81-ba2c-b243e584d028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968401854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.3968401854
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.2295979547
Short name T228
Test name
Test status
Simulation time 65915021 ps
CPU time 2.66 seconds
Started Aug 09 06:54:30 PM PDT 24
Finished Aug 09 06:54:33 PM PDT 24
Peak memory 233472 kb
Host smart-f201c91a-f83c-4ced-a069-2f82da4de1a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295979547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.2295979547
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.3375205161
Short name T995
Test name
Test status
Simulation time 42308808 ps
CPU time 0.68 seconds
Started Aug 09 06:54:44 PM PDT 24
Finished Aug 09 06:54:45 PM PDT 24
Peak memory 205172 kb
Host smart-e984187c-62d9-41ba-bf3d-c6087464a7ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375205161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
3375205161
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.2154889407
Short name T765
Test name
Test status
Simulation time 294765293 ps
CPU time 3.81 seconds
Started Aug 09 06:54:35 PM PDT 24
Finished Aug 09 06:54:39 PM PDT 24
Peak memory 233448 kb
Host smart-874ed6ef-83e0-41ff-a986-7d0995f1080e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154889407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.2154889407
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.417959894
Short name T728
Test name
Test status
Simulation time 132871863 ps
CPU time 0.74 seconds
Started Aug 09 06:54:28 PM PDT 24
Finished Aug 09 06:54:28 PM PDT 24
Peak memory 207356 kb
Host smart-73eecf18-9d0c-4411-8058-04243bb774ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417959894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.417959894
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.3714404811
Short name T1008
Test name
Test status
Simulation time 39713979725 ps
CPU time 113.65 seconds
Started Aug 09 06:54:33 PM PDT 24
Finished Aug 09 06:56:27 PM PDT 24
Peak memory 270712 kb
Host smart-a6d2697e-9475-4abe-a877-0429365a0535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714404811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.3714404811
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.483318042
Short name T702
Test name
Test status
Simulation time 48902359450 ps
CPU time 161.57 seconds
Started Aug 09 06:54:42 PM PDT 24
Finished Aug 09 06:57:24 PM PDT 24
Peak memory 255636 kb
Host smart-a79abb1f-0381-4d83-b831-76231be36938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483318042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idle
.483318042
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.243283868
Short name T582
Test name
Test status
Simulation time 6816206575 ps
CPU time 38.48 seconds
Started Aug 09 06:54:35 PM PDT 24
Finished Aug 09 06:55:14 PM PDT 24
Peak memory 239392 kb
Host smart-a29a9fbd-e20c-477e-b8bc-c1eeddda90aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243283868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmds
.243283868
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/15.spi_device_intercept.1540621082
Short name T924
Test name
Test status
Simulation time 3034779100 ps
CPU time 36.62 seconds
Started Aug 09 06:54:34 PM PDT 24
Finished Aug 09 06:55:11 PM PDT 24
Peak memory 225288 kb
Host smart-1cdd5e65-2bd4-4faf-9069-15e282066a4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540621082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.1540621082
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.1739406137
Short name T830
Test name
Test status
Simulation time 3123771662 ps
CPU time 34.84 seconds
Started Aug 09 06:54:36 PM PDT 24
Finished Aug 09 06:55:11 PM PDT 24
Peak memory 233372 kb
Host smart-5f678942-22c0-4422-b846-cc5b2f420d53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739406137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.1739406137
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.1736789868
Short name T887
Test name
Test status
Simulation time 60791761 ps
CPU time 1.16 seconds
Started Aug 09 06:54:38 PM PDT 24
Finished Aug 09 06:54:39 PM PDT 24
Peak memory 217196 kb
Host smart-0b655083-7899-4802-bda2-b1b9ba311ddd
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736789868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.spi_device_mem_parity.1736789868
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.1394444072
Short name T1020
Test name
Test status
Simulation time 391045741 ps
CPU time 5.59 seconds
Started Aug 09 06:54:38 PM PDT 24
Finished Aug 09 06:54:44 PM PDT 24
Peak memory 233416 kb
Host smart-c35a51ce-24d4-4f09-9a4c-7de6f760d1cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394444072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.1394444072
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.1062156986
Short name T943
Test name
Test status
Simulation time 50761244 ps
CPU time 2.13 seconds
Started Aug 09 06:54:33 PM PDT 24
Finished Aug 09 06:54:36 PM PDT 24
Peak memory 224580 kb
Host smart-f27f6ec7-c499-413b-b72e-af11aeb7dfe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062156986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.1062156986
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.46147814
Short name T15
Test name
Test status
Simulation time 792274503 ps
CPU time 4.65 seconds
Started Aug 09 06:54:32 PM PDT 24
Finished Aug 09 06:54:37 PM PDT 24
Peak memory 223560 kb
Host smart-491a7ddd-def7-4930-9c1d-3ec0ddf89c3d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=46147814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_direc
t.46147814
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.1834303307
Short name T179
Test name
Test status
Simulation time 59959417300 ps
CPU time 481.13 seconds
Started Aug 09 06:54:43 PM PDT 24
Finished Aug 09 07:02:44 PM PDT 24
Peak memory 257172 kb
Host smart-7cb8a6a0-900e-47c8-8b85-d0718ff494dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834303307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.1834303307
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.327621838
Short name T843
Test name
Test status
Simulation time 1725980033 ps
CPU time 13.23 seconds
Started Aug 09 06:54:34 PM PDT 24
Finished Aug 09 06:54:47 PM PDT 24
Peak memory 216892 kb
Host smart-e9213fb6-0111-4c1c-afed-a96f65e0f3d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327621838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.327621838
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.2730216564
Short name T949
Test name
Test status
Simulation time 3469678807 ps
CPU time 5.22 seconds
Started Aug 09 06:54:34 PM PDT 24
Finished Aug 09 06:54:39 PM PDT 24
Peak memory 217012 kb
Host smart-8b5a42b2-cda4-4622-85b1-6865e31eaa94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730216564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.2730216564
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.3123649984
Short name T493
Test name
Test status
Simulation time 153673472 ps
CPU time 2.67 seconds
Started Aug 09 06:54:34 PM PDT 24
Finished Aug 09 06:54:37 PM PDT 24
Peak memory 216964 kb
Host smart-3ff43db1-459b-4708-be34-b0a1f040f8dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123649984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.3123649984
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.3176966992
Short name T1014
Test name
Test status
Simulation time 19699470 ps
CPU time 0.75 seconds
Started Aug 09 06:54:33 PM PDT 24
Finished Aug 09 06:54:34 PM PDT 24
Peak memory 206536 kb
Host smart-477412ad-66c3-4674-b32f-b13db2c5a24f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176966992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.3176966992
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.3398207835
Short name T255
Test name
Test status
Simulation time 208604171 ps
CPU time 2.55 seconds
Started Aug 09 06:54:34 PM PDT 24
Finished Aug 09 06:54:36 PM PDT 24
Peak memory 225220 kb
Host smart-51c81df4-3d5a-441a-8e4f-d719129dc9b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398207835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.3398207835
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.1229039210
Short name T614
Test name
Test status
Simulation time 71363402 ps
CPU time 0.71 seconds
Started Aug 09 06:54:50 PM PDT 24
Finished Aug 09 06:54:51 PM PDT 24
Peak memory 205856 kb
Host smart-c42c2729-7a05-4423-b480-d833b6e31892
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229039210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
1229039210
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.3897693313
Short name T959
Test name
Test status
Simulation time 55973747 ps
CPU time 1.98 seconds
Started Aug 09 06:54:42 PM PDT 24
Finished Aug 09 06:54:44 PM PDT 24
Peak memory 223624 kb
Host smart-a6ab3fac-6f92-44a4-b949-3bf6431345b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897693313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.3897693313
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.2481229320
Short name T57
Test name
Test status
Simulation time 54291322 ps
CPU time 0.78 seconds
Started Aug 09 06:54:44 PM PDT 24
Finished Aug 09 06:54:45 PM PDT 24
Peak memory 205972 kb
Host smart-f1c36d65-4f77-4ee6-9487-d7bb2ee261c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481229320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.2481229320
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.1416198910
Short name T853
Test name
Test status
Simulation time 104658907942 ps
CPU time 218.58 seconds
Started Aug 09 06:54:52 PM PDT 24
Finished Aug 09 06:58:30 PM PDT 24
Peak memory 251832 kb
Host smart-bdb48555-e907-4768-a979-db0bc6f9724e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416198910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.1416198910
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.177760734
Short name T714
Test name
Test status
Simulation time 27591106973 ps
CPU time 292.59 seconds
Started Aug 09 06:54:50 PM PDT 24
Finished Aug 09 06:59:42 PM PDT 24
Peak memory 255784 kb
Host smart-7d21d360-17ba-4a8e-82e4-a6902a6e36a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177760734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idle
.177760734
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.2891821864
Short name T794
Test name
Test status
Simulation time 305997298 ps
CPU time 2.48 seconds
Started Aug 09 06:54:43 PM PDT 24
Finished Aug 09 06:54:45 PM PDT 24
Peak memory 225164 kb
Host smart-fed55b66-3e6d-4a0c-bc53-960924d69250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891821864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.2891821864
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_intercept.1715950875
Short name T4
Test name
Test status
Simulation time 91964994 ps
CPU time 3.55 seconds
Started Aug 09 06:54:43 PM PDT 24
Finished Aug 09 06:54:47 PM PDT 24
Peak memory 233448 kb
Host smart-d97ab063-9b9b-4ad0-b28d-e661fa91f967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715950875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.1715950875
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.4184474115
Short name T942
Test name
Test status
Simulation time 772584091 ps
CPU time 2.92 seconds
Started Aug 09 06:54:40 PM PDT 24
Finished Aug 09 06:54:43 PM PDT 24
Peak memory 233492 kb
Host smart-2db69af3-983f-49e9-80b4-cea331688426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184474115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.4184474115
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.3273368673
Short name T538
Test name
Test status
Simulation time 33203537 ps
CPU time 1.11 seconds
Started Aug 09 06:54:42 PM PDT 24
Finished Aug 09 06:54:43 PM PDT 24
Peak memory 217140 kb
Host smart-a391ea5b-5eb8-4f2b-9cc7-f731a9713fa6
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273368673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.spi_device_mem_parity.3273368673
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.2265480245
Short name T757
Test name
Test status
Simulation time 373567797 ps
CPU time 3.57 seconds
Started Aug 09 06:54:42 PM PDT 24
Finished Aug 09 06:54:46 PM PDT 24
Peak memory 225204 kb
Host smart-1dd1227c-2718-455c-bbf1-d4e7701cfa78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265480245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.2265480245
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.403583956
Short name T999
Test name
Test status
Simulation time 14017517746 ps
CPU time 21.72 seconds
Started Aug 09 06:54:43 PM PDT 24
Finished Aug 09 06:55:05 PM PDT 24
Peak memory 233500 kb
Host smart-43c1d388-5af4-4682-b286-72faa330f10b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403583956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.403583956
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.739591513
Short name T139
Test name
Test status
Simulation time 299216567 ps
CPU time 4.83 seconds
Started Aug 09 06:54:51 PM PDT 24
Finished Aug 09 06:54:56 PM PDT 24
Peak memory 223696 kb
Host smart-66380ffd-e0fd-4783-955f-5258bbbb6e29
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=739591513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dire
ct.739591513
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.771463077
Short name T1004
Test name
Test status
Simulation time 63437471 ps
CPU time 1.13 seconds
Started Aug 09 06:54:50 PM PDT 24
Finished Aug 09 06:54:51 PM PDT 24
Peak memory 208084 kb
Host smart-717ff5fb-31e1-420e-91f3-996b699d4d88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771463077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stres
s_all.771463077
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.2171822626
Short name T601
Test name
Test status
Simulation time 241346236 ps
CPU time 2.77 seconds
Started Aug 09 06:54:43 PM PDT 24
Finished Aug 09 06:54:46 PM PDT 24
Peak memory 217296 kb
Host smart-d7c7b66b-04f1-4696-a002-b28eec6fe54e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171822626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.2171822626
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.163493833
Short name T820
Test name
Test status
Simulation time 1918588994 ps
CPU time 8.26 seconds
Started Aug 09 06:54:43 PM PDT 24
Finished Aug 09 06:54:51 PM PDT 24
Peak memory 217040 kb
Host smart-82aefa27-04aa-411f-b6ac-ece1ccdfb7c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163493833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.163493833
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.2962493463
Short name T583
Test name
Test status
Simulation time 1001507311 ps
CPU time 3.36 seconds
Started Aug 09 06:54:43 PM PDT 24
Finished Aug 09 06:54:47 PM PDT 24
Peak memory 208820 kb
Host smart-f6278324-bdcb-461b-8fd1-ef841e163dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962493463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.2962493463
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.2333299191
Short name T391
Test name
Test status
Simulation time 456543021 ps
CPU time 1.06 seconds
Started Aug 09 06:54:43 PM PDT 24
Finished Aug 09 06:54:44 PM PDT 24
Peak memory 207580 kb
Host smart-abcfcead-91ff-45aa-b413-a1da177a2afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333299191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.2333299191
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.269852239
Short name T646
Test name
Test status
Simulation time 298878148 ps
CPU time 3.12 seconds
Started Aug 09 06:54:44 PM PDT 24
Finished Aug 09 06:54:47 PM PDT 24
Peak memory 233312 kb
Host smart-3da20597-88f9-4a37-a0a1-a3a204d7d2fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269852239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.269852239
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.1601653082
Short name T641
Test name
Test status
Simulation time 20449052 ps
CPU time 0.75 seconds
Started Aug 09 06:55:04 PM PDT 24
Finished Aug 09 06:55:05 PM PDT 24
Peak memory 205232 kb
Host smart-ae062770-ebd6-4a12-abc6-1d1166d53f4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601653082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
1601653082
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.2269835903
Short name T505
Test name
Test status
Simulation time 131079502 ps
CPU time 2.45 seconds
Started Aug 09 06:54:50 PM PDT 24
Finished Aug 09 06:54:52 PM PDT 24
Peak memory 232988 kb
Host smart-62a2e078-a1b0-46eb-92f1-7781744757b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269835903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.2269835903
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.1203834059
Short name T459
Test name
Test status
Simulation time 28510672 ps
CPU time 0.77 seconds
Started Aug 09 06:54:50 PM PDT 24
Finished Aug 09 06:54:51 PM PDT 24
Peak memory 207032 kb
Host smart-93d82f5e-7c5d-4802-8346-c289c1dd7315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203834059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.1203834059
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.4107710632
Short name T1035
Test name
Test status
Simulation time 166360911374 ps
CPU time 108.75 seconds
Started Aug 09 06:54:49 PM PDT 24
Finished Aug 09 06:56:38 PM PDT 24
Peak memory 250032 kb
Host smart-c8b1323d-6ade-4225-8aa8-4f2a2f9ac127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107710632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.4107710632
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.3090056919
Short name T287
Test name
Test status
Simulation time 4347238161 ps
CPU time 51.22 seconds
Started Aug 09 06:54:52 PM PDT 24
Finished Aug 09 06:55:43 PM PDT 24
Peak memory 253852 kb
Host smart-080dcba6-f8c0-4539-a858-64bd93c44b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090056919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.3090056919
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.2385819663
Short name T207
Test name
Test status
Simulation time 12593474400 ps
CPU time 172.25 seconds
Started Aug 09 06:54:49 PM PDT 24
Finished Aug 09 06:57:42 PM PDT 24
Peak memory 273540 kb
Host smart-88768e93-250a-4934-91e1-d5d180a37b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385819663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.2385819663
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.2880777791
Short name T313
Test name
Test status
Simulation time 6486770189 ps
CPU time 61.04 seconds
Started Aug 09 06:54:51 PM PDT 24
Finished Aug 09 06:55:52 PM PDT 24
Peak memory 235932 kb
Host smart-371d02df-1aa7-436f-8d0a-152d0f77b3d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880777791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.2880777791
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_intercept.3168509170
Short name T157
Test name
Test status
Simulation time 1579662525 ps
CPU time 6.54 seconds
Started Aug 09 06:54:49 PM PDT 24
Finished Aug 09 06:54:56 PM PDT 24
Peak memory 225256 kb
Host smart-71154edc-8a4e-489e-9db9-a222448a2e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168509170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.3168509170
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.3544410522
Short name T779
Test name
Test status
Simulation time 20655169580 ps
CPU time 53.69 seconds
Started Aug 09 06:54:49 PM PDT 24
Finished Aug 09 06:55:42 PM PDT 24
Peak memory 234204 kb
Host smart-081ef119-fe84-436a-b431-ad8a4cadc27f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544410522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.3544410522
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.1673225367
Short name T682
Test name
Test status
Simulation time 171696300 ps
CPU time 1 seconds
Started Aug 09 06:54:51 PM PDT 24
Finished Aug 09 06:54:52 PM PDT 24
Peak memory 218492 kb
Host smart-87815655-3260-4cff-89a3-e84588f14987
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673225367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.spi_device_mem_parity.1673225367
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.3467401972
Short name T486
Test name
Test status
Simulation time 7441347552 ps
CPU time 14.12 seconds
Started Aug 09 06:54:51 PM PDT 24
Finished Aug 09 06:55:05 PM PDT 24
Peak memory 249340 kb
Host smart-dacdc600-e8d1-4d31-9ec5-31ab281b77c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467401972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.3467401972
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.3243303691
Short name T428
Test name
Test status
Simulation time 43740542359 ps
CPU time 22.18 seconds
Started Aug 09 06:54:49 PM PDT 24
Finished Aug 09 06:55:11 PM PDT 24
Peak memory 241100 kb
Host smart-191d92ca-5e33-4f49-89d4-8b764ba53259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243303691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.3243303691
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.2703616395
Short name T699
Test name
Test status
Simulation time 1005560042 ps
CPU time 15.66 seconds
Started Aug 09 06:54:50 PM PDT 24
Finished Aug 09 06:55:06 PM PDT 24
Peak memory 219472 kb
Host smart-3ccdc9e2-0de9-4669-bfbc-0e1f97895d67
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2703616395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.2703616395
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.1141923392
Short name T970
Test name
Test status
Simulation time 32948328208 ps
CPU time 237.83 seconds
Started Aug 09 06:55:02 PM PDT 24
Finished Aug 09 06:59:00 PM PDT 24
Peak memory 255012 kb
Host smart-8b9baaba-766c-42ef-8351-62984b1c555c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141923392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.1141923392
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.427876480
Short name T321
Test name
Test status
Simulation time 36511216788 ps
CPU time 42.13 seconds
Started Aug 09 06:54:49 PM PDT 24
Finished Aug 09 06:55:31 PM PDT 24
Peak memory 217016 kb
Host smart-4a77964d-2a4f-49cc-b818-6fe1c20094f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427876480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.427876480
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.3289781599
Short name T350
Test name
Test status
Simulation time 1551567333 ps
CPU time 6.21 seconds
Started Aug 09 06:54:50 PM PDT 24
Finished Aug 09 06:54:56 PM PDT 24
Peak memory 216900 kb
Host smart-229e5239-7579-414c-b815-7951d4f51895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289781599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.3289781599
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.448396531
Short name T629
Test name
Test status
Simulation time 71131187 ps
CPU time 1.11 seconds
Started Aug 09 06:54:51 PM PDT 24
Finished Aug 09 06:54:52 PM PDT 24
Peak memory 216764 kb
Host smart-29d70501-9d38-4cbb-8183-195298544e05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448396531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.448396531
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.1829562015
Short name T639
Test name
Test status
Simulation time 159582431 ps
CPU time 0.86 seconds
Started Aug 09 06:54:52 PM PDT 24
Finished Aug 09 06:54:53 PM PDT 24
Peak memory 206572 kb
Host smart-710f41dd-e664-4c94-9e31-3b6987d973b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829562015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.1829562015
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.3193570693
Short name T271
Test name
Test status
Simulation time 2125318448 ps
CPU time 5.7 seconds
Started Aug 09 06:54:50 PM PDT 24
Finished Aug 09 06:54:56 PM PDT 24
Peak memory 225164 kb
Host smart-7e92d10e-e810-4bf0-a198-64d7f8bc73e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193570693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.3193570693
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.204320255
Short name T764
Test name
Test status
Simulation time 19922622 ps
CPU time 0.7 seconds
Started Aug 09 06:55:12 PM PDT 24
Finished Aug 09 06:55:13 PM PDT 24
Peak memory 205288 kb
Host smart-23cad789-b22e-46d6-8e02-b52bc90a6fec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204320255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.204320255
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.698907874
Short name T828
Test name
Test status
Simulation time 1148066740 ps
CPU time 5.52 seconds
Started Aug 09 06:55:02 PM PDT 24
Finished Aug 09 06:55:07 PM PDT 24
Peak memory 233420 kb
Host smart-b8237a7a-0db3-442e-816b-46e5c8de135f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698907874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.698907874
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.1112906957
Short name T998
Test name
Test status
Simulation time 55561207 ps
CPU time 0.81 seconds
Started Aug 09 06:55:02 PM PDT 24
Finished Aug 09 06:55:03 PM PDT 24
Peak memory 207052 kb
Host smart-c51c942d-2d22-42ca-a8eb-1a1aaea771a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112906957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.1112906957
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.2929855585
Short name T877
Test name
Test status
Simulation time 292784666 ps
CPU time 0.97 seconds
Started Aug 09 06:55:04 PM PDT 24
Finished Aug 09 06:55:06 PM PDT 24
Peak memory 216680 kb
Host smart-0cec9e74-816e-4565-a9b5-8390189b0f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929855585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.2929855585
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.1403353342
Short name T609
Test name
Test status
Simulation time 108986299215 ps
CPU time 259.17 seconds
Started Aug 09 06:55:03 PM PDT 24
Finished Aug 09 06:59:22 PM PDT 24
Peak memory 250968 kb
Host smart-38705664-3aa4-4e53-b56e-67bf276098e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403353342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.1403353342
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.2580842075
Short name T548
Test name
Test status
Simulation time 16759312344 ps
CPU time 68.36 seconds
Started Aug 09 06:55:04 PM PDT 24
Finished Aug 09 06:56:13 PM PDT 24
Peak memory 258100 kb
Host smart-1da309b9-900f-4fde-ab12-e878a23975b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580842075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.2580842075
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.3111677128
Short name T722
Test name
Test status
Simulation time 125542308 ps
CPU time 5.79 seconds
Started Aug 09 06:55:01 PM PDT 24
Finished Aug 09 06:55:07 PM PDT 24
Peak memory 233452 kb
Host smart-8cdbc556-9cdf-4593-9323-d56f3162163f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111677128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.3111677128
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.743411531
Short name T59
Test name
Test status
Simulation time 6589260805 ps
CPU time 25.12 seconds
Started Aug 09 06:55:02 PM PDT 24
Finished Aug 09 06:55:28 PM PDT 24
Peak memory 249848 kb
Host smart-8ef0c88d-09f8-42f5-8f97-a6a999def980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743411531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmds
.743411531
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/18.spi_device_intercept.4216439739
Short name T446
Test name
Test status
Simulation time 60658317 ps
CPU time 2.25 seconds
Started Aug 09 06:55:01 PM PDT 24
Finished Aug 09 06:55:03 PM PDT 24
Peak memory 233120 kb
Host smart-642d2620-a836-45ba-b202-4b5cd3929e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216439739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.4216439739
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.1111491796
Short name T973
Test name
Test status
Simulation time 1624808996 ps
CPU time 24.06 seconds
Started Aug 09 06:55:01 PM PDT 24
Finished Aug 09 06:55:26 PM PDT 24
Peak memory 241412 kb
Host smart-34cc79eb-bc62-4ee0-9554-389f08735779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111491796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.1111491796
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.2502411911
Short name T463
Test name
Test status
Simulation time 23393821 ps
CPU time 1.14 seconds
Started Aug 09 06:55:04 PM PDT 24
Finished Aug 09 06:55:05 PM PDT 24
Peak memory 218368 kb
Host smart-27892541-eb45-4de0-ad30-610af52cfb5b
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502411911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.spi_device_mem_parity.2502411911
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.1748745348
Short name T13
Test name
Test status
Simulation time 946288836 ps
CPU time 5.08 seconds
Started Aug 09 06:55:01 PM PDT 24
Finished Aug 09 06:55:06 PM PDT 24
Peak memory 225224 kb
Host smart-f3fe7b29-70fd-4c3c-80b9-8791eee71747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748745348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.1748745348
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.4267743151
Short name T892
Test name
Test status
Simulation time 7484013342 ps
CPU time 15.76 seconds
Started Aug 09 06:55:01 PM PDT 24
Finished Aug 09 06:55:17 PM PDT 24
Peak memory 241376 kb
Host smart-f1b258da-0d58-4006-948c-78845bc71029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267743151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.4267743151
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.1014067526
Short name T796
Test name
Test status
Simulation time 1305322241 ps
CPU time 16.99 seconds
Started Aug 09 06:55:02 PM PDT 24
Finished Aug 09 06:55:19 PM PDT 24
Peak memory 219504 kb
Host smart-444c752e-8749-470b-99dd-daaed92be488
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1014067526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.1014067526
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.1058834608
Short name T967
Test name
Test status
Simulation time 107375590663 ps
CPU time 249.72 seconds
Started Aug 09 06:55:11 PM PDT 24
Finished Aug 09 06:59:21 PM PDT 24
Peak memory 252060 kb
Host smart-7ac20e84-78e7-4964-b7db-55cdf5a70a1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058834608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.1058834608
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.186876095
Short name T450
Test name
Test status
Simulation time 8965437634 ps
CPU time 21.41 seconds
Started Aug 09 06:55:01 PM PDT 24
Finished Aug 09 06:55:23 PM PDT 24
Peak memory 217424 kb
Host smart-521205dd-43b8-47c2-a57e-e94cd59c5364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186876095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.186876095
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.2928486501
Short name T886
Test name
Test status
Simulation time 41518710 ps
CPU time 0.74 seconds
Started Aug 09 06:55:02 PM PDT 24
Finished Aug 09 06:55:02 PM PDT 24
Peak memory 206132 kb
Host smart-d488dd4f-d53b-40b9-b5a5-cdaaacb0b978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928486501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.2928486501
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.3072113511
Short name T476
Test name
Test status
Simulation time 143779462 ps
CPU time 1.4 seconds
Started Aug 09 06:55:04 PM PDT 24
Finished Aug 09 06:55:05 PM PDT 24
Peak memory 208812 kb
Host smart-e2cea952-764c-43fe-b119-5f9f30f9e9f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072113511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.3072113511
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.3729207854
Short name T469
Test name
Test status
Simulation time 29708208 ps
CPU time 0.78 seconds
Started Aug 09 06:55:02 PM PDT 24
Finished Aug 09 06:55:03 PM PDT 24
Peak memory 206560 kb
Host smart-7fa82c6c-e1ff-4cf3-99bd-5209a70244c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729207854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.3729207854
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.561899001
Short name T911
Test name
Test status
Simulation time 738091315 ps
CPU time 7.18 seconds
Started Aug 09 06:55:01 PM PDT 24
Finished Aug 09 06:55:09 PM PDT 24
Peak memory 233632 kb
Host smart-7c39f384-04e9-4bf9-85a2-c6670af1e7b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561899001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.561899001
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.451976767
Short name T365
Test name
Test status
Simulation time 144610194 ps
CPU time 0.74 seconds
Started Aug 09 06:55:12 PM PDT 24
Finished Aug 09 06:55:13 PM PDT 24
Peak memory 205748 kb
Host smart-acc8d69b-3afd-4d20-98aa-e04d7bcff95a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451976767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.451976767
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.1018287901
Short name T521
Test name
Test status
Simulation time 135575719 ps
CPU time 3.4 seconds
Started Aug 09 06:55:10 PM PDT 24
Finished Aug 09 06:55:14 PM PDT 24
Peak memory 225204 kb
Host smart-aea20af4-a5c1-4d9e-bb18-e06285c3ecf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018287901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.1018287901
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.3690468338
Short name T436
Test name
Test status
Simulation time 16352418 ps
CPU time 0.78 seconds
Started Aug 09 06:55:11 PM PDT 24
Finished Aug 09 06:55:12 PM PDT 24
Peak memory 207044 kb
Host smart-67f60559-46fa-42ad-9178-e58a0015a517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690468338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.3690468338
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.2898893154
Short name T230
Test name
Test status
Simulation time 5218136286 ps
CPU time 36.37 seconds
Started Aug 09 06:55:10 PM PDT 24
Finished Aug 09 06:55:46 PM PDT 24
Peak memory 251404 kb
Host smart-df5931ac-fe4a-4ae2-9ca4-750b3f164ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898893154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.2898893154
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.2379377068
Short name T187
Test name
Test status
Simulation time 9848834465 ps
CPU time 131.16 seconds
Started Aug 09 06:55:13 PM PDT 24
Finished Aug 09 06:57:25 PM PDT 24
Peak memory 267384 kb
Host smart-9630a5bc-fe26-41d9-bfc1-0fe0464f874e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379377068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.2379377068
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.1606877214
Short name T610
Test name
Test status
Simulation time 17130158608 ps
CPU time 48.04 seconds
Started Aug 09 06:55:12 PM PDT 24
Finished Aug 09 06:56:00 PM PDT 24
Peak memory 251476 kb
Host smart-4c381d6f-b0db-4b0c-af25-da35da770d17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606877214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.1606877214
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.4067482822
Short name T613
Test name
Test status
Simulation time 18244615955 ps
CPU time 151.86 seconds
Started Aug 09 06:55:10 PM PDT 24
Finished Aug 09 06:57:42 PM PDT 24
Peak memory 260968 kb
Host smart-93d9cf26-b897-4df7-8ab1-c3109c237270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067482822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmd
s.4067482822
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/19.spi_device_intercept.468311985
Short name T507
Test name
Test status
Simulation time 109777096 ps
CPU time 4.29 seconds
Started Aug 09 06:55:11 PM PDT 24
Finished Aug 09 06:55:16 PM PDT 24
Peak memory 233400 kb
Host smart-5a1e03ab-73f8-4822-a357-2ba4b78790e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468311985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.468311985
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.117848602
Short name T245
Test name
Test status
Simulation time 2586909272 ps
CPU time 16.78 seconds
Started Aug 09 06:55:10 PM PDT 24
Finished Aug 09 06:55:27 PM PDT 24
Peak memory 225336 kb
Host smart-411f9752-aa29-48f1-98af-09ffdc79a845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117848602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.117848602
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.2933904244
Short name T413
Test name
Test status
Simulation time 78575756 ps
CPU time 1.06 seconds
Started Aug 09 06:55:13 PM PDT 24
Finished Aug 09 06:55:14 PM PDT 24
Peak memory 217204 kb
Host smart-4f342820-7a02-4d78-a868-924e52e7fe01
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933904244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.spi_device_mem_parity.2933904244
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.818229129
Short name T524
Test name
Test status
Simulation time 6038296813 ps
CPU time 21.1 seconds
Started Aug 09 06:55:13 PM PDT 24
Finished Aug 09 06:55:34 PM PDT 24
Peak memory 248988 kb
Host smart-7556da4c-815f-4fbf-9525-48f7fda3f713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818229129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swap
.818229129
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.915065803
Short name T220
Test name
Test status
Simulation time 310361311 ps
CPU time 6.42 seconds
Started Aug 09 06:55:08 PM PDT 24
Finished Aug 09 06:55:15 PM PDT 24
Peak memory 241092 kb
Host smart-d0a72745-c93f-4d60-90e3-7e8d06459f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915065803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.915065803
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.2524677579
Short name T902
Test name
Test status
Simulation time 1062843180 ps
CPU time 12.58 seconds
Started Aug 09 06:55:14 PM PDT 24
Finished Aug 09 06:55:26 PM PDT 24
Peak memory 219332 kb
Host smart-4b1fb17a-2b99-407b-871c-b05b35e50b8c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2524677579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.2524677579
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.4271324705
Short name T979
Test name
Test status
Simulation time 107127680 ps
CPU time 1.1 seconds
Started Aug 09 06:55:13 PM PDT 24
Finished Aug 09 06:55:14 PM PDT 24
Peak memory 216492 kb
Host smart-13c10438-1cc8-4ef1-b896-fbc6ac5fe19c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271324705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.4271324705
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.2676006604
Short name T324
Test name
Test status
Simulation time 1026180195 ps
CPU time 7.6 seconds
Started Aug 09 06:55:10 PM PDT 24
Finished Aug 09 06:55:18 PM PDT 24
Peak memory 216936 kb
Host smart-56b46890-bce9-4337-badd-2bca0c7310eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676006604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.2676006604
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.1096916612
Short name T458
Test name
Test status
Simulation time 12043833 ps
CPU time 0.72 seconds
Started Aug 09 06:55:09 PM PDT 24
Finished Aug 09 06:55:10 PM PDT 24
Peak memory 206168 kb
Host smart-536b5c29-a22b-4caa-bbae-635e3cd5e0ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096916612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.1096916612
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.3838401586
Short name T994
Test name
Test status
Simulation time 57634689 ps
CPU time 1.77 seconds
Started Aug 09 06:55:10 PM PDT 24
Finished Aug 09 06:55:12 PM PDT 24
Peak memory 216924 kb
Host smart-9257b583-27a0-46df-8344-7250e2d6d19e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838401586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.3838401586
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.3914379194
Short name T965
Test name
Test status
Simulation time 59631982 ps
CPU time 0.82 seconds
Started Aug 09 06:55:09 PM PDT 24
Finished Aug 09 06:55:10 PM PDT 24
Peak memory 206544 kb
Host smart-f7388627-6223-4767-b267-066439d969f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914379194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.3914379194
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.3206070546
Short name T172
Test name
Test status
Simulation time 10585260950 ps
CPU time 33.63 seconds
Started Aug 09 06:55:13 PM PDT 24
Finished Aug 09 06:55:47 PM PDT 24
Peak memory 249876 kb
Host smart-a52e07f2-2195-4a2e-a616-eb18f793349d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206070546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.3206070546
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.1991791053
Short name T473
Test name
Test status
Simulation time 10642210 ps
CPU time 0.69 seconds
Started Aug 09 06:52:41 PM PDT 24
Finished Aug 09 06:52:42 PM PDT 24
Peak memory 205276 kb
Host smart-fac6a3a9-b23b-4f85-a253-e65992811592
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991791053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.1
991791053
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.51805304
Short name T552
Test name
Test status
Simulation time 235827398 ps
CPU time 3.23 seconds
Started Aug 09 06:52:20 PM PDT 24
Finished Aug 09 06:52:24 PM PDT 24
Peak memory 225208 kb
Host smart-e1bda8c0-fa1c-4a36-893e-12e3fc438afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51805304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.51805304
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.4212050245
Short name T898
Test name
Test status
Simulation time 67559441 ps
CPU time 0.82 seconds
Started Aug 09 06:52:42 PM PDT 24
Finished Aug 09 06:52:43 PM PDT 24
Peak memory 207064 kb
Host smart-abfceb1b-5f92-4ab0-ad44-6fdebefff519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212050245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.4212050245
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.3005986898
Short name T387
Test name
Test status
Simulation time 12671413260 ps
CPU time 77.8 seconds
Started Aug 09 06:52:21 PM PDT 24
Finished Aug 09 06:53:39 PM PDT 24
Peak memory 249804 kb
Host smart-6709a76d-5ca1-463b-bc88-7c5d27b1b674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005986898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.3005986898
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.1434263325
Short name T332
Test name
Test status
Simulation time 13758060000 ps
CPU time 59.96 seconds
Started Aug 09 06:52:22 PM PDT 24
Finished Aug 09 06:53:22 PM PDT 24
Peak memory 233484 kb
Host smart-706f31aa-a48c-4965-8bc1-d00c8e5395a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434263325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.1434263325
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.1460098548
Short name T284
Test name
Test status
Simulation time 9925374767 ps
CPU time 123.49 seconds
Started Aug 09 06:52:24 PM PDT 24
Finished Aug 09 06:54:27 PM PDT 24
Peak memory 249940 kb
Host smart-893adda8-e682-44ce-a6ee-a3b6ecc508ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460098548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.1460098548
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.4063426831
Short name T315
Test name
Test status
Simulation time 5682477405 ps
CPU time 19.33 seconds
Started Aug 09 06:52:23 PM PDT 24
Finished Aug 09 06:52:42 PM PDT 24
Peak memory 235480 kb
Host smart-c12e7bc9-7386-4561-bf58-2fa6efeff4e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063426831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.4063426831
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.3284853408
Short name T235
Test name
Test status
Simulation time 1398405772 ps
CPU time 15.9 seconds
Started Aug 09 06:52:23 PM PDT 24
Finished Aug 09 06:52:39 PM PDT 24
Peak memory 225224 kb
Host smart-3b519582-0a6a-4606-9437-26d24c445f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284853408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds
.3284853408
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_intercept.3970813702
Short name T904
Test name
Test status
Simulation time 1061801211 ps
CPU time 12.16 seconds
Started Aug 09 06:52:22 PM PDT 24
Finished Aug 09 06:52:34 PM PDT 24
Peak memory 233428 kb
Host smart-c589810e-b144-4a93-a1c4-24a416e93a41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970813702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.3970813702
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.3144921500
Short name T562
Test name
Test status
Simulation time 1800891030 ps
CPU time 29.55 seconds
Started Aug 09 06:52:21 PM PDT 24
Finished Aug 09 06:52:51 PM PDT 24
Peak memory 235536 kb
Host smart-f635e494-799b-422b-a2dc-0ca0feb23106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144921500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.3144921500
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.2261879998
Short name T871
Test name
Test status
Simulation time 26659647 ps
CPU time 1.04 seconds
Started Aug 09 06:52:22 PM PDT 24
Finished Aug 09 06:52:23 PM PDT 24
Peak memory 217184 kb
Host smart-04918921-6660-45af-bd6d-f32835eb5d44
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261879998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.spi_device_mem_parity.2261879998
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.1878130052
Short name T410
Test name
Test status
Simulation time 5857140621 ps
CPU time 7.21 seconds
Started Aug 09 06:52:20 PM PDT 24
Finished Aug 09 06:52:27 PM PDT 24
Peak memory 233508 kb
Host smart-ab7440fb-12e9-4e8e-a71c-29eccdffa0bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878130052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.1878130052
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.3592692574
Short name T953
Test name
Test status
Simulation time 3347887499 ps
CPU time 11.4 seconds
Started Aug 09 06:52:22 PM PDT 24
Finished Aug 09 06:52:33 PM PDT 24
Peak memory 225272 kb
Host smart-12f378d2-dcea-4ca2-8688-ae835f74fdd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592692574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.3592692574
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.174153630
Short name T650
Test name
Test status
Simulation time 1718770532 ps
CPU time 15.6 seconds
Started Aug 09 06:52:21 PM PDT 24
Finished Aug 09 06:52:37 PM PDT 24
Peak memory 222232 kb
Host smart-4049d759-d31f-439d-a117-387c17b1ca71
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=174153630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_direc
t.174153630
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.1881762838
Short name T20
Test name
Test status
Simulation time 409046826 ps
CPU time 1.15 seconds
Started Aug 09 06:52:39 PM PDT 24
Finished Aug 09 06:52:41 PM PDT 24
Peak memory 235640 kb
Host smart-c8294bdc-6836-4459-9fc4-029033213698
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881762838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.1881762838
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.1947866494
Short name T28
Test name
Test status
Simulation time 3615028476 ps
CPU time 27.18 seconds
Started Aug 09 06:52:20 PM PDT 24
Finished Aug 09 06:52:47 PM PDT 24
Peak memory 220252 kb
Host smart-5f79fc59-37c0-4da5-8b3e-a431bb829d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947866494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.1947866494
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.2656403012
Short name T803
Test name
Test status
Simulation time 1622649742 ps
CPU time 7.92 seconds
Started Aug 09 06:52:21 PM PDT 24
Finished Aug 09 06:52:29 PM PDT 24
Peak memory 217112 kb
Host smart-1c0a138c-575c-4338-bd4e-990e664531c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656403012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.2656403012
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.1314311052
Short name T431
Test name
Test status
Simulation time 516568575 ps
CPU time 2.44 seconds
Started Aug 09 06:52:21 PM PDT 24
Finished Aug 09 06:52:24 PM PDT 24
Peak memory 216968 kb
Host smart-0ffbe435-d23e-455e-a957-3d300faa2e69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314311052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.1314311052
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.727156259
Short name T419
Test name
Test status
Simulation time 78171676 ps
CPU time 0.82 seconds
Started Aug 09 06:52:20 PM PDT 24
Finished Aug 09 06:52:21 PM PDT 24
Peak memory 206560 kb
Host smart-3fb82a74-d9be-4e5f-819a-bda9b1d670f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727156259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.727156259
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.1704710888
Short name T955
Test name
Test status
Simulation time 105220165382 ps
CPU time 19.51 seconds
Started Aug 09 06:52:22 PM PDT 24
Finished Aug 09 06:52:42 PM PDT 24
Peak memory 233484 kb
Host smart-00cf95c1-f0bf-455c-9fe2-1ec38a44e696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704710888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.1704710888
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.1994461789
Short name T1011
Test name
Test status
Simulation time 21463719 ps
CPU time 0.71 seconds
Started Aug 09 06:55:19 PM PDT 24
Finished Aug 09 06:55:20 PM PDT 24
Peak memory 205228 kb
Host smart-65ca87d6-a5ec-44af-acd5-5ec01360d554
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994461789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
1994461789
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.253493874
Short name T721
Test name
Test status
Simulation time 2634963404 ps
CPU time 8.39 seconds
Started Aug 09 06:55:18 PM PDT 24
Finished Aug 09 06:55:27 PM PDT 24
Peak memory 233512 kb
Host smart-d3205945-9a49-42fe-887d-c0ddfbc61245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253493874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.253493874
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.1410139711
Short name T1018
Test name
Test status
Simulation time 12232790 ps
CPU time 0.78 seconds
Started Aug 09 06:55:13 PM PDT 24
Finished Aug 09 06:55:13 PM PDT 24
Peak memory 206396 kb
Host smart-777e6cd6-eca8-44d6-b03d-caaeafb581bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410139711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.1410139711
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.2078670943
Short name T638
Test name
Test status
Simulation time 2374348839 ps
CPU time 36.27 seconds
Started Aug 09 06:55:20 PM PDT 24
Finished Aug 09 06:55:56 PM PDT 24
Peak memory 257624 kb
Host smart-5d0380b3-881f-4ee2-8c6e-702118ce70f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078670943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.2078670943
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.2045426907
Short name T305
Test name
Test status
Simulation time 25120387510 ps
CPU time 90.68 seconds
Started Aug 09 06:55:19 PM PDT 24
Finished Aug 09 06:56:49 PM PDT 24
Peak memory 257168 kb
Host smart-64fbabbd-ac45-4c2c-ac37-b9e82f6884b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045426907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.2045426907
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.3532580306
Short name T590
Test name
Test status
Simulation time 219542619 ps
CPU time 4.2 seconds
Started Aug 09 06:55:21 PM PDT 24
Finished Aug 09 06:55:25 PM PDT 24
Peak memory 225212 kb
Host smart-d17238c4-c77d-45b8-bcdf-b71c11ef9e88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532580306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.3532580306
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.1136707750
Short name T34
Test name
Test status
Simulation time 13245818242 ps
CPU time 82.51 seconds
Started Aug 09 06:55:18 PM PDT 24
Finished Aug 09 06:56:40 PM PDT 24
Peak memory 249912 kb
Host smart-a8a28e4c-bf7f-47d7-bd06-e2bd5693906e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136707750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmd
s.1136707750
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/20.spi_device_intercept.994623140
Short name T432
Test name
Test status
Simulation time 270137463 ps
CPU time 3.99 seconds
Started Aug 09 06:55:12 PM PDT 24
Finished Aug 09 06:55:16 PM PDT 24
Peak memory 225236 kb
Host smart-288a6d1c-3379-436f-abb7-fa0c3f011ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994623140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.994623140
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.499230484
Short name T96
Test name
Test status
Simulation time 5392014094 ps
CPU time 40.38 seconds
Started Aug 09 06:55:14 PM PDT 24
Finished Aug 09 06:55:55 PM PDT 24
Peak memory 233464 kb
Host smart-9a44e31a-7742-41f3-bb2b-6a1673ef35b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499230484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.499230484
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.4106271880
Short name T269
Test name
Test status
Simulation time 1034819652 ps
CPU time 4.13 seconds
Started Aug 09 06:55:12 PM PDT 24
Finished Aug 09 06:55:16 PM PDT 24
Peak memory 233332 kb
Host smart-b7ef3fd1-d147-40c9-a0cc-979d56c291c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106271880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.4106271880
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.3765710283
Short name T399
Test name
Test status
Simulation time 445775496 ps
CPU time 3.07 seconds
Started Aug 09 06:55:13 PM PDT 24
Finished Aug 09 06:55:16 PM PDT 24
Peak memory 225232 kb
Host smart-c51f5bd0-1eda-476c-9942-f11efff04705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765710283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.3765710283
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.267178306
Short name T683
Test name
Test status
Simulation time 1255685020 ps
CPU time 5.82 seconds
Started Aug 09 06:55:20 PM PDT 24
Finished Aug 09 06:55:26 PM PDT 24
Peak memory 220692 kb
Host smart-db7526db-c5fe-4b3c-932c-b8050cc5c86d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=267178306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dire
ct.267178306
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.2695486345
Short name T648
Test name
Test status
Simulation time 6699377904 ps
CPU time 45.74 seconds
Started Aug 09 06:55:14 PM PDT 24
Finished Aug 09 06:55:59 PM PDT 24
Peak memory 216876 kb
Host smart-cb8d75e3-67fd-4b0c-8895-43f00e80f7aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695486345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.2695486345
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.4150327657
Short name T816
Test name
Test status
Simulation time 3185169429 ps
CPU time 7.39 seconds
Started Aug 09 06:55:13 PM PDT 24
Finished Aug 09 06:55:20 PM PDT 24
Peak memory 216988 kb
Host smart-6cdfdc69-3d6e-4359-a61e-dd72ad80df5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150327657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.4150327657
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.692209880
Short name T516
Test name
Test status
Simulation time 51295521 ps
CPU time 1.26 seconds
Started Aug 09 06:55:16 PM PDT 24
Finished Aug 09 06:55:17 PM PDT 24
Peak memory 208668 kb
Host smart-d1cf4edf-4d08-49cb-92d2-e460cdb957b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692209880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.692209880
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.1411420374
Short name T654
Test name
Test status
Simulation time 60658858 ps
CPU time 0.78 seconds
Started Aug 09 06:55:11 PM PDT 24
Finished Aug 09 06:55:12 PM PDT 24
Peak memory 206592 kb
Host smart-3e9648d0-ce05-45cd-8da0-912f8ff20513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411420374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.1411420374
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.3070225306
Short name T68
Test name
Test status
Simulation time 870612379 ps
CPU time 4.19 seconds
Started Aug 09 06:55:17 PM PDT 24
Finished Aug 09 06:55:22 PM PDT 24
Peak memory 233416 kb
Host smart-668d8c95-84c4-48da-b518-bf1b8e3368a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070225306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.3070225306
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.3248836606
Short name T777
Test name
Test status
Simulation time 14530498 ps
CPU time 0.74 seconds
Started Aug 09 06:55:28 PM PDT 24
Finished Aug 09 06:55:29 PM PDT 24
Peak memory 205184 kb
Host smart-87784ae2-11e5-47b4-9a85-b192f98ba894
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248836606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
3248836606
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.231211367
Short name T763
Test name
Test status
Simulation time 1511241201 ps
CPU time 8.78 seconds
Started Aug 09 06:55:18 PM PDT 24
Finished Aug 09 06:55:27 PM PDT 24
Peak memory 225252 kb
Host smart-cbc0cb30-17b8-475c-b100-971e5d840d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231211367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.231211367
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.2658346658
Short name T900
Test name
Test status
Simulation time 18658106 ps
CPU time 0.81 seconds
Started Aug 09 06:55:21 PM PDT 24
Finished Aug 09 06:55:22 PM PDT 24
Peak memory 207028 kb
Host smart-948b61bf-69bd-4be7-81d4-2c1a61dc4183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658346658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.2658346658
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.2083044514
Short name T579
Test name
Test status
Simulation time 824705392 ps
CPU time 0.93 seconds
Started Aug 09 06:55:24 PM PDT 24
Finished Aug 09 06:55:25 PM PDT 24
Peak memory 216656 kb
Host smart-06dee79d-50a2-4e20-9881-6f815dd813a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083044514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.2083044514
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.133140330
Short name T553
Test name
Test status
Simulation time 43998644680 ps
CPU time 238.24 seconds
Started Aug 09 06:55:25 PM PDT 24
Finished Aug 09 06:59:24 PM PDT 24
Peak memory 256324 kb
Host smart-5a516957-813e-4f9a-879a-83a71f1c1b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133140330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.133140330
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.1428631328
Short name T515
Test name
Test status
Simulation time 250422703112 ps
CPU time 355.95 seconds
Started Aug 09 06:55:25 PM PDT 24
Finished Aug 09 07:01:21 PM PDT 24
Peak memory 254112 kb
Host smart-026150d9-174e-4539-9c02-e23c9f457c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428631328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.1428631328
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.1600199826
Short name T992
Test name
Test status
Simulation time 8244114391 ps
CPU time 17.95 seconds
Started Aug 09 06:55:21 PM PDT 24
Finished Aug 09 06:55:39 PM PDT 24
Peak memory 236388 kb
Host smart-fc070df8-c0e1-47d5-8d72-de27b68c8f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600199826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.1600199826
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.1595116451
Short name T50
Test name
Test status
Simulation time 6764440901 ps
CPU time 50.69 seconds
Started Aug 09 06:55:25 PM PDT 24
Finished Aug 09 06:56:16 PM PDT 24
Peak memory 249900 kb
Host smart-440ec41c-5675-49dd-9809-f9127bf2c351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595116451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmd
s.1595116451
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_intercept.138364098
Short name T347
Test name
Test status
Simulation time 3295317748 ps
CPU time 8.23 seconds
Started Aug 09 06:55:21 PM PDT 24
Finished Aug 09 06:55:29 PM PDT 24
Peak memory 233516 kb
Host smart-36fb51ae-b488-4e35-8f7d-46a24da20c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138364098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.138364098
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.3627864639
Short name T644
Test name
Test status
Simulation time 1519408714 ps
CPU time 13.9 seconds
Started Aug 09 06:55:21 PM PDT 24
Finished Aug 09 06:55:35 PM PDT 24
Peak memory 241644 kb
Host smart-17eb96a8-eb73-4b34-bdb9-95bcfd04524b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627864639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.3627864639
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.1375926557
Short name T502
Test name
Test status
Simulation time 15532259282 ps
CPU time 13.04 seconds
Started Aug 09 06:55:17 PM PDT 24
Finished Aug 09 06:55:30 PM PDT 24
Peak memory 225172 kb
Host smart-9c1b1685-0b45-4347-a609-a24c6a94286e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375926557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.1375926557
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.3866234688
Short name T265
Test name
Test status
Simulation time 2995822591 ps
CPU time 8.07 seconds
Started Aug 09 06:55:19 PM PDT 24
Finished Aug 09 06:55:28 PM PDT 24
Peak memory 225260 kb
Host smart-6cbce652-b80d-4375-8483-cbb246643a14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866234688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.3866234688
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.1384782931
Short name T701
Test name
Test status
Simulation time 2458729768 ps
CPU time 13.42 seconds
Started Aug 09 06:55:30 PM PDT 24
Finished Aug 09 06:55:44 PM PDT 24
Peak memory 221244 kb
Host smart-f34156f3-c920-4ebe-973a-0484761c873f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1384782931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.1384782931
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.3171899941
Short name T149
Test name
Test status
Simulation time 55050233885 ps
CPU time 410.21 seconds
Started Aug 09 06:55:26 PM PDT 24
Finished Aug 09 07:02:16 PM PDT 24
Peak memory 266304 kb
Host smart-09a9f4b6-e3d3-4973-9680-88cb739fcdb2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171899941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.3171899941
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.1612213482
Short name T329
Test name
Test status
Simulation time 742710509 ps
CPU time 12.5 seconds
Started Aug 09 06:55:19 PM PDT 24
Finished Aug 09 06:55:31 PM PDT 24
Peak memory 216960 kb
Host smart-6a26de41-1224-4c71-9a8f-d3baee848a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612213482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.1612213482
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.3833348817
Short name T447
Test name
Test status
Simulation time 14854832880 ps
CPU time 6.98 seconds
Started Aug 09 06:55:20 PM PDT 24
Finished Aug 09 06:55:27 PM PDT 24
Peak memory 217028 kb
Host smart-f9905408-9706-4b94-a67c-4a10fb460c22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833348817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.3833348817
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.25176506
Short name T589
Test name
Test status
Simulation time 91260974 ps
CPU time 1.71 seconds
Started Aug 09 06:55:16 PM PDT 24
Finished Aug 09 06:55:18 PM PDT 24
Peak memory 216972 kb
Host smart-ad037802-3de5-4f12-a042-7a99e6c7cf27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25176506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.25176506
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.2452466441
Short name T416
Test name
Test status
Simulation time 31508238 ps
CPU time 0.85 seconds
Started Aug 09 06:55:21 PM PDT 24
Finished Aug 09 06:55:22 PM PDT 24
Peak memory 206520 kb
Host smart-db98ba23-72de-4467-b56a-c1877b97b781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452466441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.2452466441
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.3171316347
Short name T11
Test name
Test status
Simulation time 11280759161 ps
CPU time 37.15 seconds
Started Aug 09 06:55:18 PM PDT 24
Finished Aug 09 06:55:55 PM PDT 24
Peak memory 233504 kb
Host smart-8117412b-5f1a-49a7-ba46-981ea02d50bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171316347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.3171316347
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.2732888986
Short name T651
Test name
Test status
Simulation time 15473684 ps
CPU time 0.72 seconds
Started Aug 09 06:55:35 PM PDT 24
Finished Aug 09 06:55:36 PM PDT 24
Peak memory 205268 kb
Host smart-f172eb51-da3f-440e-b119-12f8bfed7367
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732888986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
2732888986
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.3757208934
Short name T258
Test name
Test status
Simulation time 2230553689 ps
CPU time 20.86 seconds
Started Aug 09 06:55:25 PM PDT 24
Finished Aug 09 06:55:46 PM PDT 24
Peak memory 233508 kb
Host smart-7743903e-b8b4-4a37-b65f-9c26df9ba2f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757208934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.3757208934
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.3703513395
Short name T558
Test name
Test status
Simulation time 13596732 ps
CPU time 0.82 seconds
Started Aug 09 06:55:27 PM PDT 24
Finished Aug 09 06:55:28 PM PDT 24
Peak memory 207064 kb
Host smart-d1734bbc-9112-4152-b989-d47f51731c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703513395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.3703513395
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.65368633
Short name T71
Test name
Test status
Simulation time 7622287881 ps
CPU time 61.01 seconds
Started Aug 09 06:55:27 PM PDT 24
Finished Aug 09 06:56:28 PM PDT 24
Peak memory 253692 kb
Host smart-4b485804-b9fc-4c7b-8d21-620420978072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65368633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.65368633
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.2863903092
Short name T449
Test name
Test status
Simulation time 8161617902 ps
CPU time 24.07 seconds
Started Aug 09 06:55:31 PM PDT 24
Finished Aug 09 06:55:55 PM PDT 24
Peak memory 218464 kb
Host smart-94ef91ac-e83d-419e-91a6-6305808fe99e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863903092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.2863903092
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.1047086277
Short name T927
Test name
Test status
Simulation time 784569131 ps
CPU time 6.65 seconds
Started Aug 09 06:55:33 PM PDT 24
Finished Aug 09 06:55:40 PM PDT 24
Peak memory 218472 kb
Host smart-94a864d9-e1bd-485c-bd69-a8a416b374c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047086277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.1047086277
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.918824112
Short name T309
Test name
Test status
Simulation time 1468078001 ps
CPU time 17.25 seconds
Started Aug 09 06:55:26 PM PDT 24
Finished Aug 09 06:55:43 PM PDT 24
Peak memory 233528 kb
Host smart-27889be1-ff8a-40e6-b633-c58719623399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918824112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.918824112
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.2994165400
Short name T560
Test name
Test status
Simulation time 16310405418 ps
CPU time 69.51 seconds
Started Aug 09 06:55:28 PM PDT 24
Finished Aug 09 06:56:38 PM PDT 24
Peak memory 249844 kb
Host smart-844d0175-b45c-4217-a1d8-5533f71d29f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994165400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmd
s.2994165400
Directory /workspace/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/22.spi_device_intercept.2435596888
Short name T814
Test name
Test status
Simulation time 282356120 ps
CPU time 3.15 seconds
Started Aug 09 06:55:31 PM PDT 24
Finished Aug 09 06:55:34 PM PDT 24
Peak memory 225260 kb
Host smart-f8a7349c-f833-484a-927e-ca0a1a4da325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435596888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.2435596888
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.1782140683
Short name T563
Test name
Test status
Simulation time 5374980717 ps
CPU time 53.67 seconds
Started Aug 09 06:55:30 PM PDT 24
Finished Aug 09 06:56:24 PM PDT 24
Peak memory 253712 kb
Host smart-077ae342-0fd0-4a20-a06a-35ba8d0369ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782140683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.1782140683
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.892687756
Short name T221
Test name
Test status
Simulation time 187199834 ps
CPU time 2.33 seconds
Started Aug 09 06:55:26 PM PDT 24
Finished Aug 09 06:55:28 PM PDT 24
Peak memory 225228 kb
Host smart-1f3fe0ab-fdab-46c3-a608-6c9000d80e98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892687756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swap
.892687756
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.493033634
Short name T455
Test name
Test status
Simulation time 7663034608 ps
CPU time 23.23 seconds
Started Aug 09 06:55:29 PM PDT 24
Finished Aug 09 06:55:52 PM PDT 24
Peak memory 249656 kb
Host smart-9796e202-4cf0-4ca9-9c34-7033020e39a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493033634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.493033634
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.3189004238
Short name T371
Test name
Test status
Simulation time 206352797 ps
CPU time 4.81 seconds
Started Aug 09 06:55:27 PM PDT 24
Finished Aug 09 06:55:32 PM PDT 24
Peak memory 219380 kb
Host smart-109e623e-393b-4360-ad40-3882608024b1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3189004238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.3189004238
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.3304828301
Short name T626
Test name
Test status
Simulation time 2574688592 ps
CPU time 52.79 seconds
Started Aug 09 06:55:34 PM PDT 24
Finished Aug 09 06:56:27 PM PDT 24
Peak memory 251088 kb
Host smart-5ede4d66-5421-41b9-852b-4b822bd6c157
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304828301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.3304828301
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.4164457246
Short name T369
Test name
Test status
Simulation time 767409745 ps
CPU time 11.96 seconds
Started Aug 09 06:55:26 PM PDT 24
Finished Aug 09 06:55:38 PM PDT 24
Peak memory 217404 kb
Host smart-6186656e-55a6-46e8-9298-f423eac06302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164457246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.4164457246
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.83288194
Short name T662
Test name
Test status
Simulation time 12807730029 ps
CPU time 16.3 seconds
Started Aug 09 06:55:29 PM PDT 24
Finished Aug 09 06:55:46 PM PDT 24
Peak memory 216924 kb
Host smart-6f9c6bbf-581c-484d-a2b9-4d35f4ae3034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83288194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.83288194
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.1270449457
Short name T619
Test name
Test status
Simulation time 1016124285 ps
CPU time 1.41 seconds
Started Aug 09 06:55:25 PM PDT 24
Finished Aug 09 06:55:27 PM PDT 24
Peak memory 208828 kb
Host smart-71fa198f-e67e-4f13-8648-2744d5036c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270449457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.1270449457
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.2331091167
Short name T341
Test name
Test status
Simulation time 16025153 ps
CPU time 0.71 seconds
Started Aug 09 06:55:24 PM PDT 24
Finished Aug 09 06:55:25 PM PDT 24
Peak memory 206116 kb
Host smart-78096d26-cdc8-4aef-8045-d3b785379bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331091167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.2331091167
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.1006999036
Short name T513
Test name
Test status
Simulation time 368154535 ps
CPU time 6.02 seconds
Started Aug 09 06:55:28 PM PDT 24
Finished Aug 09 06:55:34 PM PDT 24
Peak memory 233404 kb
Host smart-208ec6bf-44c1-4573-8b67-bbb78e36a7f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006999036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.1006999036
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.2135643502
Short name T344
Test name
Test status
Simulation time 58765100 ps
CPU time 0.71 seconds
Started Aug 09 06:55:34 PM PDT 24
Finished Aug 09 06:55:35 PM PDT 24
Peak memory 205276 kb
Host smart-99b2d98b-e9d2-4f6c-8494-8031d847aefb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135643502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
2135643502
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.618540140
Short name T257
Test name
Test status
Simulation time 509696720 ps
CPU time 3.85 seconds
Started Aug 09 06:55:35 PM PDT 24
Finished Aug 09 06:55:39 PM PDT 24
Peak memory 233396 kb
Host smart-a82c0d8e-ee12-431c-9284-1e7b6eb4a48c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618540140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.618540140
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.2143935464
Short name T498
Test name
Test status
Simulation time 39628040 ps
CPU time 0.73 seconds
Started Aug 09 06:55:36 PM PDT 24
Finished Aug 09 06:55:36 PM PDT 24
Peak memory 205976 kb
Host smart-1239c43e-5a7d-48aa-bfb1-5957b0ad0b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143935464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.2143935464
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.3717929952
Short name T501
Test name
Test status
Simulation time 25294904074 ps
CPU time 84.26 seconds
Started Aug 09 06:55:33 PM PDT 24
Finished Aug 09 06:56:57 PM PDT 24
Peak memory 249920 kb
Host smart-433e5a3e-0936-4b1d-865f-9b7485fa8e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717929952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.3717929952
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.2149742411
Short name T173
Test name
Test status
Simulation time 4519189872 ps
CPU time 69.9 seconds
Started Aug 09 06:55:36 PM PDT 24
Finished Aug 09 06:56:46 PM PDT 24
Peak memory 255284 kb
Host smart-3dd5b8f0-b3e1-47ba-8ab7-d05a25a5ab7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149742411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.2149742411
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.2957589158
Short name T708
Test name
Test status
Simulation time 1698660091 ps
CPU time 25.03 seconds
Started Aug 09 06:55:35 PM PDT 24
Finished Aug 09 06:56:01 PM PDT 24
Peak memory 218248 kb
Host smart-592e045f-86ca-4e79-96df-2687552a41c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957589158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.2957589158
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.3878925443
Short name T608
Test name
Test status
Simulation time 401958591 ps
CPU time 2.88 seconds
Started Aug 09 06:55:35 PM PDT 24
Finished Aug 09 06:55:38 PM PDT 24
Peak memory 225156 kb
Host smart-3305ebd0-cdbc-4a06-997d-5ed4b3627d26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878925443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.3878925443
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.626333277
Short name T633
Test name
Test status
Simulation time 4305925991 ps
CPU time 29.51 seconds
Started Aug 09 06:55:34 PM PDT 24
Finished Aug 09 06:56:04 PM PDT 24
Peak memory 241700 kb
Host smart-207b7286-465d-4322-ba1d-8ff70e4a6253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626333277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmds
.626333277
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/23.spi_device_intercept.859466678
Short name T808
Test name
Test status
Simulation time 134501847 ps
CPU time 3.58 seconds
Started Aug 09 06:55:34 PM PDT 24
Finished Aug 09 06:55:38 PM PDT 24
Peak memory 233460 kb
Host smart-45106453-5137-4cd1-9597-54b1349228e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859466678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.859466678
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.886366823
Short name T372
Test name
Test status
Simulation time 294189470 ps
CPU time 3.26 seconds
Started Aug 09 06:55:34 PM PDT 24
Finished Aug 09 06:55:37 PM PDT 24
Peak memory 233480 kb
Host smart-36fe4d6f-b79d-43ce-ad29-e7c350417c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886366823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.886366823
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.2127581622
Short name T977
Test name
Test status
Simulation time 319687819 ps
CPU time 6.58 seconds
Started Aug 09 06:55:34 PM PDT 24
Finished Aug 09 06:55:40 PM PDT 24
Peak memory 225252 kb
Host smart-ab3c1473-71cd-4785-829f-9ad1c8fcc5ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127581622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.2127581622
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.1155892095
Short name T607
Test name
Test status
Simulation time 673739983 ps
CPU time 5.06 seconds
Started Aug 09 06:55:33 PM PDT 24
Finished Aug 09 06:55:39 PM PDT 24
Peak memory 233444 kb
Host smart-2079a7e3-12d8-4ada-a628-393f1101b80e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155892095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.1155892095
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.3602862210
Short name T993
Test name
Test status
Simulation time 154450824 ps
CPU time 3.52 seconds
Started Aug 09 06:55:34 PM PDT 24
Finished Aug 09 06:55:37 PM PDT 24
Peak memory 221092 kb
Host smart-a3a8c06a-6d51-4b22-945d-2c5c167e426d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3602862210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.3602862210
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.1549033875
Short name T152
Test name
Test status
Simulation time 53305161705 ps
CPU time 72.14 seconds
Started Aug 09 06:55:34 PM PDT 24
Finished Aug 09 06:56:46 PM PDT 24
Peak memory 241768 kb
Host smart-0e82d9a6-ff91-4e65-b0a1-e3f826b6b77c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549033875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.1549033875
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.1943276790
Short name T55
Test name
Test status
Simulation time 4218744262 ps
CPU time 18.41 seconds
Started Aug 09 06:55:34 PM PDT 24
Finished Aug 09 06:55:52 PM PDT 24
Peak memory 220640 kb
Host smart-8ac93251-9668-4758-9b5b-34b1342b8af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943276790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.1943276790
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.1224998291
Short name T694
Test name
Test status
Simulation time 866190046 ps
CPU time 4.06 seconds
Started Aug 09 06:55:34 PM PDT 24
Finished Aug 09 06:55:38 PM PDT 24
Peak memory 217004 kb
Host smart-9931358e-fbc1-4a5c-9707-8443e099513d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224998291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.1224998291
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.3914183281
Short name T812
Test name
Test status
Simulation time 13285458 ps
CPU time 0.71 seconds
Started Aug 09 06:55:35 PM PDT 24
Finished Aug 09 06:55:36 PM PDT 24
Peak memory 206104 kb
Host smart-5475d4cf-f1af-483a-8d94-3def68c4ecbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914183281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.3914183281
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.3872322875
Short name T586
Test name
Test status
Simulation time 167686361 ps
CPU time 0.81 seconds
Started Aug 09 06:55:35 PM PDT 24
Finished Aug 09 06:55:36 PM PDT 24
Peak memory 206460 kb
Host smart-8dfc8d22-d6e3-485e-92a4-2796d67c94ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872322875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.3872322875
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.2298737521
Short name T969
Test name
Test status
Simulation time 9994450937 ps
CPU time 10.87 seconds
Started Aug 09 06:55:35 PM PDT 24
Finished Aug 09 06:55:46 PM PDT 24
Peak memory 225252 kb
Host smart-90ba7fa2-c233-4272-acdb-4b3339cc002d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298737521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.2298737521
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.2494962815
Short name T706
Test name
Test status
Simulation time 17593895 ps
CPU time 0.72 seconds
Started Aug 09 06:55:42 PM PDT 24
Finished Aug 09 06:55:43 PM PDT 24
Peak memory 205796 kb
Host smart-7ec60299-2b27-4518-a534-1fe61071f691
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494962815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
2494962815
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.135800964
Short name T41
Test name
Test status
Simulation time 220903728 ps
CPU time 4.18 seconds
Started Aug 09 06:55:42 PM PDT 24
Finished Aug 09 06:55:47 PM PDT 24
Peak memory 225276 kb
Host smart-404825f5-b094-4aec-8bc4-b82aa991fd63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135800964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.135800964
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.285059535
Short name T905
Test name
Test status
Simulation time 24762804 ps
CPU time 0.8 seconds
Started Aug 09 06:55:35 PM PDT 24
Finished Aug 09 06:55:35 PM PDT 24
Peak memory 206376 kb
Host smart-988625b9-a49f-4682-b70b-0e7685894a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285059535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.285059535
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.933849004
Short name T1012
Test name
Test status
Simulation time 11846288651 ps
CPU time 142.09 seconds
Started Aug 09 06:55:43 PM PDT 24
Finished Aug 09 06:58:05 PM PDT 24
Peak memory 250076 kb
Host smart-3a078bb3-0cd1-4820-b7c9-e3555e4ae636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933849004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.933849004
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.3678698222
Short name T302
Test name
Test status
Simulation time 23247853337 ps
CPU time 138.85 seconds
Started Aug 09 06:55:43 PM PDT 24
Finished Aug 09 06:58:02 PM PDT 24
Peak memory 253020 kb
Host smart-38f8d2a6-8cea-49f5-a287-189fe37265bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678698222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.3678698222
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.1698359868
Short name T381
Test name
Test status
Simulation time 4045484940 ps
CPU time 31.26 seconds
Started Aug 09 06:55:44 PM PDT 24
Finished Aug 09 06:56:16 PM PDT 24
Peak memory 225232 kb
Host smart-14eb9390-1abe-4ff3-be05-7bd9f735b85b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698359868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.1698359868
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.3716307557
Short name T526
Test name
Test status
Simulation time 225453109 ps
CPU time 6.05 seconds
Started Aug 09 06:55:43 PM PDT 24
Finished Aug 09 06:55:49 PM PDT 24
Peak memory 235296 kb
Host smart-261343aa-5ae1-47c4-9f20-3fd22c526bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716307557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.3716307557
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.410490403
Short name T1006
Test name
Test status
Simulation time 25924957 ps
CPU time 0.77 seconds
Started Aug 09 06:55:41 PM PDT 24
Finished Aug 09 06:55:41 PM PDT 24
Peak memory 216456 kb
Host smart-dcebd854-ac42-4375-8689-19b96763d7b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410490403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmds
.410490403
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/24.spi_device_intercept.1152672949
Short name T1029
Test name
Test status
Simulation time 9888228249 ps
CPU time 10.27 seconds
Started Aug 09 06:55:42 PM PDT 24
Finished Aug 09 06:55:52 PM PDT 24
Peak memory 233548 kb
Host smart-92c98a7c-da79-4c85-885c-c1b662857377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152672949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.1152672949
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.2340135466
Short name T1028
Test name
Test status
Simulation time 14556689430 ps
CPU time 28.07 seconds
Started Aug 09 06:55:45 PM PDT 24
Finished Aug 09 06:56:13 PM PDT 24
Peak memory 233440 kb
Host smart-fa46404c-3e66-4835-afc8-309c1812169a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340135466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.2340135466
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.4178024412
Short name T778
Test name
Test status
Simulation time 13564663911 ps
CPU time 30.81 seconds
Started Aug 09 06:55:41 PM PDT 24
Finished Aug 09 06:56:12 PM PDT 24
Peak memory 233400 kb
Host smart-210ed3d8-c8c8-4182-9adb-3110f9ebb324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178024412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.4178024412
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.3693818272
Short name T982
Test name
Test status
Simulation time 75452435 ps
CPU time 2.28 seconds
Started Aug 09 06:55:43 PM PDT 24
Finished Aug 09 06:55:45 PM PDT 24
Peak memory 224412 kb
Host smart-062be8d9-7713-42e7-a1d6-8fcb5a0291bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693818272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.3693818272
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.2994397561
Short name T549
Test name
Test status
Simulation time 3040547124 ps
CPU time 12.28 seconds
Started Aug 09 06:55:42 PM PDT 24
Finished Aug 09 06:55:54 PM PDT 24
Peak memory 219460 kb
Host smart-9c10552c-e356-460e-89be-8b7a4ccd6e42
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2994397561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.2994397561
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.2790469385
Short name T151
Test name
Test status
Simulation time 15664786128 ps
CPU time 54.68 seconds
Started Aug 09 06:55:42 PM PDT 24
Finished Aug 09 06:56:37 PM PDT 24
Peak memory 237100 kb
Host smart-d573475c-4698-4cc5-af0f-a018cda60633
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790469385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.2790469385
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.3969079577
Short name T27
Test name
Test status
Simulation time 18113917020 ps
CPU time 29.23 seconds
Started Aug 09 06:55:42 PM PDT 24
Finished Aug 09 06:56:11 PM PDT 24
Peak memory 217212 kb
Host smart-16e8c888-6163-4eb5-97d4-9844d7765438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969079577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.3969079577
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.374094596
Short name T680
Test name
Test status
Simulation time 703194146 ps
CPU time 4.91 seconds
Started Aug 09 06:55:44 PM PDT 24
Finished Aug 09 06:55:49 PM PDT 24
Peak memory 216888 kb
Host smart-2c3f696a-06f0-41f6-988e-5c74542b7f21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374094596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.374094596
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.2971667007
Short name T354
Test name
Test status
Simulation time 22888511 ps
CPU time 0.7 seconds
Started Aug 09 06:55:42 PM PDT 24
Finished Aug 09 06:55:42 PM PDT 24
Peak memory 206136 kb
Host smart-d039b5c4-8e0a-4cd3-b5ca-8817ad71f2c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971667007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.2971667007
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.3524060511
Short name T919
Test name
Test status
Simulation time 49953176 ps
CPU time 0.72 seconds
Started Aug 09 06:55:43 PM PDT 24
Finished Aug 09 06:55:44 PM PDT 24
Peak memory 206568 kb
Host smart-0e6136a3-0ab8-4e68-a303-dc75c854ba90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524060511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.3524060511
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.4140796766
Short name T577
Test name
Test status
Simulation time 2744812213 ps
CPU time 23.31 seconds
Started Aug 09 06:55:42 PM PDT 24
Finished Aug 09 06:56:05 PM PDT 24
Peak memory 240548 kb
Host smart-6a5fa2b6-a8ea-4c9a-8ef8-a641f7583c9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140796766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.4140796766
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.554822237
Short name T559
Test name
Test status
Simulation time 32088651 ps
CPU time 0.69 seconds
Started Aug 09 06:55:49 PM PDT 24
Finished Aug 09 06:55:50 PM PDT 24
Peak memory 205744 kb
Host smart-57a50969-532b-400b-a227-6001ce97fa02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554822237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.554822237
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.2304093006
Short name T184
Test name
Test status
Simulation time 120008681 ps
CPU time 2.7 seconds
Started Aug 09 06:55:50 PM PDT 24
Finished Aug 09 06:55:53 PM PDT 24
Peak memory 233432 kb
Host smart-676c3b77-621b-43c3-8aeb-b8922c599398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304093006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.2304093006
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.902169353
Short name T370
Test name
Test status
Simulation time 14835667 ps
CPU time 0.77 seconds
Started Aug 09 06:55:42 PM PDT 24
Finished Aug 09 06:55:43 PM PDT 24
Peak memory 207032 kb
Host smart-57390774-4373-4eaa-9e89-609a9dc88bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902169353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.902169353
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.3638913021
Short name T295
Test name
Test status
Simulation time 62937233843 ps
CPU time 288.09 seconds
Started Aug 09 06:55:50 PM PDT 24
Finished Aug 09 07:00:38 PM PDT 24
Peak memory 253020 kb
Host smart-bb3852ef-f728-4188-b16a-c4b4db27c5ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638913021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.3638913021
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.4048267136
Short name T227
Test name
Test status
Simulation time 4237340740 ps
CPU time 19.47 seconds
Started Aug 09 06:55:50 PM PDT 24
Finished Aug 09 06:56:10 PM PDT 24
Peak memory 225372 kb
Host smart-90238a74-ef18-4b94-b47a-675f235ae117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048267136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.4048267136
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.1531852263
Short name T956
Test name
Test status
Simulation time 60899450139 ps
CPU time 97.24 seconds
Started Aug 09 06:55:50 PM PDT 24
Finished Aug 09 06:57:28 PM PDT 24
Peak memory 241716 kb
Host smart-9daddc1e-b1d3-4b4a-a68a-1f80d53e4849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531852263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.1531852263
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.2099959641
Short name T451
Test name
Test status
Simulation time 407374244 ps
CPU time 7.72 seconds
Started Aug 09 06:55:50 PM PDT 24
Finished Aug 09 06:55:58 PM PDT 24
Peak memory 233524 kb
Host smart-0efb4fda-e81f-467a-a8f4-9b168b4b94ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099959641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.2099959641
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.340599936
Short name T42
Test name
Test status
Simulation time 18272842374 ps
CPU time 25.69 seconds
Started Aug 09 06:55:50 PM PDT 24
Finished Aug 09 06:56:16 PM PDT 24
Peak memory 250152 kb
Host smart-38b296de-61aa-4800-a698-ac9c2300cde3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340599936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmds
.340599936
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/25.spi_device_intercept.2306750318
Short name T748
Test name
Test status
Simulation time 1169450367 ps
CPU time 12.66 seconds
Started Aug 09 06:55:50 PM PDT 24
Finished Aug 09 06:56:03 PM PDT 24
Peak memory 225232 kb
Host smart-1fb0fec4-e38e-4704-8db6-76444a1c18b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306750318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.2306750318
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.1691925238
Short name T854
Test name
Test status
Simulation time 7688239960 ps
CPU time 94.05 seconds
Started Aug 09 06:55:51 PM PDT 24
Finished Aug 09 06:57:25 PM PDT 24
Peak memory 241636 kb
Host smart-019bbb67-63ee-43ae-a6e9-8fc0ce9671a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691925238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.1691925238
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.3421477573
Short name T795
Test name
Test status
Simulation time 107493110 ps
CPU time 2.43 seconds
Started Aug 09 06:55:51 PM PDT 24
Finished Aug 09 06:55:54 PM PDT 24
Peak memory 224568 kb
Host smart-07d35743-2a54-4233-a9f6-8950415c82ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421477573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.3421477573
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.2808118698
Short name T561
Test name
Test status
Simulation time 34970286 ps
CPU time 2.57 seconds
Started Aug 09 06:55:53 PM PDT 24
Finished Aug 09 06:55:55 PM PDT 24
Peak memory 233468 kb
Host smart-22b4912d-0eaf-4735-be2a-f605ada2d45c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808118698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.2808118698
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.3216756782
Short name T12
Test name
Test status
Simulation time 93745606 ps
CPU time 4.26 seconds
Started Aug 09 06:55:51 PM PDT 24
Finished Aug 09 06:55:55 PM PDT 24
Peak memory 223052 kb
Host smart-9ad7f9c0-f6d0-493f-ba27-b885de8537c6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3216756782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.3216756782
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.515571273
Short name T864
Test name
Test status
Simulation time 37377188 ps
CPU time 0.9 seconds
Started Aug 09 06:55:51 PM PDT 24
Finished Aug 09 06:55:52 PM PDT 24
Peak memory 207088 kb
Host smart-49984aac-47f4-4d77-9532-ad158169d400
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515571273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stres
s_all.515571273
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.1109661039
Short name T805
Test name
Test status
Simulation time 17779471065 ps
CPU time 20.21 seconds
Started Aug 09 06:55:50 PM PDT 24
Finished Aug 09 06:56:11 PM PDT 24
Peak memory 217020 kb
Host smart-5e181b7a-87ab-420b-bf9f-f486d9ca3e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109661039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.1109661039
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.3230488671
Short name T487
Test name
Test status
Simulation time 380276552 ps
CPU time 1.39 seconds
Started Aug 09 06:55:42 PM PDT 24
Finished Aug 09 06:55:44 PM PDT 24
Peak memory 208364 kb
Host smart-4e873bef-1b50-4223-874d-c5fcb8860d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230488671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.3230488671
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.2394967644
Short name T362
Test name
Test status
Simulation time 912663047 ps
CPU time 3.34 seconds
Started Aug 09 06:55:50 PM PDT 24
Finished Aug 09 06:55:53 PM PDT 24
Peak memory 216928 kb
Host smart-699a7ec7-a7a8-40b7-bd7f-82d007f6cc5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394967644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.2394967644
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.784434094
Short name T542
Test name
Test status
Simulation time 38873827 ps
CPU time 0.76 seconds
Started Aug 09 06:55:49 PM PDT 24
Finished Aug 09 06:55:50 PM PDT 24
Peak memory 206544 kb
Host smart-79283aab-ed97-4e45-b119-e57f9e993ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784434094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.784434094
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.731719116
Short name T243
Test name
Test status
Simulation time 1911892291 ps
CPU time 4.37 seconds
Started Aug 09 06:55:52 PM PDT 24
Finished Aug 09 06:55:56 PM PDT 24
Peak memory 233432 kb
Host smart-5ca46389-049e-4054-b33e-8eca6b4fbe53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731719116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.731719116
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.2012355060
Short name T761
Test name
Test status
Simulation time 76182788 ps
CPU time 0.72 seconds
Started Aug 09 06:55:59 PM PDT 24
Finished Aug 09 06:56:00 PM PDT 24
Peak memory 206140 kb
Host smart-46e4b9f0-537e-4000-813a-af27cf54c705
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012355060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
2012355060
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.2535705112
Short name T825
Test name
Test status
Simulation time 289208415 ps
CPU time 5.42 seconds
Started Aug 09 06:55:59 PM PDT 24
Finished Aug 09 06:56:04 PM PDT 24
Peak memory 233396 kb
Host smart-0a27c0bd-2e5a-4674-b29f-cea06aa2d13d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535705112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.2535705112
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.122841077
Short name T1022
Test name
Test status
Simulation time 30073964 ps
CPU time 0.75 seconds
Started Aug 09 06:55:50 PM PDT 24
Finished Aug 09 06:55:51 PM PDT 24
Peak memory 207248 kb
Host smart-d5a3c41e-5e76-466b-ae89-2bf663860619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122841077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.122841077
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.3152440684
Short name T202
Test name
Test status
Simulation time 37671538654 ps
CPU time 177.29 seconds
Started Aug 09 06:56:00 PM PDT 24
Finished Aug 09 06:58:57 PM PDT 24
Peak memory 251500 kb
Host smart-70a91435-f2af-40c7-94ac-65cd50be8bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152440684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.3152440684
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.3313299652
Short name T128
Test name
Test status
Simulation time 31706996368 ps
CPU time 139.23 seconds
Started Aug 09 06:55:59 PM PDT 24
Finished Aug 09 06:58:18 PM PDT 24
Peak memory 270268 kb
Host smart-3c7ecda2-9d90-46a1-a141-42a5efd62117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313299652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.3313299652
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.1338085975
Short name T411
Test name
Test status
Simulation time 238212305 ps
CPU time 3.69 seconds
Started Aug 09 06:55:59 PM PDT 24
Finished Aug 09 06:56:03 PM PDT 24
Peak memory 222960 kb
Host smart-5c8501c3-9ec0-4181-b324-6989b6f0aa41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338085975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.1338085975
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.3657002130
Short name T385
Test name
Test status
Simulation time 1973889223 ps
CPU time 5.36 seconds
Started Aug 09 06:56:00 PM PDT 24
Finished Aug 09 06:56:05 PM PDT 24
Peak memory 225224 kb
Host smart-eaba7afe-f57a-4360-b9f4-4618ebfa873c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657002130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.3657002130
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.288622220
Short name T815
Test name
Test status
Simulation time 50612031 ps
CPU time 0.77 seconds
Started Aug 09 06:55:58 PM PDT 24
Finished Aug 09 06:55:58 PM PDT 24
Peak memory 216444 kb
Host smart-6a1bc374-82ed-4211-803b-8f97f30ac057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288622220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmds
.288622220
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_intercept.2454737341
Short name T223
Test name
Test status
Simulation time 2322036964 ps
CPU time 9.33 seconds
Started Aug 09 06:55:54 PM PDT 24
Finished Aug 09 06:56:04 PM PDT 24
Peak memory 233572 kb
Host smart-eef37962-12e7-4905-8fb3-bfc77d0d7995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454737341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.2454737341
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.1201209396
Short name T204
Test name
Test status
Simulation time 103887027024 ps
CPU time 71.91 seconds
Started Aug 09 06:55:52 PM PDT 24
Finished Aug 09 06:57:04 PM PDT 24
Peak memory 233552 kb
Host smart-8b3bea2d-1b0b-4d15-9cc4-97bd21b380c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201209396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.1201209396
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.2873960058
Short name T266
Test name
Test status
Simulation time 24242324812 ps
CPU time 14.57 seconds
Started Aug 09 06:55:50 PM PDT 24
Finished Aug 09 06:56:04 PM PDT 24
Peak memory 233436 kb
Host smart-f44e5c92-122e-4d13-be10-4af03c325004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873960058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.2873960058
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.805968203
Short name T896
Test name
Test status
Simulation time 1453344557 ps
CPU time 6.6 seconds
Started Aug 09 06:55:52 PM PDT 24
Finished Aug 09 06:55:59 PM PDT 24
Peak memory 225260 kb
Host smart-64b82533-669e-4800-913c-a499fd84cf7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805968203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.805968203
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.2940202680
Short name T37
Test name
Test status
Simulation time 764767447 ps
CPU time 3.66 seconds
Started Aug 09 06:55:59 PM PDT 24
Finished Aug 09 06:56:03 PM PDT 24
Peak memory 220200 kb
Host smart-4bc34df9-45f5-494c-81c7-d27625541003
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2940202680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.2940202680
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.2153298741
Short name T132
Test name
Test status
Simulation time 34855837295 ps
CPU time 356.82 seconds
Started Aug 09 06:56:00 PM PDT 24
Finished Aug 09 07:01:57 PM PDT 24
Peak memory 258132 kb
Host smart-ceacb9ca-2fe2-4100-8177-52178fe3b3cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153298741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.2153298741
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.33414243
Short name T611
Test name
Test status
Simulation time 6006096797 ps
CPU time 11.31 seconds
Started Aug 09 06:55:52 PM PDT 24
Finished Aug 09 06:56:04 PM PDT 24
Peak memory 217364 kb
Host smart-25ee962a-ac96-488f-bd65-aaaa7a09b580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33414243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.33414243
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.1924163188
Short name T433
Test name
Test status
Simulation time 857173511 ps
CPU time 5.21 seconds
Started Aug 09 06:55:52 PM PDT 24
Finished Aug 09 06:55:58 PM PDT 24
Peak memory 216940 kb
Host smart-60a38c83-9dc8-4668-bf1c-95327ba7143b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924163188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.1924163188
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.3624202591
Short name T468
Test name
Test status
Simulation time 63908027 ps
CPU time 0.79 seconds
Started Aug 09 06:55:50 PM PDT 24
Finished Aug 09 06:55:51 PM PDT 24
Peak memory 206448 kb
Host smart-0d4eb719-b0d6-4247-ba27-bb30e53481b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624202591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.3624202591
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.251259619
Short name T496
Test name
Test status
Simulation time 222759097 ps
CPU time 0.8 seconds
Started Aug 09 06:55:52 PM PDT 24
Finished Aug 09 06:55:53 PM PDT 24
Peak memory 206580 kb
Host smart-f5e74b04-6d51-450f-969a-afa97b3e1769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251259619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.251259619
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.3304473903
Short name T885
Test name
Test status
Simulation time 538421258 ps
CPU time 2.44 seconds
Started Aug 09 06:55:58 PM PDT 24
Finished Aug 09 06:56:01 PM PDT 24
Peak memory 225148 kb
Host smart-b694168e-6ddd-4944-a8ff-639f9999fb55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304473903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.3304473903
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.3208985078
Short name T357
Test name
Test status
Simulation time 33150287 ps
CPU time 0.72 seconds
Started Aug 09 06:56:06 PM PDT 24
Finished Aug 09 06:56:07 PM PDT 24
Peak memory 205300 kb
Host smart-0c0dd3ba-8e6e-4cbd-a84f-10edde0640e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208985078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
3208985078
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.2502351438
Short name T670
Test name
Test status
Simulation time 56870026 ps
CPU time 2.27 seconds
Started Aug 09 06:55:58 PM PDT 24
Finished Aug 09 06:56:01 PM PDT 24
Peak memory 232992 kb
Host smart-5f573f3b-dbc9-48c5-b94e-df3de209f9bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502351438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.2502351438
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.266844910
Short name T430
Test name
Test status
Simulation time 19423320 ps
CPU time 0.81 seconds
Started Aug 09 06:56:10 PM PDT 24
Finished Aug 09 06:56:11 PM PDT 24
Peak memory 207080 kb
Host smart-701fa22a-a54d-4184-8b88-3d44a22c930c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266844910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.266844910
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.1430088012
Short name T174
Test name
Test status
Simulation time 12189198409 ps
CPU time 92.56 seconds
Started Aug 09 06:56:08 PM PDT 24
Finished Aug 09 06:57:41 PM PDT 24
Peak memory 250220 kb
Host smart-ccc38689-3f2a-4841-ab1e-b09803ee0648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430088012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.1430088012
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.563658210
Short name T822
Test name
Test status
Simulation time 49640162472 ps
CPU time 135.89 seconds
Started Aug 09 06:56:12 PM PDT 24
Finished Aug 09 06:58:28 PM PDT 24
Peak memory 257024 kb
Host smart-acbac48c-d552-4f45-a662-3768e62a7942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563658210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.563658210
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.1169310388
Short name T270
Test name
Test status
Simulation time 2677400681 ps
CPU time 36.23 seconds
Started Aug 09 06:56:07 PM PDT 24
Finished Aug 09 06:56:44 PM PDT 24
Peak memory 249912 kb
Host smart-6dd508ec-3d1f-4178-ae4d-f77a9f578ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169310388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.1169310388
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.2097400306
Short name T237
Test name
Test status
Simulation time 287547285 ps
CPU time 2.24 seconds
Started Aug 09 06:56:10 PM PDT 24
Finished Aug 09 06:56:12 PM PDT 24
Peak memory 225276 kb
Host smart-23cecc72-5452-43d7-884f-f69735f69b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097400306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.2097400306
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.2896392653
Short name T937
Test name
Test status
Simulation time 27942335102 ps
CPU time 204.2 seconds
Started Aug 09 06:56:04 PM PDT 24
Finished Aug 09 06:59:28 PM PDT 24
Peak memory 266500 kb
Host smart-81b46cfe-651e-4fec-bd26-fde6131bd58f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896392653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmd
s.2896392653
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/27.spi_device_intercept.4082315061
Short name T978
Test name
Test status
Simulation time 2652818724 ps
CPU time 4.27 seconds
Started Aug 09 06:55:58 PM PDT 24
Finished Aug 09 06:56:03 PM PDT 24
Peak memory 225352 kb
Host smart-2b2b2ffb-bea3-4fc7-8241-a0e4f8119cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082315061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.4082315061
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.1708801869
Short name T793
Test name
Test status
Simulation time 751236441 ps
CPU time 8.93 seconds
Started Aug 09 06:55:57 PM PDT 24
Finished Aug 09 06:56:06 PM PDT 24
Peak memory 233420 kb
Host smart-f0246a2c-0ac6-4265-afb9-06a00c64c8a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708801869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.1708801869
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.2118762756
Short name T831
Test name
Test status
Simulation time 307391970 ps
CPU time 7.31 seconds
Started Aug 09 06:56:09 PM PDT 24
Finished Aug 09 06:56:16 PM PDT 24
Peak memory 240880 kb
Host smart-6de8b01f-d73d-451b-b658-41706d844a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118762756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.2118762756
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.2966342472
Short name T264
Test name
Test status
Simulation time 14804001327 ps
CPU time 7.34 seconds
Started Aug 09 06:56:10 PM PDT 24
Finished Aug 09 06:56:17 PM PDT 24
Peak memory 225348 kb
Host smart-b0f7f19c-63a6-492e-bd76-7475046e9e8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966342472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.2966342472
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.2158804804
Short name T550
Test name
Test status
Simulation time 610419628 ps
CPU time 3.98 seconds
Started Aug 09 06:56:06 PM PDT 24
Finished Aug 09 06:56:10 PM PDT 24
Peak memory 219492 kb
Host smart-0e5e2efc-fbdd-4d3d-98c4-48ceaf905eca
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2158804804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.2158804804
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.2737710016
Short name T664
Test name
Test status
Simulation time 104911510 ps
CPU time 0.72 seconds
Started Aug 09 06:56:00 PM PDT 24
Finished Aug 09 06:56:00 PM PDT 24
Peak memory 206180 kb
Host smart-bac607a8-d1c5-47d2-8d58-dced816bbeec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737710016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.2737710016
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.2713239555
Short name T771
Test name
Test status
Simulation time 13684205319 ps
CPU time 8.43 seconds
Started Aug 09 06:55:57 PM PDT 24
Finished Aug 09 06:56:06 PM PDT 24
Peak memory 217056 kb
Host smart-872a1bda-7e14-48fd-9fb7-26bfb507629f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713239555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.2713239555
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.2152694516
Short name T858
Test name
Test status
Simulation time 148482939 ps
CPU time 4.35 seconds
Started Aug 09 06:55:59 PM PDT 24
Finished Aug 09 06:56:03 PM PDT 24
Peak memory 216960 kb
Host smart-330277aa-c0ae-409b-bd05-f6afbdc58448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152694516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.2152694516
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.3040279200
Short name T901
Test name
Test status
Simulation time 21818177 ps
CPU time 0.79 seconds
Started Aug 09 06:55:58 PM PDT 24
Finished Aug 09 06:55:59 PM PDT 24
Peak memory 206564 kb
Host smart-560e5d71-686c-44f7-892d-23e6de4387cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040279200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.3040279200
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.4258536342
Short name T971
Test name
Test status
Simulation time 7195262402 ps
CPU time 23.86 seconds
Started Aug 09 06:56:09 PM PDT 24
Finished Aug 09 06:56:33 PM PDT 24
Peak memory 234576 kb
Host smart-406cef85-2a2d-42c0-8be4-b5b8f4956a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258536342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.4258536342
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.1841476371
Short name T776
Test name
Test status
Simulation time 53067628 ps
CPU time 0.73 seconds
Started Aug 09 06:56:17 PM PDT 24
Finished Aug 09 06:56:17 PM PDT 24
Peak memory 206176 kb
Host smart-85b070e2-c78c-4dd8-8f4f-8ce22f5ea611
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841476371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
1841476371
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.2111376485
Short name T261
Test name
Test status
Simulation time 7678621922 ps
CPU time 5.04 seconds
Started Aug 09 06:56:05 PM PDT 24
Finished Aug 09 06:56:10 PM PDT 24
Peak memory 225272 kb
Host smart-292f80a6-c8b2-4ff7-bf61-562d3f18a463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111376485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.2111376485
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.3584371405
Short name T884
Test name
Test status
Simulation time 21107033 ps
CPU time 0.8 seconds
Started Aug 09 06:56:05 PM PDT 24
Finished Aug 09 06:56:06 PM PDT 24
Peak memory 207044 kb
Host smart-99c23677-6c2a-4fff-9bad-5ed36eef6530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584371405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.3584371405
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.3497486331
Short name T190
Test name
Test status
Simulation time 38757234833 ps
CPU time 93.71 seconds
Started Aug 09 06:56:14 PM PDT 24
Finished Aug 09 06:57:48 PM PDT 24
Peak memory 252184 kb
Host smart-30fec31c-154d-4e65-bdb6-bf0bacf344c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497486331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.3497486331
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.3415087488
Short name T511
Test name
Test status
Simulation time 2179504140 ps
CPU time 14 seconds
Started Aug 09 06:56:05 PM PDT 24
Finished Aug 09 06:56:19 PM PDT 24
Peak memory 235072 kb
Host smart-a94253f9-3375-409b-a513-292e41447abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415087488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.3415087488
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_intercept.3213846220
Short name T497
Test name
Test status
Simulation time 170443832 ps
CPU time 2.65 seconds
Started Aug 09 06:56:06 PM PDT 24
Finished Aug 09 06:56:08 PM PDT 24
Peak memory 225180 kb
Host smart-f37c5241-cea9-47ea-8b75-783ac9682ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213846220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.3213846220
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.4041838871
Short name T991
Test name
Test status
Simulation time 85251654 ps
CPU time 2.24 seconds
Started Aug 09 06:56:07 PM PDT 24
Finished Aug 09 06:56:10 PM PDT 24
Peak memory 219584 kb
Host smart-293f9322-4f5e-4aef-914a-a926c0fa66c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041838871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.4041838871
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.511396034
Short name T274
Test name
Test status
Simulation time 1876354702 ps
CPU time 9.84 seconds
Started Aug 09 06:56:06 PM PDT 24
Finished Aug 09 06:56:16 PM PDT 24
Peak memory 234408 kb
Host smart-d3204bbe-2de5-48a1-bc45-76bd798a4c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511396034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swap
.511396034
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.1629696621
Short name T438
Test name
Test status
Simulation time 311554978 ps
CPU time 2.57 seconds
Started Aug 09 06:56:05 PM PDT 24
Finished Aug 09 06:56:08 PM PDT 24
Peak memory 233444 kb
Host smart-58f64fa0-1c75-4112-a58f-e7ead4348758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629696621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.1629696621
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.4251196025
Short name T420
Test name
Test status
Simulation time 1644094841 ps
CPU time 11.84 seconds
Started Aug 09 06:56:05 PM PDT 24
Finished Aug 09 06:56:17 PM PDT 24
Peak memory 222056 kb
Host smart-59e11252-4b37-4cc4-852e-94fcf60d61f8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4251196025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.4251196025
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.3903089426
Short name T934
Test name
Test status
Simulation time 19469569848 ps
CPU time 258.89 seconds
Started Aug 09 06:56:14 PM PDT 24
Finished Aug 09 07:00:33 PM PDT 24
Peak memory 274500 kb
Host smart-1ebc28ad-ff52-496e-af4e-493b5a02f14d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903089426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.3903089426
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.249392813
Short name T964
Test name
Test status
Simulation time 2458230244 ps
CPU time 19.27 seconds
Started Aug 09 06:56:05 PM PDT 24
Finished Aug 09 06:56:25 PM PDT 24
Peak memory 217000 kb
Host smart-44022df1-1a01-4674-a5ec-c2b741aee612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249392813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.249392813
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.2510920743
Short name T78
Test name
Test status
Simulation time 4966934982 ps
CPU time 9.87 seconds
Started Aug 09 06:56:08 PM PDT 24
Finished Aug 09 06:56:17 PM PDT 24
Peak memory 216976 kb
Host smart-3752b880-63e1-489d-ba57-6de8e0e65b49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510920743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.2510920743
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.27140727
Short name T1010
Test name
Test status
Simulation time 23059100 ps
CPU time 1.01 seconds
Started Aug 09 06:56:06 PM PDT 24
Finished Aug 09 06:56:07 PM PDT 24
Peak memory 208416 kb
Host smart-3f480270-c4b8-4fad-a5bb-bb795de51758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27140727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.27140727
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.779678164
Short name T442
Test name
Test status
Simulation time 399875203 ps
CPU time 1.02 seconds
Started Aug 09 06:56:07 PM PDT 24
Finished Aug 09 06:56:08 PM PDT 24
Peak memory 207608 kb
Host smart-faeddb61-c1f2-47e1-8ef3-27e0039f88a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779678164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.779678164
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.4241281081
Short name T983
Test name
Test status
Simulation time 6753305217 ps
CPU time 21.35 seconds
Started Aug 09 06:56:06 PM PDT 24
Finished Aug 09 06:56:28 PM PDT 24
Peak memory 241228 kb
Host smart-5f85a268-e0f7-482f-b7ac-f0080046c9e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241281081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.4241281081
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.3231154189
Short name T747
Test name
Test status
Simulation time 39923291 ps
CPU time 0.71 seconds
Started Aug 09 06:56:14 PM PDT 24
Finished Aug 09 06:56:15 PM PDT 24
Peak memory 206116 kb
Host smart-217c478c-ba45-4c94-889d-21ee41f38989
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231154189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
3231154189
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.1521479677
Short name T849
Test name
Test status
Simulation time 137683658 ps
CPU time 3.79 seconds
Started Aug 09 06:56:16 PM PDT 24
Finished Aug 09 06:56:20 PM PDT 24
Peak memory 233460 kb
Host smart-cf03b626-75a9-4ede-bbe6-06a62abb8446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521479677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.1521479677
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.1920459361
Short name T126
Test name
Test status
Simulation time 84202148 ps
CPU time 0.76 seconds
Started Aug 09 06:56:16 PM PDT 24
Finished Aug 09 06:56:17 PM PDT 24
Peak memory 207064 kb
Host smart-82adf79a-b34c-4477-8217-a3432827e79b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920459361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.1920459361
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.2083314651
Short name T528
Test name
Test status
Simulation time 2908442190 ps
CPU time 52.84 seconds
Started Aug 09 06:56:16 PM PDT 24
Finished Aug 09 06:57:09 PM PDT 24
Peak memory 258132 kb
Host smart-207da4b5-b8c5-4da4-b64e-d8bcc9613ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083314651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.2083314651
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.2206747439
Short name T267
Test name
Test status
Simulation time 73788005558 ps
CPU time 723.03 seconds
Started Aug 09 06:56:14 PM PDT 24
Finished Aug 09 07:08:18 PM PDT 24
Peak memory 274544 kb
Host smart-a2b28eb8-69d1-47a4-a5a4-aef1f7f78991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206747439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.2206747439
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.1485859345
Short name T713
Test name
Test status
Simulation time 3003199746 ps
CPU time 17.43 seconds
Started Aug 09 06:56:16 PM PDT 24
Finished Aug 09 06:56:33 PM PDT 24
Peak memory 249812 kb
Host smart-d4781d5c-d6c1-47de-9244-e669e62f267b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485859345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.1485859345
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.2964202262
Short name T1007
Test name
Test status
Simulation time 8081165318 ps
CPU time 53.77 seconds
Started Aug 09 06:56:14 PM PDT 24
Finished Aug 09 06:57:08 PM PDT 24
Peak memory 249904 kb
Host smart-0bb4d170-b0f3-48e3-85ea-4280234a808a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964202262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmd
s.2964202262
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/29.spi_device_intercept.2290205034
Short name T879
Test name
Test status
Simulation time 1267585571 ps
CPU time 5.01 seconds
Started Aug 09 06:56:14 PM PDT 24
Finished Aug 09 06:56:19 PM PDT 24
Peak memory 233472 kb
Host smart-ebfacbac-6f6e-4edd-86c4-ad6d3c11c5a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290205034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.2290205034
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.3707091038
Short name T533
Test name
Test status
Simulation time 491484445 ps
CPU time 7.46 seconds
Started Aug 09 06:56:16 PM PDT 24
Finished Aug 09 06:56:23 PM PDT 24
Peak memory 239688 kb
Host smart-04b54d0a-3f42-4b5f-a7ea-59171534c267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707091038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.3707091038
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.751319659
Short name T1026
Test name
Test status
Simulation time 9980700963 ps
CPU time 20.01 seconds
Started Aug 09 06:56:15 PM PDT 24
Finished Aug 09 06:56:35 PM PDT 24
Peak memory 241572 kb
Host smart-60f537d6-754a-4d38-8c2a-f5a151b72465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751319659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swap
.751319659
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.373098321
Short name T253
Test name
Test status
Simulation time 363461295 ps
CPU time 4.12 seconds
Started Aug 09 06:56:18 PM PDT 24
Finished Aug 09 06:56:22 PM PDT 24
Peak memory 233432 kb
Host smart-4e4dc330-7bc1-4a6c-9231-9641285e64b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373098321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.373098321
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.355460139
Short name T724
Test name
Test status
Simulation time 15863270209 ps
CPU time 9.86 seconds
Started Aug 09 06:56:19 PM PDT 24
Finished Aug 09 06:56:29 PM PDT 24
Peak memory 220632 kb
Host smart-69d7e533-5153-4e04-bea6-ba16ab995e6a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=355460139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dire
ct.355460139
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.2287221652
Short name T209
Test name
Test status
Simulation time 72136196175 ps
CPU time 92.63 seconds
Started Aug 09 06:56:14 PM PDT 24
Finished Aug 09 06:57:46 PM PDT 24
Peak memory 249948 kb
Host smart-a2bed761-f9bb-4662-b3d4-08f7661c4e7b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287221652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.2287221652
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.229393666
Short name T407
Test name
Test status
Simulation time 1550962984 ps
CPU time 13.15 seconds
Started Aug 09 06:56:14 PM PDT 24
Finished Aug 09 06:56:27 PM PDT 24
Peak memory 219748 kb
Host smart-d9213f4c-07c5-4245-824a-021325da3013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229393666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.229393666
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.1997244920
Short name T718
Test name
Test status
Simulation time 458632208 ps
CPU time 2.54 seconds
Started Aug 09 06:56:14 PM PDT 24
Finished Aug 09 06:56:16 PM PDT 24
Peak memory 216984 kb
Host smart-105967fc-6164-4688-8327-ca8bd35a23bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997244920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.1997244920
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.2786940927
Short name T327
Test name
Test status
Simulation time 442973697 ps
CPU time 1.3 seconds
Started Aug 09 06:56:15 PM PDT 24
Finished Aug 09 06:56:16 PM PDT 24
Peak memory 216972 kb
Host smart-7a15e971-b7ce-4ea3-b2a9-49349219aa9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786940927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.2786940927
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.621423523
Short name T359
Test name
Test status
Simulation time 96910335 ps
CPU time 0.86 seconds
Started Aug 09 06:56:16 PM PDT 24
Finished Aug 09 06:56:17 PM PDT 24
Peak memory 206584 kb
Host smart-42637fb8-4c56-4e7d-9fe4-8a2051cfa954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621423523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.621423523
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.630482486
Short name T483
Test name
Test status
Simulation time 6402443871 ps
CPU time 8.27 seconds
Started Aug 09 06:56:16 PM PDT 24
Finished Aug 09 06:56:24 PM PDT 24
Peak memory 225324 kb
Host smart-50648113-048e-4b29-bed2-4216571a831c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630482486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.630482486
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.2858906720
Short name T405
Test name
Test status
Simulation time 26314910 ps
CPU time 0.7 seconds
Started Aug 09 06:52:30 PM PDT 24
Finished Aug 09 06:52:30 PM PDT 24
Peak memory 205824 kb
Host smart-660ebe6a-e406-4cf9-9c5d-ca4710913714
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858906720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.2
858906720
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.3068573655
Short name T603
Test name
Test status
Simulation time 18647097800 ps
CPU time 15.93 seconds
Started Aug 09 06:52:33 PM PDT 24
Finished Aug 09 06:52:49 PM PDT 24
Peak memory 233488 kb
Host smart-d4002ca8-2781-4e72-927d-a859bf76a970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068573655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.3068573655
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.3150190056
Short name T811
Test name
Test status
Simulation time 72408532 ps
CPU time 0.76 seconds
Started Aug 09 06:52:41 PM PDT 24
Finished Aug 09 06:52:41 PM PDT 24
Peak memory 207052 kb
Host smart-160a1ec1-c47c-4383-878d-49bfb087a78b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150190056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.3150190056
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.4052244600
Short name T985
Test name
Test status
Simulation time 15671701653 ps
CPU time 103.7 seconds
Started Aug 09 06:52:33 PM PDT 24
Finished Aug 09 06:54:17 PM PDT 24
Peak memory 233504 kb
Host smart-988a857b-15e2-4d2c-9f71-36a12f33059e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052244600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.4052244600
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.3816028852
Short name T634
Test name
Test status
Simulation time 6458792363 ps
CPU time 54.17 seconds
Started Aug 09 06:52:31 PM PDT 24
Finished Aug 09 06:53:25 PM PDT 24
Peak memory 241892 kb
Host smart-8005463e-bf9c-45c6-94fd-25fd42dd788a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816028852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.3816028852
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.1328739216
Short name T691
Test name
Test status
Simulation time 843334785 ps
CPU time 10.92 seconds
Started Aug 09 06:52:30 PM PDT 24
Finished Aug 09 06:52:41 PM PDT 24
Peak memory 218132 kb
Host smart-3c4a8240-5e65-45cf-82a1-55b86a8d0ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328739216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.1328739216
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.3907176097
Short name T471
Test name
Test status
Simulation time 1863836869 ps
CPU time 27.4 seconds
Started Aug 09 06:52:30 PM PDT 24
Finished Aug 09 06:52:58 PM PDT 24
Peak memory 241140 kb
Host smart-46790c02-f59d-4760-bc09-fa4429b01a86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907176097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.3907176097
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.883024456
Short name T1019
Test name
Test status
Simulation time 16565069124 ps
CPU time 121.55 seconds
Started Aug 09 06:52:29 PM PDT 24
Finished Aug 09 06:54:31 PM PDT 24
Peak memory 250508 kb
Host smart-d196eb12-9c0e-4b86-bdfe-34ad00005647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883024456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds.
883024456
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/3.spi_device_intercept.3039617693
Short name T745
Test name
Test status
Simulation time 11067314063 ps
CPU time 22.53 seconds
Started Aug 09 06:52:41 PM PDT 24
Finished Aug 09 06:53:04 PM PDT 24
Peak memory 225284 kb
Host smart-9bed92fa-5be6-4d59-93e2-17b4f107b1c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039617693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.3039617693
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.52697500
Short name T665
Test name
Test status
Simulation time 318536657 ps
CPU time 7.91 seconds
Started Aug 09 06:52:39 PM PDT 24
Finished Aug 09 06:52:47 PM PDT 24
Peak memory 225164 kb
Host smart-6d1c09f9-e637-4184-aa27-d5fcef1dd22f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52697500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.52697500
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.952562649
Short name T845
Test name
Test status
Simulation time 150642239 ps
CPU time 1.03 seconds
Started Aug 09 06:52:39 PM PDT 24
Finished Aug 09 06:52:40 PM PDT 24
Peak memory 218392 kb
Host smart-fde2f4d7-845b-48fe-8c20-ef338993fa34
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952562649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.spi_device_mem_parity.952562649
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.3465824176
Short name T308
Test name
Test status
Simulation time 4458283590 ps
CPU time 5.81 seconds
Started Aug 09 06:52:40 PM PDT 24
Finished Aug 09 06:52:46 PM PDT 24
Peak memory 233468 kb
Host smart-43c93c0e-8d44-4437-adfb-1e4bfd5a99a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465824176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.3465824176
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.2066704733
Short name T681
Test name
Test status
Simulation time 71123903284 ps
CPU time 15.27 seconds
Started Aug 09 06:52:40 PM PDT 24
Finished Aug 09 06:52:56 PM PDT 24
Peak memory 225256 kb
Host smart-d565cb85-f807-44dd-93ae-0b71be01d63c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066704733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.2066704733
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.2413138849
Short name T418
Test name
Test status
Simulation time 3404796105 ps
CPU time 11.11 seconds
Started Aug 09 06:52:40 PM PDT 24
Finished Aug 09 06:52:51 PM PDT 24
Peak memory 220960 kb
Host smart-1e9e879e-cf68-4dc9-87a0-4c225c762393
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2413138849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.2413138849
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.1134326242
Short name T65
Test name
Test status
Simulation time 1471463384 ps
CPU time 1.57 seconds
Started Aug 09 06:52:31 PM PDT 24
Finished Aug 09 06:52:33 PM PDT 24
Peak memory 235428 kb
Host smart-d60d73e9-ce81-4ce8-b864-42c258cbd76d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134326242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.1134326242
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.3096433985
Short name T268
Test name
Test status
Simulation time 90119363082 ps
CPU time 195.42 seconds
Started Aug 09 06:52:31 PM PDT 24
Finished Aug 09 06:55:46 PM PDT 24
Peak memory 250980 kb
Host smart-f66f37ba-e43d-4851-b725-d90c2d878df8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096433985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.3096433985
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.3328290326
Short name T334
Test name
Test status
Simulation time 6237871291 ps
CPU time 35.7 seconds
Started Aug 09 06:52:41 PM PDT 24
Finished Aug 09 06:53:17 PM PDT 24
Peak memory 217056 kb
Host smart-331b2c3e-af5b-43a1-8243-80dbacb653df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328290326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.3328290326
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.1480683226
Short name T652
Test name
Test status
Simulation time 8281985102 ps
CPU time 21.39 seconds
Started Aug 09 06:52:40 PM PDT 24
Finished Aug 09 06:53:02 PM PDT 24
Peak memory 217016 kb
Host smart-13653613-6dc8-4a19-84ae-a84fc20164be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480683226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.1480683226
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.3459631677
Short name T368
Test name
Test status
Simulation time 53842023 ps
CPU time 0.77 seconds
Started Aug 09 06:52:40 PM PDT 24
Finished Aug 09 06:52:41 PM PDT 24
Peak memory 206532 kb
Host smart-3411c8c3-8c6b-4bcc-be79-a5bae785e69a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459631677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.3459631677
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.1295311442
Short name T355
Test name
Test status
Simulation time 106751578 ps
CPU time 0.83 seconds
Started Aug 09 06:52:41 PM PDT 24
Finished Aug 09 06:52:42 PM PDT 24
Peak memory 206580 kb
Host smart-27644fb0-59ad-4e53-8959-4dd00c25d3bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295311442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.1295311442
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.504135348
Short name T256
Test name
Test status
Simulation time 3715255381 ps
CPU time 11.96 seconds
Started Aug 09 06:52:29 PM PDT 24
Finished Aug 09 06:52:42 PM PDT 24
Peak memory 233464 kb
Host smart-ca330af8-dbf2-485f-ba5e-2d6de26f41b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504135348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.504135348
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.719237329
Short name T806
Test name
Test status
Simulation time 43435986 ps
CPU time 0.73 seconds
Started Aug 09 06:56:25 PM PDT 24
Finished Aug 09 06:56:26 PM PDT 24
Peak memory 205828 kb
Host smart-4a1c843a-4c17-486d-91d5-cbf9c590e64c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719237329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.719237329
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.2211340686
Short name T737
Test name
Test status
Simulation time 1003388676 ps
CPU time 5.07 seconds
Started Aug 09 06:56:24 PM PDT 24
Finished Aug 09 06:56:30 PM PDT 24
Peak memory 225200 kb
Host smart-4921184f-e008-4357-92d7-82fe1dc4a705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211340686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.2211340686
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.2613636723
Short name T503
Test name
Test status
Simulation time 37665189 ps
CPU time 0.73 seconds
Started Aug 09 06:56:16 PM PDT 24
Finished Aug 09 06:56:17 PM PDT 24
Peak memory 206356 kb
Host smart-3d80e7cd-ae97-48bb-85ea-e347549d1b73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613636723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.2613636723
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.677171586
Short name T201
Test name
Test status
Simulation time 90780587054 ps
CPU time 161.33 seconds
Started Aug 09 06:56:23 PM PDT 24
Finished Aug 09 06:59:04 PM PDT 24
Peak memory 254928 kb
Host smart-5d538825-4bc8-4d9e-a082-7b64792ffa76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677171586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.677171586
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.709836347
Short name T733
Test name
Test status
Simulation time 167274631089 ps
CPU time 405.83 seconds
Started Aug 09 06:56:26 PM PDT 24
Finished Aug 09 07:03:12 PM PDT 24
Peak memory 255124 kb
Host smart-6a83e51d-fc60-4006-9a6c-96419d376bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709836347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.709836347
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.1029061240
Short name T890
Test name
Test status
Simulation time 20251544355 ps
CPU time 155.65 seconds
Started Aug 09 06:56:23 PM PDT 24
Finished Aug 09 06:58:59 PM PDT 24
Peak memory 249944 kb
Host smart-b3828c57-7a5d-4880-8789-609744ea09cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029061240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.1029061240
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.2465595647
Short name T1002
Test name
Test status
Simulation time 21584348451 ps
CPU time 30.86 seconds
Started Aug 09 06:56:23 PM PDT 24
Finished Aug 09 06:56:54 PM PDT 24
Peak memory 241740 kb
Host smart-5fe2ac45-2727-4203-b29c-addb68601c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465595647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.2465595647
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.1974143533
Short name T425
Test name
Test status
Simulation time 172553227 ps
CPU time 0.99 seconds
Started Aug 09 06:56:25 PM PDT 24
Finished Aug 09 06:56:27 PM PDT 24
Peak memory 216572 kb
Host smart-b0257ceb-424f-4591-b8c1-592fc7e991c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974143533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmd
s.1974143533
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/30.spi_device_intercept.786130552
Short name T193
Test name
Test status
Simulation time 15173010743 ps
CPU time 21.97 seconds
Started Aug 09 06:56:22 PM PDT 24
Finished Aug 09 06:56:44 PM PDT 24
Peak memory 233528 kb
Host smart-9fb9a362-67b1-4ae9-b97a-e6cf8edeb702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786130552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.786130552
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.3977086487
Short name T160
Test name
Test status
Simulation time 3335075076 ps
CPU time 40.09 seconds
Started Aug 09 06:56:23 PM PDT 24
Finished Aug 09 06:57:03 PM PDT 24
Peak memory 233552 kb
Host smart-f3733fb9-c890-4592-8bac-6616d1defc55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977086487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.3977086487
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.1137281561
Short name T635
Test name
Test status
Simulation time 1654411162 ps
CPU time 6.89 seconds
Started Aug 09 06:56:24 PM PDT 24
Finished Aug 09 06:56:31 PM PDT 24
Peak memory 233472 kb
Host smart-6e20fe48-9d3e-44f1-8456-1f9ef181cdd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137281561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.1137281561
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.1814778643
Short name T786
Test name
Test status
Simulation time 1174108502 ps
CPU time 5.66 seconds
Started Aug 09 06:56:22 PM PDT 24
Finished Aug 09 06:56:28 PM PDT 24
Peak memory 225124 kb
Host smart-66d6cdf7-9e10-46a7-9b75-c241b4dbb645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814778643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.1814778643
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.4113282763
Short name T56
Test name
Test status
Simulation time 788615336 ps
CPU time 4.63 seconds
Started Aug 09 06:56:24 PM PDT 24
Finished Aug 09 06:56:28 PM PDT 24
Peak memory 221332 kb
Host smart-3ac5c0a9-e32c-41dc-b94a-75982aa8d7fc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4113282763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.4113282763
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.1156990710
Short name T906
Test name
Test status
Simulation time 838840263 ps
CPU time 18.16 seconds
Started Aug 09 06:56:23 PM PDT 24
Finished Aug 09 06:56:41 PM PDT 24
Peak memory 250992 kb
Host smart-c3eddfd2-d34a-41c8-816d-cae80190af0f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156990710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.1156990710
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.1629375981
Short name T330
Test name
Test status
Simulation time 10667800826 ps
CPU time 27.56 seconds
Started Aug 09 06:56:15 PM PDT 24
Finished Aug 09 06:56:43 PM PDT 24
Peak memory 217084 kb
Host smart-c14d8fe2-8300-4c4f-bb7b-aa43f4600653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629375981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.1629375981
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.3795239741
Short name T156
Test name
Test status
Simulation time 1816831238 ps
CPU time 9.29 seconds
Started Aug 09 06:56:20 PM PDT 24
Finished Aug 09 06:56:29 PM PDT 24
Peak memory 216928 kb
Host smart-4b822926-e872-458c-9cfa-36d61d761ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795239741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.3795239741
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.1215410095
Short name T337
Test name
Test status
Simulation time 305750639 ps
CPU time 1.37 seconds
Started Aug 09 06:56:24 PM PDT 24
Finished Aug 09 06:56:26 PM PDT 24
Peak memory 216952 kb
Host smart-3c80ec97-c609-411d-8fc9-0e8dd5f67513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215410095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.1215410095
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.312368750
Short name T736
Test name
Test status
Simulation time 58037812 ps
CPU time 0.71 seconds
Started Aug 09 06:56:24 PM PDT 24
Finished Aug 09 06:56:25 PM PDT 24
Peak memory 206580 kb
Host smart-0af2f4d7-c36a-4bc1-89a6-30cd78fdbb2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312368750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.312368750
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.1344708776
Short name T756
Test name
Test status
Simulation time 1924953809 ps
CPU time 8.15 seconds
Started Aug 09 06:56:24 PM PDT 24
Finished Aug 09 06:56:32 PM PDT 24
Peak memory 233436 kb
Host smart-62e9b3db-43e1-41f5-8e54-970126bc5dbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344708776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.1344708776
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.2181443856
Short name T339
Test name
Test status
Simulation time 105929765 ps
CPU time 0.71 seconds
Started Aug 09 06:56:33 PM PDT 24
Finished Aug 09 06:56:34 PM PDT 24
Peak memory 205236 kb
Host smart-8dd69938-109b-4d9a-9826-288c2e19f050
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181443856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
2181443856
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.1626544517
Short name T636
Test name
Test status
Simulation time 220075469 ps
CPU time 4.57 seconds
Started Aug 09 06:56:22 PM PDT 24
Finished Aug 09 06:56:26 PM PDT 24
Peak memory 233428 kb
Host smart-a0e53453-54d2-4aa3-844c-b347c24608ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626544517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.1626544517
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.223201142
Short name T671
Test name
Test status
Simulation time 60367457 ps
CPU time 0.77 seconds
Started Aug 09 06:56:22 PM PDT 24
Finished Aug 09 06:56:22 PM PDT 24
Peak memory 207356 kb
Host smart-1431a035-bae5-4ca4-acb2-e5c8234ec16a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223201142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.223201142
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.1225514222
Short name T481
Test name
Test status
Simulation time 67229989190 ps
CPU time 122.77 seconds
Started Aug 09 06:56:31 PM PDT 24
Finished Aug 09 06:58:34 PM PDT 24
Peak memory 249836 kb
Host smart-b071ee4f-9914-42a0-8f39-fca418a3243d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225514222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.1225514222
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.3940565530
Short name T840
Test name
Test status
Simulation time 3801582505 ps
CPU time 87.39 seconds
Started Aug 09 06:56:31 PM PDT 24
Finished Aug 09 06:57:59 PM PDT 24
Peak memory 250984 kb
Host smart-5bd89b6c-cacb-4360-8f99-54d6ab915db9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940565530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.3940565530
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.384539816
Short name T888
Test name
Test status
Simulation time 82752531209 ps
CPU time 179.88 seconds
Started Aug 09 06:56:32 PM PDT 24
Finished Aug 09 06:59:32 PM PDT 24
Peak memory 249932 kb
Host smart-2d22723c-dd5e-474b-8232-54f0a430b51d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384539816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idle
.384539816
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.2170764469
Short name T310
Test name
Test status
Simulation time 229679944 ps
CPU time 5.89 seconds
Started Aug 09 06:56:24 PM PDT 24
Finished Aug 09 06:56:30 PM PDT 24
Peak memory 219488 kb
Host smart-46160274-d45b-4c05-9fbf-a8ff93e48903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170764469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.2170764469
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_intercept.3112392789
Short name T989
Test name
Test status
Simulation time 5408552676 ps
CPU time 13.32 seconds
Started Aug 09 06:56:24 PM PDT 24
Finished Aug 09 06:56:38 PM PDT 24
Peak memory 225264 kb
Host smart-3218b6a5-9442-4231-86e3-2a5db9705d21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112392789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.3112392789
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.2647099530
Short name T488
Test name
Test status
Simulation time 7356870152 ps
CPU time 18.02 seconds
Started Aug 09 06:56:22 PM PDT 24
Finished Aug 09 06:56:40 PM PDT 24
Peak memory 225316 kb
Host smart-b2610dca-c431-420b-b1b5-8db001ba36de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647099530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.2647099530
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.1832605415
Short name T543
Test name
Test status
Simulation time 1547268907 ps
CPU time 6.23 seconds
Started Aug 09 06:56:27 PM PDT 24
Finished Aug 09 06:56:33 PM PDT 24
Peak memory 225216 kb
Host smart-64f495b4-541d-4b86-823e-b04310ac7a13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832605415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.1832605415
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.38324516
Short name T826
Test name
Test status
Simulation time 49123498710 ps
CPU time 37.09 seconds
Started Aug 09 06:56:23 PM PDT 24
Finished Aug 09 06:57:00 PM PDT 24
Peak memory 249908 kb
Host smart-2a58a423-3453-47e3-9cd5-96cbc8d58866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38324516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.38324516
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.3185632393
Short name T554
Test name
Test status
Simulation time 2515837725 ps
CPU time 12.39 seconds
Started Aug 09 06:56:32 PM PDT 24
Finished Aug 09 06:56:45 PM PDT 24
Peak memory 219812 kb
Host smart-9a99e3f7-9e8c-4953-9bfb-9b044bdce192
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3185632393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.3185632393
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.3744859623
Short name T742
Test name
Test status
Simulation time 46542465 ps
CPU time 1.06 seconds
Started Aug 09 06:56:32 PM PDT 24
Finished Aug 09 06:56:33 PM PDT 24
Peak memory 207444 kb
Host smart-9df026e8-45fb-412a-86ca-4163f2caba18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744859623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.3744859623
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.3155365505
Short name T790
Test name
Test status
Simulation time 16250659274 ps
CPU time 27.81 seconds
Started Aug 09 06:56:26 PM PDT 24
Finished Aug 09 06:56:54 PM PDT 24
Peak memory 217060 kb
Host smart-bcaa5a2e-460a-44bd-aa19-b80e87595532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155365505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.3155365505
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.1097974631
Short name T537
Test name
Test status
Simulation time 14410778844 ps
CPU time 15.03 seconds
Started Aug 09 06:56:22 PM PDT 24
Finished Aug 09 06:56:37 PM PDT 24
Peak memory 217056 kb
Host smart-d414efe4-4734-4c9f-a0bd-f82016e9b66c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097974631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.1097974631
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.3085144506
Short name T492
Test name
Test status
Simulation time 24109603 ps
CPU time 0.89 seconds
Started Aug 09 06:56:23 PM PDT 24
Finished Aug 09 06:56:24 PM PDT 24
Peak memory 208532 kb
Host smart-c4f33df0-b1be-4dc3-9759-ba64f322996c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085144506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.3085144506
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.305377002
Short name T440
Test name
Test status
Simulation time 154902752 ps
CPU time 0.85 seconds
Started Aug 09 06:56:25 PM PDT 24
Finished Aug 09 06:56:26 PM PDT 24
Peak memory 206444 kb
Host smart-66a7bfee-2620-455c-8905-0c4d5ed1ac0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305377002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.305377002
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.1028101124
Short name T723
Test name
Test status
Simulation time 8568920759 ps
CPU time 12.18 seconds
Started Aug 09 06:56:23 PM PDT 24
Finished Aug 09 06:56:35 PM PDT 24
Peak memory 233492 kb
Host smart-40eb30d7-2215-4406-bbb3-e60421c83f29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028101124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.1028101124
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.4185788828
Short name T361
Test name
Test status
Simulation time 23559426 ps
CPU time 0.7 seconds
Started Aug 09 06:56:40 PM PDT 24
Finished Aug 09 06:56:41 PM PDT 24
Peak memory 205840 kb
Host smart-11771f0a-25a3-4117-849b-7bfd2691c874
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185788828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
4185788828
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.3913521849
Short name T448
Test name
Test status
Simulation time 6496759811 ps
CPU time 14.58 seconds
Started Aug 09 06:56:33 PM PDT 24
Finished Aug 09 06:56:48 PM PDT 24
Peak memory 225304 kb
Host smart-f9439d07-d8c8-4f77-b20a-30d758253400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913521849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.3913521849
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.3331361116
Short name T792
Test name
Test status
Simulation time 66570435 ps
CPU time 0.77 seconds
Started Aug 09 06:56:31 PM PDT 24
Finished Aug 09 06:56:32 PM PDT 24
Peak memory 207388 kb
Host smart-7014e486-993c-45bd-a442-da6ab354db16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331361116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.3331361116
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.2317129512
Short name T743
Test name
Test status
Simulation time 14264863612 ps
CPU time 100.2 seconds
Started Aug 09 06:56:33 PM PDT 24
Finished Aug 09 06:58:13 PM PDT 24
Peak memory 249936 kb
Host smart-db6ab42a-c59d-44ea-b09c-c9a1210cd5c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317129512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.2317129512
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.1182767748
Short name T738
Test name
Test status
Simulation time 7656629383 ps
CPU time 43.13 seconds
Started Aug 09 06:56:30 PM PDT 24
Finished Aug 09 06:57:14 PM PDT 24
Peak memory 249868 kb
Host smart-26c5f520-f858-40c9-8138-64866f8d8c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182767748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.1182767748
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.204710906
Short name T475
Test name
Test status
Simulation time 2928828086 ps
CPU time 20.35 seconds
Started Aug 09 06:56:33 PM PDT 24
Finished Aug 09 06:56:54 PM PDT 24
Peak memory 241696 kb
Host smart-9630a273-8f54-445a-bd9e-c3d351750f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204710906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idle
.204710906
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.4231573351
Short name T316
Test name
Test status
Simulation time 385925143 ps
CPU time 10.75 seconds
Started Aug 09 06:56:30 PM PDT 24
Finished Aug 09 06:56:40 PM PDT 24
Peak memory 236772 kb
Host smart-283ff4f0-a539-4518-bb0a-9eb324208e05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231573351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.4231573351
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.1694796836
Short name T307
Test name
Test status
Simulation time 3328698364 ps
CPU time 83.11 seconds
Started Aug 09 06:56:34 PM PDT 24
Finished Aug 09 06:57:57 PM PDT 24
Peak memory 256668 kb
Host smart-aa5e05c0-313d-4dc6-afa3-a9d44ac44c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694796836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmd
s.1694796836
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/32.spi_device_intercept.3233839483
Short name T591
Test name
Test status
Simulation time 1391324838 ps
CPU time 5.7 seconds
Started Aug 09 06:56:34 PM PDT 24
Finished Aug 09 06:56:40 PM PDT 24
Peak memory 225236 kb
Host smart-7c94d5e3-b034-4192-a588-163f0d4dbb8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233839483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.3233839483
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.1338092809
Short name T832
Test name
Test status
Simulation time 1292754646 ps
CPU time 20.89 seconds
Started Aug 09 06:56:30 PM PDT 24
Finished Aug 09 06:56:51 PM PDT 24
Peak memory 233500 kb
Host smart-323acc04-43e1-4cc5-badc-730af6549bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338092809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.1338092809
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.1340897875
Short name T556
Test name
Test status
Simulation time 3882284596 ps
CPU time 9.3 seconds
Started Aug 09 06:56:32 PM PDT 24
Finished Aug 09 06:56:41 PM PDT 24
Peak memory 249804 kb
Host smart-d2443461-23e4-4d02-b0ff-5f34dfe35555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340897875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.1340897875
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.697198222
Short name T865
Test name
Test status
Simulation time 17602105332 ps
CPU time 17.23 seconds
Started Aug 09 06:56:31 PM PDT 24
Finished Aug 09 06:56:48 PM PDT 24
Peak memory 234712 kb
Host smart-1c3b4fed-7a8f-49ae-ae18-3e500c075c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697198222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.697198222
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.2072173067
Short name T141
Test name
Test status
Simulation time 558864574 ps
CPU time 6.19 seconds
Started Aug 09 06:56:31 PM PDT 24
Finished Aug 09 06:56:38 PM PDT 24
Peak memory 220788 kb
Host smart-4d4adff6-94fe-47c2-91b2-3474b8c076a1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2072173067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.2072173067
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.45973688
Short name T212
Test name
Test status
Simulation time 157825401194 ps
CPU time 335.47 seconds
Started Aug 09 06:56:39 PM PDT 24
Finished Aug 09 07:02:15 PM PDT 24
Peak memory 262220 kb
Host smart-30ede46c-3489-4e8c-86d8-5bad40f5300a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45973688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stress
_all.45973688
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.3102519776
Short name T916
Test name
Test status
Simulation time 7064906369 ps
CPU time 41.13 seconds
Started Aug 09 06:56:32 PM PDT 24
Finished Aug 09 06:57:13 PM PDT 24
Peak memory 216968 kb
Host smart-2094fbe5-cd5b-4467-b4c7-b856cb235e34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102519776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.3102519776
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.4277104453
Short name T698
Test name
Test status
Simulation time 935321288 ps
CPU time 6.57 seconds
Started Aug 09 06:56:32 PM PDT 24
Finished Aug 09 06:56:38 PM PDT 24
Peak memory 216832 kb
Host smart-baee8334-4b05-4345-be14-9140346cd765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277104453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.4277104453
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.1067827652
Short name T957
Test name
Test status
Simulation time 54305434 ps
CPU time 0.76 seconds
Started Aug 09 06:56:32 PM PDT 24
Finished Aug 09 06:56:33 PM PDT 24
Peak memory 206492 kb
Host smart-51ef0802-21b7-44a1-b3a1-7b3fe29f9b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067827652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.1067827652
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.647925606
Short name T453
Test name
Test status
Simulation time 61931766 ps
CPU time 0.86 seconds
Started Aug 09 06:56:32 PM PDT 24
Finished Aug 09 06:56:33 PM PDT 24
Peak memory 206548 kb
Host smart-3ea57f9f-b4f2-4424-a32b-2ebd21a459fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647925606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.647925606
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.2227671860
Short name T576
Test name
Test status
Simulation time 18813509296 ps
CPU time 19.36 seconds
Started Aug 09 06:56:34 PM PDT 24
Finished Aug 09 06:56:53 PM PDT 24
Peak memory 225220 kb
Host smart-7493321c-0885-4a12-ad31-fb5a6eda9a5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227671860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.2227671860
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.143843249
Short name T749
Test name
Test status
Simulation time 36210188 ps
CPU time 0.7 seconds
Started Aug 09 06:56:39 PM PDT 24
Finished Aug 09 06:56:40 PM PDT 24
Peak memory 205868 kb
Host smart-a17d993b-b940-41ab-bb5b-92ae21531d0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143843249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.143843249
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.4254220869
Short name T278
Test name
Test status
Simulation time 2070710256 ps
CPU time 25.02 seconds
Started Aug 09 06:56:39 PM PDT 24
Finished Aug 09 06:57:04 PM PDT 24
Peak memory 233416 kb
Host smart-7b878a6a-401b-4701-bd12-1e40235518da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254220869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.4254220869
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.968102377
Short name T1021
Test name
Test status
Simulation time 32670340 ps
CPU time 0.79 seconds
Started Aug 09 06:56:42 PM PDT 24
Finished Aug 09 06:56:43 PM PDT 24
Peak memory 207032 kb
Host smart-ce2109ce-36d8-4b4d-82a2-23002f6c24e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968102377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.968102377
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.426766573
Short name T398
Test name
Test status
Simulation time 2009238237 ps
CPU time 5.03 seconds
Started Aug 09 06:56:39 PM PDT 24
Finished Aug 09 06:56:44 PM PDT 24
Peak memory 225124 kb
Host smart-5d29a931-0d27-4c8b-9a5c-6343d1eff3a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426766573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.426766573
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.1333027259
Short name T933
Test name
Test status
Simulation time 74399519832 ps
CPU time 230.12 seconds
Started Aug 09 06:56:40 PM PDT 24
Finished Aug 09 07:00:30 PM PDT 24
Peak memory 265300 kb
Host smart-0f30db18-83b1-40dd-8d04-ec6bad52df2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333027259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.1333027259
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.3281291639
Short name T627
Test name
Test status
Simulation time 1428174607 ps
CPU time 17.98 seconds
Started Aug 09 06:56:41 PM PDT 24
Finished Aug 09 06:56:59 PM PDT 24
Peak memory 223944 kb
Host smart-4ba3ec40-87e5-4b4f-9f07-bca9f8972e3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281291639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.3281291639
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.2786209558
Short name T311
Test name
Test status
Simulation time 281382786 ps
CPU time 6.54 seconds
Started Aug 09 06:56:40 PM PDT 24
Finished Aug 09 06:56:46 PM PDT 24
Peak memory 241612 kb
Host smart-ace71234-fb7e-4cf6-8038-a8407ca21570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786209558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.2786209558
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.2473956361
Short name T841
Test name
Test status
Simulation time 95318583915 ps
CPU time 206.48 seconds
Started Aug 09 06:56:40 PM PDT 24
Finished Aug 09 07:00:07 PM PDT 24
Peak memory 250896 kb
Host smart-667357d6-6ef3-464f-9526-dd1b741d0044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473956361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmd
s.2473956361
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/33.spi_device_intercept.3719539838
Short name T584
Test name
Test status
Simulation time 155967779 ps
CPU time 2.77 seconds
Started Aug 09 06:56:38 PM PDT 24
Finished Aug 09 06:56:41 PM PDT 24
Peak memory 225232 kb
Host smart-bf7ec44e-a117-49f2-8a6e-e032a732c595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719539838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.3719539838
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.1263344144
Short name T842
Test name
Test status
Simulation time 28690137 ps
CPU time 2.38 seconds
Started Aug 09 06:56:40 PM PDT 24
Finished Aug 09 06:56:42 PM PDT 24
Peak memory 233056 kb
Host smart-ce03be96-0df4-4c1f-bdfd-2e8926f5cf3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263344144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.1263344144
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.570374914
Short name T69
Test name
Test status
Simulation time 10608640579 ps
CPU time 26.39 seconds
Started Aug 09 06:56:40 PM PDT 24
Finished Aug 09 06:57:07 PM PDT 24
Peak memory 240336 kb
Host smart-9adeff14-f0ab-4ceb-a9d8-db67e1fecb5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570374914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swap
.570374914
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.2819105289
Short name T210
Test name
Test status
Simulation time 7909326973 ps
CPU time 12.78 seconds
Started Aug 09 06:56:39 PM PDT 24
Finished Aug 09 06:56:52 PM PDT 24
Peak memory 233500 kb
Host smart-04e5a6aa-254d-46b6-931c-cc8db99bf3a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819105289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.2819105289
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.948380897
Short name T704
Test name
Test status
Simulation time 493017399 ps
CPU time 7.44 seconds
Started Aug 09 06:56:39 PM PDT 24
Finished Aug 09 06:56:47 PM PDT 24
Peak memory 221040 kb
Host smart-63130190-0e0f-4f51-83f6-3eade2c53241
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=948380897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dire
ct.948380897
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.3528835469
Short name T545
Test name
Test status
Simulation time 442115954788 ps
CPU time 699.18 seconds
Started Aug 09 06:56:38 PM PDT 24
Finished Aug 09 07:08:17 PM PDT 24
Peak memory 270504 kb
Host smart-1e0dc26a-d18a-4afb-945f-aa73e650b806
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528835469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.3528835469
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.1103742811
Short name T1005
Test name
Test status
Simulation time 6563601715 ps
CPU time 33.26 seconds
Started Aug 09 06:56:39 PM PDT 24
Finished Aug 09 06:57:13 PM PDT 24
Peak memory 216944 kb
Host smart-a41e6236-528e-4cd6-8839-99b9df055007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103742811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.1103742811
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.1150496870
Short name T667
Test name
Test status
Simulation time 1967904364 ps
CPU time 1.65 seconds
Started Aug 09 06:56:40 PM PDT 24
Finished Aug 09 06:56:42 PM PDT 24
Peak memory 208460 kb
Host smart-e57676e8-a9a3-404a-aa66-baf054dc8b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150496870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.1150496870
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.56577964
Short name T936
Test name
Test status
Simulation time 13499005 ps
CPU time 0.72 seconds
Started Aug 09 06:56:41 PM PDT 24
Finished Aug 09 06:56:41 PM PDT 24
Peak memory 206064 kb
Host smart-dc507f20-6152-44ce-8e59-50bc5b93965b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56577964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.56577964
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.3396654084
Short name T731
Test name
Test status
Simulation time 64100201 ps
CPU time 0.88 seconds
Started Aug 09 06:56:41 PM PDT 24
Finished Aug 09 06:56:42 PM PDT 24
Peak memory 206512 kb
Host smart-6d9d7e8f-52b8-45ea-8a92-3b17f924d9ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396654084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.3396654084
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.3607355766
Short name T541
Test name
Test status
Simulation time 413414196 ps
CPU time 7.4 seconds
Started Aug 09 06:56:40 PM PDT 24
Finished Aug 09 06:56:48 PM PDT 24
Peak memory 241396 kb
Host smart-58f65e79-2215-41fd-8602-4ba3ef0cf96b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607355766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.3607355766
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.860313588
Short name T557
Test name
Test status
Simulation time 112914662 ps
CPU time 0.67 seconds
Started Aug 09 06:56:48 PM PDT 24
Finished Aug 09 06:56:49 PM PDT 24
Peak memory 206216 kb
Host smart-2abf5ba4-9dd8-4e94-ae96-25b4afd7e4b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860313588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.860313588
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.2971169474
Short name T910
Test name
Test status
Simulation time 753487105 ps
CPU time 5.25 seconds
Started Aug 09 06:56:48 PM PDT 24
Finished Aug 09 06:56:53 PM PDT 24
Peak memory 225204 kb
Host smart-bf89070d-669f-4d63-962b-aa75b176a203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971169474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.2971169474
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.2263924658
Short name T696
Test name
Test status
Simulation time 43375905 ps
CPU time 0.82 seconds
Started Aug 09 06:56:40 PM PDT 24
Finished Aug 09 06:56:41 PM PDT 24
Peak memory 206960 kb
Host smart-0ca238a8-f374-4559-a256-28e4c4cadc37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263924658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.2263924658
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.3394518929
Short name T154
Test name
Test status
Simulation time 3394322646 ps
CPU time 22.63 seconds
Started Aug 09 06:56:49 PM PDT 24
Finished Aug 09 06:57:12 PM PDT 24
Peak memory 250068 kb
Host smart-95221e2e-4123-49ce-aed4-f36ec53e129d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394518929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.3394518929
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.3062908436
Short name T1009
Test name
Test status
Simulation time 153600279738 ps
CPU time 389.2 seconds
Started Aug 09 06:56:46 PM PDT 24
Finished Aug 09 07:03:15 PM PDT 24
Peak memory 253152 kb
Host smart-7ac0da74-5911-45db-b6fa-3f6cf19c7bc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062908436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.3062908436
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.963689061
Short name T1025
Test name
Test status
Simulation time 1064528887 ps
CPU time 24.8 seconds
Started Aug 09 06:56:48 PM PDT 24
Finished Aug 09 06:57:13 PM PDT 24
Peak memory 240488 kb
Host smart-850c2f6c-9713-4f79-8653-712199d878e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963689061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.963689061
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.3682239150
Short name T48
Test name
Test status
Simulation time 85296040245 ps
CPU time 107.93 seconds
Started Aug 09 06:56:48 PM PDT 24
Finished Aug 09 06:58:36 PM PDT 24
Peak memory 250264 kb
Host smart-c21de403-0a28-4c26-a1c6-cca53e78dcab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682239150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmd
s.3682239150
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/34.spi_device_intercept.4223291176
Short name T976
Test name
Test status
Simulation time 1304497968 ps
CPU time 7.17 seconds
Started Aug 09 06:56:46 PM PDT 24
Finished Aug 09 06:56:53 PM PDT 24
Peak memory 233420 kb
Host smart-d14ad635-94f7-4207-9929-4803d2de71ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223291176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.4223291176
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.2387494329
Short name T686
Test name
Test status
Simulation time 341988951 ps
CPU time 6.37 seconds
Started Aug 09 06:56:48 PM PDT 24
Finished Aug 09 06:56:54 PM PDT 24
Peak memory 233372 kb
Host smart-f2fa3b84-f5b4-4fb4-b542-a5907bef0351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387494329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.2387494329
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.3913236160
Short name T656
Test name
Test status
Simulation time 141765171 ps
CPU time 2.7 seconds
Started Aug 09 06:56:48 PM PDT 24
Finished Aug 09 06:56:50 PM PDT 24
Peak memory 233396 kb
Host smart-24831788-50ff-46e0-b03d-34d113af7fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913236160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.3913236160
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.3015874105
Short name T414
Test name
Test status
Simulation time 2469126220 ps
CPU time 8.43 seconds
Started Aug 09 06:56:48 PM PDT 24
Finished Aug 09 06:56:57 PM PDT 24
Peak memory 225240 kb
Host smart-ef223889-8cfe-4d96-80b8-2144b7a9876c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015874105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.3015874105
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.2769592931
Short name T94
Test name
Test status
Simulation time 2324343124 ps
CPU time 9.07 seconds
Started Aug 09 06:56:47 PM PDT 24
Finished Aug 09 06:56:57 PM PDT 24
Peak memory 223448 kb
Host smart-4e7d7ee5-537a-40ef-b041-f303c3fb8e4f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2769592931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.2769592931
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.3503405953
Short name T290
Test name
Test status
Simulation time 162400582236 ps
CPU time 236.38 seconds
Started Aug 09 06:56:47 PM PDT 24
Finished Aug 09 07:00:44 PM PDT 24
Peak memory 265180 kb
Host smart-c451a140-7309-44c7-9ca0-78c56fe78a6c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503405953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.3503405953
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.2232919316
Short name T47
Test name
Test status
Simulation time 1273660701 ps
CPU time 11.5 seconds
Started Aug 09 06:56:38 PM PDT 24
Finished Aug 09 06:56:50 PM PDT 24
Peak memory 217284 kb
Host smart-84b3d44f-8ea3-4a50-baaf-4f70aba50d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232919316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.2232919316
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.2694260831
Short name T24
Test name
Test status
Simulation time 4771491661 ps
CPU time 7.2 seconds
Started Aug 09 06:56:40 PM PDT 24
Finished Aug 09 06:56:47 PM PDT 24
Peak memory 217048 kb
Host smart-4db0c8e2-5d77-4824-91ed-cfb1ee3fe0d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694260831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.2694260831
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.1310196627
Short name T544
Test name
Test status
Simulation time 13035778 ps
CPU time 0.72 seconds
Started Aug 09 06:56:43 PM PDT 24
Finished Aug 09 06:56:43 PM PDT 24
Peak memory 206088 kb
Host smart-cc0eb8c4-168b-4edc-8134-133c2f561ef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310196627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.1310196627
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.1326017976
Short name T859
Test name
Test status
Simulation time 17799106 ps
CPU time 0.77 seconds
Started Aug 09 06:56:40 PM PDT 24
Finished Aug 09 06:56:41 PM PDT 24
Peak memory 206556 kb
Host smart-9b5e625c-de97-4066-ad3a-abfb8f2d093e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326017976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.1326017976
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.1088901236
Short name T529
Test name
Test status
Simulation time 2685349429 ps
CPU time 4.14 seconds
Started Aug 09 06:56:48 PM PDT 24
Finished Aug 09 06:56:52 PM PDT 24
Peak memory 225280 kb
Host smart-4a6affae-714a-4c5c-9c97-d293cc7f702a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088901236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.1088901236
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.3261707750
Short name T739
Test name
Test status
Simulation time 32453403 ps
CPU time 0.7 seconds
Started Aug 09 06:56:55 PM PDT 24
Finished Aug 09 06:56:55 PM PDT 24
Peak memory 205276 kb
Host smart-57644ea2-71ab-4055-b18c-47160eee7dd8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261707750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
3261707750
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.1673252158
Short name T802
Test name
Test status
Simulation time 44192993 ps
CPU time 2.65 seconds
Started Aug 09 06:56:57 PM PDT 24
Finished Aug 09 06:57:00 PM PDT 24
Peak memory 233404 kb
Host smart-4eb87182-ca88-4e61-b1dc-806ab8b8df80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673252158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.1673252158
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.3451605751
Short name T408
Test name
Test status
Simulation time 17670034 ps
CPU time 0.78 seconds
Started Aug 09 06:56:46 PM PDT 24
Finished Aug 09 06:56:47 PM PDT 24
Peak memory 207016 kb
Host smart-446ac2a3-cccc-4bdf-bb6e-cf204c2c9c65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451605751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.3451605751
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.1807093113
Short name T348
Test name
Test status
Simulation time 600063526 ps
CPU time 12.03 seconds
Started Aug 09 06:56:57 PM PDT 24
Finished Aug 09 06:57:09 PM PDT 24
Peak memory 234552 kb
Host smart-81a7185d-c694-465d-889e-5b797d0d6120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807093113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.1807093113
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.1945581629
Short name T215
Test name
Test status
Simulation time 3571725402 ps
CPU time 66.65 seconds
Started Aug 09 06:56:58 PM PDT 24
Finished Aug 09 06:58:05 PM PDT 24
Peak memory 252912 kb
Host smart-b552772f-d1b8-4923-a5cf-7c5227f5c429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945581629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.1945581629
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.3613077529
Short name T769
Test name
Test status
Simulation time 8940495927 ps
CPU time 49.7 seconds
Started Aug 09 06:56:55 PM PDT 24
Finished Aug 09 06:57:45 PM PDT 24
Peak memory 241728 kb
Host smart-811347fc-4647-4a94-9ed7-96fece08a12b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613077529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.3613077529
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.208075145
Short name T893
Test name
Test status
Simulation time 114006694267 ps
CPU time 213.99 seconds
Started Aug 09 06:56:55 PM PDT 24
Finished Aug 09 07:00:29 PM PDT 24
Peak memory 254580 kb
Host smart-feda6e0c-c981-431c-953f-c2e17d75e713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208075145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmds
.208075145
Directory /workspace/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/35.spi_device_intercept.1916711500
Short name T252
Test name
Test status
Simulation time 493005633 ps
CPU time 5.88 seconds
Started Aug 09 06:56:50 PM PDT 24
Finished Aug 09 06:56:56 PM PDT 24
Peak memory 233412 kb
Host smart-4596712f-6acb-47a8-b72b-34bccdd5bde7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916711500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.1916711500
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.626234412
Short name T592
Test name
Test status
Simulation time 242628556 ps
CPU time 4.21 seconds
Started Aug 09 06:56:49 PM PDT 24
Finished Aug 09 06:56:53 PM PDT 24
Peak memory 225228 kb
Host smart-9a47fbe0-b304-4ab1-b995-d1cd6f452148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626234412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.626234412
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.1679405435
Short name T661
Test name
Test status
Simulation time 281502682 ps
CPU time 5.82 seconds
Started Aug 09 06:56:46 PM PDT 24
Finished Aug 09 06:56:52 PM PDT 24
Peak memory 233496 kb
Host smart-feccde14-aa49-45ad-ab2e-ef081e773f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679405435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.1679405435
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.2029907267
Short name T767
Test name
Test status
Simulation time 508241515 ps
CPU time 3.97 seconds
Started Aug 09 06:56:49 PM PDT 24
Finished Aug 09 06:56:53 PM PDT 24
Peak memory 219488 kb
Host smart-960922d4-a280-4e2b-83fc-182b16d04c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029907267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.2029907267
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.2326722178
Short name T891
Test name
Test status
Simulation time 3556522664 ps
CPU time 11.99 seconds
Started Aug 09 06:56:57 PM PDT 24
Finished Aug 09 06:57:09 PM PDT 24
Peak memory 222492 kb
Host smart-25a7e7c1-4b1f-46db-a6f8-567fd5c580e6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2326722178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.2326722178
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.399134479
Short name T53
Test name
Test status
Simulation time 31984549512 ps
CPU time 276.63 seconds
Started Aug 09 06:56:56 PM PDT 24
Finished Aug 09 07:01:33 PM PDT 24
Peak memory 273940 kb
Host smart-8b82d303-e83c-4c33-8059-9eee7b3adb41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399134479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stres
s_all.399134479
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.4283445019
Short name T452
Test name
Test status
Simulation time 4274947868 ps
CPU time 24.79 seconds
Started Aug 09 06:56:50 PM PDT 24
Finished Aug 09 06:57:15 PM PDT 24
Peak memory 217024 kb
Host smart-34a4b441-b6fa-45fc-ac3e-576d9c921f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283445019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.4283445019
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.3133309151
Short name T379
Test name
Test status
Simulation time 21902171419 ps
CPU time 10.7 seconds
Started Aug 09 06:56:47 PM PDT 24
Finished Aug 09 06:56:57 PM PDT 24
Peak memory 216964 kb
Host smart-c7b30a97-3415-49cb-aa29-6ab559e5d2d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133309151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.3133309151
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.1819012193
Short name T725
Test name
Test status
Simulation time 223774158 ps
CPU time 0.95 seconds
Started Aug 09 06:56:47 PM PDT 24
Finished Aug 09 06:56:48 PM PDT 24
Peak memory 207572 kb
Host smart-2941f11c-e53d-4dd7-b44b-aae70aaefd10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819012193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.1819012193
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.1147065435
Short name T801
Test name
Test status
Simulation time 13759812 ps
CPU time 0.69 seconds
Started Aug 09 06:56:49 PM PDT 24
Finished Aug 09 06:56:50 PM PDT 24
Peak memory 206572 kb
Host smart-bdeb86c4-f624-42e6-852c-e94a5178d1de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147065435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.1147065435
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.2406156011
Short name T555
Test name
Test status
Simulation time 3827874619 ps
CPU time 8 seconds
Started Aug 09 06:56:48 PM PDT 24
Finished Aug 09 06:56:56 PM PDT 24
Peak memory 225228 kb
Host smart-c993eacc-cccd-42e4-8fc1-d3383121df9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406156011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.2406156011
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.2543298956
Short name T897
Test name
Test status
Simulation time 33277359 ps
CPU time 0.73 seconds
Started Aug 09 06:57:06 PM PDT 24
Finished Aug 09 06:57:07 PM PDT 24
Peak memory 205244 kb
Host smart-d6d2d8ca-95bf-442e-bf12-73c513b42c09
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543298956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
2543298956
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.3908570984
Short name T244
Test name
Test status
Simulation time 983415767 ps
CPU time 10.73 seconds
Started Aug 09 06:56:58 PM PDT 24
Finished Aug 09 06:57:08 PM PDT 24
Peak memory 233388 kb
Host smart-823ef8c7-9d2c-474c-be73-b410cbf5d690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908570984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.3908570984
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.111611444
Short name T461
Test name
Test status
Simulation time 24072352 ps
CPU time 0.81 seconds
Started Aug 09 06:56:58 PM PDT 24
Finished Aug 09 06:56:59 PM PDT 24
Peak memory 207080 kb
Host smart-372de912-a183-4442-8175-6e50faeb2223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111611444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.111611444
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.2103332950
Short name T200
Test name
Test status
Simulation time 2552598273 ps
CPU time 23.2 seconds
Started Aug 09 06:56:56 PM PDT 24
Finished Aug 09 06:57:19 PM PDT 24
Peak memory 236956 kb
Host smart-cb251c87-19d6-47d2-8a43-2a759d6073ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103332950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.2103332950
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.1026675555
Short name T782
Test name
Test status
Simulation time 2474225531 ps
CPU time 50.84 seconds
Started Aug 09 06:56:58 PM PDT 24
Finished Aug 09 06:57:49 PM PDT 24
Peak memory 253356 kb
Host smart-c1b40332-e2ec-4dbb-92bb-364b045a3866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026675555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.1026675555
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.3984864560
Short name T873
Test name
Test status
Simulation time 696837441 ps
CPU time 5.74 seconds
Started Aug 09 06:56:56 PM PDT 24
Finished Aug 09 06:57:02 PM PDT 24
Peak memory 225260 kb
Host smart-deaefeb2-40d9-47f7-9266-c3563c5093fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984864560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.3984864560
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.2274403050
Short name T299
Test name
Test status
Simulation time 5675563233 ps
CPU time 38.15 seconds
Started Aug 09 06:56:56 PM PDT 24
Finished Aug 09 06:57:35 PM PDT 24
Peak memory 255608 kb
Host smart-af769ec1-acb0-4ae2-84be-91f247089689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274403050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmd
s.2274403050
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_intercept.3242069748
Short name T192
Test name
Test status
Simulation time 2719436332 ps
CPU time 10.5 seconds
Started Aug 09 06:56:57 PM PDT 24
Finished Aug 09 06:57:08 PM PDT 24
Peak memory 225300 kb
Host smart-0c54d9b9-af25-4819-91a1-7d9fcef88f5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242069748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.3242069748
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.4015435687
Short name T658
Test name
Test status
Simulation time 1980289237 ps
CPU time 4.72 seconds
Started Aug 09 06:56:56 PM PDT 24
Finished Aug 09 06:57:01 PM PDT 24
Peak memory 233464 kb
Host smart-8c853e61-0876-4622-b921-8d0153febe00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015435687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.4015435687
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.868386327
Short name T301
Test name
Test status
Simulation time 11047801538 ps
CPU time 17.78 seconds
Started Aug 09 06:56:55 PM PDT 24
Finished Aug 09 06:57:13 PM PDT 24
Peak memory 241580 kb
Host smart-5f5c0e66-7d3a-4209-8c95-ff921afee737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868386327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swap
.868386327
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.1542325249
Short name T249
Test name
Test status
Simulation time 777037942 ps
CPU time 4.82 seconds
Started Aug 09 06:56:57 PM PDT 24
Finished Aug 09 06:57:01 PM PDT 24
Peak memory 241296 kb
Host smart-6ca3a63d-202d-4caa-9069-4843b8e000ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542325249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.1542325249
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.1441988597
Short name T412
Test name
Test status
Simulation time 135994001 ps
CPU time 4.23 seconds
Started Aug 09 06:56:55 PM PDT 24
Finished Aug 09 06:56:59 PM PDT 24
Peak memory 220808 kb
Host smart-4aaaa0c0-6fc7-43a6-b3c5-94da9eb7817e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1441988597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.1441988597
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.2771612733
Short name T768
Test name
Test status
Simulation time 6520473246 ps
CPU time 110.9 seconds
Started Aug 09 06:57:06 PM PDT 24
Finished Aug 09 06:58:57 PM PDT 24
Peak memory 258068 kb
Host smart-24427604-0195-4ab4-8bfd-3a1ef2801f6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771612733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.2771612733
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.3513106203
Short name T470
Test name
Test status
Simulation time 973901627 ps
CPU time 13.54 seconds
Started Aug 09 06:56:58 PM PDT 24
Finished Aug 09 06:57:11 PM PDT 24
Peak memory 217312 kb
Host smart-0e007e69-644b-4bc6-9f69-5e18b4c36bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513106203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.3513106203
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.2047901701
Short name T9
Test name
Test status
Simulation time 27073019909 ps
CPU time 16.55 seconds
Started Aug 09 06:56:57 PM PDT 24
Finished Aug 09 06:57:14 PM PDT 24
Peak memory 216988 kb
Host smart-33c4c7e6-88ce-44a5-b04f-dfffd6eac1ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047901701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.2047901701
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.3657301280
Short name T663
Test name
Test status
Simulation time 159400547 ps
CPU time 1.09 seconds
Started Aug 09 06:56:55 PM PDT 24
Finished Aug 09 06:56:56 PM PDT 24
Peak memory 207572 kb
Host smart-80c20c0c-555e-41f4-9935-f66e9e49460d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657301280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.3657301280
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.342493173
Short name T161
Test name
Test status
Simulation time 115891497 ps
CPU time 0.94 seconds
Started Aug 09 06:56:54 PM PDT 24
Finished Aug 09 06:56:55 PM PDT 24
Peak memory 206548 kb
Host smart-d4f3faf5-902d-4e41-b114-fd6102f75886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342493173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.342493173
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.499110281
Short name T668
Test name
Test status
Simulation time 20525835794 ps
CPU time 16.07 seconds
Started Aug 09 06:56:55 PM PDT 24
Finished Aug 09 06:57:11 PM PDT 24
Peak memory 225208 kb
Host smart-7cb3e1e6-61b8-4176-a596-c92c100bf452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499110281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.499110281
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.1952080142
Short name T5
Test name
Test status
Simulation time 11953545 ps
CPU time 0.71 seconds
Started Aug 09 06:57:07 PM PDT 24
Finished Aug 09 06:57:08 PM PDT 24
Peak memory 205240 kb
Host smart-7a196952-8166-4266-9e8d-2852792c00ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952080142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
1952080142
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.3227060448
Short name T929
Test name
Test status
Simulation time 182253829 ps
CPU time 2.65 seconds
Started Aug 09 06:57:06 PM PDT 24
Finished Aug 09 06:57:08 PM PDT 24
Peak memory 233428 kb
Host smart-b2260136-7f58-4741-a0c6-f4a540225095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227060448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.3227060448
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.726195272
Short name T60
Test name
Test status
Simulation time 86807159 ps
CPU time 0.77 seconds
Started Aug 09 06:57:06 PM PDT 24
Finished Aug 09 06:57:07 PM PDT 24
Peak memory 207064 kb
Host smart-cc333711-67f2-4cf5-bb38-05027f36f36a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726195272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.726195272
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.3350123517
Short name T222
Test name
Test status
Simulation time 67108949957 ps
CPU time 242.93 seconds
Started Aug 09 06:57:05 PM PDT 24
Finished Aug 09 07:01:08 PM PDT 24
Peak memory 254712 kb
Host smart-0b2cf3ba-7ea1-4ffc-9dc9-1a9dd883e00a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350123517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.3350123517
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.3098114310
Short name T575
Test name
Test status
Simulation time 76523837611 ps
CPU time 150.5 seconds
Started Aug 09 06:57:05 PM PDT 24
Finished Aug 09 06:59:36 PM PDT 24
Peak memory 253700 kb
Host smart-b7cc7530-6d7e-4a7c-aa61-f25c4e31abbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098114310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.3098114310
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.1447488821
Short name T300
Test name
Test status
Simulation time 172092779172 ps
CPU time 376.37 seconds
Started Aug 09 06:57:07 PM PDT 24
Finished Aug 09 07:03:23 PM PDT 24
Peak memory 264456 kb
Host smart-573bd35b-822a-4b31-9e71-b6e765807a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447488821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.1447488821
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.3706905157
Short name T479
Test name
Test status
Simulation time 13796479993 ps
CPU time 27.91 seconds
Started Aug 09 06:57:05 PM PDT 24
Finished Aug 09 06:57:33 PM PDT 24
Peak memory 250604 kb
Host smart-c7ebb2be-1ad4-4b2b-86e1-1cac57460a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706905157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.3706905157
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.3531926796
Short name T225
Test name
Test status
Simulation time 52804880075 ps
CPU time 152.17 seconds
Started Aug 09 06:57:05 PM PDT 24
Finished Aug 09 06:59:37 PM PDT 24
Peak memory 249888 kb
Host smart-bcfa783b-afde-4d12-b196-94cc5f3f7524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531926796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmd
s.3531926796
Directory /workspace/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/37.spi_device_intercept.2201366406
Short name T941
Test name
Test status
Simulation time 752755134 ps
CPU time 7.51 seconds
Started Aug 09 06:57:05 PM PDT 24
Finished Aug 09 06:57:12 PM PDT 24
Peak memory 225088 kb
Host smart-c74c766a-69d7-4afa-a5ea-f73351e8bfb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201366406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.2201366406
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.812447965
Short name T80
Test name
Test status
Simulation time 18253994396 ps
CPU time 26.15 seconds
Started Aug 09 06:57:04 PM PDT 24
Finished Aug 09 06:57:31 PM PDT 24
Peak memory 239524 kb
Host smart-3b57bb87-4374-498e-88bf-fb256753cb5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812447965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.812447965
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.731356394
Short name T640
Test name
Test status
Simulation time 449521628 ps
CPU time 8.54 seconds
Started Aug 09 06:57:06 PM PDT 24
Finished Aug 09 06:57:15 PM PDT 24
Peak memory 249572 kb
Host smart-54ce7f76-b35c-48d8-a0b3-6f604d0d1ef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731356394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swap
.731356394
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.1491890843
Short name T899
Test name
Test status
Simulation time 896079999 ps
CPU time 8.37 seconds
Started Aug 09 06:57:07 PM PDT 24
Finished Aug 09 06:57:15 PM PDT 24
Peak memory 241536 kb
Host smart-93fe3004-2237-4963-9955-af7554b441c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491890843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.1491890843
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.3704874563
Short name T766
Test name
Test status
Simulation time 619967677 ps
CPU time 3.69 seconds
Started Aug 09 06:57:08 PM PDT 24
Finished Aug 09 06:57:12 PM PDT 24
Peak memory 219944 kb
Host smart-137b8339-d84d-47b4-840d-8b860100a689
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3704874563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.3704874563
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.3222368631
Short name T319
Test name
Test status
Simulation time 809014876 ps
CPU time 11.09 seconds
Started Aug 09 06:57:05 PM PDT 24
Finished Aug 09 06:57:16 PM PDT 24
Peak memory 220072 kb
Host smart-d487673e-385d-48d0-ab6c-8cd4d05fb08b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222368631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.3222368631
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.183247419
Short name T462
Test name
Test status
Simulation time 2808510261 ps
CPU time 8.63 seconds
Started Aug 09 06:57:07 PM PDT 24
Finished Aug 09 06:57:15 PM PDT 24
Peak memory 217052 kb
Host smart-57d03503-5a7b-4ab2-a196-293e3dc6d864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183247419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.183247419
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.1413896
Short name T677
Test name
Test status
Simulation time 70823207 ps
CPU time 1.19 seconds
Started Aug 09 06:57:06 PM PDT 24
Finished Aug 09 06:57:07 PM PDT 24
Peak memory 216928 kb
Host smart-f8a1c35d-cefa-4d1d-90ae-af20bf6a4754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.1413896
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.2115669358
Short name T963
Test name
Test status
Simulation time 101178299 ps
CPU time 0.83 seconds
Started Aug 09 06:57:07 PM PDT 24
Finished Aug 09 06:57:08 PM PDT 24
Peak memory 206560 kb
Host smart-4c6cdb59-112b-4e19-83a5-f277d9fc330a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115669358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.2115669358
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.1613856057
Short name T889
Test name
Test status
Simulation time 1164348998 ps
CPU time 6.99 seconds
Started Aug 09 06:57:05 PM PDT 24
Finished Aug 09 06:57:12 PM PDT 24
Peak memory 233504 kb
Host smart-87e9205f-9e7f-40f8-befe-50848d5846e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613856057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.1613856057
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.4143509208
Short name T930
Test name
Test status
Simulation time 13869709 ps
CPU time 0.73 seconds
Started Aug 09 06:57:17 PM PDT 24
Finished Aug 09 06:57:18 PM PDT 24
Peak memory 205772 kb
Host smart-0c622f02-8914-47ad-9203-4bda7b0630c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143509208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
4143509208
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.2407454355
Short name T1013
Test name
Test status
Simulation time 589785942 ps
CPU time 3.37 seconds
Started Aug 09 06:57:18 PM PDT 24
Finished Aug 09 06:57:21 PM PDT 24
Peak memory 225272 kb
Host smart-ee23aece-d676-4b6e-9812-09f1b74c2918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407454355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.2407454355
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.1274089803
Short name T509
Test name
Test status
Simulation time 13472887 ps
CPU time 0.75 seconds
Started Aug 09 06:57:05 PM PDT 24
Finished Aug 09 06:57:06 PM PDT 24
Peak memory 207064 kb
Host smart-7ec57aa2-6923-4986-ab53-c6d078c1f403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274089803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.1274089803
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.2566320241
Short name T755
Test name
Test status
Simulation time 142012483589 ps
CPU time 112.33 seconds
Started Aug 09 06:57:15 PM PDT 24
Finished Aug 09 06:59:08 PM PDT 24
Peak memory 250208 kb
Host smart-a276c423-1c73-48ff-94a1-7d6ff6e4381f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566320241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.2566320241
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.3161670366
Short name T248
Test name
Test status
Simulation time 9879062708 ps
CPU time 37.94 seconds
Started Aug 09 06:57:17 PM PDT 24
Finished Aug 09 06:57:55 PM PDT 24
Peak memory 239944 kb
Host smart-1e3fa0d1-164f-4c14-a2d0-4b98d2d27e76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161670366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.3161670366
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.1973992415
Short name T931
Test name
Test status
Simulation time 3394730154 ps
CPU time 78.95 seconds
Started Aug 09 06:57:16 PM PDT 24
Finished Aug 09 06:58:35 PM PDT 24
Peak memory 261880 kb
Host smart-b1468975-f0c1-4795-875e-5657ada7fe09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973992415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.1973992415
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.2178702114
Short name T127
Test name
Test status
Simulation time 81643200 ps
CPU time 3.08 seconds
Started Aug 09 06:57:16 PM PDT 24
Finished Aug 09 06:57:19 PM PDT 24
Peak memory 233476 kb
Host smart-66ee6750-11ab-490f-b9e5-6b9aa948a88b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178702114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.2178702114
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.206948361
Short name T185
Test name
Test status
Simulation time 19781717803 ps
CPU time 76.36 seconds
Started Aug 09 06:57:15 PM PDT 24
Finished Aug 09 06:58:31 PM PDT 24
Peak memory 250968 kb
Host smart-16f860c3-d30f-4954-9528-44506b3de5e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206948361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmds
.206948361
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/38.spi_device_intercept.3482370717
Short name T219
Test name
Test status
Simulation time 407330050 ps
CPU time 6.3 seconds
Started Aug 09 06:57:17 PM PDT 24
Finished Aug 09 06:57:23 PM PDT 24
Peak memory 228700 kb
Host smart-fe1d5349-3c9b-484b-bed8-0ede7b2be6d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482370717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.3482370717
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.739342296
Short name T155
Test name
Test status
Simulation time 324873662 ps
CPU time 3.52 seconds
Started Aug 09 06:57:16 PM PDT 24
Finished Aug 09 06:57:19 PM PDT 24
Peak memory 233352 kb
Host smart-9027706b-bca7-4c41-83ec-c53cb794cdcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739342296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.739342296
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.309320516
Short name T304
Test name
Test status
Simulation time 20431602288 ps
CPU time 10.66 seconds
Started Aug 09 06:57:16 PM PDT 24
Finished Aug 09 06:57:27 PM PDT 24
Peak memory 249436 kb
Host smart-d4ad1e60-85bc-4b39-b62b-1b882ec6163f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309320516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swap
.309320516
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.1927720911
Short name T628
Test name
Test status
Simulation time 10646648258 ps
CPU time 11.92 seconds
Started Aug 09 06:57:18 PM PDT 24
Finished Aug 09 06:57:29 PM PDT 24
Peak memory 233508 kb
Host smart-17512cb7-1139-4c5e-bce5-50250c446bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927720911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.1927720911
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.2707652250
Short name T917
Test name
Test status
Simulation time 2198897847 ps
CPU time 4.85 seconds
Started Aug 09 06:57:17 PM PDT 24
Finished Aug 09 06:57:22 PM PDT 24
Peak memory 219760 kb
Host smart-58c2d85e-4205-45a0-9844-e10d3d7d87b0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2707652250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.2707652250
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.725343782
Short name T867
Test name
Test status
Simulation time 40758463048 ps
CPU time 117.07 seconds
Started Aug 09 06:57:16 PM PDT 24
Finished Aug 09 06:59:13 PM PDT 24
Peak memory 251008 kb
Host smart-60377405-b7d0-4f16-98e3-8df5a93e5593
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725343782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stres
s_all.725343782
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.3025869463
Short name T807
Test name
Test status
Simulation time 32357355131 ps
CPU time 45.98 seconds
Started Aug 09 06:57:16 PM PDT 24
Finished Aug 09 06:58:02 PM PDT 24
Peak memory 217012 kb
Host smart-41086ce2-d74d-4816-9c82-06841eace9d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025869463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.3025869463
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.4234443697
Short name T377
Test name
Test status
Simulation time 19341777710 ps
CPU time 11.66 seconds
Started Aug 09 06:57:07 PM PDT 24
Finished Aug 09 06:57:18 PM PDT 24
Peak memory 217056 kb
Host smart-55e4f0f1-da39-417e-bc6b-413c79dad01a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234443697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.4234443697
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.4256015477
Short name T762
Test name
Test status
Simulation time 66079254 ps
CPU time 1.16 seconds
Started Aug 09 06:57:14 PM PDT 24
Finished Aug 09 06:57:15 PM PDT 24
Peak memory 216952 kb
Host smart-9aa35c85-b228-432d-9f42-e20e491ef531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256015477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.4256015477
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.2487145469
Short name T581
Test name
Test status
Simulation time 170774167 ps
CPU time 0.89 seconds
Started Aug 09 06:57:19 PM PDT 24
Finished Aug 09 06:57:20 PM PDT 24
Peak memory 206576 kb
Host smart-1ddc1901-0e41-4667-9964-3aa0a854fe07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487145469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.2487145469
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.1050097802
Short name T506
Test name
Test status
Simulation time 140934739 ps
CPU time 2.32 seconds
Started Aug 09 06:57:19 PM PDT 24
Finished Aug 09 06:57:21 PM PDT 24
Peak memory 224844 kb
Host smart-4bd9c461-7c56-4797-84bf-99e603397834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050097802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.1050097802
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.608643206
Short name T364
Test name
Test status
Simulation time 42132612 ps
CPU time 0.7 seconds
Started Aug 09 06:57:28 PM PDT 24
Finished Aug 09 06:57:28 PM PDT 24
Peak memory 205844 kb
Host smart-ec96d3ec-9ce6-48d7-9cf0-58505a21be78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608643206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.608643206
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.3742105393
Short name T602
Test name
Test status
Simulation time 493082514 ps
CPU time 2.98 seconds
Started Aug 09 06:57:25 PM PDT 24
Finished Aug 09 06:57:28 PM PDT 24
Peak memory 225272 kb
Host smart-6456e90d-a018-4344-8a34-0faf7d1a92b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742105393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.3742105393
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.2854106739
Short name T784
Test name
Test status
Simulation time 23138415 ps
CPU time 0.79 seconds
Started Aug 09 06:57:18 PM PDT 24
Finished Aug 09 06:57:19 PM PDT 24
Peak memory 207380 kb
Host smart-1358d9ce-a522-4c0e-ade9-9ad6a3407d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854106739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.2854106739
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.4032085666
Short name T460
Test name
Test status
Simulation time 2220296446 ps
CPU time 44.93 seconds
Started Aug 09 06:57:25 PM PDT 24
Finished Aug 09 06:58:10 PM PDT 24
Peak memory 253624 kb
Host smart-c57bd2b6-0b76-4aee-8de9-0940b942eea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032085666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.4032085666
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.58270990
Short name T296
Test name
Test status
Simulation time 442157522392 ps
CPU time 257.97 seconds
Started Aug 09 06:57:27 PM PDT 24
Finished Aug 09 07:01:45 PM PDT 24
Peak memory 265840 kb
Host smart-b7c29359-5fab-4737-affd-eb2f940f5b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58270990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.58270990
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.1119533592
Short name T242
Test name
Test status
Simulation time 5009827439 ps
CPU time 78.42 seconds
Started Aug 09 06:57:27 PM PDT 24
Finished Aug 09 06:58:45 PM PDT 24
Peak memory 251260 kb
Host smart-47ac6292-29f1-497d-878c-b256ce7174ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119533592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.1119533592
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.1279594582
Short name T318
Test name
Test status
Simulation time 3700914645 ps
CPU time 17.86 seconds
Started Aug 09 06:57:27 PM PDT 24
Finished Aug 09 06:57:45 PM PDT 24
Peak memory 241436 kb
Host smart-7f7297f3-da9b-4e5b-9453-b0e2a06299b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279594582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.1279594582
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.1233664323
Short name T335
Test name
Test status
Simulation time 256130807 ps
CPU time 0.99 seconds
Started Aug 09 06:57:25 PM PDT 24
Finished Aug 09 06:57:27 PM PDT 24
Peak memory 216700 kb
Host smart-71787b48-e408-43e2-b24a-0c867f624545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233664323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmd
s.1233664323
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/39.spi_device_intercept.3118335820
Short name T631
Test name
Test status
Simulation time 18897010452 ps
CPU time 34.62 seconds
Started Aug 09 06:57:16 PM PDT 24
Finished Aug 09 06:57:51 PM PDT 24
Peak memory 233436 kb
Host smart-14617051-33ed-44cd-b5aa-6908b7a7a56b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118335820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.3118335820
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.1519954541
Short name T630
Test name
Test status
Simulation time 12715531427 ps
CPU time 33.62 seconds
Started Aug 09 06:57:28 PM PDT 24
Finished Aug 09 06:58:02 PM PDT 24
Peak memory 241420 kb
Host smart-5f4b6354-484f-445c-aa1c-ff5fd2921db0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519954541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.1519954541
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.1190415172
Short name T294
Test name
Test status
Simulation time 531222098 ps
CPU time 4.16 seconds
Started Aug 09 06:57:16 PM PDT 24
Finished Aug 09 06:57:20 PM PDT 24
Peak memory 233440 kb
Host smart-08bac406-2ade-416e-828b-71891f136c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190415172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.1190415172
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.902700189
Short name T810
Test name
Test status
Simulation time 4173661193 ps
CPU time 12.12 seconds
Started Aug 09 06:57:18 PM PDT 24
Finished Aug 09 06:57:30 PM PDT 24
Peak memory 219644 kb
Host smart-5ce34310-546e-413e-9516-d7242db12afb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902700189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.902700189
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.236444325
Short name T564
Test name
Test status
Simulation time 433851244 ps
CPU time 4.32 seconds
Started Aug 09 06:57:25 PM PDT 24
Finished Aug 09 06:57:29 PM PDT 24
Peak memory 220736 kb
Host smart-4b171c4d-f9b1-4a73-a1a9-677b03d7daaa
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=236444325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dire
ct.236444325
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.1346249269
Short name T409
Test name
Test status
Simulation time 35505223903 ps
CPU time 43.84 seconds
Started Aug 09 06:57:18 PM PDT 24
Finished Aug 09 06:58:02 PM PDT 24
Peak memory 217012 kb
Host smart-3fb92bc4-f1a5-4cbc-931f-a934cc8ab986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346249269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.1346249269
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.1352304134
Short name T878
Test name
Test status
Simulation time 9867441032 ps
CPU time 9.4 seconds
Started Aug 09 06:57:16 PM PDT 24
Finished Aug 09 06:57:26 PM PDT 24
Peak memory 217024 kb
Host smart-68d57992-a5c2-4733-9733-b5fc005487e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352304134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.1352304134
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.874424528
Short name T981
Test name
Test status
Simulation time 54789462 ps
CPU time 1.05 seconds
Started Aug 09 06:57:17 PM PDT 24
Finished Aug 09 06:57:18 PM PDT 24
Peak memory 208540 kb
Host smart-289dfb75-99e0-45ff-8d61-f57b8e9d2dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874424528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.874424528
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.1951046393
Short name T343
Test name
Test status
Simulation time 29152279 ps
CPU time 0.73 seconds
Started Aug 09 06:57:16 PM PDT 24
Finished Aug 09 06:57:17 PM PDT 24
Peak memory 206548 kb
Host smart-9796f7aa-2533-4f0b-b4a9-4e1922ccc743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951046393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.1951046393
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.1080572396
Short name T876
Test name
Test status
Simulation time 321888064 ps
CPU time 2.51 seconds
Started Aug 09 06:57:26 PM PDT 24
Finished Aug 09 06:57:29 PM PDT 24
Peak memory 225260 kb
Host smart-03a8f35d-9df4-4b19-8b4d-286d1e592b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080572396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.1080572396
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.4275456905
Short name T376
Test name
Test status
Simulation time 43826317 ps
CPU time 0.75 seconds
Started Aug 09 06:53:02 PM PDT 24
Finished Aug 09 06:53:03 PM PDT 24
Peak memory 205868 kb
Host smart-50beb2ce-5217-432b-aca3-b6b49de2178f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275456905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.4
275456905
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.1884488388
Short name T674
Test name
Test status
Simulation time 1731159479 ps
CPU time 6.96 seconds
Started Aug 09 06:52:50 PM PDT 24
Finished Aug 09 06:52:57 PM PDT 24
Peak memory 225188 kb
Host smart-5a28c6a7-e80e-411a-89f5-5854b88a195c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884488388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.1884488388
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.673366541
Short name T839
Test name
Test status
Simulation time 18169932 ps
CPU time 0.8 seconds
Started Aug 09 06:53:19 PM PDT 24
Finished Aug 09 06:53:20 PM PDT 24
Peak memory 207068 kb
Host smart-404ca435-ef52-473b-af9b-1c229cf1c103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673366541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.673366541
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.726678129
Short name T789
Test name
Test status
Simulation time 49607923781 ps
CPU time 58.22 seconds
Started Aug 09 06:52:49 PM PDT 24
Finished Aug 09 06:53:47 PM PDT 24
Peak memory 252332 kb
Host smart-689e0964-176d-47ca-aec4-9175debb456e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726678129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.726678129
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.615191095
Short name T741
Test name
Test status
Simulation time 17211972702 ps
CPU time 116.74 seconds
Started Aug 09 06:53:01 PM PDT 24
Finished Aug 09 06:54:58 PM PDT 24
Peak memory 249600 kb
Host smart-a54d9cac-49fd-4211-a2e9-148e54b545ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615191095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.615191095
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.2478129385
Short name T58
Test name
Test status
Simulation time 8009789909 ps
CPU time 67.99 seconds
Started Aug 09 06:53:01 PM PDT 24
Finished Aug 09 06:54:10 PM PDT 24
Peak memory 265612 kb
Host smart-7e57548c-d81a-4363-8dcf-6778d4388e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478129385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.2478129385
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.1921087175
Short name T140
Test name
Test status
Simulation time 282666290 ps
CPU time 5.56 seconds
Started Aug 09 06:52:49 PM PDT 24
Finished Aug 09 06:52:54 PM PDT 24
Peak memory 225196 kb
Host smart-daba5901-5d04-495b-b12e-af4a80ea95a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921087175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.1921087175
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.312151700
Short name T444
Test name
Test status
Simulation time 45548603816 ps
CPU time 156.57 seconds
Started Aug 09 06:52:48 PM PDT 24
Finished Aug 09 06:55:25 PM PDT 24
Peak memory 252468 kb
Host smart-a4dc1f0f-22e9-4830-8343-85c977b591c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312151700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds.
312151700
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/4.spi_device_intercept.3205372653
Short name T273
Test name
Test status
Simulation time 1126342404 ps
CPU time 14.74 seconds
Started Aug 09 06:52:51 PM PDT 24
Finished Aug 09 06:53:05 PM PDT 24
Peak memory 225172 kb
Host smart-45d6a8c3-850c-483e-9232-508f06487661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205372653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.3205372653
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.2062820477
Short name T862
Test name
Test status
Simulation time 649047358 ps
CPU time 9.41 seconds
Started Aug 09 06:52:49 PM PDT 24
Finished Aug 09 06:52:59 PM PDT 24
Peak memory 225236 kb
Host smart-0acdd63d-6afd-4524-a269-f252fb3f2c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062820477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.2062820477
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.2630277394
Short name T606
Test name
Test status
Simulation time 33561077 ps
CPU time 1 seconds
Started Aug 09 06:53:18 PM PDT 24
Finished Aug 09 06:53:19 PM PDT 24
Peak memory 217084 kb
Host smart-53befafc-68de-4433-a5aa-37b7a8a6c72f
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630277394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.spi_device_mem_parity.2630277394
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.2553677784
Short name T705
Test name
Test status
Simulation time 21918778112 ps
CPU time 19.59 seconds
Started Aug 09 06:52:50 PM PDT 24
Finished Aug 09 06:53:09 PM PDT 24
Peak memory 233500 kb
Host smart-4a47cad3-0a4a-4616-81b2-09492f9fa7a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553677784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.2553677784
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.2259111728
Short name T226
Test name
Test status
Simulation time 4351263241 ps
CPU time 14.41 seconds
Started Aug 09 06:52:51 PM PDT 24
Finished Aug 09 06:53:05 PM PDT 24
Peak memory 233392 kb
Host smart-6ab26ca0-5c0b-458e-8141-ea8ff346f183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259111728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.2259111728
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.2598774871
Short name T574
Test name
Test status
Simulation time 1707860588 ps
CPU time 9.92 seconds
Started Aug 09 06:52:52 PM PDT 24
Finished Aug 09 06:53:02 PM PDT 24
Peak memory 221324 kb
Host smart-81887d84-c2e4-489f-a9da-0d89ecc8bab6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2598774871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.2598774871
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.2868783703
Short name T66
Test name
Test status
Simulation time 40937201 ps
CPU time 1.04 seconds
Started Aug 09 06:53:01 PM PDT 24
Finished Aug 09 06:53:03 PM PDT 24
Peak memory 235924 kb
Host smart-c575004f-73c6-4965-b9a3-50fbf23c9701
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868783703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.2868783703
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.3808693514
Short name T293
Test name
Test status
Simulation time 35533562425 ps
CPU time 266.67 seconds
Started Aug 09 06:53:01 PM PDT 24
Finished Aug 09 06:57:27 PM PDT 24
Peak memory 266324 kb
Host smart-cb07a1be-65e0-4c60-b39a-9083d600e4b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808693514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.3808693514
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.1832894203
Short name T980
Test name
Test status
Simulation time 1248331153 ps
CPU time 12.69 seconds
Started Aug 09 06:53:19 PM PDT 24
Finished Aug 09 06:53:31 PM PDT 24
Peak memory 220180 kb
Host smart-aa34af70-ad0f-4d8e-8f61-12634aa9db05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832894203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.1832894203
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.412761555
Short name T834
Test name
Test status
Simulation time 34233127756 ps
CPU time 23.59 seconds
Started Aug 09 06:53:20 PM PDT 24
Finished Aug 09 06:53:44 PM PDT 24
Peak memory 217000 kb
Host smart-bd4a6bca-e26b-4603-b045-1c663f7d4a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412761555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.412761555
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.3183059635
Short name T908
Test name
Test status
Simulation time 84952067 ps
CPU time 1.47 seconds
Started Aug 09 06:52:53 PM PDT 24
Finished Aug 09 06:52:54 PM PDT 24
Peak memory 216992 kb
Host smart-a02a0c50-9c14-41aa-b740-ff1218c366f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183059635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.3183059635
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.3806891704
Short name T666
Test name
Test status
Simulation time 184112633 ps
CPU time 0.9 seconds
Started Aug 09 06:53:21 PM PDT 24
Finished Aug 09 06:53:22 PM PDT 24
Peak memory 207616 kb
Host smart-391612a8-d557-4e09-8ce9-24adcd979855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806891704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.3806891704
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.2194545597
Short name T800
Test name
Test status
Simulation time 4972981928 ps
CPU time 8.52 seconds
Started Aug 09 06:52:51 PM PDT 24
Finished Aug 09 06:52:59 PM PDT 24
Peak memory 233472 kb
Host smart-45310b4d-a145-4233-8aa2-292ee6410291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194545597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.2194545597
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.2779112250
Short name T861
Test name
Test status
Simulation time 23528766 ps
CPU time 0.72 seconds
Started Aug 09 06:57:27 PM PDT 24
Finished Aug 09 06:57:28 PM PDT 24
Peak memory 206196 kb
Host smart-34e40327-9b49-4958-aa0d-2c17f28dbe71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779112250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
2779112250
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.885509120
Short name T276
Test name
Test status
Simulation time 162102610 ps
CPU time 2.34 seconds
Started Aug 09 06:57:27 PM PDT 24
Finished Aug 09 06:57:29 PM PDT 24
Peak memory 225176 kb
Host smart-a17d74f9-89ef-4ea4-b77f-fb13c384b507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885509120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.885509120
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.2596279111
Short name T928
Test name
Test status
Simulation time 13591571 ps
CPU time 0.8 seconds
Started Aug 09 06:57:27 PM PDT 24
Finished Aug 09 06:57:28 PM PDT 24
Peak memory 207364 kb
Host smart-74a6c6d9-5c2e-4636-8cc2-43a30234481e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596279111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.2596279111
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.2047207454
Short name T246
Test name
Test status
Simulation time 23441431977 ps
CPU time 45.65 seconds
Started Aug 09 06:57:25 PM PDT 24
Finished Aug 09 06:58:10 PM PDT 24
Peak memory 250100 kb
Host smart-7c1cb8ba-8185-460f-b4c4-0219686821b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047207454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.2047207454
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.2859562737
Short name T429
Test name
Test status
Simulation time 23984127443 ps
CPU time 39.72 seconds
Started Aug 09 06:57:26 PM PDT 24
Finished Aug 09 06:58:06 PM PDT 24
Peak memory 249912 kb
Host smart-976bcea7-277d-4baf-9c30-e30365a85d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859562737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.2859562737
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.2851746561
Short name T625
Test name
Test status
Simulation time 80964891394 ps
CPU time 177.11 seconds
Started Aug 09 06:57:27 PM PDT 24
Finished Aug 09 07:00:24 PM PDT 24
Peak memory 254228 kb
Host smart-de7d15ae-98ab-4ee5-9687-c5766019ee39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851746561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.2851746561
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.2463526323
Short name T717
Test name
Test status
Simulation time 249918774 ps
CPU time 3.48 seconds
Started Aug 09 06:57:25 PM PDT 24
Finished Aug 09 06:57:29 PM PDT 24
Peak memory 225280 kb
Host smart-336036b6-de4e-4abe-b935-4614ec5569bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463526323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.2463526323
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.3505897049
Short name T298
Test name
Test status
Simulation time 31485905231 ps
CPU time 183.45 seconds
Started Aug 09 06:57:25 PM PDT 24
Finished Aug 09 07:00:29 PM PDT 24
Peak memory 249920 kb
Host smart-24467530-fa97-4483-8477-298a05157f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505897049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmd
s.3505897049
Directory /workspace/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/40.spi_device_intercept.1781231623
Short name T596
Test name
Test status
Simulation time 150987807 ps
CPU time 2.5 seconds
Started Aug 09 06:57:28 PM PDT 24
Finished Aug 09 06:57:31 PM PDT 24
Peak memory 233428 kb
Host smart-df611975-3222-436e-a45d-baa12ece7e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781231623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.1781231623
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.1641878245
Short name T882
Test name
Test status
Simulation time 30085391 ps
CPU time 2.37 seconds
Started Aug 09 06:57:27 PM PDT 24
Finished Aug 09 06:57:29 PM PDT 24
Peak memory 233076 kb
Host smart-009370b6-bbde-4ca1-9299-365b979e2abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641878245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.1641878245
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.2725970091
Short name T1023
Test name
Test status
Simulation time 15819028690 ps
CPU time 13.16 seconds
Started Aug 09 06:57:26 PM PDT 24
Finished Aug 09 06:57:39 PM PDT 24
Peak memory 225256 kb
Host smart-239d1ed0-af44-4d97-ba37-d0fe0f86e8f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725970091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.2725970091
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.2661499703
Short name T423
Test name
Test status
Simulation time 5283210815 ps
CPU time 16.6 seconds
Started Aug 09 06:57:27 PM PDT 24
Finished Aug 09 06:57:44 PM PDT 24
Peak memory 225268 kb
Host smart-90914421-5bec-4f3a-a662-5fa6fb57541f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661499703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.2661499703
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.1247216198
Short name T692
Test name
Test status
Simulation time 2777809669 ps
CPU time 6.62 seconds
Started Aug 09 06:57:26 PM PDT 24
Finished Aug 09 06:57:33 PM PDT 24
Peak memory 220916 kb
Host smart-00a98c4f-3e94-4fc3-9d06-906fffcd7542
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1247216198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.1247216198
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.3238653006
Short name T788
Test name
Test status
Simulation time 31486534274 ps
CPU time 496.39 seconds
Started Aug 09 06:57:28 PM PDT 24
Finished Aug 09 07:05:44 PM PDT 24
Peak memory 307080 kb
Host smart-4cd9b746-ada5-4c23-a022-315921d5cda0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238653006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.3238653006
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.2236141835
Short name T500
Test name
Test status
Simulation time 3675065264 ps
CPU time 11.45 seconds
Started Aug 09 06:57:26 PM PDT 24
Finished Aug 09 06:57:38 PM PDT 24
Peak memory 217004 kb
Host smart-668e0dde-bf0a-4203-8314-cbaf63ea6837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236141835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.2236141835
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.1653010175
Short name T797
Test name
Test status
Simulation time 2456616048 ps
CPU time 4.36 seconds
Started Aug 09 06:57:28 PM PDT 24
Finished Aug 09 06:57:32 PM PDT 24
Peak memory 216832 kb
Host smart-dff81b7e-338d-4b73-b02d-1d2590a86cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653010175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.1653010175
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.2426247042
Short name T532
Test name
Test status
Simulation time 27516193 ps
CPU time 1.8 seconds
Started Aug 09 06:57:27 PM PDT 24
Finished Aug 09 06:57:29 PM PDT 24
Peak memory 216888 kb
Host smart-1f39e2ee-2372-4569-ad0a-ac319905be74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426247042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.2426247042
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.3558854995
Short name T612
Test name
Test status
Simulation time 107644966 ps
CPU time 0.8 seconds
Started Aug 09 06:57:28 PM PDT 24
Finished Aug 09 06:57:29 PM PDT 24
Peak memory 206592 kb
Host smart-01af75e6-9185-4452-ba8d-2ec5e1703238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558854995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.3558854995
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.3684791651
Short name T158
Test name
Test status
Simulation time 3108208502 ps
CPU time 7.04 seconds
Started Aug 09 06:57:25 PM PDT 24
Finished Aug 09 06:57:32 PM PDT 24
Peak memory 233500 kb
Host smart-2ae5ec90-f156-4f82-b319-fb0371d6b3eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684791651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.3684791651
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.1589869177
Short name T62
Test name
Test status
Simulation time 187862527 ps
CPU time 0.7 seconds
Started Aug 09 06:57:38 PM PDT 24
Finished Aug 09 06:57:39 PM PDT 24
Peak memory 206216 kb
Host smart-7fafa8bd-f184-417d-9640-b1e99288f065
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589869177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
1589869177
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.2862315763
Short name T996
Test name
Test status
Simulation time 866425287 ps
CPU time 5.4 seconds
Started Aug 09 06:57:41 PM PDT 24
Finished Aug 09 06:57:47 PM PDT 24
Peak memory 225208 kb
Host smart-38cc80a1-c92a-4664-806c-e90fc7a1a75c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862315763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.2862315763
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.4249255025
Short name T415
Test name
Test status
Simulation time 22723554 ps
CPU time 0.79 seconds
Started Aug 09 06:57:27 PM PDT 24
Finished Aug 09 06:57:28 PM PDT 24
Peak memory 207088 kb
Host smart-5f6bea61-69a4-44e4-93df-d679003ababb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249255025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.4249255025
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.1398603768
Short name T239
Test name
Test status
Simulation time 48648775433 ps
CPU time 89.94 seconds
Started Aug 09 06:57:39 PM PDT 24
Finished Aug 09 06:59:09 PM PDT 24
Peak memory 242000 kb
Host smart-4ef30233-9775-47f4-8a52-38579b0d65df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398603768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.1398603768
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.906931786
Short name T358
Test name
Test status
Simulation time 8494784337 ps
CPU time 34.86 seconds
Started Aug 09 06:57:38 PM PDT 24
Finished Aug 09 06:58:13 PM PDT 24
Peak memory 240756 kb
Host smart-c5c55ce5-443b-42c2-9492-9fe618449ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906931786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.906931786
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.1662669981
Short name T770
Test name
Test status
Simulation time 1244104838 ps
CPU time 20.44 seconds
Started Aug 09 06:57:38 PM PDT 24
Finished Aug 09 06:57:59 PM PDT 24
Peak memory 233412 kb
Host smart-71178e36-b17f-4a3b-82b0-6bea07c3b55b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662669981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.1662669981
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.1195533549
Short name T570
Test name
Test status
Simulation time 451619987 ps
CPU time 7.8 seconds
Started Aug 09 06:57:40 PM PDT 24
Finished Aug 09 06:57:48 PM PDT 24
Peak memory 225172 kb
Host smart-3a2baa96-3e28-4c91-ba82-6eafc86cecda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195533549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmd
s.1195533549
Directory /workspace/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/41.spi_device_intercept.1759485913
Short name T211
Test name
Test status
Simulation time 796567283 ps
CPU time 4.08 seconds
Started Aug 09 06:57:26 PM PDT 24
Finished Aug 09 06:57:30 PM PDT 24
Peak memory 233380 kb
Host smart-615ee8b1-3729-4ff8-b048-91a41fa1e68b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759485913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.1759485913
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.898153406
Short name T798
Test name
Test status
Simulation time 65527311076 ps
CPU time 98.22 seconds
Started Aug 09 06:57:28 PM PDT 24
Finished Aug 09 06:59:06 PM PDT 24
Peak memory 241528 kb
Host smart-5414346a-ae63-4270-96ae-dac29f2ff12b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898153406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.898153406
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.3498520100
Short name T406
Test name
Test status
Simulation time 4784434404 ps
CPU time 11.5 seconds
Started Aug 09 06:57:27 PM PDT 24
Finished Aug 09 06:57:38 PM PDT 24
Peak memory 233508 kb
Host smart-267ae6d3-b691-484f-875e-b5f714b93887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498520100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.3498520100
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.3637626519
Short name T279
Test name
Test status
Simulation time 8285940473 ps
CPU time 16.65 seconds
Started Aug 09 06:57:25 PM PDT 24
Finished Aug 09 06:57:42 PM PDT 24
Peak memory 241136 kb
Host smart-24f912c7-daa8-419e-98fd-9d2e466199c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637626519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.3637626519
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.4127028069
Short name T684
Test name
Test status
Simulation time 4581012618 ps
CPU time 9.79 seconds
Started Aug 09 06:57:40 PM PDT 24
Finished Aug 09 06:57:50 PM PDT 24
Peak memory 219940 kb
Host smart-e9f7f4ed-ae9d-46c9-b86f-34ebca15a9c8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4127028069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.4127028069
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.2690225043
Short name T236
Test name
Test status
Simulation time 11478015082 ps
CPU time 157.83 seconds
Started Aug 09 06:57:41 PM PDT 24
Finished Aug 09 07:00:19 PM PDT 24
Peak memory 266312 kb
Host smart-efcf7191-c932-414f-a892-36817790121a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690225043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.2690225043
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.3897024462
Short name T422
Test name
Test status
Simulation time 4376163154 ps
CPU time 22.34 seconds
Started Aug 09 06:57:25 PM PDT 24
Finished Aug 09 06:57:47 PM PDT 24
Peak memory 217128 kb
Host smart-f7b5a562-6818-4b68-ae25-e4b78265b77e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897024462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.3897024462
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.3379481504
Short name T565
Test name
Test status
Simulation time 784334768 ps
CPU time 1.38 seconds
Started Aug 09 06:57:25 PM PDT 24
Finished Aug 09 06:57:27 PM PDT 24
Peak memory 207620 kb
Host smart-009d2f26-a7ad-4a4e-82d2-9f29e822aa79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379481504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.3379481504
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.956830537
Short name T690
Test name
Test status
Simulation time 377715846 ps
CPU time 1.14 seconds
Started Aug 09 06:57:28 PM PDT 24
Finished Aug 09 06:57:29 PM PDT 24
Peak memory 208528 kb
Host smart-c5fc0d30-728f-45d3-9dab-27d5cec41574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956830537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.956830537
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.500374249
Short name T819
Test name
Test status
Simulation time 195829494 ps
CPU time 0.86 seconds
Started Aug 09 06:57:27 PM PDT 24
Finished Aug 09 06:57:28 PM PDT 24
Peak memory 206584 kb
Host smart-a93570f8-324c-4249-9053-847197e9b609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500374249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.500374249
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.3242092853
Short name T659
Test name
Test status
Simulation time 2667647892 ps
CPU time 6.54 seconds
Started Aug 09 06:57:39 PM PDT 24
Finished Aug 09 06:57:45 PM PDT 24
Peak memory 233560 kb
Host smart-58cc60f0-50ca-46b2-996e-4ec42bc088df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242092853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.3242092853
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.3812814695
Short name T773
Test name
Test status
Simulation time 14582109 ps
CPU time 0.76 seconds
Started Aug 09 06:57:39 PM PDT 24
Finished Aug 09 06:57:40 PM PDT 24
Peak memory 205868 kb
Host smart-b32b6c9c-9198-4d8c-965a-123e4bb79a2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812814695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
3812814695
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.4121937640
Short name T491
Test name
Test status
Simulation time 176016965 ps
CPU time 2.61 seconds
Started Aug 09 06:57:43 PM PDT 24
Finished Aug 09 06:57:46 PM PDT 24
Peak memory 233388 kb
Host smart-a64fcc6e-92dd-4287-ab74-5d35bf1757db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121937640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.4121937640
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.1012742254
Short name T504
Test name
Test status
Simulation time 14976936 ps
CPU time 0.76 seconds
Started Aug 09 06:57:42 PM PDT 24
Finished Aug 09 06:57:43 PM PDT 24
Peak memory 207068 kb
Host smart-0b70c324-1101-4925-95e1-38e22fdf5c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012742254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.1012742254
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.381160703
Short name T134
Test name
Test status
Simulation time 47044458446 ps
CPU time 168.14 seconds
Started Aug 09 06:57:39 PM PDT 24
Finished Aug 09 07:00:28 PM PDT 24
Peak memory 249912 kb
Host smart-47e1e696-4870-4c4a-995c-769ec6c0336b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381160703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.381160703
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.1616014020
Short name T131
Test name
Test status
Simulation time 19047272731 ps
CPU time 209.15 seconds
Started Aug 09 06:57:39 PM PDT 24
Finished Aug 09 07:01:08 PM PDT 24
Peak memory 251564 kb
Host smart-28c1ea96-93e5-43e1-a363-9775c99615e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616014020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.1616014020
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.4136631692
Short name T95
Test name
Test status
Simulation time 1101566754 ps
CPU time 6.44 seconds
Started Aug 09 06:57:39 PM PDT 24
Finished Aug 09 06:57:45 PM PDT 24
Peak memory 233452 kb
Host smart-0ee2d86a-8c0e-4033-86c7-5e14c834261d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136631692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.4136631692
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.622366673
Short name T679
Test name
Test status
Simulation time 27668845067 ps
CPU time 34.78 seconds
Started Aug 09 06:57:39 PM PDT 24
Finished Aug 09 06:58:14 PM PDT 24
Peak memory 241708 kb
Host smart-a607356b-18d6-4464-bcba-48c385913ea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622366673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmds
.622366673
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/42.spi_device_intercept.4069669020
Short name T189
Test name
Test status
Simulation time 3699326730 ps
CPU time 19.82 seconds
Started Aug 09 06:57:38 PM PDT 24
Finished Aug 09 06:57:58 PM PDT 24
Peak memory 233472 kb
Host smart-c731ac78-d9ff-4bd5-95f0-f6857dda9818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069669020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.4069669020
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.784122826
Short name T710
Test name
Test status
Simulation time 258766754 ps
CPU time 5.72 seconds
Started Aug 09 06:57:42 PM PDT 24
Finished Aug 09 06:57:47 PM PDT 24
Peak memory 225212 kb
Host smart-9f359139-8d5c-444b-88ff-77131b6af601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784122826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.784122826
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.735276134
Short name T947
Test name
Test status
Simulation time 30559582058 ps
CPU time 12.63 seconds
Started Aug 09 06:57:40 PM PDT 24
Finished Aug 09 06:57:53 PM PDT 24
Peak memory 233508 kb
Host smart-b16339d7-c2e7-48fb-8fae-04e5e1ef76e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735276134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swap
.735276134
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.3781925577
Short name T752
Test name
Test status
Simulation time 978554677 ps
CPU time 8.05 seconds
Started Aug 09 06:57:39 PM PDT 24
Finished Aug 09 06:57:47 PM PDT 24
Peak memory 241324 kb
Host smart-051ce6b3-80a9-4473-a4df-982b70f9fa00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781925577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.3781925577
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.3297819685
Short name T363
Test name
Test status
Simulation time 2144291125 ps
CPU time 6.12 seconds
Started Aug 09 06:57:34 PM PDT 24
Finished Aug 09 06:57:40 PM PDT 24
Peak memory 220032 kb
Host smart-9ae59ac9-b4e6-4cc8-9177-473974696955
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3297819685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.3297819685
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.4091996963
Short name T206
Test name
Test status
Simulation time 11646990147 ps
CPU time 105.49 seconds
Started Aug 09 06:57:37 PM PDT 24
Finished Aug 09 06:59:23 PM PDT 24
Peak memory 253076 kb
Host smart-ea0bce43-d197-49b8-8a53-6bdfb3bf74c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091996963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.4091996963
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.729501803
Short name T1031
Test name
Test status
Simulation time 13080392337 ps
CPU time 13.57 seconds
Started Aug 09 06:57:40 PM PDT 24
Finished Aug 09 06:57:54 PM PDT 24
Peak memory 220560 kb
Host smart-0b1fa9ae-74fe-4a73-9946-a81be6875e89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729501803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.729501803
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.2758886578
Short name T829
Test name
Test status
Simulation time 550299256 ps
CPU time 4.57 seconds
Started Aug 09 06:57:39 PM PDT 24
Finished Aug 09 06:57:44 PM PDT 24
Peak memory 216960 kb
Host smart-e41ca8af-3c53-403c-b897-be81e8c21dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758886578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.2758886578
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.2837991787
Short name T569
Test name
Test status
Simulation time 1861264220 ps
CPU time 4.4 seconds
Started Aug 09 06:57:40 PM PDT 24
Finished Aug 09 06:57:44 PM PDT 24
Peak memory 216968 kb
Host smart-7f71fdf5-c7c5-4b63-acf8-ad01360a1398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837991787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.2837991787
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.902097870
Short name T478
Test name
Test status
Simulation time 81411891 ps
CPU time 0.82 seconds
Started Aug 09 06:57:40 PM PDT 24
Finished Aug 09 06:57:40 PM PDT 24
Peak memory 206532 kb
Host smart-d1d73dcb-c231-4fb9-a68a-727c44a2418e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902097870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.902097870
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.3403034174
Short name T421
Test name
Test status
Simulation time 1513172316 ps
CPU time 9.17 seconds
Started Aug 09 06:57:33 PM PDT 24
Finished Aug 09 06:57:42 PM PDT 24
Peak memory 233420 kb
Host smart-8970865a-dcfd-4546-877e-c0306f7aab0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403034174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.3403034174
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.3038912374
Short name T402
Test name
Test status
Simulation time 35701712 ps
CPU time 0.75 seconds
Started Aug 09 06:57:47 PM PDT 24
Finished Aug 09 06:57:47 PM PDT 24
Peak memory 205796 kb
Host smart-0cb1139a-ab68-499f-97b0-70e8b0b9a109
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038912374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
3038912374
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.709733555
Short name T645
Test name
Test status
Simulation time 1203309765 ps
CPU time 5.57 seconds
Started Aug 09 06:57:47 PM PDT 24
Finished Aug 09 06:57:52 PM PDT 24
Peak memory 225236 kb
Host smart-27d3ae6c-e93e-43b3-bd8b-f553d2af4f73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709733555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.709733555
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.1624031731
Short name T345
Test name
Test status
Simulation time 20724704 ps
CPU time 0.78 seconds
Started Aug 09 06:57:39 PM PDT 24
Finished Aug 09 06:57:40 PM PDT 24
Peak memory 207032 kb
Host smart-18efd363-9ea3-46fe-aaf0-f05a4c91c8fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624031731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.1624031731
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.1775278513
Short name T213
Test name
Test status
Simulation time 3720569819 ps
CPU time 50.79 seconds
Started Aug 09 06:57:47 PM PDT 24
Finished Aug 09 06:58:38 PM PDT 24
Peak memory 249864 kb
Host smart-92c4bec2-933c-41d6-8b13-a522b1633f35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775278513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.1775278513
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.3770695234
Short name T205
Test name
Test status
Simulation time 13177623347 ps
CPU time 82.03 seconds
Started Aug 09 06:57:42 PM PDT 24
Finished Aug 09 06:59:04 PM PDT 24
Peak memory 262868 kb
Host smart-b9537ed1-783f-4b93-9d7b-0c5efe9521bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770695234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.3770695234
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.2018925516
Short name T289
Test name
Test status
Simulation time 25488099785 ps
CPU time 200.55 seconds
Started Aug 09 06:57:47 PM PDT 24
Finished Aug 09 07:01:07 PM PDT 24
Peak memory 250472 kb
Host smart-1801c081-e7ea-4230-b9f4-1742dfa357b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018925516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmd
s.2018925516
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/43.spi_device_intercept.3376327195
Short name T744
Test name
Test status
Simulation time 2506892213 ps
CPU time 17.04 seconds
Started Aug 09 06:57:47 PM PDT 24
Finished Aug 09 06:58:04 PM PDT 24
Peak memory 233468 kb
Host smart-89b20f6b-6667-4406-8e50-d023314b3244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376327195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.3376327195
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.4238333861
Short name T263
Test name
Test status
Simulation time 5451912875 ps
CPU time 33.64 seconds
Started Aug 09 06:57:42 PM PDT 24
Finished Aug 09 06:58:16 PM PDT 24
Peak memory 241428 kb
Host smart-0a35ca80-3ead-4656-a7f2-550c77fe6d26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238333861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.4238333861
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.1751085725
Short name T277
Test name
Test status
Simulation time 64463884114 ps
CPU time 18.18 seconds
Started Aug 09 06:57:44 PM PDT 24
Finished Aug 09 06:58:02 PM PDT 24
Peak memory 225280 kb
Host smart-ae0c57e7-b177-4c8b-96d8-4619a5096162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751085725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.1751085725
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.3210454094
Short name T443
Test name
Test status
Simulation time 34941194699 ps
CPU time 21.11 seconds
Started Aug 09 06:57:42 PM PDT 24
Finished Aug 09 06:58:03 PM PDT 24
Peak memory 225236 kb
Host smart-2b4c9b59-6deb-4631-b8ab-83d143455579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210454094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.3210454094
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.2438806341
Short name T945
Test name
Test status
Simulation time 848724966 ps
CPU time 9.78 seconds
Started Aug 09 06:57:43 PM PDT 24
Finished Aug 09 06:57:53 PM PDT 24
Peak memory 222968 kb
Host smart-8566d746-264a-4019-83b2-abb53581b3cb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2438806341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.2438806341
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.2996512868
Short name T987
Test name
Test status
Simulation time 8005698821 ps
CPU time 119.77 seconds
Started Aug 09 06:57:43 PM PDT 24
Finished Aug 09 06:59:43 PM PDT 24
Peak memory 256236 kb
Host smart-6a58e25b-ffc0-4198-8081-3d71282e8eff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996512868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.2996512868
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.2744460618
Short name T695
Test name
Test status
Simulation time 3619922228 ps
CPU time 26.11 seconds
Started Aug 09 06:57:39 PM PDT 24
Finished Aug 09 06:58:06 PM PDT 24
Peak memory 220616 kb
Host smart-9a06ae5a-7e7c-44f6-8e21-6412ae76b03f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744460618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.2744460618
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.1479216437
Short name T938
Test name
Test status
Simulation time 1946493229 ps
CPU time 6.18 seconds
Started Aug 09 06:57:38 PM PDT 24
Finished Aug 09 06:57:44 PM PDT 24
Peak memory 216992 kb
Host smart-34bc2431-c5f5-43dd-a0d8-c630ba6f4a24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479216437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.1479216437
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.1746984877
Short name T693
Test name
Test status
Simulation time 13898047 ps
CPU time 0.69 seconds
Started Aug 09 06:57:40 PM PDT 24
Finished Aug 09 06:57:40 PM PDT 24
Peak memory 206088 kb
Host smart-c0c1745d-4e67-46ca-9c97-45c1fd06ad5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746984877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.1746984877
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.393337317
Short name T351
Test name
Test status
Simulation time 19904832 ps
CPU time 0.8 seconds
Started Aug 09 06:57:40 PM PDT 24
Finished Aug 09 06:57:41 PM PDT 24
Peak memory 206532 kb
Host smart-0aaa9c79-3664-4953-aa27-fadf3649a227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393337317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.393337317
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.3465565087
Short name T617
Test name
Test status
Simulation time 527114385 ps
CPU time 5.16 seconds
Started Aug 09 06:57:47 PM PDT 24
Finished Aug 09 06:57:52 PM PDT 24
Peak memory 225148 kb
Host smart-39949ed7-56e5-49b2-80ee-bfaba384e5d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465565087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.3465565087
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.181994931
Short name T454
Test name
Test status
Simulation time 45366122 ps
CPU time 0.71 seconds
Started Aug 09 06:57:50 PM PDT 24
Finished Aug 09 06:57:51 PM PDT 24
Peak memory 205844 kb
Host smart-a15e9e1a-b3c6-4f35-b692-221d80f2df78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181994931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.181994931
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.3315245582
Short name T571
Test name
Test status
Simulation time 155962331 ps
CPU time 4.58 seconds
Started Aug 09 06:57:51 PM PDT 24
Finished Aug 09 06:57:56 PM PDT 24
Peak memory 233420 kb
Host smart-febc67e8-d049-419f-a1c8-740ab84c8dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315245582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.3315245582
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.2617465978
Short name T373
Test name
Test status
Simulation time 15938384 ps
CPU time 0.8 seconds
Started Aug 09 06:57:44 PM PDT 24
Finished Aug 09 06:57:45 PM PDT 24
Peak memory 207084 kb
Host smart-c8096feb-8992-4219-8346-0b031bf46199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617465978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.2617465978
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.1376645443
Short name T920
Test name
Test status
Simulation time 26212556799 ps
CPU time 84.6 seconds
Started Aug 09 06:57:55 PM PDT 24
Finished Aug 09 06:59:20 PM PDT 24
Peak memory 271156 kb
Host smart-824b6fd2-13d5-4a3f-8c1c-19820d2542ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376645443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.1376645443
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.3429368329
Short name T197
Test name
Test status
Simulation time 10429632332 ps
CPU time 48.45 seconds
Started Aug 09 06:57:52 PM PDT 24
Finished Aug 09 06:58:41 PM PDT 24
Peak memory 249964 kb
Host smart-52744e36-5686-4c49-8dd8-854b0009e0ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429368329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.3429368329
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.4285048414
Short name T939
Test name
Test status
Simulation time 90384335828 ps
CPU time 237.48 seconds
Started Aug 09 06:57:53 PM PDT 24
Finished Aug 09 07:01:51 PM PDT 24
Peak memory 249984 kb
Host smart-51026ef4-56ec-4022-b3e4-390de02d8593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285048414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.4285048414
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.490277347
Short name T138
Test name
Test status
Simulation time 636382788 ps
CPU time 4.43 seconds
Started Aug 09 06:57:52 PM PDT 24
Finished Aug 09 06:57:56 PM PDT 24
Peak memory 225244 kb
Host smart-4bddedbf-6f37-4bb4-b9c0-10c97e67f86a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490277347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.490277347
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_intercept.2316906568
Short name T196
Test name
Test status
Simulation time 2703529465 ps
CPU time 30.45 seconds
Started Aug 09 06:57:53 PM PDT 24
Finished Aug 09 06:58:24 PM PDT 24
Peak memory 225220 kb
Host smart-5843f363-166b-470b-9247-f81e19cc7a2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316906568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.2316906568
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.4185669424
Short name T918
Test name
Test status
Simulation time 43097660018 ps
CPU time 128.42 seconds
Started Aug 09 06:57:54 PM PDT 24
Finished Aug 09 07:00:02 PM PDT 24
Peak memory 225356 kb
Host smart-74ce01a2-0fad-49a6-9b58-40fa38b2eab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185669424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.4185669424
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.3497900403
Short name T921
Test name
Test status
Simulation time 35544058 ps
CPU time 2.61 seconds
Started Aug 09 06:57:55 PM PDT 24
Finished Aug 09 06:57:57 PM PDT 24
Peak memory 233060 kb
Host smart-f944a2a9-82ef-4e5e-9e87-6c69216dece0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497900403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.3497900403
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.717341786
Short name T67
Test name
Test status
Simulation time 2059525174 ps
CPU time 5.08 seconds
Started Aug 09 06:57:54 PM PDT 24
Finished Aug 09 06:57:59 PM PDT 24
Peak memory 233448 kb
Host smart-b3892be5-85f1-41a9-b278-d07a40285b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717341786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.717341786
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.331598550
Short name T775
Test name
Test status
Simulation time 441631903 ps
CPU time 7.88 seconds
Started Aug 09 06:57:52 PM PDT 24
Finished Aug 09 06:58:00 PM PDT 24
Peak memory 223172 kb
Host smart-7842c200-9e4a-4f24-b4ed-41d66ec3a65a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=331598550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dire
ct.331598550
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.3926055311
Short name T72
Test name
Test status
Simulation time 95828277257 ps
CPU time 160.88 seconds
Started Aug 09 06:57:51 PM PDT 24
Finished Aug 09 07:00:32 PM PDT 24
Peak memory 274232 kb
Host smart-a35164f0-36e5-434d-9399-3722c634a716
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926055311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.3926055311
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.1905714349
Short name T328
Test name
Test status
Simulation time 4940175632 ps
CPU time 24.54 seconds
Started Aug 09 06:57:42 PM PDT 24
Finished Aug 09 06:58:07 PM PDT 24
Peak memory 217064 kb
Host smart-ee5a48c1-4f26-42d4-bd66-5b4c0d7e8e90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905714349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.1905714349
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.3464857098
Short name T922
Test name
Test status
Simulation time 2754261522 ps
CPU time 5.8 seconds
Started Aug 09 06:57:43 PM PDT 24
Finished Aug 09 06:57:49 PM PDT 24
Peak memory 217024 kb
Host smart-02a33a6f-9437-4e51-b178-7800da8d9c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464857098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.3464857098
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.1788591348
Short name T974
Test name
Test status
Simulation time 44899106 ps
CPU time 0.83 seconds
Started Aug 09 06:57:44 PM PDT 24
Finished Aug 09 06:57:45 PM PDT 24
Peak memory 207296 kb
Host smart-1c0c0784-cacb-4b86-81e7-214b89c18360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788591348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.1788591348
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.2175569063
Short name T566
Test name
Test status
Simulation time 34264990 ps
CPU time 0.73 seconds
Started Aug 09 06:57:44 PM PDT 24
Finished Aug 09 06:57:45 PM PDT 24
Peak memory 206584 kb
Host smart-5bff91ac-228a-4f7d-9a1e-0bd3825d4ac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175569063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.2175569063
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.4133278061
Short name T534
Test name
Test status
Simulation time 14309001893 ps
CPU time 44.07 seconds
Started Aug 09 06:57:54 PM PDT 24
Finished Aug 09 06:58:38 PM PDT 24
Peak memory 241660 kb
Host smart-ad51c087-628b-451b-9745-c05c2cd63ba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133278061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.4133278061
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.1387402022
Short name T578
Test name
Test status
Simulation time 20437977 ps
CPU time 0.75 seconds
Started Aug 09 06:58:03 PM PDT 24
Finished Aug 09 06:58:04 PM PDT 24
Peak memory 205804 kb
Host smart-ceca33a8-c346-4f88-acd8-f9c0f68cd163
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387402022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
1387402022
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.1109911392
Short name T181
Test name
Test status
Simulation time 118223424 ps
CPU time 2.42 seconds
Started Aug 09 06:57:51 PM PDT 24
Finished Aug 09 06:57:54 PM PDT 24
Peak memory 225132 kb
Host smart-41eb978c-c8f9-4590-a542-84a9386432ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109911392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.1109911392
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.3340532812
Short name T392
Test name
Test status
Simulation time 17732450 ps
CPU time 0.78 seconds
Started Aug 09 06:57:54 PM PDT 24
Finished Aug 09 06:57:54 PM PDT 24
Peak memory 206004 kb
Host smart-0ba5adbf-dbbc-4d79-8612-dc3089d1c460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340532812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.3340532812
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.3421462761
Short name T523
Test name
Test status
Simulation time 7534800928 ps
CPU time 44.93 seconds
Started Aug 09 06:57:54 PM PDT 24
Finished Aug 09 06:58:39 PM PDT 24
Peak memory 241716 kb
Host smart-af1475c6-c64f-4c18-bc65-1c68cd48312a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421462761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.3421462761
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.1832221823
Short name T997
Test name
Test status
Simulation time 4099128649 ps
CPU time 117.69 seconds
Started Aug 09 06:57:55 PM PDT 24
Finished Aug 09 06:59:53 PM PDT 24
Peak memory 276248 kb
Host smart-e84a71fe-e22a-44be-bd39-b48f4cd3e6fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832221823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.1832221823
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.3313196148
Short name T314
Test name
Test status
Simulation time 276646383 ps
CPU time 6.36 seconds
Started Aug 09 06:57:54 PM PDT 24
Finished Aug 09 06:58:00 PM PDT 24
Peak memory 225276 kb
Host smart-231fce9d-c2e9-412e-a5b6-6fa7ea1fa149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313196148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.3313196148
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.1269216326
Short name T38
Test name
Test status
Simulation time 12276225943 ps
CPU time 121.01 seconds
Started Aug 09 06:57:54 PM PDT 24
Finished Aug 09 06:59:55 PM PDT 24
Peak memory 255420 kb
Host smart-e427cf8d-7295-4beb-851e-c738916f10c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269216326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmd
s.1269216326
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_intercept.4036418767
Short name T895
Test name
Test status
Simulation time 80532053 ps
CPU time 2.29 seconds
Started Aug 09 06:57:54 PM PDT 24
Finished Aug 09 06:57:56 PM PDT 24
Peak memory 225216 kb
Host smart-c92b786d-6d26-48ed-9ea9-28c0be571ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036418767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.4036418767
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.1201782777
Short name T231
Test name
Test status
Simulation time 41779135344 ps
CPU time 70.18 seconds
Started Aug 09 06:57:50 PM PDT 24
Finished Aug 09 06:59:01 PM PDT 24
Peak memory 225288 kb
Host smart-062ce093-dfea-449d-8592-11d3fc2c26f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201782777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.1201782777
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.7849849
Short name T712
Test name
Test status
Simulation time 127915256 ps
CPU time 2.48 seconds
Started Aug 09 06:57:53 PM PDT 24
Finished Aug 09 06:57:56 PM PDT 24
Peak memory 233404 kb
Host smart-937a91b4-2ed0-4c1a-814f-3273fea38254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7849849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swap.7849849
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.2267122791
Short name T751
Test name
Test status
Simulation time 1414550972 ps
CPU time 9.95 seconds
Started Aug 09 06:57:53 PM PDT 24
Finished Aug 09 06:58:03 PM PDT 24
Peak memory 241192 kb
Host smart-b126b7e3-fecc-4f3e-a05b-cf03dae372b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267122791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.2267122791
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.823705438
Short name T642
Test name
Test status
Simulation time 1134661672 ps
CPU time 3.77 seconds
Started Aug 09 06:57:53 PM PDT 24
Finished Aug 09 06:57:57 PM PDT 24
Peak memory 223832 kb
Host smart-6df83852-cf97-4239-a58a-38f389302eb2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=823705438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dire
ct.823705438
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.219803471
Short name T153
Test name
Test status
Simulation time 34643131999 ps
CPU time 344.45 seconds
Started Aug 09 06:58:01 PM PDT 24
Finished Aug 09 07:03:46 PM PDT 24
Peak memory 258176 kb
Host smart-8980755b-c66b-4477-aa7b-feb0bce51969
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219803471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stres
s_all.219803471
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.618992430
Short name T604
Test name
Test status
Simulation time 4989626643 ps
CPU time 30.81 seconds
Started Aug 09 06:57:52 PM PDT 24
Finished Aug 09 06:58:23 PM PDT 24
Peak memory 217088 kb
Host smart-d10a6761-a0d9-4834-9cf0-c14528e3c874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618992430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.618992430
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.3093716495
Short name T1032
Test name
Test status
Simulation time 1647133902 ps
CPU time 5.37 seconds
Started Aug 09 06:57:54 PM PDT 24
Finished Aug 09 06:58:00 PM PDT 24
Peak memory 216960 kb
Host smart-f1a99484-ae5b-4324-bf29-67ff589ea295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093716495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.3093716495
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.2640782925
Short name T925
Test name
Test status
Simulation time 10701447 ps
CPU time 0.74 seconds
Started Aug 09 06:57:52 PM PDT 24
Finished Aug 09 06:57:53 PM PDT 24
Peak memory 206068 kb
Host smart-813f9f0e-cf9e-485e-99df-7e75aa331842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640782925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.2640782925
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.1412702985
Short name T25
Test name
Test status
Simulation time 31443771 ps
CPU time 0.84 seconds
Started Aug 09 06:57:52 PM PDT 24
Finished Aug 09 06:57:53 PM PDT 24
Peak memory 207600 kb
Host smart-690bdcb5-7768-4bb4-aa76-354ee844fd57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412702985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.1412702985
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.1353675196
Short name T866
Test name
Test status
Simulation time 129165803 ps
CPU time 2.34 seconds
Started Aug 09 06:57:51 PM PDT 24
Finished Aug 09 06:57:53 PM PDT 24
Peak memory 225240 kb
Host smart-b1c92b56-3f04-4f3b-9a34-a456efa0da48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353675196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.1353675196
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.1980423942
Short name T780
Test name
Test status
Simulation time 12525947 ps
CPU time 0.69 seconds
Started Aug 09 06:58:13 PM PDT 24
Finished Aug 09 06:58:13 PM PDT 24
Peak memory 206188 kb
Host smart-9d455375-7bcb-4326-b169-6151483c78ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980423942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
1980423942
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.4116634996
Short name T183
Test name
Test status
Simulation time 78115530 ps
CPU time 3.6 seconds
Started Aug 09 06:58:01 PM PDT 24
Finished Aug 09 06:58:05 PM PDT 24
Peak memory 233344 kb
Host smart-40d5cf69-4006-4af2-aa7a-b17061a964b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116634996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.4116634996
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.1891903406
Short name T466
Test name
Test status
Simulation time 78881253 ps
CPU time 0.75 seconds
Started Aug 09 06:57:59 PM PDT 24
Finished Aug 09 06:58:00 PM PDT 24
Peak memory 207076 kb
Host smart-3dc21173-3853-40cc-b263-abc5127c1db0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891903406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.1891903406
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.174958570
Short name T495
Test name
Test status
Simulation time 1437676856 ps
CPU time 20.56 seconds
Started Aug 09 06:58:00 PM PDT 24
Finished Aug 09 06:58:21 PM PDT 24
Peak memory 241668 kb
Host smart-68a14237-3c68-4eea-bc44-530ffae355ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174958570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.174958570
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.714557144
Short name T288
Test name
Test status
Simulation time 521725332 ps
CPU time 14.4 seconds
Started Aug 09 06:58:01 PM PDT 24
Finished Aug 09 06:58:15 PM PDT 24
Peak memory 233508 kb
Host smart-7ff73cf4-582b-4cc1-b0de-2966136e2379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714557144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.714557144
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.2067445057
Short name T297
Test name
Test status
Simulation time 35216217382 ps
CPU time 101.65 seconds
Started Aug 09 06:58:09 PM PDT 24
Finished Aug 09 06:59:51 PM PDT 24
Peak memory 253040 kb
Host smart-d57bde41-338c-40e9-b01c-f0c406d85f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067445057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.2067445057
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.2443146130
Short name T317
Test name
Test status
Simulation time 7719377955 ps
CPU time 29.96 seconds
Started Aug 09 06:58:07 PM PDT 24
Finished Aug 09 06:58:37 PM PDT 24
Peak memory 249864 kb
Host smart-317bc372-e735-49e7-9524-6e8a59406c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443146130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.2443146130
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.3346611322
Short name T984
Test name
Test status
Simulation time 10673067 ps
CPU time 0.73 seconds
Started Aug 09 06:58:07 PM PDT 24
Finished Aug 09 06:58:08 PM PDT 24
Peak memory 216412 kb
Host smart-d95fcb9e-22b6-4cf8-8b3a-fdbb67f96de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346611322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmd
s.3346611322
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_intercept.2830998048
Short name T874
Test name
Test status
Simulation time 975567544 ps
CPU time 10.28 seconds
Started Aug 09 06:58:00 PM PDT 24
Finished Aug 09 06:58:11 PM PDT 24
Peak memory 225124 kb
Host smart-46786cab-90ab-41d1-8f7f-9ebb8165c358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830998048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.2830998048
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.696763331
Short name T572
Test name
Test status
Simulation time 471469485 ps
CPU time 6.61 seconds
Started Aug 09 06:58:01 PM PDT 24
Finished Aug 09 06:58:08 PM PDT 24
Peak memory 241328 kb
Host smart-721c6f01-e5e8-48b0-b792-a71a54466e0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696763331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.696763331
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.3603850960
Short name T282
Test name
Test status
Simulation time 1460710777 ps
CPU time 9.66 seconds
Started Aug 09 06:58:00 PM PDT 24
Finished Aug 09 06:58:10 PM PDT 24
Peak memory 240788 kb
Host smart-02c8ef83-9d08-4a29-8765-070c72ba6b1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603850960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.3603850960
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.1057605983
Short name T673
Test name
Test status
Simulation time 183326181 ps
CPU time 2.4 seconds
Started Aug 09 06:58:03 PM PDT 24
Finished Aug 09 06:58:05 PM PDT 24
Peak memory 233032 kb
Host smart-90873a32-07d0-4656-b9ea-3e4cb20a8cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057605983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.1057605983
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.4148362893
Short name T847
Test name
Test status
Simulation time 1550401847 ps
CPU time 14.86 seconds
Started Aug 09 06:58:01 PM PDT 24
Finished Aug 09 06:58:16 PM PDT 24
Peak memory 223732 kb
Host smart-52572d1f-c553-48a2-8ca8-bd2d6676bce5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4148362893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.4148362893
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.56348718
Short name T689
Test name
Test status
Simulation time 133661087 ps
CPU time 0.91 seconds
Started Aug 09 06:58:09 PM PDT 24
Finished Aug 09 06:58:10 PM PDT 24
Peak memory 207952 kb
Host smart-d45f9619-acaf-41b5-b675-fb624d8b464b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56348718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stress
_all.56348718
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.312679566
Short name T395
Test name
Test status
Simulation time 13393550 ps
CPU time 0.77 seconds
Started Aug 09 06:58:01 PM PDT 24
Finished Aug 09 06:58:03 PM PDT 24
Peak memory 206528 kb
Host smart-bb2a9679-d4ba-4975-ba92-ffd8b23a794a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312679566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.312679566
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.111437859
Short name T383
Test name
Test status
Simulation time 893051473 ps
CPU time 6.66 seconds
Started Aug 09 06:58:04 PM PDT 24
Finished Aug 09 06:58:10 PM PDT 24
Peak memory 216776 kb
Host smart-d677a55b-fe22-4c67-b5f0-0dba06f73512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111437859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.111437859
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.3453176133
Short name T356
Test name
Test status
Simulation time 63886032 ps
CPU time 1.28 seconds
Started Aug 09 06:58:00 PM PDT 24
Finished Aug 09 06:58:01 PM PDT 24
Peak memory 216760 kb
Host smart-da75758f-6860-4321-a35d-8fed0f0f52fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453176133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.3453176133
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.1546093173
Short name T77
Test name
Test status
Simulation time 20474427 ps
CPU time 0.8 seconds
Started Aug 09 06:58:01 PM PDT 24
Finished Aug 09 06:58:01 PM PDT 24
Peak memory 206516 kb
Host smart-d9ea7dbe-0ad3-4e71-9012-bcab696b6dd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546093173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.1546093173
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.2329240588
Short name T894
Test name
Test status
Simulation time 15776363788 ps
CPU time 26.73 seconds
Started Aug 09 06:58:04 PM PDT 24
Finished Aug 09 06:58:31 PM PDT 24
Peak memory 240924 kb
Host smart-d0846dbd-fbd2-4438-8e74-ce7e375abe83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329240588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.2329240588
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.2579380646
Short name T380
Test name
Test status
Simulation time 15842516 ps
CPU time 0.71 seconds
Started Aug 09 06:58:10 PM PDT 24
Finished Aug 09 06:58:11 PM PDT 24
Peak memory 205288 kb
Host smart-a01bb648-961f-4d4e-85da-7bc52b161a10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579380646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
2579380646
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.2803865623
Short name T393
Test name
Test status
Simulation time 1235738905 ps
CPU time 11.08 seconds
Started Aug 09 06:58:09 PM PDT 24
Finished Aug 09 06:58:21 PM PDT 24
Peak memory 233416 kb
Host smart-52e07f25-8e57-4b38-93e3-a0ab1bbb02be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803865623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.2803865623
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.1350696337
Short name T785
Test name
Test status
Simulation time 42549001 ps
CPU time 0.81 seconds
Started Aug 09 06:58:13 PM PDT 24
Finished Aug 09 06:58:14 PM PDT 24
Peak memory 207060 kb
Host smart-18ac68c1-27d1-458d-96e8-ea30f9552f73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350696337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.1350696337
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.4029382135
Short name T216
Test name
Test status
Simulation time 23884709857 ps
CPU time 133.12 seconds
Started Aug 09 06:58:12 PM PDT 24
Finished Aug 09 07:00:25 PM PDT 24
Peak memory 258104 kb
Host smart-5da95281-a432-425c-880f-e7ee476183c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029382135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.4029382135
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.1257735008
Short name T950
Test name
Test status
Simulation time 104713713732 ps
CPU time 94.88 seconds
Started Aug 09 06:58:09 PM PDT 24
Finished Aug 09 06:59:44 PM PDT 24
Peak memory 249944 kb
Host smart-b4bf5155-ca56-4389-9d66-e14a02a1d624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257735008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.1257735008
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.2443817313
Short name T234
Test name
Test status
Simulation time 51291944885 ps
CPU time 69.75 seconds
Started Aug 09 06:58:09 PM PDT 24
Finished Aug 09 06:59:19 PM PDT 24
Peak memory 250736 kb
Host smart-f29a848d-b4b7-430b-a037-dc505cbc3008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443817313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.2443817313
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.2692626136
Short name T817
Test name
Test status
Simulation time 408452300 ps
CPU time 6.79 seconds
Started Aug 09 06:58:09 PM PDT 24
Finished Aug 09 06:58:16 PM PDT 24
Peak memory 235636 kb
Host smart-de8d83f6-2652-4bb8-ab91-6bd5c5ad0cc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692626136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.2692626136
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.321784708
Short name T456
Test name
Test status
Simulation time 115983130117 ps
CPU time 110.87 seconds
Started Aug 09 06:58:08 PM PDT 24
Finished Aug 09 06:59:59 PM PDT 24
Peak memory 249828 kb
Host smart-d2b859c0-7f68-4a16-ac94-b956b4159738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321784708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmds
.321784708
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/47.spi_device_intercept.329119177
Short name T84
Test name
Test status
Simulation time 1861008049 ps
CPU time 4.35 seconds
Started Aug 09 06:58:09 PM PDT 24
Finished Aug 09 06:58:13 PM PDT 24
Peak memory 233404 kb
Host smart-cdef3544-162d-4713-8092-c7d979610888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329119177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.329119177
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.1834103493
Short name T262
Test name
Test status
Simulation time 110967453 ps
CPU time 4.7 seconds
Started Aug 09 06:58:10 PM PDT 24
Finished Aug 09 06:58:15 PM PDT 24
Peak memory 225288 kb
Host smart-e63c672d-9b39-483b-87b5-4916d2ee931c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834103493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.1834103493
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.3620732409
Short name T632
Test name
Test status
Simulation time 9826080630 ps
CPU time 12.08 seconds
Started Aug 09 06:58:10 PM PDT 24
Finished Aug 09 06:58:22 PM PDT 24
Peak memory 233392 kb
Host smart-a99e14a2-76f3-4d07-9be6-fdc43922e918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620732409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.3620732409
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.2327300459
Short name T719
Test name
Test status
Simulation time 7634404567 ps
CPU time 7.13 seconds
Started Aug 09 06:58:08 PM PDT 24
Finished Aug 09 06:58:15 PM PDT 24
Peak memory 233536 kb
Host smart-5f7c7fff-571f-41e9-bcdc-70679e8b37ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327300459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.2327300459
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.2682878398
Short name T404
Test name
Test status
Simulation time 353514592 ps
CPU time 5.11 seconds
Started Aug 09 06:58:09 PM PDT 24
Finished Aug 09 06:58:14 PM PDT 24
Peak memory 219316 kb
Host smart-3ffa77c5-8bc9-4cf5-aca5-bb66a85dea8f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2682878398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.2682878398
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.2673284678
Short name T7
Test name
Test status
Simulation time 18728773879 ps
CPU time 91.36 seconds
Started Aug 09 06:58:10 PM PDT 24
Finished Aug 09 06:59:41 PM PDT 24
Peak memory 257892 kb
Host smart-0f9e2a3b-b1d9-49ab-957d-4311ef0f4326
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673284678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.2673284678
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.3302260635
Short name T474
Test name
Test status
Simulation time 32083906606 ps
CPU time 6.31 seconds
Started Aug 09 06:58:12 PM PDT 24
Finished Aug 09 06:58:18 PM PDT 24
Peak memory 217044 kb
Host smart-d9d88bd2-ccc9-478e-a6dd-843a251f724d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302260635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.3302260635
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.3621928475
Short name T833
Test name
Test status
Simulation time 283648950 ps
CPU time 1.51 seconds
Started Aug 09 06:58:09 PM PDT 24
Finished Aug 09 06:58:11 PM PDT 24
Peak memory 217000 kb
Host smart-d05dfead-905a-4d48-8d0b-881522a22b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621928475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.3621928475
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.396511356
Short name T465
Test name
Test status
Simulation time 78418042 ps
CPU time 0.76 seconds
Started Aug 09 06:58:12 PM PDT 24
Finished Aug 09 06:58:13 PM PDT 24
Peak memory 206572 kb
Host smart-ce9353a2-f4b0-4824-af0d-32bb6498fe2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396511356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.396511356
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.393634687
Short name T781
Test name
Test status
Simulation time 11754126255 ps
CPU time 22.39 seconds
Started Aug 09 06:58:09 PM PDT 24
Finished Aug 09 06:58:31 PM PDT 24
Peak memory 241212 kb
Host smart-0cd1fc37-abfa-46c2-af4a-71a83b5429b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393634687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.393634687
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.778942753
Short name T400
Test name
Test status
Simulation time 51127633 ps
CPU time 0.76 seconds
Started Aug 09 06:58:21 PM PDT 24
Finished Aug 09 06:58:22 PM PDT 24
Peak memory 205232 kb
Host smart-ad8be96e-885e-4d9a-8aa6-96010fa522f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778942753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.778942753
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.3448905549
Short name T753
Test name
Test status
Simulation time 110460715 ps
CPU time 2.12 seconds
Started Aug 09 06:58:10 PM PDT 24
Finished Aug 09 06:58:12 PM PDT 24
Peak memory 224752 kb
Host smart-f16f1824-12b8-4f1c-b094-3fd18150aa2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448905549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.3448905549
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.611425199
Short name T1015
Test name
Test status
Simulation time 13497483 ps
CPU time 0.74 seconds
Started Aug 09 06:58:09 PM PDT 24
Finished Aug 09 06:58:10 PM PDT 24
Peak memory 205968 kb
Host smart-b9bf5355-a9f9-45cc-a92e-d08251834dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611425199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.611425199
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.1067284061
Short name T707
Test name
Test status
Simulation time 88169673845 ps
CPU time 73.99 seconds
Started Aug 09 06:58:19 PM PDT 24
Finished Aug 09 06:59:33 PM PDT 24
Peak memory 241604 kb
Host smart-ddb03fe3-d11b-47ef-8772-b8daf1a6a486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067284061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.1067284061
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.1134777544
Short name T374
Test name
Test status
Simulation time 20840394145 ps
CPU time 194.3 seconds
Started Aug 09 06:58:26 PM PDT 24
Finished Aug 09 07:01:40 PM PDT 24
Peak memory 249952 kb
Host smart-b54e9991-e848-4bef-9b7d-83bd0bd0fca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134777544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.1134777544
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.2023489671
Short name T986
Test name
Test status
Simulation time 2577453683 ps
CPU time 35.98 seconds
Started Aug 09 06:58:19 PM PDT 24
Finished Aug 09 06:58:56 PM PDT 24
Peak memory 241716 kb
Host smart-ac55a764-1578-4188-b5d8-e3d00e92c44c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023489671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.2023489671
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.2993874591
Short name T312
Test name
Test status
Simulation time 7360232584 ps
CPU time 12.42 seconds
Started Aug 09 06:58:09 PM PDT 24
Finished Aug 09 06:58:22 PM PDT 24
Peak memory 241604 kb
Host smart-9e41cf60-215e-407d-8528-e499f7ca1a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993874591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.2993874591
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.3623668874
Short name T51
Test name
Test status
Simulation time 5036133866 ps
CPU time 89.05 seconds
Started Aug 09 06:58:11 PM PDT 24
Finished Aug 09 06:59:40 PM PDT 24
Peak memory 266252 kb
Host smart-c753749a-738a-4342-a4c4-807df3730787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623668874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmd
s.3623668874
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/48.spi_device_intercept.3709839951
Short name T585
Test name
Test status
Simulation time 781473774 ps
CPU time 6.93 seconds
Started Aug 09 06:58:09 PM PDT 24
Finished Aug 09 06:58:16 PM PDT 24
Peak memory 225196 kb
Host smart-a2a67c2b-50bc-436d-8406-87a75e4cc161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709839951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.3709839951
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.1353764049
Short name T494
Test name
Test status
Simulation time 6485772785 ps
CPU time 45.86 seconds
Started Aug 09 06:58:10 PM PDT 24
Finished Aug 09 06:58:56 PM PDT 24
Peak memory 241052 kb
Host smart-cf12cc56-f1cc-4cbd-8952-cb35e6c6be77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353764049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.1353764049
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.917995274
Short name T272
Test name
Test status
Simulation time 334566814 ps
CPU time 4.6 seconds
Started Aug 09 06:58:09 PM PDT 24
Finished Aug 09 06:58:14 PM PDT 24
Peak memory 233420 kb
Host smart-01ab0f0d-c294-4575-a7f8-19332bf8dc8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917995274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swap
.917995274
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.3866658212
Short name T259
Test name
Test status
Simulation time 606045608 ps
CPU time 3.22 seconds
Started Aug 09 06:58:10 PM PDT 24
Finished Aug 09 06:58:14 PM PDT 24
Peak memory 225180 kb
Host smart-e032fe36-fb87-41da-b4c7-86c110581cea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866658212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.3866658212
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.1135372048
Short name T568
Test name
Test status
Simulation time 1411524296 ps
CPU time 12.54 seconds
Started Aug 09 06:58:11 PM PDT 24
Finished Aug 09 06:58:24 PM PDT 24
Peak memory 220916 kb
Host smart-9d9fc24b-537f-4a67-aaa6-87ffadde19a2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1135372048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.1135372048
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.1061200633
Short name T326
Test name
Test status
Simulation time 4865675639 ps
CPU time 25.44 seconds
Started Aug 09 06:58:09 PM PDT 24
Finished Aug 09 06:58:35 PM PDT 24
Peak memory 217064 kb
Host smart-ab3c5c66-8413-4ab4-93d9-69b9ac3b7516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061200633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.1061200633
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.1712141833
Short name T966
Test name
Test status
Simulation time 10953528905 ps
CPU time 15.22 seconds
Started Aug 09 06:58:11 PM PDT 24
Finished Aug 09 06:58:26 PM PDT 24
Peak memory 217092 kb
Host smart-befef862-f079-46eb-853b-5fcc2786aed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712141833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.1712141833
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.1139120929
Short name T948
Test name
Test status
Simulation time 70049541 ps
CPU time 1.3 seconds
Started Aug 09 06:58:09 PM PDT 24
Finished Aug 09 06:58:11 PM PDT 24
Peak memory 216712 kb
Host smart-0450a0a4-4595-4d6e-b262-ea97242f6ff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139120929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.1139120929
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.1478824906
Short name T616
Test name
Test status
Simulation time 139516822 ps
CPU time 0.93 seconds
Started Aug 09 06:58:12 PM PDT 24
Finished Aug 09 06:58:13 PM PDT 24
Peak memory 206556 kb
Host smart-e874bd5c-f68a-47d3-88e3-691ea8e38d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478824906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.1478824906
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.4097777231
Short name T621
Test name
Test status
Simulation time 17950746020 ps
CPU time 11.22 seconds
Started Aug 09 06:58:10 PM PDT 24
Finished Aug 09 06:58:21 PM PDT 24
Peak memory 233520 kb
Host smart-2da26767-6ab7-4c0d-a09c-5c1ef3d80e3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097777231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.4097777231
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.3602501489
Short name T759
Test name
Test status
Simulation time 40588313 ps
CPU time 0.7 seconds
Started Aug 09 06:58:27 PM PDT 24
Finished Aug 09 06:58:28 PM PDT 24
Peak memory 205832 kb
Host smart-388ae7f4-4498-4d69-bce1-b03cc2a93723
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602501489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
3602501489
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.3669162675
Short name T531
Test name
Test status
Simulation time 1515066879 ps
CPU time 6.87 seconds
Started Aug 09 06:58:18 PM PDT 24
Finished Aug 09 06:58:26 PM PDT 24
Peak memory 225220 kb
Host smart-b4154547-2016-45ec-9246-49b8b6375746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669162675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.3669162675
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.1107067598
Short name T340
Test name
Test status
Simulation time 47550965 ps
CPU time 0.77 seconds
Started Aug 09 06:58:19 PM PDT 24
Finished Aug 09 06:58:20 PM PDT 24
Peak memory 207024 kb
Host smart-6458060a-7006-42a7-bcfc-3d9e097a15f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107067598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.1107067598
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.3681409116
Short name T514
Test name
Test status
Simulation time 11964682189 ps
CPU time 39.18 seconds
Started Aug 09 06:58:27 PM PDT 24
Finished Aug 09 06:59:06 PM PDT 24
Peak memory 249976 kb
Host smart-b65d8a95-1f0b-4f33-a7cd-bd000569a745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681409116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.3681409116
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.4037440389
Short name T325
Test name
Test status
Simulation time 13859415542 ps
CPU time 60.53 seconds
Started Aug 09 06:58:27 PM PDT 24
Finished Aug 09 06:59:28 PM PDT 24
Peak memory 249344 kb
Host smart-60a8778f-69de-4ad5-8a32-fdf86f1b4192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037440389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.4037440389
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.3537509940
Short name T375
Test name
Test status
Simulation time 3425789824 ps
CPU time 11.06 seconds
Started Aug 09 06:58:28 PM PDT 24
Finished Aug 09 06:58:39 PM PDT 24
Peak memory 251748 kb
Host smart-5a706875-5a00-4583-ad98-a718d45ba635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537509940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.3537509940
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.4032671324
Short name T824
Test name
Test status
Simulation time 158025112251 ps
CPU time 203.2 seconds
Started Aug 09 06:58:28 PM PDT 24
Finished Aug 09 07:01:51 PM PDT 24
Peak memory 257580 kb
Host smart-f1cce69b-9af3-4f14-a5ca-354a4cc0fe9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032671324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmd
s.4032671324
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/49.spi_device_intercept.1673995083
Short name T83
Test name
Test status
Simulation time 1660523395 ps
CPU time 16.76 seconds
Started Aug 09 06:58:19 PM PDT 24
Finished Aug 09 06:58:35 PM PDT 24
Peak memory 233460 kb
Host smart-b086df4c-5063-48ae-acec-b07fd26710cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673995083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.1673995083
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.202734191
Short name T709
Test name
Test status
Simulation time 2870841091 ps
CPU time 40.28 seconds
Started Aug 09 06:58:17 PM PDT 24
Finished Aug 09 06:58:57 PM PDT 24
Peak memory 251912 kb
Host smart-8c41fd51-7681-4465-85ae-5d2378679fd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202734191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.202734191
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.3909575104
Short name T44
Test name
Test status
Simulation time 4627315624 ps
CPU time 3.58 seconds
Started Aug 09 06:58:19 PM PDT 24
Finished Aug 09 06:58:23 PM PDT 24
Peak memory 233488 kb
Host smart-8158101d-921a-4199-8fbe-388842dd4bd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909575104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.3909575104
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.475223399
Short name T597
Test name
Test status
Simulation time 480629929 ps
CPU time 4.02 seconds
Started Aug 09 06:58:18 PM PDT 24
Finished Aug 09 06:58:22 PM PDT 24
Peak memory 225260 kb
Host smart-337418bc-6c76-4e57-93f8-db2664056443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475223399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.475223399
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.3995977575
Short name T850
Test name
Test status
Simulation time 750668473 ps
CPU time 7.62 seconds
Started Aug 09 06:58:28 PM PDT 24
Finished Aug 09 06:58:35 PM PDT 24
Peak memory 223268 kb
Host smart-d5c40136-208c-432e-89bb-d98a728cf651
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3995977575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.3995977575
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.1857561436
Short name T133
Test name
Test status
Simulation time 161035896243 ps
CPU time 526.32 seconds
Started Aug 09 06:58:28 PM PDT 24
Finished Aug 09 07:07:14 PM PDT 24
Peak memory 273352 kb
Host smart-2b4c3674-1052-42cc-8675-b2125419d310
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857561436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.1857561436
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.32589178
Short name T594
Test name
Test status
Simulation time 798458208 ps
CPU time 12.5 seconds
Started Aug 09 06:58:20 PM PDT 24
Finished Aug 09 06:58:32 PM PDT 24
Peak memory 217212 kb
Host smart-843b42b1-4b3b-4c5a-a11d-ab7106903550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32589178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.32589178
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.360788269
Short name T804
Test name
Test status
Simulation time 108870146 ps
CPU time 1.08 seconds
Started Aug 09 06:58:18 PM PDT 24
Finished Aug 09 06:58:20 PM PDT 24
Peak memory 208324 kb
Host smart-6db5368e-84e6-4e05-bca1-c13676f8149a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360788269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.360788269
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.295167140
Short name T660
Test name
Test status
Simulation time 199531114 ps
CPU time 2.42 seconds
Started Aug 09 06:58:18 PM PDT 24
Finished Aug 09 06:58:21 PM PDT 24
Peak memory 216972 kb
Host smart-29f73c20-1af9-4d4f-b462-46a19f3cceed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295167140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.295167140
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.669926122
Short name T426
Test name
Test status
Simulation time 19793398 ps
CPU time 0.75 seconds
Started Aug 09 06:58:19 PM PDT 24
Finished Aug 09 06:58:20 PM PDT 24
Peak memory 206584 kb
Host smart-b19abc15-0594-4a2e-ad4a-9a9eb01678d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669926122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.669926122
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.4070395293
Short name T224
Test name
Test status
Simulation time 1606887578 ps
CPU time 6.2 seconds
Started Aug 09 06:58:18 PM PDT 24
Finished Aug 09 06:58:24 PM PDT 24
Peak memory 233444 kb
Host smart-5103a21d-7dca-45d0-a9fb-4e56f6c2e8cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070395293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.4070395293
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.2065346133
Short name T588
Test name
Test status
Simulation time 11625031 ps
CPU time 0.72 seconds
Started Aug 09 06:53:12 PM PDT 24
Finished Aug 09 06:53:13 PM PDT 24
Peak memory 205288 kb
Host smart-79e74c3b-43cf-4dca-9f4b-102fcefd6ce0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065346133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.2
065346133
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.4194993362
Short name T952
Test name
Test status
Simulation time 299542512 ps
CPU time 3.46 seconds
Started Aug 09 06:53:09 PM PDT 24
Finished Aug 09 06:53:13 PM PDT 24
Peak memory 233336 kb
Host smart-6ecc7c23-60e2-45a5-8347-6662b3ab478d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194993362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.4194993362
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.3248789486
Short name T657
Test name
Test status
Simulation time 13826567 ps
CPU time 0.72 seconds
Started Aug 09 06:52:53 PM PDT 24
Finished Aug 09 06:52:54 PM PDT 24
Peak memory 205968 kb
Host smart-ede912ef-3d98-45ad-81b4-65c9ffd61cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248789486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.3248789486
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.2506042598
Short name T527
Test name
Test status
Simulation time 6999034188 ps
CPU time 16.39 seconds
Started Aug 09 06:53:12 PM PDT 24
Finished Aug 09 06:53:29 PM PDT 24
Peak memory 233476 kb
Host smart-d1d85fb3-e066-4eed-9644-b2437cbcbe7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506042598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.2506042598
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.661996065
Short name T26
Test name
Test status
Simulation time 10716117107 ps
CPU time 17.86 seconds
Started Aug 09 06:53:12 PM PDT 24
Finished Aug 09 06:53:30 PM PDT 24
Peak memory 218244 kb
Host smart-6905aa28-a40a-494f-a5f2-bf7d76e7bd14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661996065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.661996065
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.3331647773
Short name T926
Test name
Test status
Simulation time 1829352979 ps
CPU time 35.19 seconds
Started Aug 09 06:53:10 PM PDT 24
Finished Aug 09 06:53:45 PM PDT 24
Peak memory 241388 kb
Host smart-3b0b054e-bf1a-4e87-b343-dc8eed5d06f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331647773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.3331647773
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.4161092682
Short name T434
Test name
Test status
Simulation time 192097115 ps
CPU time 2.67 seconds
Started Aug 09 06:53:08 PM PDT 24
Finished Aug 09 06:53:11 PM PDT 24
Peak memory 233428 kb
Host smart-454faef4-b35a-4699-9eef-9431fdac408a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161092682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.4161092682
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.2794693441
Short name T954
Test name
Test status
Simulation time 5513909573 ps
CPU time 10.88 seconds
Started Aug 09 06:53:10 PM PDT 24
Finished Aug 09 06:53:21 PM PDT 24
Peak memory 237108 kb
Host smart-45be606b-ec62-43d8-8102-627c0f5c6544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794693441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds
.2794693441
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/5.spi_device_intercept.2921255468
Short name T547
Test name
Test status
Simulation time 235231630 ps
CPU time 5.41 seconds
Started Aug 09 06:53:10 PM PDT 24
Finished Aug 09 06:53:15 PM PDT 24
Peak memory 225164 kb
Host smart-6ceb6819-72c2-45ab-9b5f-59876236220e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921255468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.2921255468
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.2946727050
Short name T251
Test name
Test status
Simulation time 5706411480 ps
CPU time 57.08 seconds
Started Aug 09 06:53:09 PM PDT 24
Finished Aug 09 06:54:06 PM PDT 24
Peak memory 235000 kb
Host smart-aed75125-82c2-4d52-8ccd-7bc8aa899f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946727050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.2946727050
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.1602451258
Short name T620
Test name
Test status
Simulation time 26087127 ps
CPU time 1.12 seconds
Started Aug 09 06:53:01 PM PDT 24
Finished Aug 09 06:53:03 PM PDT 24
Peak memory 218436 kb
Host smart-411e3dae-0e33-43aa-8cb3-a7ab8b0b76c0
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602451258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.spi_device_mem_parity.1602451258
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.1134864770
Short name T907
Test name
Test status
Simulation time 917373902 ps
CPU time 5.56 seconds
Started Aug 09 06:53:09 PM PDT 24
Finished Aug 09 06:53:15 PM PDT 24
Peak memory 225112 kb
Host smart-99d05912-8a43-4379-833a-9faad5e23695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134864770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.1134864770
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.1684105986
Short name T281
Test name
Test status
Simulation time 369808200 ps
CPU time 5.44 seconds
Started Aug 09 06:53:09 PM PDT 24
Finished Aug 09 06:53:14 PM PDT 24
Peak memory 233424 kb
Host smart-1e68a591-1121-45b5-8f66-19f18469853b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684105986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.1684105986
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.2354650281
Short name T546
Test name
Test status
Simulation time 375153106 ps
CPU time 4.16 seconds
Started Aug 09 06:53:09 PM PDT 24
Finished Aug 09 06:53:13 PM PDT 24
Peak memory 219756 kb
Host smart-f76dcb31-d611-4eeb-ac8f-0ae888a27053
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2354650281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.2354650281
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.3189227557
Short name T21
Test name
Test status
Simulation time 47670268 ps
CPU time 0.97 seconds
Started Aug 09 06:53:11 PM PDT 24
Finished Aug 09 06:53:12 PM PDT 24
Peak memory 208120 kb
Host smart-5a9d2fc4-1ded-4f07-8211-507b5c292ef5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189227557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.3189227557
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.2479251761
Short name T787
Test name
Test status
Simulation time 8873043586 ps
CPU time 13.36 seconds
Started Aug 09 06:53:10 PM PDT 24
Finished Aug 09 06:53:24 PM PDT 24
Peak memory 220416 kb
Host smart-e12efa77-4676-4c3c-b161-6fe7a1cf29e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479251761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.2479251761
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.3034019116
Short name T367
Test name
Test status
Simulation time 1926604703 ps
CPU time 6.96 seconds
Started Aug 09 06:53:10 PM PDT 24
Finished Aug 09 06:53:17 PM PDT 24
Peak memory 216988 kb
Host smart-a431da7b-c824-43aa-94af-0db215993a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034019116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.3034019116
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.223421661
Short name T336
Test name
Test status
Simulation time 125390067 ps
CPU time 5.36 seconds
Started Aug 09 06:53:07 PM PDT 24
Finished Aug 09 06:53:13 PM PDT 24
Peak memory 217004 kb
Host smart-6204a3d1-6615-4642-b348-3f5f794aeef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223421661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.223421661
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.4077038338
Short name T384
Test name
Test status
Simulation time 47712300 ps
CPU time 0.81 seconds
Started Aug 09 06:53:09 PM PDT 24
Finished Aug 09 06:53:10 PM PDT 24
Peak memory 206564 kb
Host smart-306bcf0c-71df-4b04-8b22-1726c6d31ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077038338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.4077038338
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.1407062410
Short name T783
Test name
Test status
Simulation time 94882369 ps
CPU time 2.35 seconds
Started Aug 09 06:53:09 PM PDT 24
Finished Aug 09 06:53:11 PM PDT 24
Peak memory 225188 kb
Host smart-560b8937-8c05-4c6b-9cbb-d16f09d23020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407062410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.1407062410
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.3134169128
Short name T912
Test name
Test status
Simulation time 12001644 ps
CPU time 0.7 seconds
Started Aug 09 06:53:29 PM PDT 24
Finished Aug 09 06:53:30 PM PDT 24
Peak memory 206092 kb
Host smart-7601c439-92ab-49ae-8090-a606d130b0e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134169128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.3
134169128
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.1928567435
Short name T81
Test name
Test status
Simulation time 133223066 ps
CPU time 2.33 seconds
Started Aug 09 06:53:23 PM PDT 24
Finished Aug 09 06:53:26 PM PDT 24
Peak memory 225212 kb
Host smart-15e5c906-00e9-4b5e-b402-db95d2b7aebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928567435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.1928567435
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.3344226083
Short name T1003
Test name
Test status
Simulation time 33026120 ps
CPU time 0.79 seconds
Started Aug 09 06:53:19 PM PDT 24
Finished Aug 09 06:53:20 PM PDT 24
Peak memory 207044 kb
Host smart-dc39bdac-51b4-43d0-9c61-561d8b609853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344226083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.3344226083
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.3894871856
Short name T396
Test name
Test status
Simulation time 22694841410 ps
CPU time 40.48 seconds
Started Aug 09 06:53:23 PM PDT 24
Finished Aug 09 06:54:03 PM PDT 24
Peak memory 240944 kb
Host smart-00413309-7e92-4e76-903a-25a9e4326a17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894871856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.3894871856
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.144543149
Short name T672
Test name
Test status
Simulation time 12599032360 ps
CPU time 118.16 seconds
Started Aug 09 06:53:23 PM PDT 24
Finished Aug 09 06:55:21 PM PDT 24
Peak memory 266120 kb
Host smart-781a9c58-8b98-443e-b3ae-8f465951438e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144543149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.144543149
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.888481059
Short name T238
Test name
Test status
Simulation time 4235107890 ps
CPU time 75.6 seconds
Started Aug 09 06:53:24 PM PDT 24
Finished Aug 09 06:54:40 PM PDT 24
Peak memory 258056 kb
Host smart-9476ee16-62c5-43dc-9615-8fbc967d1a93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888481059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle.
888481059
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.1021923788
Short name T137
Test name
Test status
Simulation time 1536066005 ps
CPU time 23.13 seconds
Started Aug 09 06:53:23 PM PDT 24
Finished Aug 09 06:53:46 PM PDT 24
Peak memory 233504 kb
Host smart-49f257f5-25d6-4167-bee9-30beb35254a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021923788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.1021923788
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.796089525
Short name T649
Test name
Test status
Simulation time 172805818 ps
CPU time 4.24 seconds
Started Aug 09 06:53:20 PM PDT 24
Finished Aug 09 06:53:25 PM PDT 24
Peak memory 237436 kb
Host smart-1eddf038-719f-4c88-a868-aac8a82ecd24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796089525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds.
796089525
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/6.spi_device_intercept.1599671502
Short name T599
Test name
Test status
Simulation time 323444739 ps
CPU time 7.86 seconds
Started Aug 09 06:53:22 PM PDT 24
Finished Aug 09 06:53:29 PM PDT 24
Peak memory 225216 kb
Host smart-10352698-ec04-4cba-91ee-69e9c216d748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599671502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.1599671502
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.3125215382
Short name T52
Test name
Test status
Simulation time 200257882 ps
CPU time 4.31 seconds
Started Aug 09 06:53:22 PM PDT 24
Finished Aug 09 06:53:27 PM PDT 24
Peak memory 233444 kb
Host smart-1dce55f8-db23-4ffb-86e3-84a2258eeb95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125215382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.3125215382
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.315970846
Short name T844
Test name
Test status
Simulation time 66703093 ps
CPU time 1.13 seconds
Started Aug 09 06:53:20 PM PDT 24
Finished Aug 09 06:53:21 PM PDT 24
Peak memory 217156 kb
Host smart-deb2ad1d-7c1a-4f8a-863c-370c22e96f8c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315970846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.spi_device_mem_parity.315970846
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.3650190422
Short name T838
Test name
Test status
Simulation time 8739109414 ps
CPU time 14.53 seconds
Started Aug 09 06:53:21 PM PDT 24
Finished Aug 09 06:53:36 PM PDT 24
Peak memory 225316 kb
Host smart-4521c315-b0e5-4123-a298-158a1b4be171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650190422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.3650190422
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.3296394297
Short name T685
Test name
Test status
Simulation time 25902069320 ps
CPU time 31.44 seconds
Started Aug 09 06:53:20 PM PDT 24
Finished Aug 09 06:53:51 PM PDT 24
Peak memory 233416 kb
Host smart-f91a47f7-0a0c-4b05-85af-577128e4f03d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296394297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.3296394297
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.3130274946
Short name T746
Test name
Test status
Simulation time 805522494 ps
CPU time 6.48 seconds
Started Aug 09 06:53:23 PM PDT 24
Finished Aug 09 06:53:29 PM PDT 24
Peak memory 223296 kb
Host smart-d2db3fd4-e7d7-4d08-ae22-f6c45cf04d71
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3130274946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.3130274946
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.439451458
Short name T962
Test name
Test status
Simulation time 221503230 ps
CPU time 1.09 seconds
Started Aug 09 06:53:23 PM PDT 24
Finished Aug 09 06:53:24 PM PDT 24
Peak memory 207248 kb
Host smart-da3ba707-fd8a-45c0-9306-cfed9cb9bc3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439451458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stress
_all.439451458
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.3712171922
Short name T726
Test name
Test status
Simulation time 310851882 ps
CPU time 1.78 seconds
Started Aug 09 06:53:21 PM PDT 24
Finished Aug 09 06:53:23 PM PDT 24
Peak memory 216988 kb
Host smart-df1b06c7-878c-4a38-8dd0-ac4a217e6a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712171922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.3712171922
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.2595287891
Short name T605
Test name
Test status
Simulation time 11982913625 ps
CPU time 18.8 seconds
Started Aug 09 06:53:17 PM PDT 24
Finished Aug 09 06:53:36 PM PDT 24
Peak memory 217052 kb
Host smart-a0c1863c-1989-4460-b2c8-25db3fc531fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595287891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.2595287891
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.2196680107
Short name T342
Test name
Test status
Simulation time 35674107 ps
CPU time 0.96 seconds
Started Aug 09 06:53:22 PM PDT 24
Finished Aug 09 06:53:23 PM PDT 24
Peak memory 207584 kb
Host smart-5090f64e-4e91-4f11-8769-dca93db4dbac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196680107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.2196680107
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.2346931576
Short name T851
Test name
Test status
Simulation time 193208695 ps
CPU time 1.02 seconds
Started Aug 09 06:53:21 PM PDT 24
Finished Aug 09 06:53:22 PM PDT 24
Peak memory 206588 kb
Host smart-3c965109-a314-435c-96ac-b982462e4ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346931576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.2346931576
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.4226034370
Short name T218
Test name
Test status
Simulation time 54162565456 ps
CPU time 24 seconds
Started Aug 09 06:53:21 PM PDT 24
Finished Aug 09 06:53:45 PM PDT 24
Peak memory 233724 kb
Host smart-c79b520f-b042-4df5-b425-0677c4bd8f96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226034370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.4226034370
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.2217434228
Short name T827
Test name
Test status
Simulation time 31118265 ps
CPU time 0.72 seconds
Started Aug 09 06:53:26 PM PDT 24
Finished Aug 09 06:53:27 PM PDT 24
Peak memory 205260 kb
Host smart-dbf124a5-fec1-41f0-8918-7853cdd43015
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217434228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.2
217434228
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.3401412131
Short name T510
Test name
Test status
Simulation time 1238003486 ps
CPU time 4.39 seconds
Started Aug 09 06:53:33 PM PDT 24
Finished Aug 09 06:53:38 PM PDT 24
Peak memory 225152 kb
Host smart-9ef72e68-fc81-4a4a-a7e8-2f299689438d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401412131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.3401412131
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.1910088734
Short name T600
Test name
Test status
Simulation time 36060031 ps
CPU time 0.8 seconds
Started Aug 09 06:53:32 PM PDT 24
Finished Aug 09 06:53:33 PM PDT 24
Peak memory 206940 kb
Host smart-11e0af0f-3736-4934-ae8a-a54f8e19b035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910088734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.1910088734
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.3829588045
Short name T883
Test name
Test status
Simulation time 17214115012 ps
CPU time 102.47 seconds
Started Aug 09 06:53:26 PM PDT 24
Finished Aug 09 06:55:09 PM PDT 24
Peak memory 249896 kb
Host smart-336f64c0-c282-48a5-aaa2-9d5f283ceea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829588045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.3829588045
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.3709636376
Short name T366
Test name
Test status
Simulation time 1862528647 ps
CPU time 6.85 seconds
Started Aug 09 06:53:27 PM PDT 24
Finished Aug 09 06:53:34 PM PDT 24
Peak memory 220324 kb
Host smart-4042bd01-ccdf-4df2-b66a-5a468ae986c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709636376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.3709636376
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.590037945
Short name T208
Test name
Test status
Simulation time 2748193960 ps
CPU time 67.89 seconds
Started Aug 09 06:53:32 PM PDT 24
Finished Aug 09 06:54:40 PM PDT 24
Peak memory 252156 kb
Host smart-1a88b2a0-b955-4a73-a978-63edee4fe39c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590037945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle.
590037945
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.3375092861
Short name T623
Test name
Test status
Simulation time 477643812 ps
CPU time 3.65 seconds
Started Aug 09 06:53:24 PM PDT 24
Finished Aug 09 06:53:28 PM PDT 24
Peak memory 225192 kb
Host smart-3205b9fe-35c2-4188-bc79-e99d378ea138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375092861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.3375092861
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.3087171422
Short name T791
Test name
Test status
Simulation time 31525511 ps
CPU time 0.85 seconds
Started Aug 09 06:53:23 PM PDT 24
Finished Aug 09 06:53:24 PM PDT 24
Peak memory 216672 kb
Host smart-cf83adc6-b63b-4dca-af30-31024f224e79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087171422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds
.3087171422
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_intercept.2072479535
Short name T863
Test name
Test status
Simulation time 693703643 ps
CPU time 5.85 seconds
Started Aug 09 06:53:27 PM PDT 24
Finished Aug 09 06:53:33 PM PDT 24
Peak memory 233560 kb
Host smart-c7ffc899-bb8b-4116-b00f-ccf27b85596f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072479535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.2072479535
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.3866071023
Short name T482
Test name
Test status
Simulation time 3354058251 ps
CPU time 36.4 seconds
Started Aug 09 06:53:25 PM PDT 24
Finished Aug 09 06:54:01 PM PDT 24
Peak memory 233528 kb
Host smart-91daba9e-617e-4911-9ba1-9ad4c408e731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866071023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.3866071023
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.3630021317
Short name T715
Test name
Test status
Simulation time 117781869 ps
CPU time 1.07 seconds
Started Aug 09 06:53:24 PM PDT 24
Finished Aug 09 06:53:25 PM PDT 24
Peak memory 217220 kb
Host smart-fa98bbf7-aa57-4232-839b-93ade0cfcb29
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630021317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.spi_device_mem_parity.3630021317
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.3916903540
Short name T909
Test name
Test status
Simulation time 610650505 ps
CPU time 7.02 seconds
Started Aug 09 06:53:27 PM PDT 24
Finished Aug 09 06:53:34 PM PDT 24
Peak memory 225252 kb
Host smart-52ba2414-c61f-4bbd-9f28-6f406e62937a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916903540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.3916903540
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.2818852224
Short name T477
Test name
Test status
Simulation time 24749496409 ps
CPU time 20.36 seconds
Started Aug 09 06:53:23 PM PDT 24
Finished Aug 09 06:53:44 PM PDT 24
Peak memory 233428 kb
Host smart-d52e6e1f-b21f-4525-a1bd-364f021c9713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818852224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.2818852224
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.4046772939
Short name T485
Test name
Test status
Simulation time 874855983 ps
CPU time 10.25 seconds
Started Aug 09 06:53:33 PM PDT 24
Finished Aug 09 06:53:44 PM PDT 24
Peak memory 220788 kb
Host smart-5a0862c7-9fe7-42a7-8b83-205689c5718f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4046772939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.4046772939
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.1239649842
Short name T130
Test name
Test status
Simulation time 88092734398 ps
CPU time 254.11 seconds
Started Aug 09 06:53:33 PM PDT 24
Finished Aug 09 06:57:47 PM PDT 24
Peak memory 272692 kb
Host smart-408f8ce3-a870-4e90-a0d1-9569c72f1344
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239649842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.1239649842
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.82149459
Short name T647
Test name
Test status
Simulation time 6086267104 ps
CPU time 10.89 seconds
Started Aug 09 06:53:29 PM PDT 24
Finished Aug 09 06:53:40 PM PDT 24
Peak memory 217040 kb
Host smart-889415c7-a274-46a3-a4ad-8e6fefcd7862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82149459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.82149459
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.3311441527
Short name T522
Test name
Test status
Simulation time 2339542704 ps
CPU time 5.21 seconds
Started Aug 09 06:53:30 PM PDT 24
Finished Aug 09 06:53:35 PM PDT 24
Peak memory 216936 kb
Host smart-c55c9e15-af55-497b-9d57-4541fe991099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311441527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.3311441527
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.1351244327
Short name T46
Test name
Test status
Simulation time 473929383 ps
CPU time 2.33 seconds
Started Aug 09 06:53:25 PM PDT 24
Finished Aug 09 06:53:27 PM PDT 24
Peak memory 216884 kb
Host smart-f3353700-9844-4d90-9d8c-29c9e2f1735f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351244327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.1351244327
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.1448154931
Short name T703
Test name
Test status
Simulation time 15043233 ps
CPU time 0.73 seconds
Started Aug 09 06:53:23 PM PDT 24
Finished Aug 09 06:53:24 PM PDT 24
Peak memory 206544 kb
Host smart-5987e877-7b24-48ff-9dff-4b465f1f3f73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448154931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.1448154931
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.661013249
Short name T16
Test name
Test status
Simulation time 5040900179 ps
CPU time 7.57 seconds
Started Aug 09 06:53:29 PM PDT 24
Finished Aug 09 06:53:36 PM PDT 24
Peak memory 233392 kb
Host smart-f69f780c-512c-4efb-bb4a-4e4ecc4f1996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661013249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.661013249
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.1327952485
Short name T961
Test name
Test status
Simulation time 24244058 ps
CPU time 0.75 seconds
Started Aug 09 06:53:40 PM PDT 24
Finished Aug 09 06:53:40 PM PDT 24
Peak memory 205836 kb
Host smart-6e1fd15c-80b8-4771-a82b-a0ac060e1a9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327952485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.1
327952485
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.2619852123
Short name T598
Test name
Test status
Simulation time 608301622 ps
CPU time 2.67 seconds
Started Aug 09 06:53:32 PM PDT 24
Finished Aug 09 06:53:35 PM PDT 24
Peak memory 225152 kb
Host smart-6612fe67-45f0-4380-9636-bba8fb87c8cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619852123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.2619852123
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.2810421773
Short name T869
Test name
Test status
Simulation time 15260769 ps
CPU time 0.75 seconds
Started Aug 09 06:53:25 PM PDT 24
Finished Aug 09 06:53:26 PM PDT 24
Peak memory 206024 kb
Host smart-67c3d2f8-a975-47b5-9495-dd2322c0f270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810421773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.2810421773
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.3003822363
Short name T643
Test name
Test status
Simulation time 18040019 ps
CPU time 0.79 seconds
Started Aug 09 06:53:40 PM PDT 24
Finished Aug 09 06:53:41 PM PDT 24
Peak memory 216448 kb
Host smart-e872b10d-e7fe-4760-a967-41c6e026c0c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003822363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.3003822363
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.1625055409
Short name T580
Test name
Test status
Simulation time 1064437496 ps
CPU time 3.5 seconds
Started Aug 09 06:53:40 PM PDT 24
Finished Aug 09 06:53:43 PM PDT 24
Peak memory 218332 kb
Host smart-711383cf-81d5-49ca-9d38-83611a895744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625055409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.1625055409
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.3255272332
Short name T729
Test name
Test status
Simulation time 56949556118 ps
CPU time 115.57 seconds
Started Aug 09 06:53:40 PM PDT 24
Finished Aug 09 06:55:35 PM PDT 24
Peak memory 225392 kb
Host smart-fecbd12f-1491-49e5-8ce8-5f919f3f66b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255272332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.3255272332
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.293882650
Short name T353
Test name
Test status
Simulation time 51859787 ps
CPU time 3.32 seconds
Started Aug 09 06:53:31 PM PDT 24
Finished Aug 09 06:53:34 PM PDT 24
Peak memory 233484 kb
Host smart-b60afa40-90de-45f5-8be1-e4f5a7ef7d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293882650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.293882650
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.3125474504
Short name T1
Test name
Test status
Simulation time 94912090949 ps
CPU time 67.56 seconds
Started Aug 09 06:53:39 PM PDT 24
Finished Aug 09 06:54:46 PM PDT 24
Peak memory 251116 kb
Host smart-83319dd8-6ca1-4e58-b28d-8a13b93df8a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125474504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds
.3125474504
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/8.spi_device_intercept.677470923
Short name T835
Test name
Test status
Simulation time 1840418150 ps
CPU time 4.62 seconds
Started Aug 09 06:53:33 PM PDT 24
Finished Aug 09 06:53:38 PM PDT 24
Peak memory 225176 kb
Host smart-8dc4d159-1437-4454-9db3-4dd4c69cc150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677470923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.677470923
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.782438515
Short name T250
Test name
Test status
Simulation time 10237815672 ps
CPU time 71.5 seconds
Started Aug 09 06:53:33 PM PDT 24
Finished Aug 09 06:54:44 PM PDT 24
Peak memory 233440 kb
Host smart-fb1dc38a-a6ee-40fb-a751-ffa1c8d62da5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782438515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.782438515
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.2425195907
Short name T972
Test name
Test status
Simulation time 14317108 ps
CPU time 0.97 seconds
Started Aug 09 06:53:33 PM PDT 24
Finished Aug 09 06:53:34 PM PDT 24
Peak memory 218360 kb
Host smart-af21deb3-b8cc-4eca-97a3-c2d2bdac356e
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425195907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.spi_device_mem_parity.2425195907
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.2754633754
Short name T774
Test name
Test status
Simulation time 7554683763 ps
CPU time 12.02 seconds
Started Aug 09 06:53:32 PM PDT 24
Finished Aug 09 06:53:45 PM PDT 24
Peak memory 237580 kb
Host smart-0d06ea77-85ec-4188-88ae-b334bc6bf9bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754633754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.2754633754
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.3951870435
Short name T401
Test name
Test status
Simulation time 232229682 ps
CPU time 2.7 seconds
Started Aug 09 06:53:32 PM PDT 24
Finished Aug 09 06:53:35 PM PDT 24
Peak memory 233460 kb
Host smart-030261ac-5446-4912-b006-d0c7cf3b0074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951870435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.3951870435
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.2321711306
Short name T382
Test name
Test status
Simulation time 9051218385 ps
CPU time 20.42 seconds
Started Aug 09 06:53:39 PM PDT 24
Finished Aug 09 06:53:59 PM PDT 24
Peak memory 221176 kb
Host smart-00e4faab-7766-4944-bd81-5e11323d95a1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2321711306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.2321711306
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.2900870556
Short name T283
Test name
Test status
Simulation time 59747026560 ps
CPU time 446.04 seconds
Started Aug 09 06:53:40 PM PDT 24
Finished Aug 09 07:01:06 PM PDT 24
Peak memory 258396 kb
Host smart-49175f7a-b2c7-4013-8131-04ea4f5127f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900870556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.2900870556
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.2434071066
Short name T618
Test name
Test status
Simulation time 1956324005 ps
CPU time 6.92 seconds
Started Aug 09 06:53:31 PM PDT 24
Finished Aug 09 06:53:38 PM PDT 24
Peak memory 217016 kb
Host smart-19344585-82f1-4711-8c5b-a7b92678c442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434071066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.2434071066
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.2868193199
Short name T349
Test name
Test status
Simulation time 21709782516 ps
CPU time 14.32 seconds
Started Aug 09 06:53:26 PM PDT 24
Finished Aug 09 06:53:40 PM PDT 24
Peak memory 217072 kb
Host smart-77926331-aa33-4afc-ae8b-e95834942cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868193199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.2868193199
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.3821295832
Short name T45
Test name
Test status
Simulation time 239457053 ps
CPU time 1.54 seconds
Started Aug 09 06:53:32 PM PDT 24
Finished Aug 09 06:53:34 PM PDT 24
Peak memory 208740 kb
Host smart-a8ba6c9d-beb6-4a60-b127-b5e03faf67a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821295832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.3821295832
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.876440323
Short name T389
Test name
Test status
Simulation time 41600570 ps
CPU time 0.92 seconds
Started Aug 09 06:53:31 PM PDT 24
Finished Aug 09 06:53:32 PM PDT 24
Peak memory 206548 kb
Host smart-59a5e246-5cee-4927-b8c9-b58ac3aac996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876440323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.876440323
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.3241928064
Short name T720
Test name
Test status
Simulation time 5764368995 ps
CPU time 4.67 seconds
Started Aug 09 06:53:33 PM PDT 24
Finished Aug 09 06:53:38 PM PDT 24
Peak memory 225288 kb
Host smart-d81d48b8-12c7-4871-b9bf-c01026dd9668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241928064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.3241928064
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.2014407598
Short name T125
Test name
Test status
Simulation time 24231584 ps
CPU time 0.72 seconds
Started Aug 09 06:53:49 PM PDT 24
Finished Aug 09 06:53:50 PM PDT 24
Peak memory 205764 kb
Host smart-ae502e2b-972d-4108-be6b-36d68cad4ebe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014407598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.2
014407598
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.1994107759
Short name T180
Test name
Test status
Simulation time 917784004 ps
CPU time 4.01 seconds
Started Aug 09 06:53:49 PM PDT 24
Finished Aug 09 06:53:53 PM PDT 24
Peak memory 233424 kb
Host smart-8395b601-5a85-4c8b-8c85-7eda9017ad5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994107759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.1994107759
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.3106133169
Short name T758
Test name
Test status
Simulation time 34380368 ps
CPU time 0.78 seconds
Started Aug 09 06:53:40 PM PDT 24
Finished Aug 09 06:53:40 PM PDT 24
Peak memory 207064 kb
Host smart-186f001e-ef0a-45c3-a902-41e7ffc54b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106133169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.3106133169
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.40963301
Short name T637
Test name
Test status
Simulation time 8579889294 ps
CPU time 64.67 seconds
Started Aug 09 06:53:49 PM PDT 24
Finished Aug 09 06:54:54 PM PDT 24
Peak memory 258136 kb
Host smart-ac32a6d1-add8-48e2-a8a6-295a4165d8f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40963301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.40963301
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.1167074749
Short name T162
Test name
Test status
Simulation time 71022067656 ps
CPU time 171.63 seconds
Started Aug 09 06:53:51 PM PDT 24
Finished Aug 09 06:56:43 PM PDT 24
Peak memory 253796 kb
Host smart-b13b777d-4bb9-4a5d-a3b4-dd1f0f972ef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167074749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.1167074749
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.322948142
Short name T191
Test name
Test status
Simulation time 5709702439 ps
CPU time 62.35 seconds
Started Aug 09 06:53:50 PM PDT 24
Finished Aug 09 06:54:53 PM PDT 24
Peak memory 258144 kb
Host smart-43c1cebe-a219-418d-b646-dd4367f765a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322948142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle.
322948142
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.929703164
Short name T403
Test name
Test status
Simulation time 132838100 ps
CPU time 3.72 seconds
Started Aug 09 06:53:51 PM PDT 24
Finished Aug 09 06:53:55 PM PDT 24
Peak memory 241608 kb
Host smart-81a38110-4c8b-4c83-b3b8-db638c273d09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929703164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.929703164
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.2741732122
Short name T1033
Test name
Test status
Simulation time 211252943275 ps
CPU time 274.27 seconds
Started Aug 09 06:53:49 PM PDT 24
Finished Aug 09 06:58:23 PM PDT 24
Peak memory 254756 kb
Host smart-061d6edf-b701-435c-ac8e-e0606ad7cfba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741732122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds
.2741732122
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/9.spi_device_intercept.658097050
Short name T809
Test name
Test status
Simulation time 487973051 ps
CPU time 7.14 seconds
Started Aug 09 06:53:49 PM PDT 24
Finished Aug 09 06:53:56 PM PDT 24
Peak memory 233492 kb
Host smart-248b29c9-aad7-4978-a8f8-4e44ed5b6773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658097050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.658097050
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.335103583
Short name T730
Test name
Test status
Simulation time 13327589449 ps
CPU time 34.8 seconds
Started Aug 09 06:53:49 PM PDT 24
Finished Aug 09 06:54:24 PM PDT 24
Peak memory 233500 kb
Host smart-3ce158e9-a567-4ffb-943a-2ed89318adfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335103583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.335103583
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.3846869181
Short name T32
Test name
Test status
Simulation time 117221610 ps
CPU time 1.08 seconds
Started Aug 09 06:53:42 PM PDT 24
Finished Aug 09 06:53:43 PM PDT 24
Peak memory 217156 kb
Host smart-f07c528c-76ed-4176-bda8-5471498e77d0
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846869181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.spi_device_mem_parity.3846869181
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.1926205724
Short name T520
Test name
Test status
Simulation time 552850015 ps
CPU time 8.72 seconds
Started Aug 09 06:53:50 PM PDT 24
Finished Aug 09 06:53:59 PM PDT 24
Peak memory 225288 kb
Host smart-5a4bd58f-ba54-4ca5-99c5-b3d47af813a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926205724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.1926205724
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.438761774
Short name T940
Test name
Test status
Simulation time 4502889361 ps
CPU time 13.9 seconds
Started Aug 09 06:53:41 PM PDT 24
Finished Aug 09 06:53:55 PM PDT 24
Peak memory 233404 kb
Host smart-c382c2d8-eaf8-4b0c-bc2a-32ebbccdbf67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438761774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.438761774
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.2120259679
Short name T740
Test name
Test status
Simulation time 620056166 ps
CPU time 8.25 seconds
Started Aug 09 06:53:51 PM PDT 24
Finished Aug 09 06:53:59 PM PDT 24
Peak memory 223688 kb
Host smart-1c99828c-433e-4e0c-a9b1-f7c960d971eb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2120259679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.2120259679
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.1357887657
Short name T22
Test name
Test status
Simulation time 6318096616 ps
CPU time 43.97 seconds
Started Aug 09 06:53:51 PM PDT 24
Finished Aug 09 06:54:35 PM PDT 24
Peak memory 219292 kb
Host smart-ad504f7a-1535-40b1-9f61-5465c2e9369b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357887657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.1357887657
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.1131706650
Short name T700
Test name
Test status
Simulation time 24243035060 ps
CPU time 29.21 seconds
Started Aug 09 06:53:39 PM PDT 24
Finished Aug 09 06:54:08 PM PDT 24
Peak memory 217020 kb
Host smart-08a682d4-feb7-4584-9f8b-1918e5e24514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131706650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.1131706650
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.3376455532
Short name T390
Test name
Test status
Simulation time 6054284757 ps
CPU time 18.55 seconds
Started Aug 09 06:53:41 PM PDT 24
Finished Aug 09 06:53:59 PM PDT 24
Peak memory 217020 kb
Host smart-372241d4-4b86-483d-8ac1-35f9d56f034b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376455532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.3376455532
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.3190145679
Short name T573
Test name
Test status
Simulation time 147897284 ps
CPU time 1.14 seconds
Started Aug 09 06:53:42 PM PDT 24
Finished Aug 09 06:53:43 PM PDT 24
Peak memory 207840 kb
Host smart-57441305-3e13-481f-8e02-3138c38478b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190145679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.3190145679
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.2717358314
Short name T653
Test name
Test status
Simulation time 13703676 ps
CPU time 0.71 seconds
Started Aug 09 06:53:41 PM PDT 24
Finished Aug 09 06:53:42 PM PDT 24
Peak memory 206532 kb
Host smart-7b81c620-6341-4284-8870-1c84174d25ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717358314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.2717358314
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.3329994912
Short name T615
Test name
Test status
Simulation time 382632446 ps
CPU time 9.31 seconds
Started Aug 09 06:53:49 PM PDT 24
Finished Aug 09 06:53:59 PM PDT 24
Peak memory 233324 kb
Host smart-eb898d30-be74-4680-919f-c77db37f8f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329994912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.3329994912
Directory /workspace/9.spi_device_upload/latest
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